A GaN HEMT device integrated with a reverse diode and a method for manufacturing the same

Abstract

The application discloses a GaN HEMT device integrated with a reverse diode and a preparation method thereof. The GaN HEMT device comprises a two-dimensional electron gas structure, a source electrode, a drain electrode, a P-GaN gate electrode, a passivation layer, a source field plate structure, a Schottky contact metal, an ohmic contact metal and a P-GaN layer. The Schottky contact metal and the surrounding structure thereof constitute a Schottky diode, and the P-GaN layer and the surrounding structure thereof constitute a P-i-N diode. The application integrates the parallel Schottky diode and P-i-N diode, and provides a new path for the reverse current of the GaN HEMT device. In the reverse conduction, the low reverse conduction voltage of the Schottky diode can be utilized, and the strong overcurrent capacity of the P-i-N diode can be exerted. The source field plate structure is utilized to build a reverse conduction loop, and the reverse conduction part is formed with the aid of the potential barrier layer. The reverse conduction part and the forward conduction part share the drain region, and the area is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of GaN power devices, and particularly relates to a GaN HEMT device integrated with a reverse diode and a preparation method thereof. BACKGROUND

[0002] GaN high electron mobility transistors (GaN HEMT) made of GaN as a material are widely used in various high-frequency high-power applications due to their fast switching speed and low on-resistance. However, in the application of power converters, new requirements are put forward for the reverse conduction capability of the device. For example, in energy storage systems and electric vehicle applications, bidirectional DC-DC converters are usually required to transmit electrical energy in two directions, so these applications usually require power devices to have reverse conduction capability. Since electrical energy can flow bidirectionally between the load and the power supply, power devices must be able to maintain low power loss in forward and reverse current states to improve energy transmission efficiency.

[0003] Although GaN HEMT has left-right symmetry in structure and there is little difference in forward and reverse conduction characteristics when turned on, there is a large reverse conduction voltage in the diode reverse conduction mode. This is because the reverse conduction voltage drop of the device is coupled with the gate voltage, and the reverse conduction voltage drop is related to the threshold voltage of the device.

[0004] In practical applications, a reverse parallel integrated Schottky diode structure is usually used to provide a path for reverse current to avoid current flowing under the gate. However, the Schottky diode is prone to failure under surge current conditions, and its Schottky diode stability is also poor in high-temperature operating environments. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a GaN HEMT device integrated with a reverse diode and a preparation method thereof. The technical problem to be solved by the application is solved by the following technical scheme:

[0006] In a first aspect, the application provides a GaN HEMT device integrated with a reverse diode, comprising:

[0007] a two-dimensional electron gas structure, a source electrode, a drain electrode, a P-GaN gate, a passivation layer, a source field plate structure, a Schottky contact metal, an ohmic contact metal and a P-GaN layer; wherein,

[0008] The source electrode and the drain electrode are respectively arranged on two sides of the potential barrier layer in the two-dimensional electron gas structure;

[0009] The P-GaN gate is arranged on a part of the upper surface of the two-dimensional electron gas structure close to the source electrode;

[0010] The Schottky contact metal and the P-GaN layer are arranged in the partial region between the upper surface of the two-dimensional electron gas structure, the drain and the P-GaN gate; the Schottky contact metal and the P-GaN layer are staggered in the lateral direction of the GaN HEMT device; the Schottky contact metal and the surrounding partial structure form a Schottky diode, and the P-GaN layer and the surrounding partial structure form a P-i-N diode.

[0011] The ohmic contact metal is arranged on the upper surface of the P-GaN layer.

[0012] The passivation layer is arranged on the remaining region of the upper surface of the two-dimensional electron gas structure and the upper surface of the P-GaN gate.

[0013] The source field plate structure is arranged on the partial region of the upper surface of the passivation layer and the side region of the passivation layer; the partial region of the upper surface of the passivation layer includes: the region between the source and the Schottky contact metal on the upper surface of the passivation layer and the partial region close to the Schottky contact metal between the drain and the Schottky contact metal.

[0014] In an embodiment of the present application, the two-dimensional electron gas structure comprises:

[0015] The substrate, the nucleation layer, the buffer layer, the channel layer and the barrier layer are sequentially stacked from bottom to top; wherein the channel layer and the barrier layer form a two-dimensional electron gas channel.

[0016] In an embodiment of the present application, the material of the substrate includes silicon; the material of the nucleation layer includes AlN; the material of the buffer layer includes AlGaN; the material of the channel layer includes GaN; and the material of the barrier layer includes AlGaN.

[0017] In an embodiment of the present application, the P-GaN gate comprises:

[0018] The partial P-GaN gate and the gate metal are sequentially arranged from bottom to top.

[0019] In an embodiment of the present application, the Schottky diode comprises:

[0020] The Schottky contact metal and the barrier layer.

[0021] In an embodiment of the present application, the P-i-N diode comprises:

[0022] The P-GaN layer, the channel layer, the barrier layer and the two-dimensional electron gas between the channel layer and the barrier layer.

[0023] In an embodiment of the present application, the remaining region of the upper surface of the two-dimensional electron gas structure comprises:

[0024] a region between the source and the P-GaN gate in the upper surface of the two-dimensional electron gas structure, a region between the P-GaN gate and the source field plate structure, a region between the source field plate structure and the drain.

[0025] In a second aspect, the present application provides a method for preparing a GaN HEMT device integrated with a reverse diode, the method comprising:

[0026] preparing an epitaxial wafer; the epitaxial wafer comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and an initial P-GaN layer; the substrate, the nucleation layer, the buffer layer, the channel layer, and the barrier layer form a two-dimensional electron gas structure;

[0027] defining a partial P-GaN gate and a P-GaN layer region on the initial P-GaN layer, and etching a region other than the partial P-GaN gate and the P-GaN layer region to the barrier layer to obtain a partial P-GaN gate and a P-GaN layer;

[0028] depositing SiN on the surface of the current sample to form a first passivation layer;

[0029] defining a source and a drain region on the surface of the first passivation layer, etching the source and the drain region to a depth extending to the channel layer to form a source and a drain recess, and preparing an ohmic contact source and an ohmic contact drain in the source and the drain recess by PVD technology;

[0030] defining an ohmic contact metal region on the surface of the first passivation layer, etching the ohmic contact metal region to the P-GaN layer to form an ohmic contact metal recess, and preparing an ohmic contact metal in the ohmic contact metal recess by PVD technology, from bottom to top, sputtering Ti, Al, Ni, and Au;

[0031] defining a P-GaN gate region on the surface of the first passivation layer, etching the P-GaN gate region to the partial P-GaN gate to form a gate recess, and preparing a gate metal in the gate recess by PVD technology, from bottom to top, sputtering Ti, Al, and Au; the partial P-GaN gate and the gate metal form a P-GaN gate;

[0032] depositing SiN on the surface of the current sample to form a second passivation layer; the first passivation layer and the second passivation layer form a passivation layer;

[0033] defining a Schottky metal region and the ohmic contact metal region on the surface of the second passivation layer, and etching the Schottky metal region and the ohmic contact metal region to the barrier layer and the ohmic contact metal, respectively;

[0034] A metal field plate pattern is defined on the surface of the current sample, and a PVD technique is used to sputter Ti, Au from bottom to top on the metal field plate pattern to prepare the source field plate structure and Schottky contact metal.

[0035] In an embodiment of the present application, an ohmic contact source and drain are prepared in the source and drain recesses using a PVD technique, comprising:

[0036] An ohmic contact source metal and drain metal are prepared in the source and drain recesses, respectively, by sputtering Ti, Al, Ni and Au from bottom to top using a PVD technique;

[0037] The source metal and drain metal are subjected to rapid thermal annealing in an N atmosphere at a preset temperature to obtain the source and drain.

[0038] In an embodiment of the present application, the region corresponding to the metal field plate pattern comprises:

[0039] The region between the source and the P-GaN gate, the region between the P-GaN gate and the source field plate structure, the region between the source field plate structure and the drain, and the upper surface of the P-GaN gate in the upper surface of the two-dimensional electron gas structure.

[0040] The present application has the following beneficial effects:

[0041] 1. The present application integrates a Schottky diode and a P-i-N diode on the basis of the original GaN HEMT, and the two diodes are connected in parallel, providing a new path for the reverse current of the GaN HEMT device. When the device is reverse conducting, the advantages of low reverse conduction voltage of the Schottky diode can be utilized, and the strong overcurrent capacity of the P-i-N diode can be exerted.

[0042] 2. By integrating the two diodes and using the source field plate structure to build a reverse conduction loop, and with the help of the barrier layer to form a reverse conduction part, this design makes the reverse conduction part share the drain region with the forward conduction part, avoiding the increase of additional structure occupying new chip area. In addition, the staggered design of the diode structure reduces the impact on the channel two-dimensional electron gas, so the original forward conduction performance of the GaN HEMT device is less affected. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 A perspective structural schematic diagram of a GaN HEMT device integrated with a reverse diode provided by an embodiment of the present application;

[0044] Figure 2 A partial structural schematic diagram of a GaN HEMT device integrated with a reverse diode provided by an embodiment of the present application;

[0045] Figure 3 A lateral sectional view of a GaN HEMT device integrated with a reverse diode along the upper surface of a P-GaN layer according to an embodiment of the present application;

[0046] Figure 4 A front view schematic diagram of a section A of a partial structure of a GaN HEMT device integrated with a reverse diode according to an embodiment of the present application;

[0047] Figure 5 A front view schematic diagram of a section B of a partial structure of a GaN HEMT device integrated with a reverse diode according to an embodiment of the present application;

[0048] Figure 6 A schematic diagram of steps of a method for manufacturing a GaN HEMT device integrated with a reverse diode according to an embodiment of the present application;

[0049] Figures 7A-7I A process flow chart of a GaN HEMT device integrated with a reverse diode according to an embodiment of the present application. DETAILED DESCRIPTION

[0050] The present application will be further described below in conjunction with specific embodiments, but the embodiments of the present application are not limited thereto.

[0051] In order to solve the problems existing in the prior art, the embodiments of the present application provide a GaN HEMT device integrated with a reverse diode and a method for manufacturing the same.

[0052] The following is a further detailed description of the present application in conjunction with specific preferred embodiments, and the specific implementation of the present application should not be limited to these descriptions. For those of ordinary skill in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can also be made, which should be considered to fall within the scope of protection of the present application.

[0053] Next, first, a GaN HEMT device integrated with a reverse diode according to an embodiment of the present application will be introduced.

[0054] As shown in Figure 1 , a GaN HEMT device integrated with a reverse diode according to an embodiment of the present application can include:

[0055] a two-dimensional electron gas structure 1, a source electrode 2, a drain electrode 3, a P-GaN gate electrode 4, a passivation layer 5, a source field plate structure 6, a Schottky contact metal 7, an ohmic contact metal 8, and a P-GaN layer 9; wherein,

[0056] The source electrode 2 and the drain electrode 3 are respectively arranged on two sides of the barrier layer 105 in the two-dimensional electron gas structure 1;

[0057] The P-GaN gate 4 is arranged on a partial region of the upper surface of the two-dimensional electron gas structure 1 close to the source electrode 2;

[0058] The Schottky contact metal 7 and the P-GaN layer 9 are arranged on a partial region between the upper surface drain electrode 3 and the P-GaN gate 4 of the two-dimensional electron gas structure 1; the Schottky contact metal 7 and the P-GaN layer 9 are staggered in the lateral direction of the GaN HEMT device; the Schottky contact metal 7 and the surrounding partial structure form a Schottky diode, and the P-GaN layer 9 and the surrounding partial structure form a P-i-N diode;

[0059] The ohmic contact metal 8 is arranged on the upper surface of the P-GaN layer 9;

[0060] The passivation layer 5 is arranged on the remaining region of the upper surface of the two-dimensional electron gas structure 1 and the upper surface of the P-GaN gate 4;

[0061] The source field plate structure 6 is arranged on a partial region of the upper surface of the passivation layer 5 and a side region of the passivation layer 5; the partial region of the upper surface of the passivation layer 5 includes a region between the source electrode 2 and the Schottky contact metal 7 and a partial region close to the Schottky contact metal 7 between the drain electrode 3 and the Schottky contact metal 7 in the upper surface of the passivation layer 5.

[0062] The GaN HEMT device provided by the embodiment of the present application integrates a Schottky diode and a P-i-N diode on the basis of the original GaN HEMT, the two diodes are connected in parallel, and a new path is provided for the reverse current of the GaN HEMT device. When the device is reversely turned on, the advantages of the low reverse turn-on voltage of the Schottky diode can be utilized, and the strong overcurrent capacity of the P-i-N diode can be utilized.

[0063] In order to facilitate understanding, the structure of the integrated reverse diode GaN HEMT device provided by the embodiment of the present application will be specifically introduced below in combination with Figure 2 , Figure 3 , Figure 4 and Figure 5 .

[0064] Specifically, in order to more clearly show the connection relationship between the source field plate structure 6, the Schottky contact metal 7, the ohmic contact metal 8 and the P-GaN layer 9, the embodiment of the present application provides a partial structure schematic diagram of the GaN HEMT device, please refer to Figure 2 . Specifically Figure 2 the partial structure of the passivation layer on the right side of the P-GaN layer 9 and the partial structure of the source field plate structure are omitted, and the connection relationship between the source field plate structure 6, the Schottky contact metal 7, the ohmic contact metal 8 and the P-GaN layer 9 is shown in the figure. Figure 2As can be seen, the Schottky contact metal 7 and the P-GaN layer 9 are disposed in a portion of the area between the drain 3 and the P-GaN gate 4 on the upper surface of the two-dimensional electron gas structure 1. To more clearly illustrate the connection relationship between the Schottky contact metal 7 and the P-GaN layer 9, this embodiment of the invention provides a transverse cross-sectional view of the GaN HEMT device along the upper surface of the P-GaN layer. Please refer to [link to relevant documentation]. Figure 3 .from Figure 3 As can be seen, the Schottky contact metal 7 and the P-GaN layer 9 are arranged side-by-side and staggered in the lateral direction of the GaN HEMT device. It can be understood that the Schottky contact metal 7, the ohmic contact metal 8, and the P-GaN layer 9 constitute a fin structure. Optionally, the widths of the Schottky contact metal 7 and the P-GaN layer 9 in the lateral direction of the GaN HEMT device can be equal, specifically set to 2 μm.

[0065] Two-dimensional electron gas structure 1 may include:

[0066] The substrate 101, nucleation layer 102, buffer layer 103, channel layer 104 and barrier layer 105 are stacked sequentially from bottom to top; wherein, the channel layer 104 and barrier layer 105 form a two-dimensional electron gas channel.

[0067] The material of substrate 101 may include silicon; the material of nucleation layer 102 may include AlN; the material of buffer layer 103 may include AlGaN; the material of channel layer 104 may include GaN; and the material of barrier layer 105 may include AlGaN.

[0068] Optionally, the substrate 101 can be made of p-type (1,1,1) oriented silicon material with a thickness of 200 μm; the nucleation layer 102 can have a thickness of 200 nm; and the buffer layer 103 can be made of Al. 0.3 Ga 0.7 The material is made of N and can be 5 μm thick; the channel layer 104 can be 200 nm thick; the barrier layer 105 can be made of Al. 0.2 Ga 0.8 It is made of N and can be 15nm thick.

[0069] The P-GaN gate 4 may include:

[0070] The P-GaN gate 41 and gate metal 42 are arranged sequentially from bottom to top.

[0071] The material of part of the P-GaN gate 41 can be Mg+ ion-doped GaN, and the Mg+ ion doping concentration can be 10. 19 cm -3 The thickness can be 70nm, forming a Schottky contact with the gate metal 42.

[0072] The GaN HEMT device provided by the embodiment of the present application realizes two functions, from bottom to top, which are a lateral power device and a reverse conduction part.

[0073] The Schottky diode can include:

[0074] The Schottky contact metal 7 and the barrier layer 105.

[0075] The upper end of the Schottky contact metal 7 is connected with the source field plate structure 6, and the lower end is connected with the barrier layer 105, so as to form a Schottky barrier. The Schottky diode can prevent current from flowing through the Schottky contact metal 7 when the device is forward conducting.

[0076] The P-i-N diode can include:

[0077] The P-GaN layer 9, the channel layer 104, the barrier layer 105 and the two-dimensional electron gas 2DEG between the channel layer 104 and the barrier layer 105.

[0078] The P-GaN layer 9 is arranged above the barrier layer 105, the upper end is connected with the ohmic contact metal 8, and the lower end is connected with the barrier layer 105. The P-i-N diode can prevent current from flowing through the P-GaN layer 9 when the device is forward conducting.

[0079] The P-GaN layer 9 can be composed of P-doped GaN, wherein the Mg+ ion doping concentration can be 10 19 cm -3 , and the thickness can be 70 nm.

[0080] The GaN HEMT device provided by the embodiment of the present application integrates two diodes and utilizes the source field plate structure to build a reverse conduction loop, and simultaneously utilizes the barrier layer to form a reverse conduction part. This design makes the reverse conduction part and the forward conduction share a drain region, avoids increasing an additional structure to occupy a new chip area. In addition, the staggered design of the diode structure reduces the influence on the channel two-dimensional electron gas, and therefore, the influence on the original forward conduction performance of the GaN HEMT device is small.

[0081] The GaN HEMT device provided by the embodiment of the present application sequentially arranges a source 2 and a drain 3 on the two-dimensional electron gas structure 1 from left to right, and simultaneously extends a source field plate structure 6 above a P-GaN gate 4 from the source 2 to the right. The source field plate structure connected with the source 2 can adjust the P-GaN gate 4 and the Schottky contact metal 6, the electric field concentration phenomenon on the right side of the P-GaN layer 8 according to the voltage applied on the source, so as to prevent the device from being prematurely broken down.

[0082] A cross section A of a part structure of a GaN HEMT device integrated with a reverse diode according to an embodiment of the present application is shown in a front view, as shown in Figure 4 ; and a cross section B of the part structure is shown in a front view, as shown in Figure 5 It can be understood that Figure 4 and Figure 5 are schematic diagrams corresponding to the part structure remaining after the part structure of the passivation layer on the right side of the P-GaN layer 9 and the part structure of the source field plate structure are omitted from the GaN HEMT device. It can be seen from Figure 2 , Figure 3 , Figure 4 and Figure 5 that the passivation layer 5 is arranged on the remaining area of the upper surface of the two-dimensional electron gas structure 1 and the upper surface of the P-GaN gate 4; wherein the remaining area of the upper surface of the two-dimensional electron gas structure 1 can include: the area between the source 2 and the P-GaN gate 4 on the upper surface of the two-dimensional electron gas structure 1, the area between the P-GaN gate 4 and the source field plate structure 6, and the area between the source field plate structure 6 and the drain 3.

[0083] The source field plate structure 6 is arranged on a part area of the upper surface of the passivation layer 5 and a side area of the passivation layer 5; the part area of the upper surface of the passivation layer 5 includes the area between the source 2 and the Schottky contact metal 7 on the upper surface of the passivation layer 5 and the part area close to the Schottky contact metal 7 between the drain 3 and the Schottky contact metal 7.

[0084] The embodiment of the present application integrates a Schottky diode and a P-i-N diode on the basis of the original GaN HEMT, and the two diodes are connected in parallel, which provides a new path for the reverse current of the GaN HEMT device. When the device is reversely turned on, the advantages of the low reverse on-voltage of the Schottky diode can be utilized, and the strong overcurrent capacity of the P-i-N diode can also be utilized; by integrating the two diodes and utilizing the source field plate structure to build a reverse on-circuit, and by means of the barrier layer to form a reverse on-part, the reverse on-part and the forward on-part share the drain region, which avoids the increase of the additional structure occupying new chip area. In addition, the staggered and side-by-side design of the diode structure reduces the influence on the channel two-dimensional electron gas, and thus the influence on the original forward on-performance of the GaN HEMT device is small.

[0085] In a second aspect, corresponding to the above embodiment, the embodiment of the present application further provides a preparation method of a GaN HEMT device integrated with a reverse diode, as shown in Figure 6 , the preparation method comprises:

[0086] S1, preparing an epitaxial wafer; the epitaxial wafer comprises, from bottom to top, a substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, and an initial P-GaN layer; the substrate 101, the nucleation layer 102, the buffer layer 103, the channel layer 104, and the barrier layer 105 constitute a two-dimensional electron gas structure 1.

[0087] The substrate 101, the nucleation layer 102, the buffer layer 103, the channel layer 104, the barrier layer 105, and the initial P-GaN layer are respectively made of Si material, AlN material, Al 0.3 Ga 0.7 N material, GaN material, Al 0.2 Ga 0.8 N material, and Mg+-doped GaN. The structure of the sample obtained after step S1 is shown in Figure 7A

[0088] Specifically, first, a low-temperature AlN nucleation layer is epitaxially grown on the upper surface of the substrate 101 by using MOCVD (Metal organic Chemical Vapor Deposition) technology, and then a high-temperature AlN nucleation layer is epitaxially grown on the upper surface of the low-temperature AlN nucleation layer, thereby obtaining the nucleation layer 102; wherein the thickness of the low-temperature AlN nucleation layer can be 30 nm, and the thickness of the high-temperature AlN nucleation layer can be 170 nm.

[0089] After the nucleation layer 102 is prepared, an undoped Al 0.3 Ga 0.7 N buffer layer is deposited on the upper surface of the nucleation layer 102 by using MOCVD technology with trimethylaluminum as the aluminum source, trimethylgallium as the gallium source, and ammonia as the ammonia source, thereby obtaining the buffer layer 103; the thickness of the buffer layer 103 can be 5 μm.

[0090] After the buffer layer 103 is prepared, an undoped GaN channel layer is deposited on the upper surface of the buffer layer 103 by using MOCVD technology with trimethylgallium as the gallium source and ammonia as the ammonia source, thereby obtaining the channel layer 104; the thickness of the channel layer 104 can be 200 nm.

[0091] After the channel layer 104 is prepared, an undoped Al 0.2 Ga 0.8 N barrier layer is deposited on the upper surface of the channel layer 104 by using MOCVD technology with trimethylgallium as the gallium source, trimethylaluminum as the aluminum source, and ammonia as the ammonia source, thereby obtaining the barrier layer 105; the thickness of the barrier layer 105 can be 15 nm.

[0092] ​After the preparation of the barrier layer 105, a Mg+ doped GaN layer is epitaxially grown on the surface of the barrier layer by MOCVD technology. The epitaxially grown Mg+ doped GaN layer is annealed at high temperature to form a layer; the thickness of the P-GaN layer can be 70 nm; and the doping concentration of Mg+ ions in the P-GaN layer can be 10 19 cm 3 .

[0093] S2, defining a partial P-GaN gate and a P-GaN layer region on the initial P-GaN layer, etching the region other than the partial P-GaN gate and the P-GaN layer region to the barrier layer 105 to obtain a partial P-GaN gate 41 and a P-GaN layer 9. The structure of the sample obtained after step S2 is shown in Figure 7B .

[0094] Specifically, first, a partial P-GaN gate and a P-GaN layer region are defined on the initial P-GaN layer; second, photoresist is spin-coated and exposed and developed on the region other than the defined partial P-GaN gate and P-GaN layer region; and then, ICP (Inductively Coupled Plasma) etching process is used to etch downward the region other than the defined partial P-GaN gate and P-GaN layer region until the etching depth extends to the barrier layer 105.

[0095] S3, depositing Si3N4 on the surface of the current sample to form a first passivation layer.

[0096] S4, defining a source and a drain region on the surface of the first passivation layer, etching the source and the drain region to the channel layer 104 to form a source and a drain recess; and using PVD technology to prepare an ohmic contact source 2 and a drain 3 in the source and the drain recess.

[0097] Specifically, a source and a drain region are defined on the surface of the first passivation layer, and ICP etching is performed on the source and the drain region to extend the etching depth to the barrier layer 105 and the channel layer 104 to form a source and a drain recess, and the sample obtained at this time is shown in Figure 7C ; and PVD technology is used to prepare an ohmic contact source 2 and a drain 3 in the source and the drain recess, which can include:

[0098] PVD technology is used to sputter Ti, Al, Ni and Au in the source and the drain recesses from bottom to top to prepare an ohmic contact source metal and a drain metal, and the sample obtained at this time is shown in Figure 7D .

[0099] The source metal and the drain metal are subjected to rapid thermal annealing at a preset temperature in a N2 atmosphere to obtain the source 2 and the drain 3. The thicknesses of Ti, Al, Ni and Au can be 20 nm, 140 nm, 50 nm and 40 nm respectively, the preset temperature can be set to 865℃, and the rapid thermal annealing time can be set to 35 s.

[0100] S5, defining an ohmic contact metal area on the surface of the first passivation layer, etching in the ohmic contact metal area to the P-GaN layer 9 to form an ohmic contact metal groove, and preparing the ohmic contact metal 8 by sputtering Ti, Al, Ni and Au from bottom to top in the ohmic contact metal groove by using the PVD technology. The structure of the sample obtained after step S5 is shown in Figure 7E .

[0101] Specifically, the photoresist is coated on the surface of the first passivation layer to define the ohmic contact metal area and is exposed and developed, the first passivation layer deposited on the surface of the P-GaN layer 9 in the ohmic contact metal area is removed by using the hydrogen ion wet method to form the ohmic contact metal groove, and the first metal is prepared by sputtering Ti, Al, Ni and Au from bottom to top in the ohmic contact metal groove by using the PVD (Physical Vapor Deposition) technology, and the thicknesses of the metal layers in the first metal can be 20 nm, 50 nm, 50 nm and 30 nm respectively; the first metal formed by sputtering is subjected to rapid thermal annealing at a temperature of 865℃ for 35 s in a N2 atmosphere to form the ohmic contact metal 8.

[0102] S6, defining a P-GaN gate region on the surface of the first passivation layer, etching in the P-GaN gate region to the partial P-GaN gate 41 to form a gate groove, and preparing the gate metal 42 by sputtering Ti, Al and Au from bottom to top by using the PVD technology; the partial P-GaN gate 41 and the gate metal 42 constitute the P-GaN gate 4. The structure of the sample obtained after step S6 is shown in Figure 7F .

[0103] Specifically, the P-GaN gate region is defined on the surface of the first passivation layer, the first passivation layer deposited on the surface of the partial P-GaN gate 41 in the P-GaN gate region is removed by using the hydrogen ion wet method, the etching depth extends to the partial P-GaN gate 41 to form the gate groove, the second metal is prepared by sputtering Ti, Al and Au from bottom to top by using the PVD technology, and the thicknesses of the metal layers can be 20 nm, 50 nm and 30 nm respectively, and the second metal formed by sputtering is subjected to annealing at a temperature of 450℃ for 300 s in a N2 atmosphere to complete the preparation of the gate metal 42 with Schottky contact.

[0104] S7, depositing Si3N4 on the surface of the current sample to form a second passivation layer; the first passivation layer and the second passivation layer constitute the passivation layer 5. The structure of the sample obtained after step S7 is shown in Figure 7G .

[0105] S8, defining a Schottky metal region and an ohmic contact metal region on the surface of the second passivation layer, and etching the Schottky metal region and the ohmic contact metal region to the barrier layer 105 and the ohmic contact metal 8 respectively. The structure of the sample obtained after step S8 is shown in Figure 7H .

[0106] Specifically, the Schottky metal region and the ohmic contact metal region defined on the surface of the second passivation layer are removed from the surface by hydrogen ion wet method in batches, and etched to the barrier layer 105 and the ohmic contact metal 8 respectively.

[0107] S9, defining a metal field plate pattern on the surface of the current sample, and preparing the source field plate structure 6 and the Schottky contact metal 7 on the metal field plate pattern by sputtering Ti and Au from bottom to top using PVD technology. The structure of the sample obtained after step S9 is shown in Figure 7I .

[0108] Specifically, a metal field plate pattern is defined on the surface of the current sample, and a metal field plate is prepared on the metal field plate pattern by sputtering Ti and Au from bottom to top using PVD technology, and the thickness of each metal layer can be 20 nm and 130 nm respectively. Annealing of the sputtered metal field plate is performed in N2 atmosphere at a temperature of 450 DEG C for 300 s to complete the preparation of the source field plate structure 6 and the Schottky contact metal 7. The region corresponding to the metal field plate pattern can include: the region between the source 2 and the P-GaN gate 4 on the upper surface of the two-dimensional electron gas structure 1, the region between the P-GaN gate 4 and the source field plate structure 6, the region between the source field plate structure 6 and the drain 3, and the upper surface of the P-GaN gate 4.

[0109] In summary, the embodiments of the present application have the following advantages:

[0110] 1. The source field plate structure is used to build a reverse conduction loop, and the barrier layer is used to form a reverse conduction part, which shares the drain region with the forward conduction, greatly reducing the area and space occupied by the additional structure.

[0111] 2. The staggered side-by-side design reduces the influence on the two-dimensional electron gas and minimizes the influence on the original forward conduction performance of the device.

[0112] 3. The advantages of the two types of diodes are combined, that is, the advantages of the lower reverse conduction voltage of the Schottky diode and the good overcurrent capacity of the P-i-N diode.

[0113] It should be noted that in the description of the present application, it is to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0114] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0115] The above only describes the preferred embodiments of the present application and is not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An integrated reverse diode GaN HEMT device, characterized by, The application relates to a GaN HEMT device, which comprises a two-dimensional electron gas structure (1), a source electrode (2), a drain electrode (3), a P-GaN gate electrode (4), a passivation layer (5), a source field plate structure (6), a Schottky contact metal (7), an ohmic contact metal (8) and a P-GaN layer (9); wherein, The source electrode (2) and the drain electrode (3) are respectively arranged on two sides of a barrier layer (105) in the two-dimensional electron gas structure (1); The P-GaN gate electrode (4) is arranged on a part of an upper surface of the two-dimensional electron gas structure (1) close to the source electrode (2); The Schottky contact metal (7) and the P-GaN layer (9) are arranged on a part of the upper surface of the two-dimensional electron gas structure (1) between the drain electrode (3) and the P-GaN gate electrode (4); the Schottky contact metal (7) and the P-GaN layer (9) are staggered in the lateral direction of the GaN HEMT device; the Schottky contact metal (7) and the surrounding part of the structure form a Schottky diode, and the P-GaN layer (9) and the surrounding part of the structure form a P-i-N diode; The ohmic contact metal (8) is arranged on an upper surface of the P-GaN layer (9); The passivation layer (5) is arranged on a remaining area of the upper surface of the two-dimensional electron gas structure (1) and an upper surface of the P-GaN gate electrode (4); The source field plate structure (6) is arranged on a part of an upper surface of the passivation layer (5) and a side area of the passivation layer (5); the part of the upper surface of the passivation layer (5) comprises a region between the source electrode (2) and the Schottky contact metal (7) and a part of a region between the drain electrode (3) and the Schottky contact metal (7) close to the Schottky contact metal (7) on the upper surface of the passivation layer (5). The two-dimensional electron gas structure (1) comprises:

2. The integrated reverse diode GaN HEMT device of claim 1, wherein, A substrate (101), a nucleation layer (102), a buffer layer (103), a channel layer (104) and a barrier layer (105) are sequentially stacked from bottom to top; wherein, the channel layer (104) and the barrier layer (105) form a two-dimensional electron gas channel. The material of the substrate (101) comprises silicon; the material of the nucleation layer (102) comprises AlN; the material of the buffer layer (103) comprises AlGaN; the material of the channel layer (104) comprises GaN; and the material of the barrier layer (105) comprises AlGaN.

3. The integrated reverse diode GaN HEMT device of claim 2, wherein, The P-GaN gate electrode (4) comprises:

4. The integrated reverse diode GaN HEMT device of claim 1, wherein, A part of a P-GaN gate electrode (41) and a gate metal (42) are sequentially arranged from bottom to top. The Schottky diode comprises:

5. The integrated reverse diode GaN HEMT device of claim 2, wherein, The Schottky contact metal (7) and the barrier layer (105). The P-i-N diode comprises:

6. The integrated reverse diode GaN HEMT device of claim 2, wherein, The P-GaN layer (9), the channel layer (104), the barrier layer (105) and the two-dimensional electron gas between the channel layer (104) and the barrier layer (105). The remaining area of the upper surface of the two-dimensional electron gas structure (1) comprises:

7. The integrated reverse diode GaN HEMT device of claim 1, wherein, ​ The region between the source (2) and the P-GaN gate (4), the region between the P-GaN gate (4) and the source field plate structure (6), and the region between the source field plate structure (6) and the drain (3) in the upper surface of the two-dimensional electron gas structure (1).

8. A method of fabricating a GaN HEMT device integrated with a reverse diode, characterized in that, Comprise: Preparation of an epitaxial wafer; The epitaxial wafer comprises, from bottom to top: a substrate (101), a nucleation layer (102), a buffer layer (103), a channel layer (104), a barrier layer (105), and an initial P-GaN layer; the substrate (101), nucleation layer (102), buffer layer (103), channel layer (104), and barrier layer (105) constitute a two-dimensional electron gas structure (1); Defining a partial P-GaN gate and P-GaN layer region on the initial P-GaN layer, and etching the region other than the partial P-GaN gate and P-GaN layer region to the barrier layer (105), to obtain a partial P-GaN gate (41) and a P-GaN layer (9); Depositing Si3N4 on the surface of the current sample to form a first passivation layer; Defining a source and drain region on the surface of the first passivation layer, etching the source and drain region to a depth extending to the channel layer (104) to form a source and drain recess; using PVD technology to prepare an ohmic contact source (2) and drain (3) in the source and drain recess; Defining an ohmic contact metal region on the surface of the first passivation layer, etching the ohmic contact metal region to the P-GaN layer (9) to form an ohmic contact metal recess, and using PVD technology to sputter Ti, Al, Ni, and Au from bottom to top in the ohmic contact metal recess to prepare an ohmic contact metal (8); Defining a P-GaN gate region on the surface of the first passivation layer, etching the P-GaN gate region to the partial P-GaN gate (41) to form a gate recess, and using PVD technology to sputter Ti, Al, and Au from bottom to top to prepare a gate metal (42); the partial P-GaN gate (41) and gate metal (42) constitute a P-GaN gate (4); Depositing Si3N4 on the surface of the current sample to form a second passivation layer; the first passivation layer and the second passivation layer constitute a passivation layer (5); Defining a Schottky metal region and the ohmic contact metal region on the surface of the second passivation layer, etching the Schottky metal region and the ohmic contact metal region to the barrier layer (105) and ohmic contact metal (8), respectively; Defining a metal field plate pattern on the surface of the current sample, and using PVD technology to sputter Ti, Au from bottom to top on the metal field plate pattern to prepare the source field plate structure (6) and Schottky contact metal (7).

9. The integrated reverse diode GaN HEMT device of claim 8, wherein, The use of PVD technology to prepare an ohmic contact source (2) and drain (3) in the source and drain recess comprises: The source metal and the drain metal are prepared by sputtering Ti, Al, Ni and Au from bottom to top in the source and drain recesses by PVD technology to form ohmic contact; The source metal and the drain metal are subjected to rapid thermal annealing at a preset temperature in N2 atmosphere to obtain the source (2) and the drain (3).

10. The integrated reverse diode GaN HEMT device of claim 8, wherein, The region corresponding to the metal field plate pattern comprises: The region between the source (2) and the P-GaN gate (4), the region between the P-GaN gate (4) and the source field plate structure (6), the region between the source field plate structure (6) and the drain (3) and the upper surface of the P-GaN gate (4) in the upper surface of the two-dimensional electron gas structure (1).

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