Satellite-borne operating system-oriented RISCV processor abnormal context protection and recovery method

Abstract

The invention discloses a satellite-borne operating system-oriented RISCV processor abnormal context protection and recovery method, which supports that the satellite-borne operating system is allowed to be abnormally interrupted no matter in a task, in an interrupt processing program or in an interrupt context protection or recovery process, and can effectively store and recover a site. In a space environment where single-particle events frequently occur, the context can be effectively protected and recovered under the abnormal condition of a processor, normal and continuous operation of software is ensured, and the reliability of a spaceborne computer is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of onboard computer operating systems, and in particular relates to a RISC-V processor abnormal context protection and recovery method for an onboard operating system. Background Art

[0002] The context protection and recovery mechanism in case of processor anomalies is an important part of the onboard operating system. In the space environment where single particle events occur frequently, whether the context can be effectively protected and restored in case of processor anomalies and whether the normal and continuous operation of the software can be guaranteed affects the reliability of the onboard computer.

[0003] RISCV is a new open source instruction set architecture based on the Reduced Instruction Set Computing (RISC) principle. It is designed for cloud computers, micro embedded systems and other application scenarios. In operating systems that support the RISCV architecture, such as FREE-RTOS, exception handlers and interrupt handlers use the mscratch function register to temporarily save the stack pointer (sp register) to complete context protection. However, under the RISCV architecture, processor exceptions cannot be shielded. In extreme cases, processor exceptions may interrupt key processes in the operating system, such as task context switching, interrupt context protection or recovery, resulting in the loss of the stack pointer in the case of processor exceptions, leading to the problem that the task or interrupt scene cannot be recovered.

[0004] Therefore, it is necessary to design a processor exception handling method for the onboard operating system so that the onboard operating system can be interrupted by exceptions regardless of whether it is in a task, an interrupt handler, or in the interrupt context protection or recovery process, and can effectively save and restore the scene. Summary of the invention

[0005] The technology of the present invention solves the problem: overcomes the shortcomings of the prior art, provides a RISCV processor exception context protection and recovery method for a satellite operating system, solves the problem of how to save the context to ensure that the exception handling program does not affect the normal operation of the program under the condition that the RISCV processor cannot shield the Trap, and the method is applied to a satellite computer based on a RISCV instruction set processor, which helps to improve the reliability of the computer.

[0006] In order to solve the above technical problems, the present invention discloses a RISC-V processor abnormal context protection and recovery method for a satellite-borne operating system, comprising:

[0007] When the processor detects an exception, it calls the exception handler to execute the following process:

[0008] Save the value of register t0 to the space pointed to by address sp-4; where sp represents the value of register sp;

[0009] Assign register t0 to the bottom of the exception handler stack, and save the value of register sp to the address space pointed to by register t0;

[0010] Assign register t0 to the context size, and decrement the value of register sp by t0; where t0 represents the value of register t0;

[0011] Save the complete context content to the address space pointed to by register sp;

[0012] The program jumps to the user handler to fix the exception.

[0013] In the above-mentioned RISC V processor exception context protection and recovery method for the onboard operating system, it also includes: when the user processing program is executed, the operating system starts to execute the exit process to exit from the exception processing program.

[0014] In the above-mentioned RISCV processor exception context protection and recovery method for the onboard operating system, the exit process is as follows:

[0015] Restore the context of the address space pointed to by register sp to the processor;

[0016] Assign register t0 to the context size, and increment register sp by t0.

[0017] Assign register t0 to the bottom of the exception handler stack, and restore the value of register sp from the address pointed to by register t0;

[0018] Restore the value of register t0 from the space pointed to by the sp-4 address.

[0019] The above-mentioned RISCV processor exception context protection and recovery method for the onboard operating system also includes: reserving an exception handler stack in the operating system for use by the exception handler; wherein the exception handler stack is independent of the task stack and the interrupt stack.

[0020] In the above-mentioned RISC V processor exception context protection and recovery method for the onboard operating system, the stack bottom of the exception handler stack is set when the operating system is started, and the stack data in the exception handler stack is set to 0.

[0021] In the above-mentioned RISCV processor exception context protection and recovery method for the onboard operating system, it also includes: designing an exception handling buffer in the task context data structure, the starting address of the exception handling buffer is the lowest address of the context data structure, and the length is 4 bytes.

[0022] The above-mentioned RISCV processor exception context protection and recovery method for the onboard operating system also includes: when the task context is initialized, the exception handling buffer is first filled with 0; when the processor detects an exception, the CPU automatically jumps to the exception handler, and the exception handler saves the general register t0 to the exception handling buffer to prevent the exception handler from being interrupted by other exceptions again.

[0023] In the above-mentioned RISC V processor exception context protection and recovery method for the onboard operating system, the exceptions include: instruction access error exceptions and illegal instruction exceptions.

[0024] The present invention has the following advantages:

[0025] The present invention discloses a RISC-V processor exception context protection and recovery method for a satellite-borne operating system, which fully considers all situations in the operation of the operating system and ensures that the software operation can be restored in any case when it is interrupted by an exception:

[0026] 1. An exception occurs during a task. At this time, sp points to the top of the task stack, and sp-4 points to an unused address in the task stack, which is the exception handling buffer. Using this address to save data will not affect the normal operation of the program.

[0027] 2. In the interrupt handler, sp now points to the top of the interrupt stack, and sp-4 points to an unused address in the interrupt stack. Using this address to save data will not affect the normal operation of the program.

[0028] 3. In the process of entering or exiting an interrupt from a task, sp at this time points to the position of the corresponding task * tcb + 4 (related to the operating system design). The space pointed to by the sp-4 address is the space reserved in tcb for abnormal interrupts. Using this address to save data will not affect the normal operation of the program.

[0029] 4. In the process of entering or exiting a high-priority interrupt from a low-priority interrupt, sp at this time points to the address space where the nested interrupt context is saved (related to the operating system design), and sp-4 points to an unused address in the nested interrupt context save space. Using this address to save data will not affect the normal operation of the program. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the main data structures in the memory and CPU when a task or interrupt handler is running;

[0031] Figure 2 This is a schematic diagram of the main data structures in the memory and CPU during the interrupt context protection phase;

[0032] Figure 3It is a schematic diagram of the abnormal context protection and recovery process. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments disclosed in the present invention will be further described in detail below with reference to the accompanying drawings.

[0034] One of the core ideas of the present invention is: a RISC-V processor exception context protection and recovery method for a satellite operating system is disclosed, in which an exception handler stack is reserved in the operating system, and the stack is independent of the task stack and the interrupt stack; an exception handling buffer is designed in the task context data structure, and the starting address of the exception handling buffer is located at the lowest address of the context data structure, and the length is 4 bytes. When the task or interrupt handler is running, the main data structures in the memory and the CPU are as follows Figure 1 As shown, the main data structures in the interrupt context protection phase memory and CPU are as follows Figure 2 shown.

[0035] In this embodiment, the RISC V processor exception context protection and recovery method for the onboard operating system includes:

[0036] Step 1: reserve an exception handler stack in the operating system for use by the exception handler.

[0037] A stack is a data structure used to store information such as function calls and local variables during the execution of a computer program. Typical embedded operating systems such as VxWorks have designed separate stacks for tasks running in the system, such as system stacks, interrupt stacks, task stacks, etc. These stacks are initialized when the operating system is started and tasks are created. In this embodiment, a separate exception handler stack is designed, which is independent of the task stack and interrupt stack and is used by the exception handler. The stack bottom of the exception handler stack is set when the operating system is started, and the stack data of the exception handler stack is set to 0.

[0038] Step 2, design an exception handling buffer in the task context data structure. The starting address of the exception handling buffer is located at the lowest address of the context data structure and has a length of 4 bytes.

[0039] Task context is the data stored in the memory for saving the running state when the operating system is interrupted and the task is switched. The task context data structure generally includes the integer and floating point register values ​​in the CPU and the CPU status register value. In the present embodiment, an exception handling buffer is designed in the task context data structure, and the starting address is located at the lowest address of the context data structure, and the length is 4 bytes. When the task context is initialized, the exception handling buffer is first filled with 0. When the processor detects an exception (such as "instruction access error exception", "illegal instruction exception", etc.), the CPU automatically jumps to the exception handling program, and the exception handling program saves the value of the general register t0 in this buffer to prevent the exception handling program from being interrupted by other exceptions again.

[0040] Step 3: When the processor detects an exception (such as "instruction access error exception", "illegal instruction exception", etc.), the exception handler is called to save the context.

[0041] like Figure 1 As shown, if an exception occurs in the CPU in a task or interrupt handler, before step S3.1 starts, the register sp in the CPU points to the bottom of the task stack or interrupt stack, and sp-4 points to the unused part of the task stack or interrupt stack, ensuring that the operation of step S3.1 does not overwrite other data.

[0042] like Figure 2 As shown, if an exception occurs in the CPU during the interrupt context protection phase, before step S3.1 starts, the register sp in the CPU points to the task context, and sp-4 points to the exception handling buffer, ensuring that the operation of step S3.1 also does not overwrite other data.

[0043] In this embodiment, if Figure 3 As shown, when the processor detects an exception, the exception handler is called to automatically start executing the following process:

[0044] S3.1, save the value of register t0 to the space pointed to by address sp-4, where sp represents the value of register sp.

[0045] The processor and operating system mechanisms ensure that: if the processor is in a task or interrupt service routine before entering the exception, sp-4 points to the unused part of the task stack or interrupt stack; if the processor is in the context protection process before entering the exception, sp-4 points to the exception handling buffer.

[0046] S3.2, assign register t0 to the bottom of the exception handler stack, and save the value sp of register sp to the address space pointed to by register t0. Register sp and register t0 are general registers in the RISCV architecture.

[0047] S3.3, register t0 is assigned the context size, and the value of register sp is decremented by t0. Wherein, t0 represents the value of register t0.

[0048] S3.4, save the complete context content to the address space pointed to by register sp.

[0049] S3.5, the program jumps to the user handler to fix the exception.

[0050] Step 4: After the user handler is executed, the operating system starts to execute the following exit process to exit from the exception handler:

[0051] S4.1, restore the context of the address space pointed to by register sp to the processor.

[0052] S4.2, register t0 is assigned the context size, and the value of register sp is incremented by t0.

[0053] S4.3, assign register t0 to the bottom of the exception handler stack, and restore the value of register sp from the address pointed to by register t0.

[0054] S4.4, restore the value of register t0 from the space pointed to by the sp-4 address.

[0055] The processor and operating system mechanisms ensure that: if the processor is in a task or interrupt service routine before entering the exception, sp-4 points to the unused part of the task stack or interrupt stack; if the processor is in the context protection process before entering the exception, the sp-4 address points to the exception handling buffer.

[0056] In summary, the present invention discloses a RISCV processor exception context protection and recovery method for a satellite operating system, and designs an exception handling program. No matter the exception occurs in a task, an interrupt handling program, or in the interrupt context protection or recovery process, the context can be effectively protected and restored, thereby solving the problem that processor exceptions cannot be shielded under the RISCV architecture.

[0057] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

[0058] The contents not described in detail in the specification of the present invention belong to the common knowledge of the professionals in this field.

Claims

1. A RISCV processor abnormal context protection and recovery method for a satellite-based operating system, characterized in that: include: When the processor detects an exception, it calls the exception handler to execute the following process: Save the value of register t0 to the space pointed to by address sp-4; where sp represents the value of register sp; Assign register t0 to the bottom of the exception handler stack, and save the value of register sp to the address space pointed to by register t0; Assign register t0 to the context size, and decrement the value of register sp by t0; where t0 represents the value of register t0; Save the complete context content to the address space pointed to by register sp; The program jumps to the user handler to fix the exception.

2. The RISCV processor abnormal context protection and recovery method for a satellite-based operating system according to claim 1, characterized in that: Also includes: When the user handler is finished executing, the operating system starts executing the exit process to exit from the exception handler.

3. The RISCV processor abnormal context protection and recovery method for a satellite-based operating system according to claim 2, characterized in that: The exit process is as follows: Restore the context of the address space pointed to by register sp to the processor; Assign register t0 to the context size, and increment register sp by t0. Assign register t0 to the bottom of the exception handler stack, and restore the value of register sp from the address pointed to by register t0; Restore the value of register t0 from the space pointed to by the sp-4 address.

4. The RISCV processor abnormal context protection and recovery method for a satellite-based operating system according to claim 1, characterized in that: Also includes: An exception handler stack is reserved in the operating system for use by the exception handler; wherein the exception handler stack is independent of the task stack and the interrupt stack.

5. The RISCV processor abnormal context protection and recovery method for a satellite-based operating system according to claim 4, characterized in that: When the operating system starts, the bottom of the exception handler stack is set, and the data in the exception handler stack is set to 0.

6. The RISCV processor abnormal context protection and recovery method for a satellite-based operating system according to claim 1, characterized in that: Also includes: An exception handling buffer is designed in the task context data structure. The starting address of the exception handling buffer is the lowest address of the context data structure and the length is 4 bytes.

7. The RISCV processor abnormal context protection and recovery method for a satellite-based operating system according to claim 6, characterized in that: Also includes: When the task context is initialized, the exception handling buffer is first filled with 0; when the processor detects an exception, the CPU automatically jumps to the exception handler, and the exception handler saves the general register t0 to the exception handling buffer to prevent the exception handler from being interrupted by other exceptions again.

8. The RISCV processor exception context protection and recovery method for a satellite-based operating system according to claim 1, characterized in that: Exceptions include: instruction access error exception and illegal instruction exception.

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