Semiconductor structure, semiconductor device and memory system

Abstract

The invention provides a semiconductor structure, a semiconductor device and a memory system, the semiconductor structure comprises a transistor, the transistor comprises a semiconductor layer and a grid electrode, and the grid electrode is located on at least one side of the semiconductor layer; the semiconductor layer comprises a channel region, a source region and a drain region, and the source region and the drain region are located at the two ends of the channel region in the first direction; each of the source region and the drain region comprises a first doped region and a second doped region; at least one of the source region and the drain region further comprises a third doped region, and the third doped region is adjacent to the channel region; and the doping concentrations of the first doped region, the second doped region and the third doped region are gradually reduced. The semiconductor structure, the semiconductor device and the memory system provided by the invention can reduce the floating gate effect.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor structure, a semiconductor device and a memory system. Background Art

[0002] With the industry's demand for miniaturization of semiconductor devices, ring-gate vertical gate transistors have developed rapidly. However, the gate induced drain leakage (GIDL) of this type of transistor is large, which can easily lead to a floating gate effect, thereby causing charge loss in the storage node. Summary of the invention

[0003] In view of this, the present application provides a semiconductor structure, a semiconductor device and a memory system that can solve the above-mentioned technical problems.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] The present application provides a semiconductor structure, which includes a transistor, and the transistor includes a semiconductor layer and a gate, and the gate is located on at least one side of the semiconductor layer; wherein the semiconductor layer includes a channel region, a source region and a drain region, and the source region and the drain region are located at both ends of the channel region in a first direction; the source region and the drain region both include a first doping region and a second doping region; at least one of the source region and the drain region also includes a third doping region, and the third doping region is adjacent to the channel region; and the doping concentrations of the first doping region, the second doping region and the third doping region gradually decrease.

[0006] In some embodiments, an orthographic projection of the gate on the semiconductor layer falls within the channel region and outside the second doped region.

[0007] In some embodiments, an orthographic projection of the gate on the semiconductor layer falls outside the third doped region.

[0008] In some embodiments, an orthographic projection of the gate on the semiconductor layer falls within the third doped region.

[0009] In some embodiments, the first doping region and the second doping region have the same doping type.

[0010] In some embodiments, a doping type of the third doping region is the same as or different from a doping type of the first doping region and a doping type of the second doping region.

[0011] In some embodiments, the second doping region is located between the third doping region and the first doping region.

[0012] In some embodiments, a doping concentration of the third doping region is greater than 0 and greater than a doping concentration of the channel region.

[0013] In some embodiments, the doping concentration of the third doping region is greater than or equal to 5E15 atom / cm 3 and less than or equal to 1E17 atom / cm 3 .

[0014] In some embodiments, a thickness of the third doping region in the first direction is greater than or equal to 5 nm and less than or equal to 20 nm.

[0015] In some embodiments, the transistor is at least one of a single-gate transistor, a double-gate transistor, a half-surrounding gate transistor, and a ring-gate transistor.

[0016] In some embodiments, the doping type of the third doping region is N-type or P-type doping.

[0017] In some embodiments, a difference in doping concentration between the third doping region and the channel region is smaller than a difference in doping concentration between the second doping region and the third doping region.

[0018] In some embodiments, the semiconductor structure further includes a bit line extending along a second direction perpendicular to the first direction and connected to the drain region of at least one of the transistors.

[0019] In some embodiments, the transistor further includes a bit line connected to the drain region.

[0020] The present application also provides a semiconductor device, comprising: a capacitor structure; and the semiconductor structure as described above; wherein the capacitor structure is connected to a source region of the transistor of the semiconductor structure.

[0021] In some embodiments, the semiconductor device further includes: an insulating layer, wherein the transistor is located in the insulating layer; wherein the gate of each of the transistors is separated from the channel layer by the insulating layer.

[0022] In some embodiments, there are multiple transistors, one capacitor structure is connected to one transistor, and one bit line of the semiconductor structure is connected to multiple transistors; the gates of two adjacent transistors that are relatively located are separated by the insulating layer.

[0023] The present application also provides a memory system, comprising: the semiconductor device as described above; and a controller configured to control the semiconductor device.

[0024] The semiconductor structure, semiconductor device and memory system provided by the present application are provided with a third doping region adjacent to the channel region in at least one of the source region and the drain region of the semiconductor layer of the transistor, and the doping concentration of the first doping region, the second doping region and the third doping region of at least one of the source region and the drain region is gradually reduced. Since the gate and the channel layer are located opposite to each other and the third doping region is provided between the channel region and the second doping region, the distance between the second doping region (lightly doped drain) and the channel layer becomes farther, and there is no overlap between the gate and the second doping region (lightly doped drain), so the gate induced drain leakage current of the transistor becomes smaller, thereby reducing the floating gate effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 A top view of some components of a semiconductor device provided in some embodiments of the present application.

[0027] Figure 2 For along Figure 1 The cross-sectional view of II-II is shown.

[0028] Figure 3 A cross-sectional view of a semiconductor device is provided for applying for other embodiments.

[0029] Figure 4 A cross-sectional view of a semiconductor device is provided for applying for some further embodiments.

[0030] Figure 5 A cross-sectional view of a semiconductor device is provided for applying for some further embodiments.

[0031] Figure 6 for Figure 1 A three-dimensional schematic diagram of the semiconductor device shown.

[0032] Figure 7 A module diagram of a memory system provided for some embodiments of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0034] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0035] In the description of the present application, it is to be understood that the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is less than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.

[0036] The present application may repeat reference numerals and / or reference letters in different implementations. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0037] The present application aims at the problem that the gate induced drain leakage current (GIDL) of the ring-gate vertical gate transistor is large, which may lead to the floating gate effect technical problem. By setting a third doping region adjacent to the channel region in at least one of the source region and the drain region of the semiconductor layer of the transistor, and gradually reducing the doping concentration of the first doping region, the second doping region and the third doping region of at least one of the source region and the drain region. Since the gate and the channel layer are located opposite to each other and the third doping region is set between the channel region and the second doping region, the second doping region (lightly doped drain) is farther away from the channel layer, and there is no overlap between the gate and the second doping region (lightly doped drain), so the gate induced drain leakage current of the transistor becomes smaller, thereby reducing the floating gate effect.

[0038] See also Figures 1 to 6 Some embodiments of the present application provide a semiconductor device 100 , wherein the semiconductor device 100 includes a semiconductor structure 110 and a capacitor structure 120 , wherein the capacitor structure 120 is connected to the semiconductor structure 110 .

[0039] See also Figure 1 and Figure 2 The semiconductor structure 110 includes a transistor 101, and the transistor 101 includes a semiconductor layer 10 and a gate 20, and the gate 20 is located on at least one side of the semiconductor layer 10. The semiconductor layer 10 includes a channel region 11, a source region 12, and a drain region 13, and the source region 12 and the drain region 13 are located at both ends of the channel region 11 in the first direction Z. The source region 12 and the drain region 13 both include a first doping region 141 and a second doping region 142, and at least one of the source region 12 and the drain region 13 further includes a third doping region 143, and the third doping region 143 is adjacent to the channel region 11, and the doping concentrations of the first doping region 141, the second doping region 142, and the third doping region 143 gradually decrease.

[0040] In some embodiments, the semiconductor layer 10 may include a single semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0041] The first direction Z is the stacking direction of the transistor 101 and the capacitor structure 120 .

[0042] The transistor 101 has a vertical channel (i.e., the channel region 11 extends in the first direction Z), and the source region 12 and the drain region 13 are respectively located at two ends of the vertical channel in the first direction Z. The positions of the source region 12 and the drain region 13 are interchangeable. That is, the source region 12 and the drain region 13 are respectively two ends of the channel region 11 that are arranged opposite to each other in the first direction Z and can be interchanged.

[0043] See also Figure 2 In some embodiments, the source region 12 and the drain region 13 both further include a third doping region 143 .

[0044] See also Figure 3 In some other embodiments, the drain region 13 further includes a third doping region 143 .

[0045] See also Figure 4 In some further embodiments, the source region 12 further includes a third doping region 143 .

[0046] The second doping region 142 is located between the third doping region 143 and the first doping region 141. The second doping region 142 is a lightly doped drain (LDD), that is, the doping concentration of the second doping region 142 is less than the doping concentration of the first doping region 141. The lightly doped drain region is a structure adopted by the device to weaken the drain region electric field to improve the hot carrier effect, that is, a drain region with a low doping concentration is set near the drain region or the source region in the channel region, so that the lightly doped drain region also bears part of the voltage. This structure can prevent the hot carrier effect.

[0047] See also Figures 2 to 5 , the orthographic projection of the gate 20 on the semiconductor layer 10 falls within the channel region 11 and outside the second doping region 142. That is, the orthographic projection of the gate 20 on the semiconductor layer 10 does not overlap with the second doping region 142.

[0048] Specifically, see Figures 2 to 4 In some embodiments, the orthographic projection of the gate 20 on the semiconductor layer 10 falls outside the second doping region 142 and the third doping region 143. That is, the orthographic projection of the gate 20 on the semiconductor layer 10 does not overlap with the second doping region 142 and does not overlap with the third doping region 143.

[0049] Specifically, see Figure 5In some other embodiments, the orthographic projection of the gate 20 on the semiconductor layer 10 falls within the third doping region 143. That is, the orthographic projection of the gate 20 on the semiconductor layer 10 does not overlap with the second doping region 142 and at least partially overlaps with the third doping region 143.

[0050] By setting a third doping region adjacent to the channel region in at least one of the source region and the drain region of the semiconductor layer of the transistor, and gradually reducing the doping concentration of the first doping region and the second doping region and the third doping region of at least one of the source region and the drain region. Since the gate and the channel layer are located opposite to each other and the third doping region is set between the channel region and the second doping region, the distance between the second doping region (lightly doped drain) and the channel layer becomes farther, and there is no overlap between the gate and the second doping region (lightly doped drain), so the gate induced drain leakage current of the transistor becomes smaller, thereby reducing the floating gate effect. In addition, due to the existence of the third doping region and the doping concentration of the third doping region is less than the doping concentration of the second doping region (lightly doped drain), the source / drain electric field of the transistor can easily extend to the bottom of the gate, so it will not affect the on-state current of the transistor.

[0051] In some embodiments, the first doping region 141 and the second doping region 142 have the same doping type. Specifically, the first doping region 141 and the second doping region 142 are N-type doped or P-type doped.

[0052] In some embodiments, the doping type of the third doping region 143 is the same as the doping type of the first doping region 141 and the second doping region 142. Specifically, when the first doping region 141 and the second doping region 142 are N-type doped, the third doping region 143 is N-type doped. When the first doping region 141 and the second doping region 142 are P-type doped, the third doping region 143 is P-type doped.

[0053] In some embodiments, the doping type of the third doping region 143 is different from the doping type of the first doping region 141 and the second doping region 142. Specifically, when the first doping region 141 and the second doping region 142 are N-type doped, the third doping region 143 is P-type doped. When the first doping region 141 and the second doping region 142 are P-type doped, the third doping region 143 is N-type doped.

[0054] In some embodiments, the doping ions of the N-type doping include at least one of the Group V elements, and the doping ions of the P-type doping include at least one of the Group III elements.

[0055] Among them, the doping concentration of the third doping region 143 is greater than 0 and greater than the doping concentration of the channel region 11. That is, the third doping region 143 is a quasi-intrinsic region, that is, the difference between the doping concentrations of the third doping region 143 and the channel region 11 is less than the difference between the doping concentrations of the second doping region 142 and the third doping region 143. That is, the doping concentration of the third doping region 143 is not much different from the doping concentration of the channel region 11.

[0056] The doping concentration of the channel region 11 may be greater than 0 or equal to 0, that is, ion doping may be performed or not performed in the substrate of the channel region 11. Of course, even if ion doping is performed, the doping concentration of the channel region 11 is relatively low.

[0057] Specifically, the doping concentration of the third doping region 143 is greater than or equal to 5E15 atom / cm3 and less than or equal to 1E17 atom / cm 3 . The atom / cm 3 Indicates the number of atoms per cubic centimeter.

[0058] It should be noted that in some specific examples, due to process problems, there may be overlapping regions between the first doping region 141 and the second doping region 142 of at least one of the source region 12 and the drain region 13, and between the second doping region 142 and the third doping region 143. The doping concentration of the overlapping regions is relatively complex and may be different from the above-mentioned doping concentration rule.

[0059] Based on this, for the sake of rigor of expression, the comparison of the doping concentrations of the third doping region 143 of the source region 12 or the drain region 13 with the first doping region 141 or the second doping region 142 or the channel region 11 is defined here as a comparison between the maximum doping concentrations.

[0060] It should be noted that the maximum concentration here can be understood as the doping concentration expected to be achieved during manufacturing. The situation where the doping concentration is different from the above-mentioned doping concentration rule due to manufacturing differences or special locations of the structure (such as the junction of different doping concentrations) is included in the scope of protection of this application.

[0061] In some embodiments, a thickness of the third doping region 143 in the first direction Z is greater than or equal to 5 nm and less than or equal to 20 nm.

[0062] Specifically, in some embodiments, the gate 20 may be located at one side of the channel region 11. In other embodiments, the gate 20 may also be located at two opposite sides of the channel region 11, or may be disposed around the channel region 11. The specific position may be set according to the actual requirements of the transistor.

[0063] The material of the gate 20 may include metal or polysilicon (Poly).

[0064] In some embodiments, a gate oxide layer is further provided between the gate 20 and the channel region 11, for electrically isolating the channel region 11 and the gate 20. In this embodiment, the gate 20 and the semiconductor layer 10 are both located in the insulating layer 30, and a portion of the insulating layer 30 between the gate 20 and the channel region 11 serves as a gate oxide layer. It can also be understood that: the semiconductor structure 110 further includes an insulating layer 30, and the transistor 101 is located in the insulating layer 30. Specifically, the gate 20 and the semiconductor layer 10 are both located in the insulating layer 30, and the gate 20 and the semiconductor layer 10 are separated by a portion of the insulating layer 30.

[0065] It can be understood that the gate oxide layer in the transistor 101 can be used to induce different electric fields and apply them to the surface of the channel region 11, so that the minority carriers of the substrate (semiconductor layer) are adsorbed to the surface of the channel region 11, accumulated and inverted, so that the gate oxide layer (insulating layer 30) becomes the same as the doping type of the source region 12 and the drain region 13, thereby achieving conduction between the source region 12 and the drain region 13.

[0066] In some embodiments, the gate 20 may also be used as a word line. The gate 20 extends along a third direction Y that is perpendicular to the first direction Z and intersects with the second direction X.

[0067] In some embodiments, after a gate voltage is applied to the gate 20, that is, a strong electric field is generated, the electrons continuously drift along the direction of the electric field and are continuously accelerated, thereby obtaining a large amount of kinetic energy. When the electrons travel from the source region 12 to the drain region 13, due to the existence of a pressure difference, the electrons collide with the gate oxide layer (insulating layer 30) and are injected into the gate oxide layer (insulating layer 30), thereby generating a hot carrier effect. The hot carrier effect has a significant impact on the reliability of the transistor 101.

[0068] In this embodiment, the material of the insulating layer 30 may include but is not limited to silicon oxide.

[0069] Please refer again Figures 1 to 5The semiconductor structure 110 may include a plurality of transistors 101 , and the plurality of transistors 101 are located in the insulating layer 30 and distributed in an array. That is, the plurality of transistors 101 share one insulating layer 30 .

[0070] The transistor 101 is at least one of a single-gate transistor, a double-gate transistor, a half-surrounding gate transistor, and a ring-gate transistor.

[0071] When the transistor 101 is a single-gate transistor, the gate 20 is located on one side of the semiconductor layer 10. One, two, or no gates 20 may be provided between two adjacent transistors 101. When one gate 20 is provided between two adjacent transistors 101, the gate 20 of one transistor 101 is separated from the other adjacent transistor 101 by a portion of the insulating layer 30; when two gates 20 are provided between two adjacent transistors 101, the gate 20 of one transistor 101 is separated from the gate 20 of the other adjacent transistor 101 by a portion of the insulating layer 30. When no gate 20 is provided between two adjacent transistors 101, the semiconductor layer 10 of one transistor 101 is separated from the semiconductor layer 10 of the other transistor 101 by a portion of the insulating layer 30.

[0072] When the transistor 101 is a dual-gate transistor, the gates 20 are located on opposite sides of the semiconductor layer 10 in a second direction X perpendicular to the first direction Z. A gate 20 of one transistor 101 is separated from a gate 20 of another adjacent transistor 101 by a portion of the insulating layer 30 .

[0073] When the transistor 101 is a semi-surrounding gate transistor or a ring gate transistor, the gate 20 surrounds at least a portion of the semiconductor layer 10. A gate 20 of one transistor 101 is separated from a gate 20 of another adjacent transistor 101 by a portion of the insulating layer 30.

[0074] The capacitor structure 120 is connected to the source region 12 of the transistor 101 of the semiconductor structure 110. Specifically, the capacitor structure 120 is connected to the first doped region 141 of the source region 12. Specifically, the capacitor structure 120 is connected to the first doped region 141 of the source region 12 through a connection pad 121.

[0075] In some embodiments, the capacitor structure 120 may have various structures.

[0076] Exemplarily, the capacitor structure 120 may include a cup-shaped capacitor, a cylindrical capacitor, or a pillar-shaped capacitor, wherein the cup-shaped capacitor, the cylindrical capacitor, or the pillar-shaped capacitor all include a bottom electrode, a top electrode, and a dielectric layer located between the bottom electrode and the top electrode.

[0077] It should be noted that the bottom electrode is connected to the source region 12 of the transistor 101 of the semiconductor structure 110 , the top electrode of the cup-shaped capacitor CUP is grounded, and the cup-shaped capacitor CUP is used to store written data.

[0078] It should be noted that, when the areas of the bottom electrodes of the cup-shaped capacitor, the cylindrical capacitor, and the pillar-shaped capacitor are equal, the area of ​​the top electrode of the cylindrical capacitor is the largest, followed by the areas of the top electrodes of the cylindrical capacitor and the pillar-shaped capacitor. Based on this, in some embodiments, a cylindrical capacitor can be used as a storage unit of a memory, which is conducive to extremely high memory integration.

[0079] Please refer again Figures 1 to 6 The semiconductor device 100 further includes a bit line 130 , and the bit line 130 is connected to the drain region 13 of the transistor 101 of the semiconductor structure 110 . Specifically, the bit line 130 is connected to the first doped region 141 of the drain region 13 .

[0080] The bit line 130 extends along the second direction X.

[0081] In some embodiments, one capacitor structure 120 is connected to one transistor 101 , and one bit line 130 is connected to a plurality of transistors 101 .

[0082] In some embodiments, in the first direction Z, the capacitor structure 120 and the bit line 130 are respectively located at two ends of the insulating layer 30 .

[0083] Please continue reading Figure 1 and Figure 2 In some embodiments, the semiconductor device 100 includes a plurality of semiconductor groups 102, each of the semiconductor groups 102 includes at least two transistors 101; the distance from the midpoint of the distance between two adjacent semiconductor groups 102 in the second direction X to the midpoint of the distance between two adjacent capacitor structures 120 in one of the semiconductor groups 102 can reach 2F 2 The distance between the midlines of two adjacent bit lines 130 along the second direction X can reach 2F. 2 That is to say, the size of the semiconductor device provided by the present application is smaller than that of the 4F 2The midline of the bit line 130 along the second direction X refers to the center line of a bit line 130 along its extending direction.

[0084] See also Figure 6 The present application also provides a memory system 1000 , which includes one or more semiconductor devices 100 as described above and a controller 200 , wherein the controller 200 is connected to the semiconductor device 100 , and the controller 200 is configured to control the semiconductor device 100 .

[0085] The memory system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The controller may be configured to control operations of the semiconductor device, such as read, erase, and program operations.

[0086] In some embodiments, the controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0087] In some embodiments, the controller is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0088] The semiconductor structure, semiconductor device and memory system provided by the present application are provided with a third doping region adjacent to the channel region in at least one of the source region and the drain region of the semiconductor layer of the transistor, and the doping concentration of the first doping region, the second doping region and the third doping region of at least one of the source region and the drain region is gradually reduced. Since the gate and the channel layer are located opposite to each other and the third doping region is provided between the channel region and the second doping region, the distance between the second doping region (lightly doped drain) and the channel layer becomes farther, and there is no overlap between the gate and the second doping region (lightly doped drain), so the gate induced drain leakage current of the transistor becomes smaller, thereby reducing the floating gate effect.

[0089] In addition, since the doping concentration of the third doping region is lower than the doping concentration of the second doping region (lightly doped drain), the source / drain electric field of the transistor can easily extend to below the gate, thus not affecting the on-state current of the transistor.

[0090] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure includes a transistor, the transistor includes a semiconductor layer and a gate, and the gate is located on at least one side of the semiconductor layer; Wherein, the semiconductor layer includes a channel region, a source region and a drain region, and the source region and the drain region are located at two ends of the channel region in a first direction; The source region and the drain region both include a first doping region and a second doping region; At least one of the source region and the drain region further includes a third doped region, and the third doped region is adjacent to the channel region; and The doping concentrations of the first doping region, the second doping region and the third doping region gradually decrease.

2. The semiconductor structure according to claim 1, wherein: An orthographic projection of the gate on the semiconductor layer falls within the channel region and outside the second doping region.

3. The semiconductor structure according to claim 2, wherein: An orthographic projection of the gate on the semiconductor layer falls outside the third doping region.

4. The semiconductor structure according to claim 2, wherein: An orthographic projection of the gate on the semiconductor layer falls within the third doping region.

5. The semiconductor structure according to claim 1, wherein: The first doping region and the second doping region have the same doping type.

6. The semiconductor structure according to claim 5, characterized in that The doping type of the third doping region is the same as or different from the doping type of the first doping region and the second doping region.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The second doping region is located between the third doping region and the first doping region.

8. The semiconductor structure according to claim 1, wherein: The doping concentration of the third doping region is greater than 0 and greater than the doping concentration of the channel region.

9. The semiconductor structure according to claim 8, characterized in that The doping concentration of the third doping region is greater than or equal to 5E15 atom / cm 3 and less than or equal to 1E17 atom / cm 3 .

10. The semiconductor structure according to claim 1, wherein: The thickness of the third doping region in the first direction is greater than or equal to 5 nm and less than or equal to 20 nm.

11. The semiconductor structure according to any one of claims 1 to 6 and 8 to 10, characterized in that: The transistor is at least one of a single-gate transistor, a double-gate transistor, a half-surrounding gate transistor, and a ring-gate transistor.

12. The semiconductor structure according to claim 5, wherein: The doping type of the third doping region is N-type or P-type doping.

13. The semiconductor structure according to any one of claims 8 to 10, characterized in that: A difference in doping concentration between the third doping region and the channel region is smaller than a difference in doping concentration between the second doping region and the third doping region.

14. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a bit line extending along a second direction perpendicular to the first direction and connected to the drain region of at least one of the transistors.

15. A semiconductor device, characterized in that: include: Capacitor structure; and The semiconductor structure according to any one of claims 1 to 14; Wherein, the capacitor structure is connected to the source region of the transistor of the semiconductor structure.

16. The semiconductor device according to claim 15, wherein: The semiconductor device further comprises: an insulating layer, wherein the transistor is located in the insulating layer; The gate electrode and the channel layer of each transistor are separated by the insulating layer.

17. The semiconductor device according to claim 16, wherein: There are multiple transistors, one capacitor structure is connected to one transistor, and one bit line of the semiconductor structure is connected to multiple transistors; The gates of two adjacent transistors that are opposite to each other are separated by the insulating layer.

18. A memory system, characterized in that: include: At least one semiconductor device according to any one of claims 15 to 17; and A controller is configured to control the semiconductor device.

Images