Protection circuit, chip and electronic equipment

Abstract

The invention discloses a protection circuit, a chip and electronic equipment, and belongs to the technical field of integrated circuits, the protection circuit comprises an equipotential line group, a control module and a detection module; the equipotential line group is located on a shielding layer of the target chip; the equipotential line group covers a protected area; the control module is located in the protected area and is arranged on the wiring layer below the shielding layer; the equipotential line group comprises a plurality of equipotential lines; the input end of the equipotential line receives a first detection signal; the equipotential lines are disconnected at the reconfiguration node and are electrically connected with the control module respectively; the control module is used for randomly controlling a routing path at the reconstruction node, and the routing path is located in a protected area, is arranged on a routing layer and comprises a plurality of equipotential line cross routing and / or independent routing; the detection module is used for outputting an alarm signal under the condition that the target chip is attacked, and the second detection signal is a detection signal output to the detection module by the equipotential line. The attack difficulty of the protection circuit can be improved, so that the protection effect is improved.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, and specifically relates to a protection circuit, a chip and an electronic device. Background Art

[0002] Currently, invasive attacks on chips are also called physical attacks, which can cause data loss in the chip.

[0003] In the related art, a shielding layer can be added to the top layer of the chip, the shielding layer includes a shielding wire, and the shielding wire is connected to the detection circuit to form a protection circuit. When the shielding wire of the shielding layer is detected or cut off, the detection circuit can send an alarm signal when it detects that the signal transmitted on the shielding wire changes, and the main control unit of the chip can take protective measures according to the alarm signal.

[0004] However, the existing shielding wires mainly adopt parallel equipotential lines, spiral lines and other graphic topological structures. The shielding wires of these structures are mostly single-shaped symmetrical or repeated, and the shielding wire is a complete line. If the first and last ends of the shielding wire, i.e. the input and output ends, are short-circuited, the entire shielding wire will lose its protective function, and the chip area covered by the short-circuited shielding wire is easy to be randomly detected and lose important data. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a protection circuit, a chip and an electronic device, which can solve the problem that the existing protection circuit has low attack difficulty and poor protection effect.

[0006] In a first aspect, an embodiment of the present application provides a protection circuit, the protection circuit comprising: an equipotential line group, a control module, and a detection module;

[0007] The equipotential line group is located in the shielding layer of the target chip; the equipotential line group covers the protected area of ​​the target chip; the control module is located in the protected area and is arranged in the routing layer under the shielding layer;

[0008] The equipotential line group includes a plurality of equipotential lines; the output end of the equipotential line is electrically connected to the detection module; the input end of the equipotential line is used to receive a first detection signal;

[0009] The equipotential line includes a reconstruction node; the equipotential line is disconnected at the reconstruction node, and two ends of the disconnected equipotential line are electrically connected to the control module respectively;

[0010] The control module is used to randomly control the routing path of the equipotential line at the reconstruction node; wherein the routing path is located in the protected area and is arranged in the routing layer; the routing path includes a plurality of cross routings of the equipotential lines, and / or independent routings of the equipotential lines;

[0011] The detection module is used to receive the first detection signal, compare the first detection signal with the second detection signal, and output an alarm signal when the comparison result indicates that the target chip is attacked; wherein the second detection signal is the detection signal output by the equipotential line to the detection module.

[0012] Optionally, at the reconstruction node, the equipotential line includes a first end and a second end;

[0013] The first end is connected to the wiring layer through a first through hole of the shielding layer, and is electrically connected to the control module through a first wiring of the wiring layer;

[0014] The second end is connected to the wiring layer through the second through hole of the shielding layer, and is electrically connected to the control module through the second wiring of the wiring layer.

[0015] Optionally, the routing layer is a metal layer of the protected area; the first routing line and the second routing line are metal routing lines of the metal layer.

[0016] Optionally, the equipotential line group includes a first equipotential line and a second equipotential line; the first equipotential line and the second equipotential line are two adjacent equipotential lines in the equipotential line group;

[0017] The output end of the first equipotential line and the output end of the second equipotential line are electrically connected to the detection module respectively; the first equipotential line and the second equipotential line are respectively used to receive the first detection signal;

[0018] The reconstructed node of the first equipotential line is the first node; the reconstructed node of the second equipotential line is the second node; and the straight-line distance between the first node and the second node is less than a preset distance threshold.

[0019] Optionally, the first node and the second node are located within a target range; and the first equipotential line and the second equipotential line in the target range are arranged in parallel.

[0020] Optionally, the equipotential lines further include confusion nodes;

[0021] The equipotential lines are disconnected at the confusion nodes, and both ends of the disconnected equipotential lines are connected to the routing layer through the through holes of the shielding layer; and the equipotential lines are restored to connection in the routing layer.

[0022] Optionally, at the confusion node, the equipotential line includes a third end and a fourth end;

[0023] The third end is connected to the routing layer through a third through hole on the shielding layer; the fourth end is connected to the routing layer through a fourth through hole on the shielding layer; the third end and the fourth end are restored to connection through a third routing of the routing layer;

[0024] Alternatively, the third end and the fourth end are connected to the routing layer through a fifth through hole on the shielding layer, and the connection is restored at the routing layer.

[0025] Optionally, the protection circuit further includes a signal generating module, or the target chip includes the signal generating module;

[0026] The signal generating module is electrically connected to the input end of the equipotential line and the detecting module respectively, and is used to send the first detecting signal to the equipotential line and the detecting module respectively.

[0027] Optionally, the signal generating module is also electrically connected to the control module, and is used to generate a random control signal, and send the random control signal to the control module; wherein the random control signal is used to instruct the control module to perform random control on the routing path.

[0028] Optionally, the signal generating module is a random number generator, or a physically unclonable function circuit.

[0029] Optionally, the signal generating module is located in the protected area;

[0030] The input end of the equipotential line is electrically connected to the signal generating module through the through hole of the shielding layer.

[0031] Optionally, the detection module is located in the protected area;

[0032] The output end of the equipotential line is electrically connected to the detection module through the through hole of the shielding layer.

[0033] Optionally, the shielding layer adopts a Hamiltonian circuit structure;

[0034] The equipotential line group is composed of equipotential lines in the Hamiltonian circuit structure.

[0035] In a second aspect, an embodiment of the present application provides a chip, wherein the chip includes the protection circuit as described in the first aspect.

[0036] In a third aspect, an embodiment of the present application provides an electronic device, wherein the electronic device comprises the chip as described in the second aspect.

[0037] A protection circuit, chip and electronic device provided in the embodiments of the present application have at least the following advantages: the protection circuit includes an equipotential line group, a control module, and a detection module; the equipotential line group is located in the shielding layer of the target chip; the equipotential line group covers the protected area of ​​the target chip; the control module is located in the protected area and is arranged in the routing layer under the shielding layer; the equipotential line group includes a plurality of equipotential lines; the output end of the equipotential line is electrically connected to the detection module; the input end of the equipotential line is used to receive a first detection signal; the equipotential line includes a reconstruction node; the equipotential line is disconnected at the reconstruction node, and the two ends of the disconnected equipotential line are respectively electrically connected to the control module. The control module is used to randomly control the routing path of the equipotential line at the reconstruction node; wherein the routing path is located in the protected area and is arranged in the routing layer; the routing path includes a plurality of equipotential line cross routings, and / or the equipotential lines are independently routed; the detection module is used to receive the first detection signal, compare the first detection signal with the second detection signal, and output an alarm signal when the comparison result indicates that the target chip is attacked; wherein the second detection signal is the detection signal output by the equipotential line to the detection module. In this way, the control module and the routing path of the reconstruction node are shielded and protected by the equipotential line group, and the attacker cannot easily distinguish the beginning, end and disconnected end of the equipotential line from the perspective of the attacker, making it difficult to directly short-circuit the input and output ends of the equipotential line to perform a rewiring attack, which can increase the difficulty of attacking the protection circuit. The control module randomly controls the routing path of the equipotential line at the reconstruction node, so that the routing path of the equipotential line can be random. The detection module compares the first detection signal of the input equipotential line with the second detection signal output by the equipotential line, and can continuously detect whether the equipotential line is attacked. When attacked, it outputs an alarm signal, which can improve the protection effect of the protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the topological structure of parallel equipotential lines of a shielding layer in the related art;

[0039] Figure 2 It is a schematic diagram of the topological structure of other common shielding layers in related technologies;

[0040] Figure 3 is a circuit structure diagram of a protection circuit provided in an embodiment of the present application;

[0041] Figure 4 is a structural schematic diagram of an equipotential line group provided in an embodiment of the present application;

[0042] Figure 5 This is a schematic diagram of a wiring path of a reconstruction node provided in an embodiment of the present application;

[0043] Figure 6 This is a schematic diagram of a routing path of an obfuscated node provided in an embodiment of the present application;

[0044] Figure 7 is a circuit structure diagram of another protection circuit provided in an embodiment of the present application;

[0045] Figure 8 This is a schematic diagram of a shielding layer topology structure provided in an embodiment of the present application;

[0046] Fig. 9 This is a schematic diagram of another shielding layer topology structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0048] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or at least two. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0049] First, the background technology involved in the embodiments of the present application is described.

[0050] In the field of integrated circuits, with the development of microelectronics technology, information security technology and deep submicron process technology, chip security technology continues to improve. For example, integrated circuit cards (IC cards), also known as smart cards, are widely used in communications, transportation, retail and other fields.

[0051] At present, the main attack methods for chips include non-invasive attacks, semi-invasive attacks and invasive attacks (also called physical attacks). In related technologies, an active shielding layer is generally added to the top layer of the chip to prevent invasive physical detection and tampering attacks. Specifically, the active shielding layer includes a detection circuit and a metal shielding wire. When the active shielding wire of the active shielding layer is detected or cut off, the detection circuit of the active shielding layer detects that the signal transmitted on the shielding wire has changed, and immediately generates an alarm signal to inform the main control unit that the chip has been attacked from the outside. The main control unit can take protective measures such as destroying key data and passwords.

[0052] Figure 1 This is a schematic diagram of the topological structure of parallel equipotential lines of a shielding layer in the related technology. Figure 2 This is a schematic diagram of the topological structure of other common shielding layers in related technologies. Figure 2 (a) shows the helical topology, Figure 2 (b) shows the Hilbert curve topology, Figure 2 (c) shows the Peano curve topology. Figure 1 and Figure 2 As shown, the shielding wire topology in the related art is mostly a single symmetrical or repeated graphic, and the shielding wire is a complete line, just arranged in a certain shape. Once the shielding layer is attacked by a probe, the beginning and end of the shielding wire are found, and the beginning and end of the shielding wire are short-circuited, that is, a rewiring attack is performed, then the short-circuited part of the entire shielding wire will lose its protective function, and the protected area of ​​the chip covered by the short-circuited shielding wire will be randomly detected and important data will be lost.

[0053] In the following, in conjunction with the accompanying drawings, a protection circuit 10, a chip and an electronic device provided in an embodiment of the present application are described in detail through specific embodiments and their application scenarios.

[0054] Figure 3 is a circuit structure diagram of a protection circuit 10 provided in an embodiment of the present application, such as Figure 3 As shown, the protection circuit 10 includes: an equipotential line group 101, a control module 102, and a detection module 103;

[0055] The equipotential line group 101 is located in the shielding layer of the target chip; the equipotential line group 101 covers the protected area of ​​the target chip; the control module 102 is located in the protected area and is arranged in the routing layer under the shielding layer;

[0056] The equipotential line group 101 includes a plurality of equipotential lines 1011; the output end of the equipotential line 1011 is electrically connected to the detection module 103; the input end of the equipotential line 1011 is used to receive the first detection signal;

[0057] The equipotential line 1011 includes a reconstruction node 1011a; the equipotential line 1011 is disconnected at the reconstruction node 1011a, and both ends of the disconnected equipotential line 1011 are electrically connected to the control module 102 respectively;

[0058] The control module 102 is used to randomly control the routing path of the equipotential line 1011 at the reconstruction node 1011a; wherein the routing path is located in the protected area and is set in the routing layer, and the routing path includes a plurality of equipotential lines 1011 cross routing, and / or the equipotential lines 1011 are independently routed;

[0059] The detection module 103 is used to receive a first detection signal, compare the first detection signal with a second detection signal, and output an alarm signal when the comparison result indicates that the target chip is attacked; wherein the second detection signal is the detection signal output by the equipotential line 1011 to the detection module 103.

[0060] The protection circuit 10 of the embodiment of the present application can be applied to chips with high requirements for safety, that is, applied to target chips. The top metal layer of the target chip is filled with a shielding layer structure as a shielding layer, and the shielding layer structure is a graphic topological structure composed of multiple shielding lines. The shielding layer of the target chip covers the protected area of ​​the target chip, and the protected area includes all hierarchical structures located in the lower layer of the shielding layer and completely covered by the shielding layer, which can play a protective role in the protected area. The hierarchical structure of the lower layer of the shielding layer includes a metal layer, and the metal layer can be provided with chip circuits, metal wiring, etc., so that the shielding layer can shield and protect the chip circuits, metal wiring, etc. in the protected area of ​​the target chip.

[0061] In the embodiment of the present application, the multiple shielding lines of the shielding layer may include different equipotential lines 1011, and the equipotential lines 1011 are shielding lines with equal electric potential. For the shielding layer of the target chip, the multiple equipotential line groups 101 of the protection circuit 10 can be filled into the top metal layer of the target chip. The graphic topological structure formed by the multiple equipotential line groups 101 is called a shielding line structure. The top metal layer after filling is used as the shielding layer of the target chip, covering the protected area of ​​the target chip, thereby shielding and protecting the protected area of ​​the target chip.

[0062] Alternatively, equipotential lines 1011 are selected from the shielding lines of the target chip shielding layer to form the equipotential line group 101 of the protection circuit 10, that is, the equipotential line group 101 can be composed of multiple equipotential lines 1011 of the target chip shielding layer, and the equipotential lines 1011 of the shielding layer are respectively connected to the control module 102 and the detection module 103 of the protection circuit 10. In addition, the protected area of ​​the target chip is covered by the graphic topological structure of the selected equipotential lines 1011, that is, the equipotential line group 101 of the protection circuit 10 covers the protected area of ​​the target chip, thereby shielding the protected area. This is only an example, and the embodiments of the present application are not limited to this.

[0063] In the embodiment of the present application, the equipotential line group 101 includes a plurality of equipotential lines 1011, and the equipotential lines 1011 in different equipotential line groups 101 may be the same or different. The input end of the equipotential line 1011 is used to receive a first detection signal, the first detection signal is transmitted through the equipotential line 1011, and is output to the detection module 103 at the output end of the equipotential line 1011, and the output detection signal is called a second detection signal.

[0064] In the embodiment of the present application, the control module 102 is set in the protected area of ​​the target chip and can be shielded and protected by the equipotential line group 101 covering the protected area. The control module 102 can be specifically set in the metal layer under the shielding layer, and the equipotential lines 1011 can restore the routing in the lower metal layer, and the lower metal layer is called the routing layer. Among them, the protected area of ​​the target chip includes the area that needs to be protected in the routing layer, and the control module 102 and the routing path of the reconstruction node 1011a can be set in the protected area of ​​the routing layer, so that the equipotential line group 101 can shield and protect the control module 102 and the routing path.

[0065] In the embodiment of the present application, a reconstruction node 1011a is provided on the equipotential line 1011, and at the reconstruction node 1011a, the equipotential line 1011 is disconnected, and the two ends of the disconnected equipotential line 1011 are respectively electrically connected to the control module 102 located in the routing layer. Wherein, the two ends of the disconnected equipotential line 1011 can enter the routing layer in the form of punching, and be electrically connected to the control module 102 of the routing layer, and perform random routing under the control of the control module 102. Wherein, the routing layer can be one or more metal layers, and the embodiment of the present application does not limit this.

[0066] Specifically, at the reconstruction node 1011a, the equipotential line 1011 can restore the original routing, that is, an independent routing, or can be connected with the terminal at the reconstruction node 1011a of other equipotential lines 1011 to perform cross routing. In this way, the routing path of the equipotential line 1011 at the reconstruction node 1011a is random, depending on the random control logic of the control module 102. In addition, the routing path is set at the routing layer, and the attacker can only see the two ends of the disconnected equipotential line 1011 from the perspective, which can be confused with the original head and tail of the equipotential line 1011, thereby increasing the difficulty of shorting the head and tail of the equipotential line 1011 to send a rewiring attack.

[0067] In an embodiment of the present application, the detection module 103 can compare the first detection signal with the second detection signal to obtain a comparison result. If the comparison result is that the second detection signal output by the equipotential line 1011 is consistent with the original first detection signal, it means that the equipotential line 1011 is not attacked. If the comparison result is that the second detection signal is inconsistent with the first detection signal, it indicates that the equipotential line 1011 is attacked, that is, the target chip is attacked. In this case, the detection module 103 can output an alarm signal to the main control unit of the chip, and the main control unit can take protective measures to avoid data leakage, which can improve the security of the target chip.

[0068] The first detection signal may be a digital signal emitted by any digital signal generating source, and may be defined according to actual application scenarios, such as a random number generated by a random number generator. This is only an example, and the present application embodiment does not limit this.

[0069] In an embodiment of the present application, the protection circuit 10 includes: an equipotential line group 101, a control module 102, and a detection module 103; the equipotential line group 101 is located in the shielding layer of the target chip; the equipotential line group 101 covers the protected area of ​​the target chip; the control module 102 is located in the protected area and is arranged in the routing layer under the shielding layer; the equipotential line group 101 includes a plurality of equipotential lines 1011; the output end of the equipotential line 1011 is electrically connected to the detection module 103; the input end of the equipotential line 1011 is used to receive a first detection signal; the equipotential line 1011 includes a reconstruction node 1011a; the equipotential line 1011 is disconnected at the reconstruction node 1011a, and the disconnected equipotential line The two ends of the line 1011 are electrically connected to the control module 102 respectively; the control module 102 is used to randomly control the routing path of the equipotential line 1011 at the reconstruction node 1011a; wherein the routing path is located in the protected area and is set in the routing layer, and the routing path includes multiple equipotential lines 1011 cross-routing, and / or, the equipotential line 1011 is independently routed; the detection module 103 is used to receive a first detection signal, and compare the first detection signal with the second detection signal, and output an alarm signal when the comparison result indicates that the target chip is attacked; wherein the second detection signal is the detection signal output by the equipotential line 1011 to the detection module 103. In this way, the control module 102 and the routing path of the reconstruction node 1011a are shielded and protected by the equipotential line group 101, and the attacker cannot easily distinguish the beginning and end and the disconnected end of the equipotential line 1011 from the perspective, and it is difficult to directly short-circuit the input end and the output end of the equipotential line 1011 to perform a rewiring attack, which can increase the attack difficulty of the protection circuit 10. The control module 102 randomly controls the routing path of the equipotential line 1011 at the reconstruction node 1011a, so that the routing path of the equipotential line 1011 can be random. The detection module 103 compares the first detection signal input to the equipotential line 1011 with the second detection signal output by the equipotential line 1011, and can continuously detect whether the equipotential line 1011 is under attack. When attacked, it outputs an alarm signal, which can improve the protection effect of the protection circuit 10.

[0070] Optionally, at the reconstruction node 1011a, the equipotential line 1011 includes a first end and a second end;

[0071] The first end is connected to the wiring layer through the first through hole of the shielding layer, and is electrically connected to the control module 102 through the first wiring of the wiring layer;

[0072] The second end is connected to the wiring layer through the second through hole of the shielding layer, and is electrically connected to the control module 102 through the second wiring of the wiring layer.

[0073] In the embodiment of the present application, at the reconstruction node 1011a, the two ends of the disconnected equipotential line 1011 are respectively the first end and the second end, and the first end and the second end can enter the routing layer by punching holes, and are electrically connected to the control module 102 through the metal routing of the routing layer. Specifically, the shielding layer is provided with a first through hole at the first end, one end of the first through hole is connected to the first end of the equipotential line 1011, and the other end is connected to one end of the first routing, and the other end of the first routing is electrically connected to the control module 102. The second end is similar, connected to the routing layer through the second through hole of the shielding layer, and electrically connected to the control module 102 through the second routing of the routing layer.

[0074] Optionally, the routing layer is a metal layer of the protected area; the first routing line and the second routing line are metal routing lines of the metal layer.

[0075] In the embodiment of the present application, the routing layer is a metal layer under the target chip shielding layer, and the routing layer is located in the protected area covered by the equipotential line group 101. The routing layer may include multiple metal routing lines, such as a first routing line and a second routing line.

[0076] In some embodiments, the control module 102 may be a multiplex switch circuit, including a plurality of connection terminals, and the first end and the second end of the equipotential line 1011 may be respectively connected to the connection terminals of the multiplex switch. In this way, the control module 102 may randomly control the equipotential line 1011 to restore the connection through the switch switching, such as the equipotential line 1011 being routed independently, or the first end of one equipotential line 1011 being connected to the second end of another equipotential line 1011, that is, multiple equipotential lines 1011 being routed crosswise. This is only an example, and the embodiments of the present application are not limited to this.

[0077] In the embodiment of the present application, since the equipotential line group 101 covers the protected area of ​​the target chip, the routing layer under the shielding layer is the metal layer of the protected area, and the first routing line and the second routing line are metal routing lines of the metal layer, the equipotential line group 101 can cover the routing layer, thereby shielding and protecting the control module 102 and the metal routing lines in the routing layer.

[0078] In the embodiment of the present application, at the reconstruction node 1011a, the first end and the second end of the equipotential line 1011 are connected to the routing layer through the first through hole and the second through hole of the shielding layer, respectively, and are electrically connected to the control module 102 located in the routing layer through the first routing line and the second routing line, respectively. In this way, the attacker can only see the through hole of the shielding layer from the perspective, and cannot see the routing path of the routing layer under the shielding layer, making it difficult to predict the routing path of the equipotential line 1011 at the reconstruction node 1011a. Therefore, the difficulty of short-circuiting the head and tail ends of the equipotential line 1011 can be increased, and the difficulty of the rewiring attack can be increased.

[0079] In some embodiments, the routing paths of the multiple equipotential lines 1011 in the equipotential line group 101 may include multiple forms, for example, a number of equipotential lines 1011 are independently routed while other equipotential lines 1011 are cross-routed, or all equipotential lines 1011 are cross-routed. Among them, the routing path of the cross-routed lines of multiple equipotential lines 1011 may be that one equipotential line 1011 crosses the routing of multiple other equipotential lines 1011, or that multiple equipotential lines 1011 cross the routing of multiple equipotential lines 1011. This is only an example, and the embodiments of the present application are not limited to this.

[0080] Optionally, the equipotential line group 101 includes a first equipotential line and a second equipotential line; the first equipotential line and the second equipotential line are two adjacent equipotential lines 1011 in the equipotential line group 101;

[0081] The output end of the first equipotential line and the output end of the second equipotential line are electrically connected to the detection module 103 respectively; the first equipotential line and the second equipotential line are used to receive the first detection signal respectively;

[0082] The reconstructed node 1011a of the first equipotential line is the first node; the reconstructed node 1011a of the second equipotential line is the second node; and the straight-line distance between the first node and the second node is less than a preset distance threshold.

[0083] The following description will be made by taking the first equipotential line and the second equipotential line as two adjacent equipotential lines 1011 in the equipotential line group 101 as an example.

[0084] In an embodiment of the present application, the input end of the first equipotential line and the input end of the second equipotential line respectively receive the first detection signal, the output end of the first equipotential line and the output end of the second equipotential line are respectively electrically connected to the detection module 103, and the first equipotential line and the second equipotential line respectively output the second detection signal to the detection module 103, so that the detection module 103 can detect whether the target chip is attacked based on the second detection signal and the first detection signal.

[0085] Specifically, at the first node, the first equipotential line is disconnected, and both ends of the disconnected first equipotential line are electrically connected to the control module 102 respectively; and at the second node, the second equipotential line is disconnected, and both ends of the disconnected second equipotential line are electrically connected to the control module 102 respectively.

[0086] In the embodiment of the present application, for the adjacent first equipotential line and the second equipotential line in the equipotential line group 101, reconstruction nodes 1011a can be respectively set at positions close to each other, which can shorten the routing distance of the first equipotential line and the second equipotential line in the routing layer, thereby reducing the resource occupation of the routing layer. Specifically, the straight-line distance between the first node of the first equipotential line and the second node of the second equipotential line is less than a preset distance threshold. Among them, the preset distance threshold can be defined according to the actual application scenario, and the embodiment of the present application does not limit this.

[0087] Figure 4 is a schematic diagram of the structure of an equipotential line group 101 provided in an embodiment of the present application, such as Figure 4 As shown, in the graph formed by two adjacent equipotential lines 1011, there are line segments that are parallel to each other and perpendicular to each other. Reconstruction nodes 1011a can be set by punching holes in two parallel line segments or perpendicular line segments that are close to each other.

[0088] Optionally, the first node and the second node are located within a target range; and the first equipotential line and the second equipotential line in the target range are arranged in parallel.

[0089] In the embodiment of the present application, the reconstruction node 1011a may be set within a preset target range, wherein the target range may be a range where the first equipotential line and the second equipotential line are parallel. Figure 4 The range shown in the dotted box is the target range, and two adjacent equipotential lines 1011 in the target range are arranged parallel to each other.

[0090] Figure 5 is a schematic diagram of a wiring path of a reconstruction node 1011a provided in an embodiment of the present application, Figure 5 Two adjacent first equipotential lines and second equipotential lines in the equipotential line group 101 are shown. The first equipotential line and the second equipotential line are arranged in parallel at the reconstruction node 1011a. The reconstruction node 1011a includes a first node of the first equipotential line and a second node of the second equipotential line, the first equipotential line is disconnected at the first node, and the second equipotential line is disconnected at the second node. Figure 5 The “black cross” in the diagram indicates a shield through hole. Figure 5 (a) is the reconstructed node 1011a from the attacker's perspective, where only the shielding layer through holes at both ends of the disconnected equipotential line 1011, namely the first through hole and the second through hole, can be seen.

[0091] like Figure 5 As shown, the routing paths of the first equipotential line and the second equipotential line include: Figure 5 (b) as shown, or Figure 5 (c) The cross-traces shown. The random number generator can generate random numbers to control Figure 5For example, if the random number is "0" at a certain moment, the control module 102 can control the first equipotential line and the second equipotential line to be routed independently at the first node and the second node. If the random number is "1" at a certain moment, the control module 102 can control the first equipotential line and the second equipotential line to be routed crosswise at the first node and the second node. Because the random number generated by the random number generator is uncontrollable, the probability of the two routing paths appearing at a certain moment can be 50% each. It is difficult to predict the routing path at the reconstruction node 1011a, so the difficulty of attack can be increased.

[0092] In an embodiment of the present application, since the first equipotential line and the second equipotential line in the target range are arranged in parallel, the first node and the second node are set within the target range, and the routing path can be conveniently randomly controlled at the first node and the second node, thereby reducing the influence of the cross routing on the first equipotential line and the second equipotential line.

[0093] In an embodiment of the present application, a reconstruction node 1011a can be set on two adjacent equipotential lines 1011 in the equipotential line group 101, namely the first equipotential line and the second equipotential line. Since the straight-line distance between the reconstructed node 1011a on the first equipotential line and the second equipotential line, namely the first node and the second node, is less than a preset distance threshold, the routing distance at the reconstruction node 1011a can be reduced, which facilitates the control module 102 to randomly control the routing path, and can reduce the resource overhead of the protection circuit 10 and improve the practicality of the protection circuit 10.

[0094] Optionally, the equipotential line 1011 further includes a confusion node 1011b;

[0095] The equipotential line 1011 is disconnected at the confusion node 1011b, and both ends of the disconnected equipotential line 1011 are connected to the routing layer through the through holes of the shielding layer; the equipotential line 1011 is restored to the routing layer.

[0096] In the embodiment of the present application, a confusion node 1011b can be set on some equipotential lines 1011 of the equipotential line group 101, and the reconstruction node 1011a is difficult to distinguish from the confusion node 1011b from the attacker's perspective, which can further increase the difficulty of the attack. Similar to the reconstruction node 1011a, the equipotential line 1011 is disconnected at the confusion node 1011b, and the two ends of the disconnected equipotential line 1011 are connected to the routing layer through the through holes of the shielding layer. However, unlike the reconstruction node 1011a, at the confusion node 1011b, the two ends of the disconnected equipotential line 1011 do not need to be connected to the control module 102, but are restored at the routing layer.

[0097] At the confusion node 1011b, the two ends of the disconnected equipotential line 1011 can enter the routing layer through the through holes of the shielding layer respectively, or, when the two ends of the disconnected equipotential line 1011 are very close, they can also enter the routing layer through the same through hole. The embodiment of the present application does not limit this.

[0098] In some embodiments, the routing layer can be the second top metal layer of the target chip. This is because there are few metal routings in other circuits in the second top layer, and therefore the impact on other circuits of the chip is smaller. This facilitates routing at reconstruction node 1011a and confusion node 1011b, and can improve the practicality of the protection circuit 10.

[0099] Optionally, at the confusion node 1011b, the equipotential line 1011 includes a third end and a fourth end;

[0100] The third end is connected to the routing layer through a third through hole on the shielding layer; the fourth end is connected to the routing layer through a fourth through hole on the shielding layer; the third end and the fourth end are restored to connection through a third routing line of the routing layer;

[0101] Alternatively, the third end and the fourth end are connected to the routing layer through a fifth through hole on the shielding layer, and the connection is restored on the routing layer.

[0102] In the embodiment of the present application, at the obfuscation node 1011b, the two ends of the disconnected equipotential line 1011 are the third end and the fourth end, respectively. The shielding layer is provided with a third through hole at the third end, one end of the third through hole is connected to the third end of the equipotential line 1011, and the other end is connected to one end of the third routing line. Also, the shielding layer is provided with a fourth through hole at the fourth end, one end of the fourth through hole is connected to the fourth end of the equipotential line 1011, and the other end is connected to the other end of the third routing line, so that the third end and the fourth end are restored to connection through the third routing line in the routing layer.

[0103] Alternatively, the third end and the fourth end are connected to the routing layer through a fifth through hole, and the connection is restored in the routing layer. Wherein, the routing layer may also be provided with a fourth routing line at the fifth through hole, so that the third end and the fourth end are connected through the fourth routing line.

[0104] Figure 6 is a schematic diagram of a wiring path of a confusion node 1011b provided in an embodiment of the present application, such as Figure 6 As shown, Figure 6 Two adjacent first equipotential lines and a second equipotential line in the equipotential line group 101 are shown. Figure 6 Based on the reconstruction node 1011a shown in (a), the first equipotential line and the second equipotential line are set as follows Figure 6 (b) Confusion node 1011b: At the confusion node 1011b, the first equipotential line and the second equipotential line are disconnected. Figure 6 The “black cross” in the diagram indicates a shield through hole. Figure 6(b) shows the reconstructed node 1011a and the obfuscated node 1011b from the attacker's perspective. The attacker can only see the through hole of the shielding layer, which makes it difficult for the attacker to distinguish the reconstructed node 1011a from the obfuscated node 1011b, further increasing the difficulty of the attack.

[0105] like Figure 6 As shown, at the confusion node 1011b, the two ends of the disconnected equipotential line 1011 can enter the routing layer through the through holes of the shielding layer respectively, or, when the two ends of the disconnected equipotential line 1011 are very close, they can also enter the routing layer through the same through hole, such as Figure 6 (c) shows the restoration of the connection on the routing layer.

[0106] In an embodiment of the present application, at the confusion node 1011b, the third end and the fourth end of the equipotential line 1011 can be flexibly selected to be connected to the third routing of the routing layer through the third through hole and the fourth through hole respectively, or to be connected to the routing layer together through the fifth through hole, and the connection is restored in the routing layer, which can play a confusing role with the shielding layer through hole at the reconstruction node 1011a, and can improve the practicality of the protection circuit 10.

[0107] In the embodiment of the present application, since the equipotential line 1011 at the confusion node 1011b is restored to the wiring layer, the confusion node 1011b is set on the equipotential line 1011, so that the equipotential line 1011 is disconnected at the confusion node 1011b and connected to the wiring layer through the through hole of the shielding layer. In this way, it can play a confusing role with the equipotential line 1011 disconnected at the reconstruction node 1011a and the through hole of the shielding layer, making it difficult to distinguish between the reconstruction node 1011a and the confusion node 1011b from the attacker's perspective, which can increase the difficulty of attack and improve the anti-attack ability of the protection circuit 10.

[0108] Optionally, the protection circuit 10 further includes a signal generating module 104, or the target chip includes the signal generating module 104;

[0109] The signal generating module 104 is electrically connected to the input end of the equipotential line 1011 and the detecting module 103 respectively, and is used to send a first detection signal to the equipotential line 1011 and the detecting module 103 respectively.

[0110] In the embodiment of the present application, the protection circuit 10 itself may include a signal generating module 104, and the signal generating module 104 in the protection circuit 10 generates a first detection signal, and sends the first detection signal to the equipotential line 1011 and the detection module 103 respectively. Alternatively, the protection circuit 10 may use the module unit of the target chip itself as the signal generating module 104, and the signal generating module 104 in the target chip sends the first detection signal to the equipotential line 1011 and the detection module 103 respectively.

[0111] Optionally, the signal generating module 104 is also electrically connected to the control module 102, and is used to generate a random control signal and send the random control signal to the control module 102; wherein the random control signal is used to instruct the control module 102 to perform random control on the routing path.

[0112] In the embodiment of the present application, the control module 102 may be a multiplex switch circuit, and the signal generation module 104 may be electrically connected to the control end of the control module 102, and send a random control signal to the control module 102, so that the control module 102 responds to the random control signal and randomly controls the routing path of the equipotential line 1011 at the reconstruction node 1011a. The random control signal may be a random number generated by a random number generator, and the random number generated by the random number generator is uncontrollable, and it is impossible to predict whether the next random number is 1 or 0, so that the routing path at the reconstruction node 1011a is completely random under the control of the random number.

[0113] Specifically, the control module 102 can perform switch switching in response to a random control signal to restore the connection between the first end and the second end of an equipotential line 1011, or to connect the first end of an equipotential line 1011 to the second end of another equipotential line 1011, that is, to randomly control the independent routing of the equipotential line 1011 at the reconstruction node 1011a or the cross routing of multiple equipotential lines 1011.

[0114] In an embodiment of the present application, the signal generation module 104 can conveniently perform random control on the routing path of the equipotential line 1011 at the reconstruction node 1011a by sending a random control signal to the control module 102. The signal generation module 104 outputs a first detection signal and a random control signal, which can reduce the resource occupation of the protection circuit 10.

[0115] Optionally, the signal generating module 104 is a random number generator, or a physically unclonable function circuit.

[0116] In the embodiment of the present application, the signal generation module 104 can be any structure for generating unpredictable numbers, i.e., random numbers, such as a random number generator, or a physically unclonable function (PUF) circuit. A portion of the random number generated by the signal generation module 104 can be input into the equipotential line 1011 and the detection module 103 as a first detection signal, and another portion can be input into the control module 102 as a random control signal to control the routing path of the equipotential line 1011.

[0117] For example, 20 equipotential lines 1011 are grouped in pairs to obtain 10 equipotential line groups 101. The signal generation module 104 is a 32-bit random number generator. The first 20 bits of the random number generator can be selected to obtain the first detection signals corresponding to the 20 equipotential lines 1011, and the last 10 bits of the random number generator can be used as the random control signals corresponding to the 10 equipotential line groups 101. Similarly, for the two equipotential line groups 101 obtained by grouping the four equipotential lines 1011 in pairs, the signal generation module 104 can be an 8-bit random number generator, and the first 4 bits of the results can be selected as the first detection signals corresponding to the four equipotential lines 1011, and the last 2 bits of the results can be used as the random control signals corresponding to the two equipotential line groups 101. This is only an example, and the embodiments of the present application are not limited to this.

[0118] It should be noted that the physical unclonable function (PUF) circuit has high requirements for environmental factors. Once the temperature or voltage exceeds the working requirements of the PUF circuit, the PUF may fail to work properly. Even if the random number generator is affected and the randomness of the generated random numbers is reduced, the probability of the generated random numbers being always 0 or 1 is also extremely low, so it is sufficient to meet the randomness requirements.

[0119] In an embodiment of the present application, the signal generation module 104 can select a device that generates random numbers, such as a random number generator or a physically unclonable function circuit, so that the routing path of the equipotential line 1011 at the reconstructed node 1011a is random, thereby improving the anti-attack ability of the protection circuit 10 and improving the security of the protected area of ​​the target chip.

[0120] Optionally, the signal generating module 104 is located in the protected area;

[0121] The input end of the equipotential line 1011 is electrically connected to the signal generating module 104 through a through hole of the shielding layer.

[0122] In the embodiment of the present application, the signal generation module 104 can be arranged in the protected area covered by the equipotential line group 101, so that the equipotential line group 101 shields the signal generation module 104. For example, the signal generation module 104 is a random number generator in the protected area of ​​the target chip, so that the original random number generator of the target chip can be used to achieve shielding protection.

[0123] Specifically, the input end of the equipotential line 1011 can enter the routing layer through the through hole of the shielding layer, and be connected to the signal generating module 104 in the protected area through the metal routing of the routing layer, so that the input end of the equipotential line 1011 is electrically connected to the signal generating module 104.

[0124] In an embodiment of the present application, the signal generating module 104 is disposed in a protected area of ​​the target chip, and the input end of the equipotential line 1011 is electrically connected to the signal generating module 104 through a through hole in the shielding layer. In this way, the attacker cannot see the signal generating module 104 from his perspective, and can only see the through hole in the shielding layer at the input end of the equipotential line 1011, which can confuse the attacker with the through hole in the shielding layer at the reconstruction node 1011a, thereby greatly increasing the difficulty of the rewiring attack.

[0125] In an embodiment of the present application, the protection circuit 10 may include a signal generating module 104, or a module unit of a target chip may be used as the signal generating module 104, so that the practicality of the protection circuit 10 can be improved and the resource occupation of the protection circuit 10 can be reduced.

[0126] Optionally, the detection module 103 is located in the protected area;

[0127] The output end of the equipotential line 1011 is electrically connected to the detection module 103 through the through hole of the shielding layer.

[0128] In the embodiment of the present application, the detection module 103 can be set in the protected area of ​​the target chip, so that the detection module 103 is covered by the equipotential line group 101. Specifically, the output end of the equipotential line 1011 can enter the wiring layer through the through hole of the shielding layer, and be connected to the detection module 103 in the protected area through the metal wiring of the wiring layer, so that the output end of the equipotential line 1011 is electrically connected to the detection module 103.

[0129] For example, the detection module 103 can be a combinational logic circuit. The random number sent by the signal generation module 104 received by the detection module 103 is a first detection signal. The random number output by the equipotential line 1011 received by the detection module 103 is a second detection signal. The first detection signal will pass through the equipotential line 1011 to reconstruct the routing path at the node 1011a. The detection module 103 compares the random numbers at the input and output ends of the equipotential line 1011. If they are consistent, it means that there is no attack. If one or more of the multiple equipotential lines 1011 are inconsistent, it means that the target chip has been attacked.

[0130] In an embodiment of the present application, the detection module 103 is set in the protected area of ​​the target chip, and the output end of the equipotential line 1011 is electrically connected to the detection module 103 through the through hole of the shielding layer. In this way, the attacker cannot see the detection module 103 from the perspective, and can only see the through hole of the shielding layer at the output end of the equipotential line 1011, which can confuse the through hole of the shielding layer at the reconstruction node 1011a, thereby greatly increasing the difficulty of the rewiring attack.

[0131] Figure 7 is a schematic diagram of the circuit structure of another protection circuit 10 provided in an embodiment of the present application, such as Figure 7As shown, the protection circuit 10 further includes a signal generating module 104. The control module 102, the detection module 103 and the signal generating module 104 are all arranged in the protected area of ​​the target chip. Figure 7 The protection circuit 10 shown fills multiple equipotential line groups 101 into the top metal layer of the target chip as a shielding layer of the target chip. The graphic topology structure formed by the multiple equipotential line groups 101 covers the protected area of ​​the target chip to shield the protected area of ​​the target chip.

[0132] See also Figure 7 , the equipotential line group 101 covers the protected area. The signal generation module 104 is electrically connected to the input end of the equipotential line 1011, the control module 102 and the detection module 103. The input end and the output end of the equipotential line 1011 are connected to the detection module 103 and the signal generation module 104 through the shielding layer through hole. Figure 7 The black dots on the isopotential line 1011 represent shielding layer through holes.

[0133] Optionally, the shielding layer adopts a Hamiltonian circuit structure;

[0134] The equipotential line group 101 is composed of equipotential lines 1011 in the Hamiltonian circuit structure.

[0135] In the embodiment of the present application, multiple equipotential line groups 101 can be formed into a Hamiltonian circuit structure and filled into the top metal layer of the target chip as a shielding layer of the target chip, so that the shielding layer of the target chip adopts a Hamiltonian circuit structure to shield and protect the protected area of ​​the target chip. Among them, the equipotential lines 1011 in different equipotential line groups 101 can be the same or different, and the embodiment of the present application does not limit this.

[0136] Alternatively, the shielding layer of the target chip itself is a Hamiltonian circuit structure, the equipotential line group 101 can be composed of multiple equipotential lines 1011 in the Hamiltonian circuit structure, and the equipotential lines 1011 in the equipotential line group 101 are respectively connected to the control module 102 and the detection module 103 of the protection circuit 10. The equipotential line group 101 covers the protected area of ​​the target chip and can shield the protected area.

[0137] In an embodiment of the present application, the equipotential line group 101 of the protection circuit 10 can be composed of equipotential lines 1011 in a Hamiltonian circuit structure. In this way, the attack difficulty of the equipotential line group 101 can be increased by the complexity of the Hamiltonian circuit structure, thereby improving the anti-attack capability of the protection circuit 10.

[0138] Figure 8 Schematic diagram of a shielding layer topology structure provided in an embodiment of the present application. Figure 8As shown, the shielding layer of the target chip adopts a Hamiltonian circuit structure, and the equipotential line group 101 is composed of multiple equipotential lines 1011 in the Hamiltonian circuit structure. An equipotential line 1011 may include a reconstruction node 1011a and / or a confusion node 1011b. The embodiment of the present application does not limit the number and position of the reconstruction node 1011a and the confusion node 1011b on an equipotential line 1011. It should be noted that the Hamiltonian circuit structure is highly complex and it is difficult to perform a rewiring attack. The attacker needs to spend a lot of time to find the beginning and end of the equipotential line 1011 before short-circuiting the equipotential line 1011 to perform a rewiring attack, and the attack cost is high.

[0139] In the embodiment of the present application, when the attacker launches an attack on the target chip, he needs to distinguish the through holes at the reconstructed node 1011a and the obfuscated node 1011b from a large number of shielding layer through holes, find the connection relationship of the equipotential line 1011, and then find the real head and tail ends of the equipotential line 1011, that is, the input end and the output end, from the connection relationship. Figure 5 For example, the probability of the two routing paths controlled by random numbers is 50% each, so there is a 50% probability of being wrong. Even if the connection is correct this time, the probability of error next time is still 50%.

[0140] Fig. 9 is another schematic diagram of the shielding layer topology provided in the embodiment of the present application, such as Fig. 9 As shown, the shielding layer through holes at the beginning and end of the equipotential line 1011, the reconstruction node 1011a and the obfuscation node 1011b can be irregularly distributed on the top metal layer of the target chip, i.e., the shielding layer, so that the area of ​​the shielding line that is easily short-circuited is as small as possible. The control module 102, the detection module 103 and the signal generation module 104 in the protection circuit 10 can be set in the protected area covered by the equipotential line group 101, so that the attacker can only see the following Fig. 9 The topological structure of the graph is shown. The attacker wants to connect all equipotential lines 1011 correctly, and the correct probability is 50% to the power of n, and the result is close to 0, so the difficulty of attack can be greatly increased. Once the protection circuit 10 starts working, the possibility of the target chip being successfully attacked will be greatly reduced. The protection circuit 10 has the advantages of simple structure and strong portability.

[0141] Moreover, once an equipotential line 1011 is attacked by a rewiring attack and discovered by the detection module 103, the detection module 103 can output an alarm signal to alert the main control unit of the target chip. If the main control unit takes protective measures, such as overwriting important data in the protected area, it will be meaningless for the attacker to continue the attack, thereby improving the security of the target chip.

[0142] An embodiment of the present application provides a chip, which includes the protection circuit 10 as described in the above embodiment.

[0143] The chip of the embodiment of the present application has the same advantages as those of the related technologies and circuit embodiments, which will not be described in detail here.

[0144] An embodiment of the present application provides an electronic device, which includes the chip described in the above embodiment.

[0145] The electronic device of the embodiment of the present application has the same advantages as those of the related art and circuit embodiments, which will not be described in detail here.

[0146] The embodiment of the present application provides a protection circuit 10, a chip and an electronic device, which can use a Hamiltonian loop structure to fill and cover the top metal layer of the chip, that is, the shielding layer, to shield the protected area of ​​the target chip. An equipotential line group 101 is composed of multiple equipotential lines 1011 in the Hamiltonian loop structure, and a reconstruction node 1011a and / or a confusion node 1011b are set on the equipotential line 1011, and a signal generation module 104, such as a random number generator, generates a random number as a first detection signal and a random control signal. The control module 103 dynamically and randomly reconstructs the shielding layer topology in response to the random control signal, and the detection module 103 compares and verifies the second detection signal output by the equipotential line 1011 with the first detection signal, and continuously detects the physical attack on the target chip. In this way, a dynamic active metal shielding layer structure can be realized, the difficulty of attack is increased, the anti-attack property of the protection circuit 10 can be improved, and a good protection effect can be achieved using a small amount of resources, thereby improving the security of the target chip.

[0147] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0148] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A protection circuit, characterized in that: The protection circuit includes: an equipotential line group, a control module, and a detection module; The equipotential line group is located in the shielding layer of the target chip; the equipotential line group covers the protected area of ​​the target chip; the control module is located in the protected area and is arranged in the routing layer under the shielding layer; The equipotential line group includes a plurality of equipotential lines; the output end of the equipotential line is electrically connected to the detection module; the input end of the equipotential line is used to receive a first detection signal; The equipotential line includes a reconstruction node; the equipotential line is disconnected at the reconstruction node, and two ends of the disconnected equipotential line are electrically connected to the control module respectively; The control module is used to randomly control the routing path of the equipotential line at the reconstruction node; wherein the routing path is located in the protected area and is arranged in the routing layer; the routing path includes a plurality of cross routings of the equipotential lines, and / or independent routings of the equipotential lines; The detection module is used to receive the first detection signal, compare the first detection signal with the second detection signal, and output an alarm signal when the comparison result indicates that the target chip is attacked; wherein the second detection signal is the detection signal output by the equipotential line to the detection module.

2. The protection circuit according to claim 1, characterized in that: At the reconstruction node, the equipotential line includes a first end and a second end; The first end is connected to the wiring layer through a first through hole of the shielding layer, and is electrically connected to the control module through a first wiring of the wiring layer; The second end is connected to the wiring layer through the second through hole of the shielding layer, and is electrically connected to the control module through the second wiring of the wiring layer.

3. The protection circuit according to claim 2, characterized in that: The routing layer is a metal layer of the protected area; the first routing line and the second routing line are metal routing lines of the metal layer.

4. The protection circuit according to claim 1, characterized in that: The equipotential line group includes a first equipotential line and a second equipotential line; the first equipotential line and the second equipotential line are two adjacent equipotential lines in the equipotential line group; The output end of the first equipotential line and the output end of the second equipotential line are electrically connected to the detection module respectively; the first equipotential line and the second equipotential line are respectively used to receive the first detection signal; The reconstruction node of the first equipotential line is a first node; The reconstruction node of the second equipotential line is a second node; A straight-line distance between the first node and the second node is less than a preset distance threshold.

5. The protection circuit according to claim 4, characterized in that: The first node and the second node are located within a target range; the first equipotential line and the second equipotential line in the target range are arranged in parallel.

6. The protection circuit according to claim 1, characterized in that: The equipotential lines also include confusion nodes; The equipotential lines are disconnected at the confusion nodes, and both ends of the disconnected equipotential lines are connected to the routing layer through the through holes of the shielding layer; and the equipotential lines are restored to connection in the routing layer.

7. The protection circuit according to claim 6, characterized in that: At the confusion node, the equipotential line includes a third end and a fourth end; The third end is connected to the routing layer through a third through hole on the shielding layer; the fourth end is connected to the routing layer through a fourth through hole on the shielding layer; the third end and the fourth end are restored to connection through a third routing of the routing layer; Alternatively, the third end and the fourth end are connected to the routing layer through a fifth through hole on the shielding layer, and the connection is restored at the routing layer.

8. The protection circuit according to any one of claims 1 to 7, characterized in that: The protection circuit further includes a signal generating module, or the target chip includes the signal generating module; The signal generating module is electrically connected to the input end of the equipotential line and the detecting module respectively, and is used to send the first detecting signal to the equipotential line and the detecting module respectively.

9. The protection circuit according to claim 8, characterized in that: The signal generating module is also electrically connected to the control module, and is used to generate a random control signal, and send the random control signal to the control module; wherein the random control signal is used to instruct the control module to perform random control on the routing path.

10. The protection circuit according to claim 8, characterized in that: The signal generating module is a random number generator, or a physically unclonable function circuit.

11. The protection circuit according to claim 8, characterized in that: The signal generating module is located in the protected area; The input end of the equipotential line is electrically connected to the signal generating module through the through hole of the shielding layer.

12. The protection circuit according to any one of claims 1 to 7, characterized in that: The detection module is located in the protected area; The output end of the equipotential line is electrically connected to the detection module through the through hole of the shielding layer.

13. The protection circuit according to any one of claims 1 to 7, characterized in that: The shielding layer adopts a Hamiltonian circuit structure; The equipotential line group is composed of equipotential lines in the Hamiltonian circuit structure.

14. A chip, characterized in that: The chip comprises the protection circuit as claimed in any one of claims 1-13.

15. An electronic device, characterized in that: The electronic device comprises the chip as claimed in claim 14.

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