SGT MOSFET made of Low-k material and preparation method of SGT MOSFET

Abstract

According to the SGT MOSFET of the Low-k material and the preparation method of the SGT MOSFET, a gate insulating layer of the SGT MOSFET is deposited by adopting the Low-k material based on carbon-doped silicon oxide, and an oxide layer on the side wall of a shielding gate adopts an ONO structure, so that on one hand, the capacitance effect of a device can be reduced through the Low-k material under the condition that the physical thickness of the insulating layer is kept unchanged and electric leakage is not influenced, and the performance of the device is improved; the performance of the device is improved; and on the other hand, the compactness of the silicon nitride layer is high, and the side wall and the bottom of the shield gate polycrystalline silicon are protected by the silicon nitride layer, so that the on resistance of the device is further reduced and the conduction loss of the device is reduced by improving the doping concentration of the epitaxial layer on the basis of not reducing the breakdown voltage. Meanwhile, by controlling the depth of the oxide layer and the silicon nitride layer which are etched on the side wall of the groove, the silicon nitride layer is far away from the grid polycrystalline silicon, and the reliability of the device is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of semiconductor devices, and specifically relates to a SGT MOSFET of Low-k material and a preparation method thereof. Background Art

[0002] At present, the gate insulation layer material of SGT MOSFET (Shield Gate Trench Metal-Oxide-Semiconductor Field-Effect Transistor) devices is mainly based on the traditional material silicon dioxide, and the dielectric constant of silicon oxide is between 3.9 and 4.5. As the process continues to advance, silicon dioxide has gradually approached its application limit.

[0003] As the requirements for device performance continue to increase, devices based mainly on traditional materials such as silicon dioxide can no longer meet the performance requirements of devices. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present application provides a SGTMOSFET made of Low-k material and a preparation method thereof. The technical problem to be solved by the present application is achieved by the following technical solution: In a first aspect, the present invention provides a method for preparing a SGT MOSFET of a Low-k material, comprising: S1, selecting an N-type substrate and growing an N-type epitaxial layer thereon; etching at least one groove inside the N-type epitaxial layer using an etching process; S2, growing a sacrificial oxide layer on the inner wall of the trench and etching it away, and then growing a gate oxide layer on the side wall of the trench; S3, depositing silicon nitride on the surface of the gate oxide layer to form a silicon nitride layer, and depositing an oxide layer on the surface of the silicon nitride layer; S4, depositing polysilicon in the trench, and etching the polysilicon to a predetermined position below the trench to form a shielding grid; S5, etching the oxide layer and the silicon nitride layer in the trench from top to bottom until they are flush with the surface of the shielding gate; S6, depositing a carbon-doped silicon oxide Low-k material in the trench to form a gate insulating layer; S7, depositing polysilicon in the trench until a polysilicon layer is formed on the surface of the N-type epitaxial layer; S8, firstly implanting B element from top to bottom around the outer wall of the trench to form a P region, and then implanting As element to form an N+ region; S9, depositing BPSG on the upper surface of the device formed in S8 to form an ILD insulating layer, and etching downward from the inner wall of the device to form a contact hole; S10, depositing a conductive material on the upper surface of the device formed in S9 to form a conductive layer, depositing a metal AL on the surface of the conductive layer, and etching away the metal AL between different regions; S11, depositing metal on the back side of the N-type substrate to form a metal electrode, thereby obtaining an ONO-structured SGT MOSFET using a Low-k material.

[0005] In a second aspect, the present invention provides an SGT MOSFET of a Low-k material, which is prepared by the preparation method described in the first aspect, and the SGT MOSFET of the Low-k material comprises: a plurality of cells arranged at equal intervals, each cell comprising an N-type substrate and an N-type epitaxial layer arranged thereon, at least one trench is arranged inside the N-type epitaxial layer, a gate oxide layer is arranged on the inner wall of the trench, a silicon nitride layer is arranged on the inward surface of the gate oxide layer, an oxide layer is arranged on the inward surface of the silicon nitride layer, and polysilicon is filled between the oxide layers; the upper surfaces of the silicon nitride layer, the oxide layer and the polysilicon are sequentially formed from bottom to top with a gate insulating layer and a polysilicon layer, and both are located in the trench; a contact hole is etched at the edge of the N-type epitaxial layer, an ILD insulating layer not covering the contact hole is deposited on the N-type epitaxial layer, a conductive layer is arranged on the ILD insulating layer, the conductive layer covers the ILD insulating layer and the contact hole, and a metal layer is arranged on the conductive layer; a metal electrode is arranged on the back side of the N-type substrate, and the gate insulating layer is formed of a Low-k material.

[0006] Beneficial effects: The present application provides a SGT MOSFET of Low-k material and a preparation method thereof, wherein the gate insulating layer of the SGT MOSFET is deposited by a Low-k material based on carbon-doped silicon oxide, and the shield gate sidewall oxide layer adopts an ONO (oxide-Nitride-oxide) structure. On the one hand, the capacitance effect of the device can be reduced by the Low-k material while keeping the physical thickness of the insulating layer unchanged and the leakage current unaffected, thereby improving the performance of the device; on the other hand, due to the high density of the silicon nitride layer, the sidewall and bottom of the shield gate polysilicon are protected by the silicon nitride layer, and the silicon nitride layer has a higher dielectric constant than the silicon dioxide layer, and the critical electric field strength is also higher, so the on-resistance of the device can be further reduced without reducing the breakdown voltage by increasing the doping concentration of the epitaxial layer, thereby reducing the conduction loss of the device. At the same time, the silicon nitride layer can be kept away from the gate polysilicon by controlling the depth of the oxide layer and the silicon nitride layer of the etched groove sidewall, thereby improving the reliability of the device.

[0007] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic flow chart of a method for preparing a SGT MOSFET of a Low-k material provided in the present application; Figure 2-Figure 13 It is a schematic diagram of the preparation process of a method for preparing a SGT MOSFET of a Low-k material provided in the present application; Fig.14 It is a schematic diagram of the structure of a SGT MOSFET made of Low-k material provided in this application. DETAILED DESCRIPTION

[0009] The present application is further described in detail below in conjunction with specific embodiments, but the implementation methods of the present application are not limited thereto.

[0010] In view of the continuous advancement of manufacturing processes and the continuous improvement of market demand for device performance, this application proposes an SGT MOSFET device and preparation method by depositing a Low-k material as a gate insulating layer. The biggest feature of this structure is that while keeping the physical thickness of the gate insulating layer unchanged and the leakage current unaffected, the device gate insulating layer is deposited with a Low-k material Black Diamond to reduce the capacitance effect of the device and improve the device performance; Black Diamond is a Low-k material based on carbon-doped silicon oxide, usually using chemical vapor deposition, so it is close to traditional semiconductor processes and the process is easier to implement.

[0011] In addition, the field oxide layer is composed of three dielectric layers of different properties: thermal oxide layer, high-K dielectric layer SiN and CVD (chemical vapor deposition) oxide layer. Due to the high density of the silicon nitride layer, the sidewall and bottom of the shielding gate polysilicon are protected by the silicon nitride layer, and the silicon nitride layer has a higher dielectric constant than the silicon dioxide layer, and the critical electric field strength is also higher. Therefore, by increasing the doping concentration of the epitaxial layer, the on-resistance of the device can be further reduced without reducing the breakdown voltage, and the conduction loss of the device can be reduced. At the same time, the depth of the etching trench sidewall oxide layer and the silicon nitride layer can be controlled to keep the silicon nitride layer away from the gate polysilicon, thereby improving the reliability of the device.

[0012] like Figure 1 As shown, the present application provides a method for preparing a SGT MOSFET of a Low-k material, comprising: S1, selecting an N-type substrate and growing an N-type epitaxial layer thereon; etching a groove inside the N-type epitaxial layer using an etching process; According to the requirements of different devices for withstand voltage, the present application selects a substrate with suitable thickness and resistivity, and then grows an N-type epitaxial layer thereon, such as Figure 2 Then the SGT MOSFET trench structure is etched out through etching process, as shown in Figure 3 The groove depth is 1.5 to 2.2 μm, the groove width is 0.25 to 0.5 μm, and the inclination angle is 89 to 90°.

[0013] S2, growing a sacrificial oxide layer on the inner wall of the trench and etching it away, and then growing a gate oxide layer on the side wall of the trench; In this step, a sacrificial oxide layer with a thickness of about 0.02 μm is formed on the sidewall of the trench by dry oxidation, and then removed by wet etching, and then a gate oxide layer with a thickness adapted to the threshold voltage is grown on the sidewall of the trench. Figure 4 , thickness is 0.04μm~0.06μm.

[0014] S3, depositing silicon nitride on the surface of the gate oxide layer to form a silicon nitride layer, and depositing a thick oxide layer on the surface of the silicon nitride layer; In this step, a layer of silicon nitride is deposited on the surface of the top of the trench and the surface of the gate oxide layer. Figure 5 The thickness of silicon nitride is 0.02-0.03 μm, and then a thick oxide layer is formed on the surface of the silicon nitride layer by CVD and oxidation. Figure 6 As shown, the thickness of the oxide layer is 0.09 to 0.16 μm.

[0015] S4, depositing polysilicon in the trench, and etching the polysilicon to a predetermined position below the trench to form a shielding grid; In this step, polysilicon is deposited in the trench and etched to a predetermined position below the trench, that is, 0.8 to 1.2 um below the surface of the polysilicon, to form a shielding gate. Figure 7 shown.

[0016] S5, etching the oxide layer and the silicon nitride layer in the trench from top to bottom until they are flush with the surface of the shielding gate; In this step, the oxide layer and silicon nitride are continuously etched until they are flush with the surface of the shielding grid. Figure 8 shown.

[0017] S6, depositing a carbon-doped silicon oxide Low-k material in the trench to form a gate insulating layer; In this step, a gate insulation layer of 0.2~0.25um is deposited as an isolation layer between the shielding gate and the control gate. Fig. 9 As shown, the gate insulating layer material is selected from the low-k material Black Diamond with carbon-doped silicon oxide, whose dielectric constant k value is about 2.7, which is the mainstream choice in the current market.

[0018] The gate insulation layer introduces Low-k materials to replace traditional silicon dioxide materials to meet the market's increasing requirements for device performance. Low-k materials mainly include: SiLK, hydrogen silses quioxane (HSQ), methyl silses quioxane (MSQ) and some Low-k materials based on carbon-doped silicon oxide, such as Aurora, Black Diamond, Coral, etc. Some Low-k materials based on carbon-doped silicon oxide usually use chemical vapor deposition, so they are close to traditional semiconductor processes and are easier to implement.

[0019] S7, depositing polysilicon in the trench until a polysilicon layer is formed on the surface of the N-type epitaxial layer; In this step, polysilicon is deposited in the trench until the surface of the N-type epitaxial layer is formed, such as Fig.10 shown.

[0020] S8, firstly implanting B element from top to bottom around the outer wall of the trench to form a P region, and then implanting As element to form an N+ region; S8 of this application includes: S8-1, injecting B element twice from top to bottom around the outer wall of the trench, and then annealing to form a P region, wherein the injection energy of the B element is 60Kev to 130Kev, the annealing temperature is 1000° C., and the time is 30 minutes; S8-2, As element is injected above the position where B element is injected, and then annealing is performed to form an N+ region, wherein the injection energy of the As element is 60 KeV, the annealing temperature is 950°C, and the time is 30 minutes. Fig.11 shown.

[0021] S9, depositing BPSG (Boro-phospho-silicate Glass) on the upper surface of the device formed in S8 to form an ILD (Interlayer Dielectric) insulating layer, and etching downward from the inner wall of the device to form a contact hole; In this step, BPSG is deposited on the upper surface of the device to form an ILD insulating layer, and contact holes are formed by etching downward from the inner wall of the device. Fig.12 As shown, the depth of the contact hole is 0.25um~0.40um.

[0022] S10, depositing a conductive material on the upper surface of the device formed in S9 to form a conductive layer, depositing a metal AL on the surface of the conductive layer, and etching away the metal AL between different regions to form a metal layer; S10 of this application includes: S10-1, depositing a Ti / TiN layer and a tungsten metal on the upper surface of the device formed in S9 to cover the contact hole and form a conductive layer on the surface of the ILD insulating layer, such as Fig.13 shown.

[0023] S10-2, depositing a metal AL with a thickness of 4 to 5 um on the surface of the conductive layer, and etching away the metal AL between different contact holes to form a metal layer, such as Fig.13 shown.

[0024] S11, depositing metal on the back side of the N-type substrate to form a metal electrode, thereby obtaining an ONO structure SGT MOSFET using a Low-k material, see Fig.13 .

[0025] In this step, the back side of the N-type substrate is thinned to 60um-100μm, and Ti, Ni and Ag are evaporated on the back side to form a drain to obtain an ONO structure SGT MOSFET using Low-k material; The thicknesses of Ti, Ni and Ag are 0.1 μm, 0.2 μm and 1 μm respectively.

[0026] In a second aspect, the present application provides a SGT MOSFET made of a Low-k material, which is prepared using the preparation method described in the first aspect, wherein the SGT MOSFET of the Low-k material The MOSFET comprises: a plurality of cells arranged at equal intervals, each cell comprising an N-type substrate and an N-type epitaxial layer arranged thereon, at least one groove is arranged inside the N-type epitaxial layer, a gate oxide layer is arranged on the inner wall of the groove, a silicon nitride layer is arranged on the inner surface of the gate oxide layer, an oxide layer is arranged on the inner surface of the silicon nitride layer, and polysilicon is filled between the oxide layers; the upper surfaces of the silicon nitride layer, the oxide layer and the polysilicon are sequentially formed from bottom to top with a gate insulating layer and a polysilicon layer, and both are located in the groove; a contact hole is etched at the edge of the N-type epitaxial layer, an ILD insulating layer not covering the contact hole is deposited on the N-type epitaxial layer, a conductive layer is arranged on the ILD insulating layer, the conductive layer covers the ILD insulating layer and the contact hole, and a metal layer is arranged on the conductive layer; a metal electrode is arranged on the back of the N-type substrate, and the gate insulating layer is formed of a Low-k material.

[0027] refer to Fig.14 As shown, in Fig.14The SGT MOSFET of the Low-k material of the present application includes an active region and a terminal region, and the terminal region is further divided into a trench terminal region and a cut-off region. The trench terminal region is the region on the left side containing the trench, and the cut-off region is the region on the right side without the trench. The distance from the terminal region to the end of the active region is equal to 90% to 100% of the spacing between the cells in the active region. The width of the trench in the terminal region can be 0.1um larger than the width of the trench in the active region, and of course it can also be equal to the trench width in the active region.

[0028] The present application provides a SGT MOSFET of Low-k material and a preparation method thereof, wherein the gate insulating layer of the SGT MOSFET is deposited by a Low-k material based on carbon-doped silicon oxide, and the shield gate sidewall oxide layer adopts an ONO (oxide-Nitride-oxide) structure. On the one hand, the capacitance effect of the device can be reduced by the Low-k material while keeping the physical thickness of the insulating layer unchanged and the leakage current unaffected, thereby improving the performance of the device; on the other hand, due to the high density of the silicon nitride layer, the sidewall and bottom of the shield gate polysilicon are protected by the silicon nitride layer, and the silicon nitride layer has a higher dielectric constant than the silicon dioxide layer, and the critical electric field strength is also higher, so the on-resistance of the device can be further reduced without reducing the breakdown voltage by increasing the doping concentration of the epitaxial layer, thereby reducing the conduction loss of the device. At the same time, the silicon nitride layer can be kept away from the gate polysilicon by controlling the depth of the oxide layer and the silicon nitride layer of the etched groove sidewall, thereby improving the reliability of the device.

[0029] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components or steps.

[0030] The above content is a further detailed description of the present application in combination with specific preferred implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A method for preparing a SGT MOSFET of a Low-k material, characterized in that: include: S1, selecting an N-type substrate and growing an N-type epitaxial layer thereon; etching at least one groove inside the N-type epitaxial layer using an etching process; S2, growing a sacrificial oxide layer on the inner wall of the trench and etching it away, and then growing a gate oxide layer on the side wall of the trench; S3, depositing silicon nitride on the surface of the gate oxide layer to form a silicon nitride layer, and depositing an oxide layer on the surface of the silicon nitride layer; S4, depositing polysilicon in the trench, and etching the polysilicon to a predetermined position below the trench to form a shielding grid; S5, etching the oxide layer and the silicon nitride layer in the trench from top to bottom until they are flush with the surface of the shielding gate; S6, depositing a carbon-doped silicon oxide Low-k material in the trench to form a gate insulating layer; S7, depositing polysilicon in the trench until a polysilicon layer is formed on the surface of the N-type epitaxial layer; S8, firstly implanting B element from top to bottom around the outer wall of the trench to form a P region, and then implanting As element to form an N+ region; S9, depositing BPSG on the upper surface of the device formed in S8 to form an ILD insulating layer, and etching downward from the inner wall of the device to form a contact hole; S10, depositing a conductive material on the upper surface of the device formed in S9 to form a conductive layer, depositing a metal AL on the surface of the conductive layer, and etching away the metal AL between different regions to form a metal layer; S11, depositing metal on the back side of the N-type substrate to form a metal electrode, thereby obtaining an ONO-structured SGT MOSFET using a Low-k material.

2. The method for preparing a SGT MOSFET of a Low-k material according to claim 1, characterized in that: The groove depth in S1 is 1.5 to 2.5 μm, the groove width is 0.25 to 0.5 μm, and the inclination angle is 89 to 90°.

3. The method for preparing a SGT MOSFET of a Low-k material according to claim 1, characterized in that: The thickness of the gate oxide layer grows according to the threshold voltage, and the thickness is 0.04 μm to 0.06 μm; the thickness of the silicon nitride layer is 0.02 to 0.03 μm; and the thickness of the oxide layer is 0.09 to 0.16 μm.

4. The method for preparing a SGT MOSFET of a Low-k material according to claim 1, characterized in that: The predetermined position in S4 is 0.8 to 1.2 um below the surface of the polysilicon.

5. The method for preparing a SGT MOSFET of a Low-k material according to claim 1, characterized in that: The thickness of the gate insulating layer is 0.2-0.25 um.

6. The method for preparing a SGT MOSFET of a Low-k material according to claim 1, characterized in that: S8 includes: S8-1, injecting B element twice from top to bottom around the outer wall of the trench, and then annealing to form a P region, wherein the injection energy of the B element is 60Kev to 130Kev, the annealing temperature is 1000° C., and the time is 30 minutes; S8-2, injecting As element above the position where B element is injected, and then performing annealing to form an N+ region, wherein the injection energy of the As element is 60Kev, the annealing temperature is 950°C, and the time is 30min.

7. The method for preparing a SGT MOSFET of a Low-k material according to claim 1, characterized in that: The depth of the contact hole in S9 is 0.25um~0.40um.

8. The method for preparing a SGT MOSFET of a Low-k material according to claim 1, characterized in that: S10 includes: S10-1, depositing a Ti / TiN layer and tungsten metal on the upper surface of the device formed in S9 to cover the contact hole and form a conductive layer on the surface of the ILD insulating layer; S10-2, depositing a metal AL with a thickness of 4-5 um on the surface of the conductive layer, and etching away the metal AL between different contact holes to form a metal layer.

9. The method for preparing a SGT MOSFET of a Low-k material according to claim 1, characterized in that: S11 includes: The back side of the N-type substrate is thinned to 60um-100μm, and Ti, Ni and Ag are evaporated on the back side to form a drain to obtain an ONO structure SGT MOSFET using a Low-k material; The thicknesses of Ti, Ni and Ag are 0.1 μm, 0.2 μm and 1 μm respectively.

10. A SGT MOSFET made of Low-k material, characterized in that: The SGT MOSFET of the Low-k material is prepared by the preparation method according to any one of claims 1 to 9, wherein the SGT MOSFET of the Low-k material comprises: a plurality of cells arranged at equal intervals, each cell comprising an N-type substrate and an N-type epitaxial layer arranged thereon, at least one trench is arranged inside the N-type epitaxial layer, a gate oxide layer is arranged on the inner wall of the trench, a silicon nitride layer is arranged on the inner surface of the gate oxide layer, an oxide layer is arranged on the inner surface of the silicon nitride layer, and polysilicon is filled between the oxide layers; the upper surfaces of the silicon nitride layer, the oxide layer and the polysilicon are sequentially formed from bottom to top as a gate insulating layer and a polysilicon layer, and both are located in the trench; a contact hole is etched at the edge of the N-type epitaxial layer, an ILD insulating layer not covering the contact hole is deposited on the N-type epitaxial layer, a conductive layer is arranged on the ILD insulating layer, the conductive layer covers the ILD insulating layer and the contact hole, and a metal layer is arranged on the conductive layer; a metal electrode is arranged on the back side of the N-type substrate, and the gate insulating layer is formed of a Low-k material.

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