Interface data transmission system and method

Abstract

The invention discloses an interface data transmission system and method. The interface data transmission system comprises a master FPGA, a slave FPGA and external equipment corresponding to a to-be-verified circuit in the master FPGA, a to-be-verified circuit, a first data conversion circuit and a first AURORA interaction circuit are arranged in the main FPGA, and a PIPE interface is arranged in the to-be-verified circuit; and a second AURORA interaction circuit, a second data conversion circuit and a data rate processing circuit are arranged in the slave FPGA. According to the embodiment of the invention, data transmission between the PIPE interface of the integrated circuit and the PIPE interface of the external equipment can be accurately realized on the basis of the first data conversion circuit and the first AURORA interaction circuit in the master FPGA and the second AURORA interaction circuit, the second data conversion circuit and the data rate processing circuit in the slave FPGA, so that the occupied resources are few, and the cost is low. And the efficiency and accuracy of the verification process are improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an interface data transmission system and method. Background Art

[0002] The PCIE (Peripheral Component Interconnect Express) protocol is a high-speed serial computer expansion bus standard. A PIPE interface is usually provided in an integrated circuit. The PIPE interface is an interface for transmitting data based on the PCIE protocol. During the verification process of the integrated circuit, data that complies with the PCIE protocol needs to be sent to the PIPE interface of an external device through the PIPE interface of the integrated circuit, and data that complies with the PCIE protocol sent by the PIPE interface of an external device needs to be received through the PIPE interface of the integrated circuit. The integrated circuit to be verified is usually set in a Field Programmable Gate Array (FPGA).

[0003] Normally, the PIPE interface of the external device sends or receives data that complies with the PCIE protocol at a standard rate, and the PIPE interface of the integrated circuit to be verified sends or receives data that complies with the PCIE protocol at a specified rate that is lower than the standard rate. In order to ensure that the data transmission between the PIPE interface of the integrated circuit and the PIPE interface of the external device is normal, it is necessary to obtain the data that complies with the PCIE protocol sent by the PIPE interface of the integrated circuit at a specified rate that is lower than the standard rate, and then send the data to the PIPE interface of the external device at the standard rate. It is necessary to obtain the data that complies with the PCIE protocol sent by the PIPE interface of the external device at the standard rate, and then send the data to the PIPE interface of the integrated circuit at a specified rate that is lower than the standard rate.

[0004] In the related art, the commonly used interface data transmission scheme is: a rate processing module is set in the FPGA where the integrated circuit to be verified is located. Through the rate processing module, the data that complies with the PCIE protocol and is sent by the PIPE interface of the integrated circuit at a specified rate lower than the standard rate is obtained, and then the data is sent to the PIPE interface of the external device at the standard rate. Through the rate processing module, the data that complies with the PCIE protocol and is sent by the PIPE interface of the external device at the standard rate is obtained, and then the data is sent to the PIPE interface of the integrated circuit at a specified rate lower than the standard rate. The interface data transmission scheme in the related art requires setting a data conversion module in the FPGA where the integrated circuit is located, which will occupy a large amount of resources in the FPGA where the integrated circuit to be verified is located, reduce the efficiency and accuracy of the verification process of the integrated circuit, and is difficult to maintain. Summary of the invention

[0005] The present invention provides an interface data transmission system and method to solve the problem that the interface data transmission scheme in the related art will occupy a large amount of resources in the FPGA where the integrated circuit to be verified is located, reduce the efficiency and accuracy of the integrated circuit verification process, and is difficult to maintain.

[0006] According to one aspect of the present invention, there is provided an interface data transmission system, comprising: a master FPGA, a slave FPGA, and an external device corresponding to a circuit to be verified in the master FPGA;

[0007] The main FPGA is provided with a circuit to be verified, a first data conversion circuit and a first AURORA interaction circuit, and the circuit to be verified is provided with a PIPE interface;

[0008] The slave FPGA is provided with a second AURORA interaction circuit, a second data conversion circuit and a data rate processing circuit;

[0009] The master FPGA converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data through the first data conversion circuit, and sends the AURORA interface data to the second AURORA interaction circuit through the first AURORA interaction circuit; the slave FPGA converts the AURORA interface data received by the second AURORA interaction circuit into the gating signal and PIPE interface data through the second data conversion circuit, and sends the PIPE interface data to the PIPE interface of the external device at a standard rate through the data rate processing circuit;

[0010] The slave FPGA receives the PIPE interface data sent by the PIPE interface of the external device through the data rate processing circuit, converts the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data through the second data conversion circuit, and sends the AURORA interface data to the first AURORA interaction circuit through the second AURORA interaction circuit; the master FPGA converts the AURORA interface data received by the first AURORA interaction circuit into a PIPE valid signal and PIPE interface data through the first data conversion circuit, and sends the PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified.

[0011] The first data conversion circuit includes a gating signal generating module, a first data transmission asynchronous FIFO, a first protocol conversion module, a second protocol conversion module and a data reception asynchronous FIFO;

[0012] The gating signal generating module is used to generate a gating signal;

[0013] The data transmission asynchronous FIFO is used to send the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified to the first protocol conversion module;

[0014] The first protocol conversion module is used to convert the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data;

[0015] The second protocol conversion module is used to convert the AURORA interface data received by the first AURORA interaction circuit into a PIPE valid signal and PIPE interface data;

[0016] The data receiving asynchronous FIFO is used to send PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified.

[0017] The second data conversion circuit includes a third protocol conversion module, a gated clock generation module, a PIPE valid signal generation module, a second data transmission asynchronous FIFO and a fourth protocol conversion module;

[0018] The third protocol conversion module is used to convert the AURORA interface data received by the second AURORA interaction circuit into a gating signal and PIPE interface data;

[0019] The gated clock generating module is used to process the gated signal to generate a gated clock;

[0020] The PIPE valid signal generating module is used to generate a PIPE valid signal;

[0021] The second data sending asynchronous FIFO is used to send the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device to the fourth protocol conversion module;

[0022] The fourth protocol conversion module is used to convert the PIPE effective signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data.

[0023] According to another aspect of the present invention, there is provided an interface data transmission method, which is applied to the interface data transmission system provided by the present invention, and comprises:

[0024] The main FPGA converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data through the first data conversion circuit, and sends the AURORA interface data to the second AURORA interaction circuit through the first AURORA interaction circuit;

[0025] The AURORA interface data received by the second AURORA interactive circuit is converted from the FPGA into a gating signal and a PIPE interface data through a second data conversion circuit, and the PIPE interface data is sent to the PIPE interface of the external device at a standard rate through a data rate processing circuit.

[0026] The method further includes: receiving PIPE interface data sent by the PIPE interface of an external device from the FPGA through a data rate processing circuit, converting a PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data through a second data conversion circuit, and sending the AURORA interface data to the first AURORA interaction circuit through a second AURORA interaction circuit;

[0027] The main FPGA converts the AURORA interface data received by the first AURORA interactive circuit into a PIPE valid signal and PIPE interface data through a first data conversion circuit, and sends the PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified.

[0028] The first data conversion circuit includes a gating signal generating module, a first data transmission asynchronous FIFO, a first protocol conversion module, a second protocol conversion module and a data reception asynchronous FIFO;

[0029] The second data conversion circuit includes a third protocol conversion module, a gated clock generation module, a PIPE valid signal generation module, a second data transmission asynchronous FIFO and a fourth protocol conversion module.

[0030] The main FPGA converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data through the first data conversion circuit, including:

[0031] After the first data transmission asynchronous FIFO receives the PIPE interface data sent by the PIPE interface of the circuit to be verified, the first data conversion circuit controls the gating signal generating module to generate a gating signal, sends the gating signal to the first data transmission asynchronous FIFO and the first protocol conversion module, and controls the first data transmission asynchronous FIFO to send the PIPE interface data sent by the PIPE interface of the circuit to be verified to the first protocol conversion module;

[0032] The first data conversion circuit controls the first protocol conversion module to convert the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data, and sends the AURORA interface data to the first AURORA interaction circuit.

[0033] The FPGA converts the AURORA interface data received by the second AURORA interaction circuit into a gating signal and PIPE interface data through a second data conversion circuit, including:

[0034] After receiving the AURORA interface data sent by the first AURORA interaction circuit, the second AURORA interaction circuit sends the AURORA interface data to the third protocol conversion module of the second data conversion circuit;

[0035] The second data conversion circuit controls the third protocol conversion module to convert the AURORA interface data received by the second AURORA interaction circuit into a gating signal and PIPE interface data, sends the gating signal to the gated clock generation module, and sends the PIPE interface data to the data rate processing circuit.

[0036] The method converts the PIPE interface data sent by the PIPE interface of the external device and the PIPE valid signal into AURORA interface data through a second data conversion circuit, including:

[0037] The second data conversion circuit controls the PIPE valid signal generating module to generate a PIPE valid signal, sends the PIPE valid signal to the fourth protocol conversion module, and controls the second data transmission asynchronous FIFO to send the PIPE interface data sent by the PIPE interface of the external device to the fourth protocol conversion module after the second data transmission asynchronous FIFO receives the PIPE interface data sent by the PIPE interface of the external device sent by the data rate processing circuit;

[0038] The second data conversion circuit controls the fourth protocol conversion module to convert the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data, and sends the AURORA interface data to the second AURORA interaction circuit.

[0039] The main FPGA converts the AURORA interface data received by the first AURORA interactive circuit into a PIPE valid signal and PIPE interface data through a first data conversion circuit, and sends the PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified, including:

[0040] The first AURORA interaction circuit sends the received AURORA interface data to the second protocol conversion module of the first data conversion circuit;

[0041] The first data conversion circuit controls the second protocol conversion module to convert the AURORA interface data into a PIPE valid signal and PIPE interface data after receiving the AURORA interface data, and sends the PIPE valid signal and the PIPE interface data to the data receiving asynchronous FIFO;

[0042] The first data conversion circuit controls the data receiving asynchronous FIFO to send the PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified.

[0043] In the technical solution of the embodiment of the present invention, the main FPGA converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data through the first data conversion circuit, and sends the AURORA interface data to the second AURORA interaction circuit through the first AURORA interaction circuit; the slave FPGA converts the AURORA interface data received by the second AURORA interaction circuit into the gating signal and PIPE interface data through the second data conversion circuit, and sends the PIPE interface data to the PIPE interface of the external device at the standard rate through the data rate processing circuit, so that the PIPE interface data sent by the PIPE interface of the circuit to be verified and need to be sent to the PIPE interface of the external device is sent to the PIPE interface of the external device at the standard rate, thereby realizing data transmission from the PIPE interface of the circuit to be verified to the PIPE interface of the external device; the slave FPGA receives the PIPE interface data sent by the PIPE interface of the external device through the data rate processing circuit, converts the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data through the second data conversion circuit, and sends the AURORA interface data to the first AURORA interaction circuit through the second AURORA interaction circuit; the main FPGA The AURORA interface data received by the first AURORA interactive circuit is converted into a PIPE valid signal and PIPE interface data through a first data conversion circuit, and the PIPE interface data is sent to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified, so that the PIPE interface data sent by the PIPE interface of the external device that needs to be sent to the PIPE interface of the circuit to be verified is sent to the PIPE interface of the circuit to be verified at the preset rate, thereby realizing data transmission from the PIPE interface of the external device to the PIPE interface of the circuit to be verified, solving the problem that the interface data transmission scheme in the related art will occupy a large amount of resources in the FPGA where the integrated circuit to be verified is located, reducing the efficiency and accuracy of the verification process of the integrated circuit, and being difficult to maintain. Based on the first data conversion circuit and the first AURORA interactive circuit in the main FPGA, the second AURORA interactive circuit, the second data conversion circuit and the data rate processing circuit in the slave FPGA, during the verification process of the integrated circuit in the main FPGA, the data transmission between the PIPE interface of the integrated circuit and the PIPE interface of the external device can be accurately realized, occupying fewer resources in the FPGA where the integrated circuit is located, improving the efficiency and accuracy of the verification process of the integrated circuit, and being easy to maintain.

[0044] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 A structural diagram of an interface data transmission system provided in Embodiment 1 of the present invention.

[0047] Figure 2 A schematic structural diagram of a first data conversion circuit provided in Embodiment 1 of the present invention.

[0048] Figure 3 A schematic diagram of the structure of a second data conversion circuit provided in Embodiment 1 of the present invention.

[0049] Figure 4 This is a flow chart of an interface data transmission method provided in Embodiment 2 of the present invention.

[0050] Figure 5 This is a flowchart of an interface data transmission method provided in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "target", "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprise", "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] Embodiment 1

[0054] Figure 1 This is a schematic diagram of the structure of an interface data transmission system provided by Embodiment 1 of the present invention. This embodiment is applicable to the case where data is transmitted between the PIPE interface of the integrated circuit and the PIPE interface of the external device during the verification process of the integrated circuit. Figure 1 As shown, the interface data transmission system may specifically include: a master FPGA 101, a slave FPGA 102, and an external device 104 corresponding to the circuit to be verified 103 in the master FPGA 101, and its structure and function are described below.

[0055] The main FPGA 101 is provided with a circuit to be verified 103 , a first data conversion circuit 105 and a first AURORA interaction circuit 106 , and the circuit to be verified 103 is provided with a PIPE interface.

[0056] The slave FPGA 102 is provided with a second AURORA interaction circuit 107 , a second data conversion circuit 108 and a data rate processing circuit 109 .

[0057] The main FPGA 101 converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified 103 into AURORA interface data through the first data conversion circuit 105, and sends the AURORA interface data to the second AURORA interaction circuit 107 through the first AURORA interaction circuit 106; the slave FPGA 102 converts the AURORA interface data received by the second AURORA interaction circuit 107 into the gating signal and PIPE interface data through the second data conversion circuit 108, and sends the PIPE interface data to the PIPE interface of the external device 104 at the standard rate through the data rate processing circuit 109.

[0058] The slave FPGA 102 receives the PIPE interface data sent by the PIPE interface of the external device 104 through the data rate processing circuit 109, converts the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device 104 into AURORA interface data through the second data conversion circuit 108, and sends the AURORA interface data to the first AURORA interaction circuit 106 through the second AURORA interaction circuit 107; the main FPGA 101 converts the AURORA interface data received by the first AURORA interaction circuit 106 into a PIPE valid signal and PIPE interface data through the first data conversion circuit 105, and sends the PIPE interface data to the PIPE interface of the circuit to be verified 103 at a preset rate corresponding to the PIPE interface of the circuit to be verified 103.

[0059] Optionally, the master FPGA 101 may be an FPGA for carrying the circuit to be verified 103. The slave FPGA 102 may be an FPGA connected to the master FPGA 101 and used to cooperate with the master FPGA 101 to complete data transmission between the PIPE interface of the circuit to be verified 103 and the PIPE interface of the external device 104. The circuit to be verified 103 may be an integrated circuit that needs to be verified. The external device 104 corresponding to the circuit to be verified 103 may be an electronic device that needs to transmit data with the circuit to be verified 103 during the verification process of the circuit to be verified 103. A PIPE interface is provided in the circuit to be verified 103. A PIPE interface is provided in the external device 104. The PIPE interface is an interface for transmitting data based on the PCIE protocol. The PIPE interface data may be data sent by the PIPE interface that complies with the PCIE protocol. During the verification process of the circuit to be verified 103, PIPE interface data needs to be sent to the PIPE interface of the external device 104 through the PIPE interface of the circuit to be verified 103, and PIPE interface data sent by the PIPE interface of the external device 104 needs to be received through the PIPE interface of the circuit to be verified 103.

[0060] Optionally, the AURORA protocol is a scalable lightweight link layer protocol for moving data between point-to-point serial links. The AURORA interface data may be data that complies with the AURORA protocol.

[0061] Optionally, the first data conversion circuit 105 may be a hardware circuit provided in the main FPGA 101 for converting the original data into AURORA interface data or converting the AURORA interface data converted based on the original data into the original data. The first AURORA interaction circuit 106 may be a hardware circuit provided in the main FPGA 101 for transmitting AURORA interface data.

[0062] Optionally, the second AURORA interaction circuit 107 may be a hardware circuit for transmitting AURORA interface data set in the FPGA 102. The second data conversion circuit 108 may be a hardware circuit for converting AURORA interface data obtained based on the original data conversion into original data or converting original data into AURORA interface data set in the FPGA 102. The data rate processing circuit 109 may be a hardware circuit for sending PIPE interface data to the PIPE interface of the external device 104 at a standard rate or receiving PIPE interface data sent by the PIPE interface of the external device 104 at a standard rate set in the FPGA 102.

[0063] Optionally, the standard rate may be a rate at which the PIPE interface of the external device 104 sends or receives PIPE interface data. The preset rate corresponding to the PIPE interface of the circuit to be verified 103 may be a rate at which the PIPE interface of the circuit to be verified 103 sends or receives PIPE interface data. The preset rate is lower than the standard rate.

[0064] Optionally, the first AURORA interactive circuit 106 is connected to the second AURORA interactive circuit 107 via an AURORA link. The first AURORA interactive circuit 106 can send AURORA interface data to the second AURORA interactive circuit 107, and can also receive AURORA interface data sent by the second AURORA interactive circuit 107. The second AURORA interactive circuit 107 can send AURORA interface data to the first AURORA interactive circuit 106, and can also receive AURORA interface data sent by the first AURORA interactive circuit 106.

[0065] Optional, Figure 2 The first data conversion circuit 105 includes a gating signal generating module 1051, a first data transmission asynchronous FIFO 1052, a first protocol conversion module 1053, a second protocol conversion module 1054 and a data reception asynchronous FIFO 1055. A gating signal generating module 1051 is used to generate a gating signal; a first data sending asynchronous FIFO 1052 is used to send the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified 103 to the first protocol conversion module 1053; the first protocol conversion module 1053 is used to convert the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified 103 into AURORA interface data; a second protocol conversion module 1054 is used to convert the AURORA interface data received by the first AURORA interactive circuit 106 into a PIPE valid signal and PIPE interface data; a data receiving asynchronous FIFO 1055 is used to send the PIPE interface data to the PIPE interface of the circuit to be verified 103 at a preset rate corresponding to the PIPE interface of the circuit to be verified 103.

[0066] Optionally, the gating signal may be a signal carrying relevant information of the PIPE interface clock and the AXI interface clock in the main FPGA 101. The PIPE interface clock in the main FPGA 101 may be the working clock of the circuit to be verified 103. The AXI interface clock in the main FPGA 101 may be the working clock of the first AURORA interactive circuit 106. The gating signal generating module 1051 may be a hardware circuit for generating a gating signal provided in the first data conversion circuit 105. The first data transmission asynchronous FIFO 1052 may be an asynchronous FIFO provided in the first data conversion circuit 105 for sending the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified 103 to the first protocol conversion module 1053. The first protocol conversion module 1053 may be a hardware circuit provided in the first data conversion circuit 105 for converting the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified 103 into AURORA interface data. The second protocol conversion module 1054 may be a hardware circuit provided in the first data conversion circuit 105 for converting the AURORA interface data received by the first AURORA interactive circuit 106 into original data, that is, converting the AURORA interface data received by the first AURORA interactive circuit 106 into a PIPE valid signal and PIPE interface data. The data receiving asynchronous FIFO 1055 may be an asynchronous FIFO provided in the first data conversion circuit 105 for sending the PIPE interface data to the PIPE interface of the circuit to be verified 103 at a preset rate corresponding to the PIPE interface of the circuit to be verified 103.

[0067] Optional, Figure 3 A schematic diagram of the structure of a second data conversion circuit provided in Embodiment 1 of the present invention. The second data conversion circuit 108 includes a third protocol conversion module 1081, a gated clock generation module 1082, a PIPE valid signal generation module 1083, a second data transmission asynchronous FIFO 1084, and a fourth protocol conversion module 1085. The third protocol conversion module 1081 is used to convert the AURORA interface data received by the second AURORA interactive circuit 107 into a gated signal and PIPE interface data; the gated clock generation module 1082 is used to process the gated signal and generate a gated clock; the PIPE valid signal generation module 1083 is used to generate a PIPE valid signal; the second data transmission asynchronous FIFO 1084 is used to send the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device 104 to the fourth protocol conversion module 1085; the fourth protocol conversion module 1085 is used to convert the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device 104 into AURORA interface data.

[0068] Optionally, the third protocol conversion module 1081 may be a hardware circuit provided in the second data conversion circuit 108 for converting the AURORA interface data received by the second AURORA interactive circuit 107 into original data, that is, converting the AURORA interface data received by the second AURORA interactive circuit 107 into a gating signal and PIPE interface data. The gated clock generation module 1082 may be a hardware circuit provided in the second data conversion circuit 108 for processing the gating signal, generating a gating clock, and providing the gating clock to the data rate processing circuit 109 as the working clock of the data rate processing circuit 109. The gated clock in the slave FPGA 102 may be a clock generated by the gated clock generation module 1082 based on the gating signal. The AXI interface clock in the slave FPGA 102 may be the working clock of the second AURORA interactive circuit 107. The PIPE valid signal may be a signal for adjusting the clock domain of the data to the PIPE interface clock in the master FPGA 101. The PIPE valid signal generation module 1083 may be a hardware circuit provided in the second data conversion circuit 108 for generating a PIPE valid signal. The second data transmission asynchronous FIFO 1084 may be a hardware circuit provided in the second data conversion circuit 108 for transmitting the PIPE valid signal and the PIPE interface data transmitted by the PIPE interface of the external device 104 to the fourth protocol conversion module 1085. The fourth protocol conversion module 1085 may be a hardware circuit provided in the second data conversion circuit 108 for converting the PIPE valid signal and the PIPE interface data transmitted by the PIPE interface of the external device 104 into AURORA interface data.

[0069] Optionally, the main FPGA 101 converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified 103 into AURORA interface data through the first data conversion circuit 105, including: after the first data sending asynchronous FIFO 1052 receives the PIPE interface data sent by the PIPE interface of the circuit to be verified 103, the first data conversion circuit 105 controls the gating signal generating module 1051 to generate a gating signal, sends the gating signal to the first data sending asynchronous FIFO 1052 and the first protocol conversion module 1053, controls the first data sending asynchronous FIFO 1052 to send the PIPE interface data sent by the PIPE interface of the circuit to be verified 103 to the first protocol conversion module 1053; the first data conversion circuit 105 controls the first protocol conversion module 1053 to convert the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified 103 into AURORA interface data, and sends the AURORA interface data to the first AURORA interaction circuit 106.

[0070] Optionally, the PIPE interface of the circuit to be verified 103 will send the PIPE interface data that needs to be sent to the PIPE interface of the external device 104 to the first data transmission asynchronous FIFO 1052. After the first data transmission asynchronous FIFO 1052 receives the PIPE interface data sent by the PIPE interface of the circuit to be verified 103, the first data conversion circuit 105 can control the gating signal generation module 1051 to generate a gating signal, send the gating signal to the first data transmission asynchronous FIFO 1052 and the first protocol conversion module 1053, and control the first data transmission asynchronous FIFO 1052 to send the PIPE interface data sent by the PIPE interface of the circuit to be verified 103 to the first protocol conversion module 1053. Then the first data conversion circuit 105 controls the first protocol conversion module 1053 to convert the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified 103 into AURORA interface data, and send the AURORA interface data to the first AURORA interaction circuit 106.

[0071] Optionally, sending the AURORA interface data to the second AURORA interaction circuit 107 through the first AURORA interaction circuit 106 includes: after receiving the AURORA interface data sent by the first protocol conversion module 1053, the first AURORA interaction circuit 106 sends the AURORA interface data to the second AURORA interaction circuit 107.

[0072] Optionally, the AURORA interface data received by the second AURORA interaction circuit 107 is converted into a gating signal and a PIPE interface data from the FPGA 102 through the second data conversion circuit 108, including: after receiving the AURORA interface data sent by the first AURORA interaction circuit 106, the second AURORA interaction circuit 107 sends the AURORA interface data to the third protocol conversion module 1081 of the second data conversion circuit 108; the second data conversion circuit 108 controls the third protocol conversion module 1081 to convert the AURORA interface data received by the second AURORA interaction circuit 107 into a gating signal and PIPE interface data, sends the gating signal to the gated clock generation module 1082, and sends the PIPE interface data to the data rate processing circuit 109.

[0073] Optionally, after receiving the AURORA interface data sent by the first AURORA interaction circuit 106, the second AURORA interaction circuit 107 will send the AURORA interface data to the third protocol conversion module 1081 of the second data conversion circuit 108. The second data conversion circuit 108 can control the third protocol conversion module 1081 to convert the AURORA interface data received by the second AURORA interaction circuit 107 based on the gating signal and the PIPE interface data into the gating signal and the PIPE interface data, and then send the gating signal to the gating clock generation module 1082, and send the PIPE interface data to the data rate processing circuit 109. The PIPE interface data is the PIPE interface data sent by the PIPE interface of the circuit to be verified 103 and needs to be sent to the PIPE interface of the external device 104. After receiving the gating signal, the gating clock generation module 1082 processes the gating signal, generates a gating clock, and provides the gating clock to the data rate processing circuit 109 as the working clock of the data rate processing circuit 109.

[0074] Optionally, the PIPE interface data is sent to the PIPE interface of the external device 104 at a standard rate through the data rate processing circuit 109, including: after receiving the PIPE interface data, the data rate processing circuit 109 sends the PIPE interface data to the PIPE interface of the external device 104 at the standard rate, thereby sending the PIPE interface data that needs to be sent to the PIPE interface of the external device 104 sent by the PIPE interface of the circuit to be verified 103 to the PIPE interface of the external device 104 at the standard rate, thereby realizing data transmission from the PIPE interface of the circuit to be verified 103 to the PIPE interface of the external device 104.

[0075] Optionally, the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device 104 are converted into AURORA interface data through the second data conversion circuit 108, including: after the second data sending asynchronous FIFO 1084 receives the PIPE interface data sent by the PIPE interface of the external device 104 sent by the data rate processing circuit 109, the second data conversion circuit 108 controls the PIPE valid signal generation module 1083 to generate a PIPE valid signal, sends the PIPE valid signal to the fourth protocol conversion module 1085, and controls the second data sending asynchronous FIFO 1084 to send the PIPE interface data sent by the PIPE interface of the external device 104 to the fourth protocol conversion module 1085; the second data conversion circuit 108 controls the fourth protocol conversion module 1085 to convert the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device 104 into AURORA interface data, and sends the AURORA interface data to the second AURORA interaction circuit 107.

[0076] Optionally, the PIPE interface of the external device 104 sends the PIPE interface data that needs to be sent to the PIPE interface of the circuit to be verified 103 to the data rate processing circuit 109. After receiving the PIPE interface data sent by the PIPE interface of the external device 104, the data rate processing circuit 109 sends the PIPE interface data sent by the PIPE interface of the external device 104 to the second data transmission asynchronous FIFO 1084. After the second data transmission asynchronous FIFO 1084 receives the PIPE interface data sent by the PIPE interface of the external device 104 sent by the data rate processing circuit 109, the second data conversion circuit 108 can control the PIPE valid signal generation module 1083 to generate a PIPE valid signal, send the PIPE valid signal to the fourth protocol conversion module 1085, and control the second data transmission asynchronous FIFO 1084 to send the PIPE interface data sent by the PIPE interface of the external device 104 to the fourth protocol conversion module 1085. Then the second data conversion circuit 108 controls the fourth protocol conversion module 1085 to convert the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device 104 into AURORA interface data, and sends the AURORA interface data to the second AURORA interaction circuit 107 .

[0077] Optionally, sending the AURORA interface data to the first AURORA interaction circuit 106 through the second AURORA interaction circuit 107 includes: after receiving the AURORA interface data sent by the fourth protocol conversion module 1085, the second AURORA interaction circuit 107 sends the AURORA interface data to the first AURORA interaction circuit 106.

[0078] Optionally, the main FPGA 101 converts the AURORA interface data received by the first AURORA interactive circuit 106 into a PIPE valid signal and PIPE interface data through the first data conversion circuit 105, and sends the PIPE interface data to the PIPE interface of the circuit 103 to be verified at a preset rate corresponding to the PIPE interface of the circuit 103 to be verified, including: the first AURORA interactive circuit 106 sends the received AURORA interface data to the second protocol conversion module 1054 of the first data conversion circuit 105; the first data conversion circuit 105 controls the second protocol conversion module 1054 to convert the AURORA interface data into a PIPE valid signal and PIPE interface data after receiving the AURORA interface data, and sends the PIPE valid signal and the PIPE interface data to the data receiving asynchronous FIFO 1055; the first data conversion circuit 105 controls the data receiving asynchronous FIFO 1055 to send the PIPE interface data to the PIPE interface of the circuit 103 to be verified at a preset rate corresponding to the PIPE interface of the circuit 103 to be verified.

[0079] Optionally, after receiving the AURORA interface data sent by the second AURORA interaction circuit 107, the first AURORA interaction circuit 106 sends the received AURORA interface data to the second protocol conversion module 1054 of the first data conversion circuit 105. The first data conversion circuit 105 can control the second protocol conversion module 1054 to convert the AURORA interface data obtained based on the PIPE valid signal and the PIPE interface data into a PIPE valid signal and PIPE interface data after receiving the AURORA interface data, and send the PIPE valid signal and the PIPE interface data to the data receiving asynchronous FIFO 1055. The PIPE interface data is the PIPE interface data sent by the PIPE interface of the external device 104 and needs to be sent to the PIPE interface of the circuit to be verified 103. Then the first data conversion circuit 105 controls the data receiving asynchronous FIFO 1055 to send the PIPE interface data to the PIPE interface of the circuit to be verified 103 at a preset rate corresponding to the PIPE interface of the circuit to be verified 103, thereby sending the PIPE interface data that needs to be sent to the PIPE interface of the circuit to be verified 103 by the PIPE interface of the external device 104 to the PIPE interface of the circuit to be verified 103 at the preset rate, thereby realizing data transmission from the PIPE interface of the external device 104 to the PIPE interface of the circuit to be verified 103. The first data conversion circuit 105 can control the data receiving asynchronous FIFO 1055 to send a PIPE valid signal to the circuit to be verified 103, so that the circuit to be verified 103 can adjust the clock domain of the PIPE interface data to the PIPE interface clock in the main FPGA 101 according to the circuit to be verified 103.

[0080] In the technical solution of the embodiment of the present invention, the main FPGA converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data through the first data conversion circuit, and sends the AURORA interface data to the second AURORA interaction circuit through the first AURORA interaction circuit; the slave FPGA converts the AURORA interface data received by the second AURORA interaction circuit into the gating signal and PIPE interface data through the second data conversion circuit, and sends the PIPE interface data to the PIPE interface of the external device at the standard rate through the data rate processing circuit, so that the PIPE interface data sent by the PIPE interface of the circuit to be verified and need to be sent to the PIPE interface of the external device is sent to the PIPE interface of the external device at the standard rate, thereby realizing data transmission from the PIPE interface of the circuit to be verified to the PIPE interface of the external device; the slave FPGA receives the PIPE interface data sent by the PIPE interface of the external device through the data rate processing circuit, converts the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data through the second data conversion circuit, and sends the AURORA interface data to the first AURORA interaction circuit through the second AURORA interaction circuit; the main FPGA The AURORA interface data received by the first AURORA interactive circuit is converted into a PIPE valid signal and PIPE interface data through a first data conversion circuit, and the PIPE interface data is sent to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified, so that the PIPE interface data sent by the PIPE interface of the external device that needs to be sent to the PIPE interface of the circuit to be verified is sent to the PIPE interface of the circuit to be verified at the preset rate, thereby realizing data transmission from the PIPE interface of the external device to the PIPE interface of the circuit to be verified, solving the problem that the interface data transmission scheme in the related art will occupy a large amount of resources in the FPGA where the integrated circuit to be verified is located, reducing the efficiency and accuracy of the verification process of the integrated circuit, and being difficult to maintain. Based on the first data conversion circuit and the first AURORA interactive circuit in the main FPGA, the second AURORA interactive circuit, the second data conversion circuit and the data rate processing circuit in the slave FPGA, during the verification process of the integrated circuit in the main FPGA, the data transmission between the PIPE interface of the integrated circuit and the PIPE interface of the external device can be accurately realized, occupying fewer resources in the FPGA where the integrated circuit is located, improving the efficiency and accuracy of the verification process of the integrated circuit, and being easy to maintain.

[0081] In an optional implementation of the embodiment of the present invention, optionally, the operating frequency of the PIPE interface clock in the main FPGA is 20 MHZ, provided by an external clock source. The operating frequency of the AXI interface clock in the main FPGA is 32 MHZ, provided by the first AURORA interaction circuit.

[0082] In an optional implementation of an embodiment of the present invention, optionally, the write enable signal of the first data transmission asynchronous FIFO in the first data conversion circuit is a non-full signal, and the read enable signal is jointly generated by the AXI interface clock, the PIPE interface clock and the first data transmission asynchronous FIFO itself. The write clock is the PIPE interface clock, and the read clock is the AXI interface clock. When the AXI interface clock frequency is higher than or equal to twice the PIPE interface clock frequency, each rising edge of the PIPE interface clock is sampled by the AXI interface clock, and each rising edge of the PIPE interface clock will generate a pulse of the length of the AXI clock cycle, and the pulse signal is used as a read enable. When the AXI interface clock frequency is lower than twice the PIPE interface clock frequency, the read enable signal is a non-empty signal of the first data transmission asynchronous FIFO. The read enable signal will be sent to the slave FPGA along with the PIPE interface data as a gating signal of the AXI interface clock of the slave FGPA.

[0083] In an optional implementation of an embodiment of the present invention, optionally, after receiving the PIPE interface data and the gated clock, the second data conversion circuit uses the gated clock as the transmission clock of the second data conversion circuit and as the write clock of the second data transmission asynchronous FIFO. The write enable signal of the second data transmission asynchronous FIFO is a non-full signal. When the AXI interface clock frequency is higher than or equal to twice the PIPE interface clock frequency, each rising edge of the PIPE interface clock is sampled by the AXI interface clock, and each rising edge of the PIPE interface clock will generate a pulse of the length of the AXI clock cycle, and the pulse signal is used as a read enable. When the AXI interface clock frequency is less than twice the PIPE interface clock frequency, the read enable signal is a non-empty signal of the second data transmission asynchronous FIFO. The read enable signal will be sent to the main FPGA along with the PIPE interface data as a PIPE valid signal.

[0084] In an optional implementation of an embodiment of the present invention, optionally, when the first data conversion circuit receives PIPE interface data and a PIPE valid signal, the write clock of the data receiving asynchronous FIFO is the AXI interface clock, and the read clock of the data receiving asynchronous FIFO is the PIPE interface clock. The read enable signal is a non-empty signal, and the write enable is the received PIPE valid signal.

[0085] In an optional implementation of the embodiment of the present invention, since most of the system is implemented inside the FPGA device, the technician can observe the data received and sent in the system through the debugging means in the FPGA, such as VIO, lia, etc., and quickly locate the problems in the first data conversion circuit and the second data conversion circuit. The technician can also analyze the interactive data between the data rate processing circuit and the external device through the external protocol analyzer hardware to locate the problems in the data rate processing circuit.

[0086] In an optional implementation of the embodiment of the present invention, optionally, the first AURORA interactive circuit is connected to the second AURORA interactive circuit via an AURORA link. The rate of the AURORA link is 10.3125 GBPS, the number of AURORA links is 8, and an 8b10b encoding method is adopted.

[0087] In an optional implementation of the embodiment of the present invention, optionally, the PIPE interface of the circuit to be verified is GEN5, the number of links is 8, the sending bit width of the PIPE interface is 440 BITS, and the receiving bit width of the PIPE interface is 433 BITS. The sending bit width and receiving bit width of the first AURORA interactive circuit and the second AURORA interactive circuit are both 512 BITS.

[0088] Embodiment 2

[0089] Figure 4 This is a flow chart of an interface data transmission method provided in Embodiment 2 of the present invention. This method can be executed by the interface data transmission system provided in Embodiment 2 of the present invention. Figure 4 As shown, the method of this embodiment specifically includes:

[0090] Step 201: The main FPGA converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data through the first data conversion circuit, and sends the AURORA interface data to the second AURORA interaction circuit through the first AURORA interaction circuit.

[0091] Optionally, the main FPGA converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data through the first data conversion circuit, including: after the first data sending asynchronous FIFO receives the PIPE interface data sent by the PIPE interface of the circuit to be verified, the first data conversion circuit controls the gating signal generating module to generate a gating signal, sends the gating signal to the first data sending asynchronous FIFO and the first protocol conversion module, and controls the first data sending asynchronous FIFO to send the PIPE interface data sent by the PIPE interface of the circuit to be verified to the first protocol conversion module; the first data conversion circuit controls the first protocol conversion module to convert the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data, and sends the AURORA interface data to the first AURORA interaction circuit.

[0092] Step 202: Convert the AURORA interface data received by the second AURORA interactive circuit into a gating signal and PIPE interface data from the FPGA through a second data conversion circuit, and send the PIPE interface data to the PIPE interface of the external device at a standard rate through a data rate processing circuit.

[0093] Optionally, the AURORA interface data received by the second AURORA interaction circuit is converted into a gating signal and PIPE interface data from the FPGA through a second data conversion circuit, including: after receiving the AURORA interface data sent by the first AURORA interaction circuit, the second AURORA interaction circuit sends the AURORA interface data to a third protocol conversion module of the second data conversion circuit; the second data conversion circuit controls the third protocol conversion module to convert the AURORA interface data received by the second AURORA interaction circuit into a gating signal and PIPE interface data, sends the gating signal to the gated clock generation module, and sends the PIPE interface data to the data rate processing circuit.

[0094] The technical solution of the embodiment of the present invention can be based on the first data conversion circuit and the first AURORA interaction circuit in the main FPGA, the second AURORA interaction circuit, the second data conversion circuit and the data rate processing circuit in the slave FPGA. During the verification process of the integrated circuit in the main FPGA, it can accurately realize the data transmission from the PIPE interface of the integrated circuit to the PIPE interface of the external device, occupying fewer resources in the FPGA where the integrated circuit is located, improving the efficiency and accuracy of the verification process of the integrated circuit, and being easy to maintain.

[0095] Embodiment 3

[0096] Figure 5 This is a flow chart of an interface data transmission method provided in Embodiment 3 of the present invention. This method can be executed by the interface data transmission system provided in Embodiment 3 of the present invention. Figure 5 As shown, the method of this embodiment specifically includes:

[0097] Step 301: Receive PIPE interface data sent by the PIPE interface of an external device from the FPGA through a data rate processing circuit, convert a PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data through a second data conversion circuit, and send the AURORA interface data to the first AURORA interaction circuit through a second AURORA interaction circuit.

[0098] Optionally, the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device are converted into AURORA interface data through a second data conversion circuit, including: after the second data sending asynchronous FIFO receives the PIPE interface data sent by the PIPE interface of the external device sent by the data rate processing circuit, the second data conversion circuit controls the PIPE valid signal generating module to generate a PIPE valid signal, sends the PIPE valid signal to the fourth protocol conversion module, and controls the second data sending asynchronous FIFO to send the PIPE interface data sent by the PIPE interface of the external device to the fourth protocol conversion module; the second data conversion circuit controls the fourth protocol conversion module to convert the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data, and sends the AURORA interface data to the second AURORA interaction circuit.

[0099] Step 302: The main FPGA converts the AURORA interface data received by the first AURORA interactive circuit into a PIPE valid signal and PIPE interface data through a first data conversion circuit, and sends the PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified.

[0100] Optionally, the main FPGA converts the AURORA interface data received by the first AURORA interactive circuit into a PIPE valid signal and PIPE interface data through a first data conversion circuit, and sends the PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified, including: the first AURORA interactive circuit sends the received AURORA interface data to the second protocol conversion module of the first data conversion circuit; the first data conversion circuit controls the second protocol conversion module to convert the AURORA interface data into a PIPE valid signal and PIPE interface data after receiving the AURORA interface data, and sends the PIPE valid signal and the PIPE interface data to the data reception asynchronous FIFO; the first data conversion circuit controls the data reception asynchronous FIFO to send the PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified.

[0101] The technical solution of the embodiment of the present invention can be based on the first data conversion circuit and the first AURORA interaction circuit in the main FPGA, the second AURORA interaction circuit, the second data conversion circuit and the data rate processing circuit in the slave FPGA. During the verification process of the integrated circuit in the main FPGA, it can accurately realize the data transmission from the PIPE interface of the external device to the PIPE interface of the integrated circuit, occupying fewer resources in the FPGA where the integrated circuit is located, improving the efficiency and accuracy of the verification process of the integrated circuit, and facilitating maintenance.

[0102] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0103] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An interface data transmission system, characterized in that: include: A master FPGA, a slave FPGA, and an external device corresponding to the circuit to be verified in the master FPGA; The main FPGA is provided with a circuit to be verified, a first data conversion circuit and a first AURORA interaction circuit, and the circuit to be verified is provided with a PIPE interface; The slave FPGA is provided with a second AURORA interaction circuit, a second data conversion circuit and a data rate processing circuit; The master FPGA converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data through the first data conversion circuit, and sends the AURORA interface data to the second AURORA interaction circuit through the first AURORA interaction circuit; the slave FPGA converts the AURORA interface data received by the second AURORA interaction circuit into the gating signal and PIPE interface data through the second data conversion circuit, and sends the PIPE interface data to the PIPE interface of the external device at a standard rate through the data rate processing circuit; The slave FPGA receives the PIPE interface data sent by the PIPE interface of the external device through the data rate processing circuit, converts the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data through the second data conversion circuit, and sends the AURORA interface data to the first AURORA interaction circuit through the second AURORA interaction circuit; the master FPGA converts the AURORA interface data received by the first AURORA interaction circuit into a PIPE valid signal and PIPE interface data through the first data conversion circuit, and sends the PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified.

2. The interface data transmission system according to claim 1, characterized in that: The first data conversion circuit includes a gating signal generating module, a first data transmission asynchronous FIFO, a first protocol conversion module, a second protocol conversion module and a data reception asynchronous FIFO; The gating signal generating module is used to generate a gating signal; The data transmission asynchronous FIFO is used to send the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified to the first protocol conversion module; The first protocol conversion module is used to convert the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data; The second protocol conversion module is used to convert the AURORA interface data received by the first AURORA interaction circuit into a PIPE valid signal and PIPE interface data; The data receiving asynchronous FIFO is used to send PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified.

3. The interface data transmission system according to claim 1, characterized in that: The second data conversion circuit includes a third protocol conversion module, a gated clock generation module, a PIPE valid signal generation module, a second data transmission asynchronous FIFO and a fourth protocol conversion module; The third protocol conversion module is used to convert the AURORA interface data received by the second AURORA interaction circuit into a gating signal and PIPE interface data; The gated clock generating module is used to process the gated signal to generate a gated clock; The PIPE valid signal generating module is used to generate a PIPE valid signal; The second data sending asynchronous FIFO is used to send the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device to the fourth protocol conversion module; The fourth protocol conversion module is used to convert the PIPE effective signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data.

4. An interface data transmission method, applied to the interface data transmission system as claimed in claim 1, characterized in that: include: The main FPGA converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data through the first data conversion circuit, and sends the AURORA interface data to the second AURORA interaction circuit through the first AURORA interaction circuit; The AURORA interface data received by the second AURORA interactive circuit is converted from the FPGA into a gating signal and a PIPE interface data through a second data conversion circuit, and the PIPE interface data is sent to the PIPE interface of the external device at a standard rate through a data rate processing circuit.

5. The interface data transmission method according to claim 4, characterized in that: Also includes: Receive PIPE interface data sent by the PIPE interface of the external device from the FPGA through the data rate processing circuit, convert the PIPE effective signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data through the second data conversion circuit, and send the AURORA interface data to the first AURORA interaction circuit through the second AURORA interaction circuit; The main FPGA converts the AURORA interface data received by the first AURORA interactive circuit into a PIPE valid signal and PIPE interface data through a first data conversion circuit, and sends the PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified.

6. The interface data transmission method according to claim 5, characterized in that: The first data conversion circuit includes a gating signal generating module, a first data transmission asynchronous FIFO, a first protocol conversion module, a second protocol conversion module and a data reception asynchronous FIFO; The second data conversion circuit includes a third protocol conversion module, a gated clock generation module, a PIPE valid signal generation module, a second data transmission asynchronous FIFO and a fourth protocol conversion module.

7. The interface data transmission method according to claim 6, characterized in that: The main FPGA converts the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data through the first data conversion circuit, including: After the first data transmission asynchronous FIFO receives the PIPE interface data sent by the PIPE interface of the circuit to be verified, the first data conversion circuit controls the gating signal generating module to generate a gating signal, sends the gating signal to the first data transmission asynchronous FIFO and the first protocol conversion module, and controls the first data transmission asynchronous FIFO to send the PIPE interface data sent by the PIPE interface of the circuit to be verified to the first protocol conversion module; The first data conversion circuit controls the first protocol conversion module to convert the gating signal and the PIPE interface data sent by the PIPE interface of the circuit to be verified into AURORA interface data, and sends the AURORA interface data to the first AURORA interaction circuit.

8. The interface data transmission method according to claim 6, characterized in that: The FPGA converts the AURORA interface data received by the second AURORA interaction circuit into a gating signal and PIPE interface data through a second data conversion circuit, including: After receiving the AURORA interface data sent by the first AURORA interaction circuit, the second AURORA interaction circuit sends the AURORA interface data to the third protocol conversion module of the second data conversion circuit; The second data conversion circuit controls the third protocol conversion module to convert the AURORA interface data received by the second AURORA interaction circuit into a gating signal and PIPE interface data, sends the gating signal to the gated clock generation module, and sends the PIPE interface data to the data rate processing circuit.

9. The interface data transmission method according to claim 6, characterized in that: The method converts the PIPE interface data sent by the PIPE interface of the external device and the PIPE valid signal into AURORA interface data through a second data conversion circuit, including: The second data conversion circuit controls the PIPE valid signal generating module to generate a PIPE valid signal, sends the PIPE valid signal to the fourth protocol conversion module, and controls the second data transmission asynchronous FIFO to send the PIPE interface data sent by the PIPE interface of the external device to the fourth protocol conversion module after the second data transmission asynchronous FIFO receives the PIPE interface data sent by the PIPE interface of the external device sent by the data rate processing circuit; The second data conversion circuit controls the fourth protocol conversion module to convert the PIPE valid signal and the PIPE interface data sent by the PIPE interface of the external device into AURORA interface data, and sends the AURORA interface data to the second AURORA interaction circuit.

10. The interface data transmission method according to claim 6, characterized in that: The main FPGA converts the AURORA interface data received by the first AURORA interactive circuit into a PIPE valid signal and PIPE interface data through a first data conversion circuit, and sends the PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified, including: The first AURORA interaction circuit sends the received AURORA interface data to the second protocol conversion module of the first data conversion circuit; The first data conversion circuit controls the second protocol conversion module to convert the AURORA interface data into a PIPE valid signal and PIPE interface data after receiving the AURORA interface data, and sends the PIPE valid signal and the PIPE interface data to the data receiving asynchronous FIFO; The first data conversion circuit controls the data receiving asynchronous FIFO to send the PIPE interface data to the PIPE interface of the circuit to be verified at a preset rate corresponding to the PIPE interface of the circuit to be verified.

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