Low-frequency low-noise charge amplifier for eliminating IO leakage current

Abstract

The invention discloses a low-frequency low-noise charge amplifier for eliminating IO leakage current. According to the low-frequency low-noise charge amplifier, the negative feedback circuit is adopted for following in the design, so that the voltage drop at the two ends of the IO diode is kept small, and the IO leakage current is effectively reduced; meanwhile, temperature resistance compensation is introduced, so that the system can automatically adjust the voltage drop of the IO diode according to the temperature change, and the leakage current change caused by temperature fluctuation is further reduced. By applying the circuit, the performance and the stability of the charge amplifier are remarkably improved, and the reliability of high-precision signal processing is ensured especially in a low-frequency and low-noise precision measurement scene.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a low-frequency and low-noise charge amplifier for eliminating IO leakage current. Background Art

[0002] Charge amplifiers are widely used in precision measurement and sensing applications, especially in low-frequency environments. They can process extremely weak charge signals and are suitable for fields that require high-precision signal processing, such as seismic sensors, bioelectric signal detection, electron microscopes, and mass spectrometers.

[0003] The charge amplifier is usually used as the first stage in the detection system. In order to facilitate the external sensor probe, the charge amplifier will lead out the input port. At the same time, in order to avoid the introduction of static electricity from the input port of the charge amplifier, the input port needs to be protected from IO static electricity. The protection circuit is usually composed of a pair of reverse-biased diodes. One end of the pair of reverse-biased diodes is externally connected, and the other end is connected to the power supply and ground respectively. The large voltage drop across the reverse-biased diode will produce leakage current.

[0004] In a typical charge amplifier design, the noise characteristics of the front-end operational amplifier are critical to the system performance, especially in the low-frequency range, where the operational amplifier needs to have an extremely low input noise voltage (usually tens of nanovolts) to ensure effective capture of weak signals. Nevertheless, in order to further reduce the noise, system designers often add resistors with resistance values ​​as high as tens of G ohms at the input to reduce noise current and improve the signal-to-noise ratio.

[0005] However, the introduction of large-value resistors also brings new challenges. As the resistance value increases, the impact of the leakage current of the input (IO) interface becomes significant, especially when the temperature rises. When this leakage current passes through the large-value resistor, it generates a large offset voltage at the input of the amplifier, which in turn causes a significant offset or even saturation at the output of the charge amplifier. This situation not only affects the normal operation of the amplifier, but also reduces the measurement accuracy. Summary of the invention

[0006] In view of the above problems, the present invention hopes to provide a charge amplifier that can ensure low noise. The present invention hopes that the charge amplifier can work stably under various temperature environments. Therefore, an effective IO leakage current elimination circuit is introduced to ensure that the IO leakage current is always maintained at an extremely low level.

[0007] The present invention provides an IO leakage current elimination circuit applied to a low-frequency and low-noise charge amplifier, which can solve the IO leakage current problem of the charge amplifier in low-frequency and low-noise application scenarios.

[0008] Specifically, the present invention provides a low-frequency low-noise charge amplifier for eliminating IO leakage current. The low-frequency low-noise charge amplifier includes an IO leakage current elimination circuit and a charge amplifier circuit, wherein the IO leakage current elimination circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a first resistor R1, a first negative temperature coefficient resistor RT1, a second negative temperature coefficient resistor RT2, a first capacitor C1, a first current source I1, a second current source I2, and a first IO diode D1, a second IO diode D2, a third IO diode D3, and a fourth IO diode D4.

[0009] The first ends of the first current source I1, the second current source I2 and the first IO diode D1 are connected to the power supply VDD; the first ends of the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the fourth IO diode D4 are connected to the ground GND;

[0010] The first negative temperature coefficient resistor RT1 and the second negative temperature coefficient resistor RT2 are connected in series, the gate end of the first MOS tube M1 is connected to the midpoint between the first negative temperature coefficient resistor RT1 and the second negative temperature coefficient resistor RT2, the source end of the first MOS tube M1 is connected to the source end of the second MOS tube M2 and the second end of the first current source I1, the drain end of the first MOS tube M1 is connected to the gate end and the drain end of the third MOS tube M3 and the gate end of the fourth MOS tube M4; the gate end of the second MOS tube M2 is connected to the negative input end Vin- of the charge amplifier, the first end of the second IO diode D2 and the first end of the third IO diode D3, and the drain end of the second MOS tube M2 is connected to the drain end of the fourth MOS tube M4, the gate end of the fifth MOS tube M5 and the first end of the first resistor R1;

[0011] The drain end of the fifth MOS transistor M5 is connected to the second end of the second negative temperature coefficient resistor RT2; the second end of the second current source I2 is connected to the second end of the first negative temperature coefficient resistor RT1, the second end of the IO diode D1 and the second end of the second IO diode D2; the first end of the first capacitor C1 is connected to the second end of the resistor R1, and the second end is connected to the second end of the third IO diode D3 and the second end of the fourth IO diode D4.

[0012] In a preferred implementation, the low-noise charge amplifier circuit includes a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a third current source I3.

[0013] The source terminals of the eighth MOS tube M8, the ninth MOS tube M9 and the tenth MOS tube M10 are connected to the power supply VDD; the first end of the third resistor R3, the third capacitor C3 and the third current source I3 are grounded GND; the gate end of the sixth MOS tube M6 is the negative input end of the charge amplifier, the first end of the fourth resistor R4 and the first end of the fourth capacitor C4, the source end of the sixth MOS tube M6 is connected to the source end of the seventh MOS tube M7, the second end of the third resistor R3 and the second end of the third capacitor C3, and the drain end of the sixth MOS tube M6 is connected to the eighth MOS The drain end of the seventh MOS tube M7 is connected to the gate end of the tenth MOS tube M10, the drain end of the ninth MOS tube M9 and the first end of the second resistor R2; the first end of the second capacitor C2 is connected to the second end of the resistor R2, the second end of the second capacitor C2 is connected to the second end of the tenth MOS tube M10, the second end of the third power supply I3, the second end of R4 and the second end of C4, which is the output end of the charge amplifier.

[0014] In a preferred implementation, the low-frequency low-noise charge amplifier uses the negative feedback effect of the operational amplifier to achieve a small voltage drop across the IO diode, and eliminates the IO leakage current through temperature resistance compensation.

[0015] In a preferred implementation, the main body of the charge amplifier circuit adopts a two-stage Miller operational amplifier structure.

[0016] On the other hand, the present invention provides an IO leakage current elimination circuit, wherein the IO leakage current elimination circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a first resistor R1, a first negative temperature coefficient resistor RT1, a second negative temperature coefficient resistor RT2, a first capacitor C1, a first current source I1, a second current source I2, and a first IO diode D1, a second IO diode D2, a third IO diode D3, and a fourth IO diode D4.

[0017] The first ends of the first current source I1, the second current source I2 and the first IO diode D1 are connected to the power supply VDD; the first ends of the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the fourth IO diode D4 are connected to the ground GND;

[0018] The first negative temperature coefficient resistor RT1 and the second negative temperature coefficient resistor RT2 are connected in series, the gate end of the first MOS tube M1 is connected to the midpoint between the first negative temperature coefficient resistor RT1 and the second negative temperature coefficient resistor RT2, the source end of the first MOS tube M1 is connected to the source end of the second MOS tube M2 and the second end of the first current source I1, the drain end of the first MOS tube M1 is connected to the gate end and the drain end of the third MOS tube M3 and the gate end of the fourth MOS tube M4; the gate end of the second MOS tube M2 is connected to the negative input end Vin- of the charge amplifier, the first end of the second IO diode D2 and the first end of the third IO diode D3, and the drain end of the second MOS tube M2 is connected to the drain end of the fourth MOS tube M4, the gate end of the fifth MOS tube M5 and the first end of the first resistor R1;

[0019] The drain end of the fifth MOS transistor M5 is connected to the second end of the second negative temperature coefficient resistor RT2; the second end of the second current source I2 is connected to the second end of the first negative temperature coefficient resistor RT1, the second end of the IO diode D1 and the second end of the second IO diode D2; the first end of the first capacitor C1 is connected to the second end of the resistor R1, and the second end is connected to the second end of the third IO diode D3 and the second end of the fourth IO diode D4.

[0020] The IO leakage current elimination circuit for low-noise charge amplifiers provided by the present invention adopts a negative feedback circuit to keep the voltage drop across the IO diode small, thereby effectively reducing the IO leakage current; at the same time, temperature resistance compensation is introduced to enable the system to automatically adjust the voltage drop of the IO diode according to temperature changes, further reducing the leakage current changes caused by temperature fluctuations. The application of this technology significantly improves the performance and stability of the charge amplifier, especially in low-frequency, low-noise precision measurement scenarios, ensuring the reliability of high-precision signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 IO leakage current elimination circuit in the amplifier of the present invention

[0022] Figure 2 The main circuit of the low noise charge amplifier in the present invention is

[0023] Figure 3 The result diagram of IO leakage current in the present invention is DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of this application more clear, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain this application and are not used to limit this application.

[0025] In this embodiment, a low-frequency and low-noise charge amplifier with a wide temperature range is provided, which includes two partial IO leakage current elimination circuits and an amplifier main circuit.

[0026] like Figure 1 As shown, the IO leakage current elimination circuit of the present application includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a resistor R1, a first negative temperature coefficient resistor RT1, a second negative temperature coefficient resistor RT2, a first capacitor C1, a first current source I1, a second current source I2, and an IO diode D1, a second IO diode D2, a third IO diode D3, and a fourth IO diode D4.

[0027] The first ends of the first current source I1, the second current source I2 and the IO diode D1 are connected to the power supply VDD; the first ends of the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the fourth IO diode D4 are connected to the ground GND;

[0028] The gate end of the MOS tube M1 is connected to the first end of the first negative temperature coefficient resistor RT1 and the second negative temperature coefficient resistor RT2 (the first negative temperature coefficient resistor RT1 and the second negative temperature coefficient resistor RT2 are connected in series, and the gate end of the MOS tube M1 is connected to the connection point between the two), the source end of M1 is connected to the source end of the second MOS tube M2 and the second end of the first current source I1, and the drain end of the MOS tube M1 is connected to the gate end of the third MOS tube M3, the drain end of the third MOS tube M3 and the gate end of the fourth MOS tube M4; the gate end of the second MOS tube M2 is connected to the negative input terminal Vin- of the charge amplifier, the first end of the second IO diode D2 and the first end of the third IO diode D3, and the drain end of the second MOS tube M2 is connected to the drain end of the fourth MOS tube M4, the gate end of the fifth MOS tube M5 and the first end of R1.

[0029] The drain end of the fifth MOS tube M5 is connected to the second end of the second negative temperature coefficient resistor RT2; the second end of the current source second current source I2 is connected to the second end of the first negative temperature coefficient resistor RT1, the second end of the IO diode D1 and the second end of the second IO diode D2; the first end of the first capacitor C1 is connected to the second end of the resistor R1, and the second end is connected to the second end of the third IO diode D3 and the second end of the fourth IO diode D4.

[0030] Figure 1In the embodiment, the gate terminal of the second MOS tube M2 is the negative input terminal of the charge amplifier. Through the negative feedback of the operational amplifier, the gate terminal voltage of M1 is approximately equal to the gate terminal voltage of the second MOS tube M2, so that the voltage difference across the second IO diode D2 is approximately equal to the voltage difference across the first negative temperature coefficient resistor RT1 (small resistor), and the voltage difference across the third IO diode D3 is approximately equal to the voltage difference across the second negative temperature coefficient resistor RT2 (small resistor). By setting the negative temperature coefficient of the first negative temperature coefficient resistor RT1, the second negative temperature coefficient resistor RT2 and the second current source I2, the first negative temperature coefficient resistor RT1 and the second negative temperature coefficient resistor RT2 are about 1K ohms, and the current I2 is used to realize a small voltage drop across the second IO diode D2 and the third IO diode D3, and also realize a negative change of the voltage drop with temperature, thereby achieving the purpose of eliminating the leakage current of the IO diode. Figure 1 The middle diode D1, the second IO diode D2, the third IO diode D3, and the fourth IO diode D4 constitute an ESD electrostatic discharge path. Figure 1 Vin- Figure 2 The Vin- in is connected.

[0031] like Figure 2 As shown, the low-noise charge amplifier circuit of the present application includes a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a third current source I3.

[0032] The source terminals of the eighth MOS tube M8, the ninth MOS tube M9 and the tenth MOS tube M10 are connected to the power supply VDD; the first terminals of the third resistor R3, the third capacitor C3 and the third current source I3 are grounded GND; the gate terminal of the sixth MOS tube M6 is the negative input terminal of the charge amplifier, the first terminal of the fourth resistor R4 and the first terminal of the capacitor C4, the source terminal of M6 is connected to the source terminal of the seventh MOS tube M7, the second terminal of the third resistor R3 and the second terminal of the third capacitor C3, the drain terminal of M6 is connected to the drain terminal of the eighth MOS tube M8, the gate terminal of the eighth MOS tube M8 and the gate terminal of the ninth MOS tube M9; the gate terminal of the seventh MOS tube M7 is the positive input terminal of the charge amplifier, the drain terminal of the seventh MOS tube M7 is connected to the gate terminal of the tenth MOS tube M10, the drain terminal of the ninth MOS tube M9 and the first terminal of the resistor R2; the first terminal of the capacitor C2 is connected to the second terminal of the resistor R2, the second terminal of C2 is connected to the second terminal of the tenth MOS tube M10, the second terminal of the third power supply I3, the second terminal of R4 and the second terminal of C4, which is the output terminal of the charge amplifier.

[0033] In this embodiment, Figure 1 and Figure 2The example values ​​of each device in are shown in the following table:

[0034]

[0035] The charge amplifier of the present invention adopts a two-stage Miller operational amplifier structure, which realizes low low-frequency noise by setting large areas of the sixth MOS tube M6 and the seventh MOS tube M7 of the input pair; and further reduces noise by using the third resistor R3 instead of the tail current.

[0036] Figure 3 : is a comparison result diagram of the leakage current of the IO diode in the present invention. The yellow curve in the figure is a curve diagram of the leakage current of the IO diode (D2 and D3) in the present invention changing with temperature, and the red curve in the figure is a curve diagram of the leakage current of the conventional IO diode (two reverse diodes are connected in series between VDD and ground, and Vin- is connected to the midpoint of the two reverse diodes) changing with temperature. By comparison, it is found that at high temperatures, such as 120 degrees Celsius, the leakage current of the IO diode in the present invention is optimized by more than 10 times.

[0037] The invention is designed to Figure 1 In the operational amplifier structure, the negative input terminal of the operational amplifier follows the positive input terminal voltage through the negative feedback effect of the operational amplifier, and the positive input terminal voltage is the negative input terminal voltage of the charge amplifier. At the same time, by designing a smaller I2 current and smaller resistors RT1 and RT2, a smaller voltage drop is obtained, and the voltage drop is the voltage drop across the reverse biased diodes D2 and D3. Because the voltage drop is small, the leakage current flowing through the negative input terminal of the charge amplifier is approximately eliminated. At the same time, the resistors RT1 and RT2 with negative temperature coefficients are used for further temperature compensation. When the temperature rises, the voltage drop across the resistors decreases, that is, the voltage drop across the reverse biased diodes D2 and D3 decreases, which offsets the positive temperature coefficient current effect of the carriers in the diodes. The temperature compensation method further offsets the change of the leakage current with temperature.

[0038] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A low-frequency, low-noise charge amplifier for eliminating IO leakage current, characterized in that: The low-frequency low-noise charge amplifier includes an IO leakage current elimination circuit and a charge amplifier circuit, wherein the IO leakage current elimination circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a first resistor R1, a first negative temperature coefficient resistor RT1, a second negative temperature coefficient resistor RT2, a first capacitor C1, a first current source I1, a second current source I2, and a first IO diode D1, a second IO diode D2, a third IO diode D3, and a fourth IO diode D4. The first ends of the first current source I1, the second current source I2 and the first IO diode D1 are connected to the power supply VDD; the first ends of the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the fourth IO diode D4 are connected to the ground GND; The first negative temperature coefficient resistor RT1 and the second negative temperature coefficient resistor RT2 are connected in series, the gate end of the first MOS tube M1 is connected to the midpoint between the first negative temperature coefficient resistor RT1 and the second negative temperature coefficient resistor RT2, the source end of the first MOS tube M1 is connected to the source end of the second MOS tube M2 and the second end of the first current source I1, the drain end of the first MOS tube M1 is connected to the gate end and the drain end of the third MOS tube M3 and the gate end of the fourth MOS tube M4; the gate end of the second MOS tube M2 is connected to the negative input end Vin- of the charge amplifier, the first end of the second IO diode D2 and the first end of the third IO diode D3, and the drain end of the second MOS tube M2 is connected to the drain end of the fourth MOS tube M4, the gate end of the fifth MOS tube M5 and the first end of the first resistor R1; The drain end of the fifth MOS transistor M5 is connected to the second end of the second negative temperature coefficient resistor RT2; the second end of the second current source I2 is connected to the second end of the first negative temperature coefficient resistor RT1, the second end of the IO diode D1 and the second end of the second IO diode D2; the first end of the first capacitor C1 is connected to the second end of the resistor R1, and the second end is connected to the second end of the third IO diode D3 and the second end of the fourth IO diode D4.

2. The low-frequency, low-noise charge amplifier according to claim 1, characterized in that: The low-noise charge amplifier circuit includes a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a third current source I3. The source terminals of the eighth MOS tube M8, the ninth MOS tube M9 and the tenth MOS tube M10 are connected to the power supply VDD; the first end of the third resistor R3, the third capacitor C3 and the third current source I3 are grounded GND; the gate end of the sixth MOS tube M6 is the negative input end of the charge amplifier, the first end of the fourth resistor R4 and the first end of the fourth capacitor C4, the source end of the sixth MOS tube M6 is connected to the source end of the seventh MOS tube M7, the second end of the third resistor R3 and the second end of the third capacitor C3, and the drain end of the sixth MOS tube M6 is connected to the eighth MOS The drain end of the seventh MOS tube M7 is connected to the gate end of the tenth MOS tube M10, the drain end of the ninth MOS tube M9 and the first end of the second resistor R2; the first end of the second capacitor C2 is connected to the second end of the resistor R2, the second end of the second capacitor C2 is connected to the second end of the tenth MOS tube M10, the second end of the third power supply I3, the second end of R4 and the second end of C4, which is the output end of the charge amplifier.

3. The low-frequency low-noise charge amplifier according to claim 1, characterized in that: The low-frequency low-noise charge amplifier uses the negative feedback effect of the operational amplifier to achieve a small voltage drop across the IO diode, and eliminates the IO leakage current through temperature resistance compensation.

4. The low-frequency low-noise charge amplifier according to claim 1, characterized in that: The main body of the charge amplifier circuit adopts a two-stage Miller operational amplifier structure.

5. An IO leakage current elimination circuit for a low-frequency low-noise charge amplifier, wherein: The IO leakage current elimination circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a first resistor R1, a first negative temperature coefficient resistor RT1, a second negative temperature coefficient resistor RT2, a first capacitor C1, a first current source I1, a second current source I2, and a first IO diode D1, a second IO diode D2, a third IO diode D3, and a fourth IO diode D4. The first ends of the first current source I1, the second current source I2 and the first IO diode D1 are connected to the power supply VDD; the first ends of the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the fourth IO diode D4 are connected to the ground GND; The first negative temperature coefficient resistor RT1 and the second negative temperature coefficient resistor RT2 are connected in series, the gate end of the first MOS tube M1 is connected to the midpoint between the first negative temperature coefficient resistor RT1 and the second negative temperature coefficient resistor RT2, the source end of the first MOS tube M1 is connected to the source end of the second MOS tube M2 and the second end of the first current source I1, the drain end of the first MOS tube M1 is connected to the gate end and the drain end of the third MOS tube M3 and the gate end of the fourth MOS tube M4; the gate end of the second MOS tube M2 is connected to the negative input end Vin- of the charge amplifier, the first end of the second IO diode D2 and the first end of the third IO diode D3, and the drain end of the second MOS tube M2 is connected to the drain end of the fourth MOS tube M4, the gate end of the fifth MOS tube M5 and the first end of the first resistor R1; The drain end of the fifth MOS transistor M5 is connected to the second end of the second negative temperature coefficient resistor RT2; the second end of the second current source I2 is connected to the second end of the first negative temperature coefficient resistor RT1, the second end of the IO diode D1 and the second end of the second IO diode D2; the first end of the first capacitor C1 is connected to the second end of the resistor R1, and the second end is connected to the second end of the third IO diode D3 and the second end of the fourth IO diode D4.

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