Dual network synchronous switch and dual network synchronous switching method

Abstract

This application discloses a dual-network synchronous switch and a dual-network synchronous switching method, relating to the field of network communication technology. The dual-network synchronous switch comprises a field programmable gate array (FPGA) and a central processing unit (CPU). The FPGA includes a high-speed interface processing module, a time frame module, a MAC processing module, a clock synchronization module, a time maintenance module, an FPGA time interaction module, and a data exchange module. The CPU includes a data processing module, a CPU time interaction module, and an Ethernet MAC module. This application implements clock information exchange through the FPGA time interaction module and the CPU time interaction module, and data exchange through the data exchange module and the data processing module. The Ethernet MAC module encapsulates the received clock information and data, which can then be communicated with other networks after encapsulation, thereby achieving clock synchronization and data exchange between the dual networks.

Description

Technical Field

[0001] The present application relates to the field of network communication technology, and in particular to a dual-network synchronous switch and a dual-network synchronous switching method. Background Art

[0002] With the rapid development of information technology, high-precision clock synchronization technology is playing an increasingly important role in communications, networking, industrial automation, and other fields. Early clock synchronization technologies primarily relied on global navigation satellite systems such as the GPS (Global Positioning System). However, with the diversification of application scenarios and the increasing requirements for synchronization accuracy, protocols based on the Precision Time Protocol (PTP) have gradually become mainstream.

[0003] Currently, most high-precision synchronization devices are based on WR (White Rabbit) radios or their improved versions. For example, some devices use internal logic within an FPGA (Field-Programmable Gate Array) to perform frequency multiplication to generate the data transmission clock and system clock. The recovered clock is then combined with the FPGA's internal clock logic to generate a DDMTD (Digital Dual Mixer Time Difference) clock to determine the timestamp phase of received data packets, achieving clock synchronization.

[0004] Although existing high-precision synchronization devices can achieve nanosecond-level synchronization accuracy in some applications, they usually do not have the function of data exchange, which limits their application in scenarios that require simultaneous data transmission and clock synchronization.

[0005] The above content is only used to assist in understanding the technical solution of this application and does not constitute an admission that the above content is prior art. Summary of the Invention

[0006] The main purpose of this application is to provide a dual-network synchronous switch and a dual-network synchronous switching method, which realizes the functions of supporting clock synchronization and data exchange at the same time.

[0007] To achieve the above objectives, the present application proposes a dual-network synchronous switch, which includes:

[0008] A field programmable gate array (FPGA) and a central processing unit (CPU), wherein the FPGA includes a high-speed interface processing module, a time frame module, a media access control (MAC) processing module, a clock synchronization module, a time maintenance module, an FPGA time interaction module, and a data exchange module; and the CPU includes a data processing module, a CPU time interaction module, and an Ethernet MAC module;

[0009] The high-speed interface processing module is used to process the acquired external data to obtain time data and MAC frame data, and send them to the time frame module and the MAC processing module respectively;

[0010] The time maintenance module is connected to the time frame module, the clock synchronization module and the FPGA time interaction module respectively, and is used to transmit synchronous clock information to each module;

[0011] The clock synchronization module is used to realize clock synchronization between devices connected to the local end according to the received synchronization clock information;

[0012] The FPGA time interaction module is used to transmit the synchronous clock information and the time data to the CPU time interaction module;

[0013] The CPU time interaction module is used to send the synchronous clock information and the time data to the Ethernet MAC module;

[0014] The data exchange module is configured to receive the MAC frame data sent by the MAC processing module and send the MAC frame data to a target interface, wherein the target interface is determined according to a destination address of the MAC frame data;

[0015] The data processing module is configured to receive the MAC frame data sent by the data exchange module and transfer the received MAC frame data to the Ethernet MAC module;

[0016] The Ethernet MAC module is used to encapsulate the synchronous clock information, the time data and the MAC frame data into a custom Ethernet frame, wherein the custom Ethernet frame is used for communication in an Ethernet local area network.

[0017] In one embodiment, the dual-network synchronous switch includes a clock phase-locked loop circuit, a local clock, and a global positioning system GPS signal processing circuit;

[0018] The local clock and the GPS signal processing circuit are used to provide a reference clock signal for the clock phase-locked loop circuit;

[0019] The clock phase-locked loop circuit is used to provide a synchronous clock signal for the FPGA according to the reference clock signal.

[0020] In one embodiment, the FPGA includes a GPS processing module, and the GPS processing module is connected to the GPS signal processing circuit and the time maintenance module respectively;

[0021] The GPS processing module is used to receive the coordinated universal time provided by the GPS signal processing circuit, and send the coordinated universal time as a synchronous clock signal to the time maintenance module.

[0022] In one embodiment, the dual-network synchronous switch includes a storage module;

[0023] The storage module is used to provide an address mapping table for the data exchange module, wherein the address mapping table is used by the data exchange module to determine a distribution outlet for the MAC frame data.

[0024] In one embodiment, the CPU includes a local time maintenance module, and the local time maintenance module is used to maintain the local time of the dual-network synchronization switch.

[0025] In one embodiment, the CPU includes a Network Time Protocol (NTP) service module, and the NTP service is used to provide time synchronization within an Ethernet local area network.

[0026] In one embodiment, the custom Ethernet frame includes a custom protocol frame header, a time synchronization frame, an Ethernet MAC data frame and a reserved frame definition, wherein the custom protocol frame header is used to determine the type of the frame, the time synchronization frame is used to achieve clock synchronization, the Ethernet MAC data frame is used to achieve data exchange, and the reserved frame definition is used to expand the purpose of the custom protocol frame.

[0027] In addition, to achieve the above-mentioned purpose, the present application also proposes a dual-network synchronous switching method based on the dual-network synchronous switch, including:

[0028] Receive the master node system clock sent by the master node in the local area network based on the precision time protocol;

[0029] Determine the time offset between the local node's recovered clock and the master node's system clock;

[0030] Adjust the local clock according to the time deviation.

[0031] In one embodiment, the dual-network synchronous exchange method further includes:

[0032] Determining a system clock of the local end according to the recovered clock of the local end, and sending the system clock of the local end to the master node;

[0033] Receiving a clock phase difference sent by the master node, wherein the clock phase difference is a phase difference between the system clock of the local end and the system clock of the master node;

[0034] The system clock of the local end is adjusted according to the clock phase difference through the clock synchronization module.

[0035] In one embodiment, the dual-network synchronous exchange method further includes:

[0036] When receiving MAC frame data, checking whether the MAC frame data has errors by the MAC processing module;

[0037] If the MAC frame data is not erroneous, the MAC frame data is sent to the data exchange module.

[0038] The dual-network synchronous switch proposed in this application includes: a field programmable gate array FPGA and a central processing unit CPU, wherein the FPGA includes a high-speed interface processing module, a time frame module, a MAC processing module, a clock synchronization module, a time maintenance module, an FPGA time interaction module and a data exchange module, and the CPU includes a data processing module, a CPU time interaction module and an Ethernet MAC module; the high-speed interface processing module is used to process the acquired external data, obtain time data and media access control MAC frame data, and send them to the time frame module and the MAC processing module respectively; the time maintenance module is connected to the time frame module, the clock synchronization module and the FPGA time interaction module respectively, and is used to transmit synchronous clock information to each module; the clock synchronization module is used to achieve clock synchronization between devices connected to the local end according to the received synchronous clock information; the FPGA time interaction module is used to transmit synchronous clock information and time data to the CPU U time interaction module; data exchange module, used to receive MAC frame data sent by the MAC processing module, and send the MAC frame data to the target interface, the target interface is determined according to the destination address of the MAC frame data; data processing module, used to receive MAC frame data distributed by the data exchange module, and pass the received MAC frame data to the Ethernet MAC module; CPU time interaction module, used to send synchronous clock information and time data to the Ethernet MAC module; Ethernet MAC module, used to encapsulate synchronous clock information, time data and MAC frame data into a custom Ethernet frame, wherein the custom Ethernet frame is used to communicate in the Ethernet local area network, thereby the Ethernet MAC module combines the high-precision time information after clock synchronization and the MAC data from the data exchange module, supports both high-precision time synchronization between different devices and data exchange functions, and realizes the function of supporting clock synchronization and data exchange at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 A schematic diagram of the structure of a dual-network synchronous switch provided in Example 1 of the present application;

[0042] Figure 2 This is an application architecture diagram of a dual-network synchronization switch provided in Example 1 of the present application;

[0043] Figure 3 A schematic diagram of the process of the dual-network synchronous switching method provided in the second embodiment of the present application;

[0044] Figure 4 A schematic diagram of clock synchronization of a dual-network synchronous switch provided in Example 2 of the present application;

[0045] Figure 5 This is a schematic diagram of the internal flow of the dual-network synchronous switch provided in Example 2 of the present application.

[0046] Description of reference numerals:

[0047] 10. FPGA; 20. CPU; 30. Clock phase-locked loop circuit; 40. Local clock; 50. GPS signal processing circuit; 60. Storage module; 70. Synchronous switching interface; 80. Ethernet port; 90. Local crystal oscillator;

[0048] 101, high-speed interface processing module; 102, time frame module; 103, MAC processing module; 104, clock synchronization module; 105, time maintenance module; 106, FPGA time interaction module; 107, data exchange module; 108, GPS processing module; 109, address mapping table;

[0049] 201, data processing module; 202, CPU time interaction module; 203, Ethernet MAC module; 204, local time maintenance module; 205, NTP service module;

[0050] 111, master node GTH TX; 112, master node GTH RX; 113, child node GTH RX; 114, child node GTH TX;

[0051] 301. GPS-tamed rubidium atomic clock; 302. Dual-network synchronization switch; 303. Synchronous sub-node; 304. Ethernet switch.

[0052] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0053] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0054] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0055] Conventional FPGA-based synchronization devices can achieve precise phase determination of the timestamp when receiving data packets, improving the accuracy of clock synchronization, but do not provide data exchange functions. Ethernet data exchange, as the current mainstream data exchange method, connects various network nodes in a ring network through a network router, achieving efficient transmission of data frames in the network. This data exchange method not only improves data transmission efficiency but also reduces network latency. However, it does not support high-precision clock synchronization, resulting in conventional technologies being unable to achieve high-precision clock synchronization and data exchange between synchronous exchange LANs and Ethernet LANs.

[0056] Based on this, the embodiment of the present application provides a dual network synchronization switch, referring to Figure 1 , Figure 1 This is a structural diagram of the dual-network synchronous switch described in the first embodiment of the present application.

[0057] The dual-network synchronous switch includes: a field programmable gate array FPGA 10 and a central processing unit CPU 20, wherein the FPGA 10 includes a high-speed interface processing module 101, a time frame module 102, a MAC processing module 103, a clock synchronization module 104, a time maintenance module 105, an FPGA time interaction module 106, and a data exchange module 107; the CPU 20 includes a data processing module 201, a CPU time interaction module 202, and an Ethernet MAC module 203;

[0058] The high-speed interface processing module 101 is used to process the acquired external data, obtain time data and MAC frame data, and send them to the time frame module 102 and the MAC processing module 103 respectively;

[0059] The time maintenance module 105 is connected to the time frame module 102, the clock synchronization module 104 and the FPGA time interaction module 106 respectively, and is used to transmit synchronous clock information to each module;

[0060] The clock synchronization module 104 is used to synchronize the clocks of the devices connected to the local end according to the received synchronization clock information;

[0061] FPGA time interaction module 106, used to transmit synchronous clock information and time data to CPU time interaction module 202;

[0062] CPU time interaction module 202, used to send synchronous clock information and time data to Ethernet MAC module 203;

[0063] The data exchange module 107 is configured to receive the MAC frame data sent by the MAC processing module 103 and send the MAC frame data to a target interface, wherein the target interface is determined according to the destination address of the MAC frame data;

[0064] The data processing module 201 is used to receive the MAC frame data sent by the data exchange module 107 and pass it to the Ethernet MAC module 203;

[0065] The Ethernet MAC module 203 is used to encapsulate the synchronous clock information, time data and MAC frame data into a custom Ethernet frame, wherein the custom Ethernet frame is used for communication in the Ethernet local area network.

[0066] It should be noted that external data refers to data from outside the current FPGA10 that needs to be clock synchronized and exchanged through FPGA10; time data refers to time-related information in the data, such as timestamps, separation time, etc.; MAC frame data is used to transmit the address of data transfer and transmit corresponding data.

[0067] In addition, it should be noted that synchronous clock information refers to a high-precision time reference obtained through a high-precision clock source (such as GPS or atomic clock), which is used to ensure the time consistency of the entire system; a custom Ethernet frame refers to a frame format that is modified or extended based on the standard Ethernet frame according to specific requirements. After modification, it may contain additional fields or information to meet specific application requirements.

[0068] The high-speed interface processing module 101 is mainly used to convert external data into internally processable data, or to convert internal data into external data, so as to realize communication between the module and the outside world.

[0069] The time frame module 102 is used to transmit time information to the time maintenance module 105 to facilitate time synchronization of the local time.

[0070] The MAC processing module 103 may check the MAC frame to see if there are errors such as frame length error and non-byte alignment.

[0071] The FPGA time interaction module 106 is an interface or processing unit that transmits the synchronized clock information after being synchronized by the time maintenance module 105 to other modules or systems that require time.

[0072] The data exchange module 107 is responsible for efficiently transmitting data between the internal bus, network interface card, processor, etc., including functions such as data caching, routing selection, and data forwarding.

[0073] The CPU (Central Processing Unit) time interaction module 202 is specifically responsible for processing time-related interaction tasks, and is used to read or adjust system time, and synchronize time with other time sources or devices.

[0074] The Ethernet MAC module 203 can encapsulate the received time information and other data, and process the sending and receiving of Ethernet data frames. It can perform tasks such as data encapsulation, decoding, verification and error handling for communication or data exchange with other devices.

[0075] For example, data packets are received from other network devices. These packets contain key information such as timestamps and MAC addresses. High-speed interface processing module 101 receives these data packets and splits them into time data and MAC frame data. Time frame module 102 then processes the time data into a time frame format that the device can understand and utilize. MAC processing module 103 then parses the MAC frame data, extracting key information such as the MAC address and frame header. This information is used for subsequent device operations, such as clock synchronization and data transmission.

[0076] Exemplarily, after receiving the corresponding MAC frame data, the data exchange module 107 finds the corresponding exit in the address mapping table according to its destination address. The exit can be an Ethernet port, a synchronous switching interface, or other switching interface. If the exit is an Ethernet port, it is processed by the data processing module 201 and then passed to the Ethernet MAC module 203 for encapsulation and then passed out through the Ethernet port; if the exit is a synchronous switching interface, it is passed out after passing through the MAC processing module 103 and subsequent processing steps; it can also be passed through other switching interfaces, which is not specifically limited in this embodiment.

[0077] It can be understood that, through address mapping, MAC frame data can be transferred to CPU20 that can exchange data with Ethernet, which helps to achieve data exchange between high-precision clock synchronization switching LAN and Ethernet LAN.

[0078] For example, the Ethernet MAC module 203 receives the synchronized clock signal and the MAC address of the financial transaction data. It then combines this information into a custom Ethernet frame that contains not only the transaction data but also a precise timestamp. This custom frame is transmitted via Ethernet to other devices or interfaces, ensuring the accuracy and timeliness of the transaction data.

[0079] It is understandable that by splitting the time data and the MAC frame data, it is convenient to perform time synchronization and data exchange separately in the future, thus avoiding waste of resources. At the same time, the processing efficiency is improved through parallel processing.

[0080] In this embodiment, the dual-network synchronous switch can ensure the timing of data during transmission by synchronizing clock information, avoid data errors or losses caused by clock asynchrony, and improve the overall performance of the system. It is particularly suitable for local area networks and Ethernet environments that require high-precision clock synchronization. Through the data exchange module, the information outlet is determined, and the MAC frame data is transferred from the FPGA to the CPU, and then transferred to the Ethernet local area network through the CPU, thereby realizing data exchange between the local area network to which the dual-network synchronous switch belongs and the Ethernet local area network, thereby simultaneously realizing time interaction and data exchange between the two networks.

[0081] In one feasible implementation, the dual-network synchronous switch includes a clock phase-locked loop circuit, a local clock, and a global positioning system GPS signal processing circuit;

[0082] A local clock and GPS signal processing circuit is used to provide a reference clock signal for a clock phase-locked loop circuit;

[0083] The clock phase-locked loop circuit is used to provide synchronous clock information to the FPGA based on the reference clock signal.

[0084] It should be noted that a phase-locked loop (PLL) circuit is a circuit that adjusts the phase and frequency of an output signal through a feedback mechanism to synchronize it with an input reference signal.

[0085] The GPS signal processing circuit is a circuit specifically designed to receive and process GPS satellite signals. It can extract the time information from the GPS signal and convert it into a reference clock signal that can be used for clock synchronization. By communicating with GPS satellites, the GPS signal processing circuit can obtain the global unified time standard in real time and provide high-precision clock synchronization services for FPGAs.

[0086] A local clock is an independent clock source that provides a stable clock signal when no external reference signal is available. It is usually used as a backup clock source.

[0087] For example, in a dual-network synchronous switch, the local clock and GPS signal processing circuit each generate their own reference clock signals. When the GPS signal is available, the GPS signal processing circuit prioritizes providing a high-precision reference clock signal; when the GPS signal is unavailable, the local clock provides a backup reference clock signal. The clock phase-locked loop circuit receives reference clock signals from the local clock and GPS signal processing circuit and adjusts its output through an internal feedback mechanism. After adjustment, the clock phase-locked loop circuit outputs a stable synchronous clock signal that remains synchronized with the reference clock signal. Network processing units within the FPGA, such as the high-speed interface processing module and the FPGA time interaction module, receive the synchronous clock signal from the clock phase-locked loop circuit and use it as a reference for clock synchronization.

[0088] In this embodiment, by introducing a GPS signal processing circuit and a clock phase-locked loop circuit, an accurate clock signal is provided for the dual-network synchronous switch to achieve high-precision clock synchronization.

[0089] In a feasible embodiment, the FPGA includes a GPS processing module, and the GPS processing module is connected to the GPS signal processing circuit and the time maintenance module respectively;

[0090] The GPS processing module is used to receive the coordinated universal time provided by the GPS signal processing circuit, and send the coordinated universal time as synchronous clock information to the time maintenance module.

[0091] For example, the GPS signal processing circuit receives signals from GPS satellites and converts them into digital signals, extracts the current clock information (Coordinated Universal Time) from them, and sends it as a synchronization clock signal to the time maintenance module to ensure that the system time of the dual-network synchronization switch is synchronized with the GPS.

[0092] In one possible implementation, the dual-network synchronous switch includes a storage module;

[0093] The storage module is used to provide an address mapping table for the data exchange module, wherein the address mapping table is used by the data exchange module to determine the target interface of the MAC frame data.

[0094] It should be noted that the address mapping table refers to a data structure used to store the correspondence between addresses, such as the mapping relationship between logical addresses (such as MAC addresses) and physical addresses (such as the port number of the network interface card or a specific channel). It is used to help the data exchange module quickly locate the target port and achieve accurate data distribution.

[0095] The storage module is mainly responsible for storing and managing various data and information, such as address mapping tables, configuration parameters, etc. It usually has high-speed read and write capabilities and large-capacity storage space to meet the switch's requirements for real-time and accuracy in data processing.

[0096] For example, when MAC frame data is transmitted to the data exchange module, the module first reads the destination MAC address in the frame data. It then requests the address mapping table information corresponding to the destination MAC address from the storage module. After the storage module returns the address mapping table information, the module determines the distribution outlet for the MAC frame data based on the information in the address mapping table and sends the data to the destination server or interface.

[0097] In a feasible implementation manner, the CPU includes a local time maintenance module, which is used to maintain the local time of the dual-network synchronous switch.

[0098] The local time maintenance module is used to synchronize with external time sources (such as NTP servers and CPU time interaction modules) to ensure the accuracy and consistency of local time.

[0099] During the operation of the dual-network synchronous switch, the local time maintenance module will regularly synchronize with the external time source to ensure the accuracy of the local time.

[0100] In a feasible implementation, the CPU includes a Network Time Protocol (NTP) service module, and the NTP service module is used to perform time synchronization within the Ethernet local area network.

[0101] It should be noted that the Network Time Protocol service module is an implementation module of the Network Time Protocol (NTP). It is responsible for providing time synchronization services in the network. It achieves time synchronization by receiving time information from a time source (such as a standard clock) and distributing it to other devices in the network.

[0102] For example, after clock synchronization is completed on a local area network (LAN) to which a dual-network synchronization switch belongs, the time interaction module obtains the synchronized standard clock and sends this standard clock information to the NTP service module. Upon receiving this standard clock information, the NTP service module uses it as a time reference and broadcasts it to all devices within the Ethernet LAN via the network. This allows devices within the Ethernet LAN to adjust their system time based on their needs and time synchronization policy to achieve synchronization with the standard clock, thereby achieving clock synchronization within the LAN to which the dual-network synchronization switch belongs.

[0103] In this embodiment, by obtaining standard clock information and performing time synchronization through the NTP service, it is ensured that all devices in the entire Ethernet LAN can obtain accurate time information, thereby improving the accuracy of time synchronization and achieving clock synchronization between the two networks.

[0104] In a feasible implementation, the custom Ethernet frame includes a custom protocol frame header, a time synchronization frame, an Ethernet MAC data frame and a reserved frame definition, wherein the custom protocol frame header is used to determine the type of the frame, the time synchronization frame is used to achieve clock synchronization, the Ethernet MAC data frame is used to achieve data exchange, and the reserved frame definition is used to extend the purpose of the custom protocol frame.

[0105] It should be noted that the custom protocol frame header refers to the starting part of the custom Ethernet frame, which is used to identify that the frame belongs to the custom protocol and contains some necessary protocol information, such as version number, frame type, length, etc.; the reserved frame definition refers to the reserved field in the custom Ethernet frame for possible future expansion or special purposes. It usually does not contain any valid information, but provides the possibility for future functional expansion.

[0106] In addition, it should be noted that the time synchronization frame is a field in the custom Ethernet frame used for time synchronization, which contains the sender's timestamp or other time synchronization information and is used to implement the time synchronization function in the network; the Ethernet MAC frame is the part of the custom Ethernet frame used for data exchange, which contains various types of data information.

[0107] For example, please refer to Figure 2 , Figure 2 A diagram of the application architecture of a dual-network synchronization switch in a dual network is provided. In a high-precision synchronous switching local area network (LAN), a GPS-trained rubidium atomic clock 301 is first used to provide a high-precision time reference for a dual-network synchronization switch 302, which spans the high-precision synchronous switching LAN and an Ethernet LAN. This dual-network synchronization switch 302 is then designated as the master node. Clock synchronization and data exchange between the dual-network synchronization switch and an Ethernet switch 304 in the Ethernet LAN are also achieved using custom Ethernet frames. Synchronization child nodes 303 cannot directly communicate or exchange data with Ethernet switch 304. However, with the help of dual-network synchronization switch 302, custom Ethernet frames containing time synchronization frames and Ethernet MAC frame data frames are constructed and sent to any receiver. The receiver can then read the time information in the time synchronization frame to perform time synchronization operations and read the actual data in the Ethernet MAC frame data frames for corresponding processing, thereby achieving clock synchronization and data exchange between the high-precision synchronous switching LAN and the Ethernet LAN.

[0108] In this embodiment, by customizing the Ethernet frame and introducing the time synchronization frame and MAC data frame at the same time, time information and data information are provided to the high-precision synchronous switching LAN and the Ethernet LAN at the same time, thereby realizing clock synchronization and data exchange between the high-precision synchronous switching LAN and the Ethernet LAN.

[0109] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above embodiment 1 can be referred to the above introduction and will not be repeated hereafter. Figure 3 , Figure 3 A flowchart of a dual-network synchronous exchange method is provided, which includes:

[0110] Step S10, receiving a master node system clock sent by a master node in a local area network based on the Precision Time Protocol;

[0111] It should be noted that PTP (Precision Time Protocol) is a network time synchronization protocol that uses a master-slave structure to synchronize the time of each node in the network by periodically sending time synchronization messages.

[0112] In addition, it should be noted that the master node refers to the switch selected as the time synchronization benchmark in a high-precision synchronous switching local area network; the master node system clock can be determined based on the synchronization clock information and used as the clock synchronization benchmark for other switches (sub-nodes) in the local area network.

[0113] Step S20, determining the time offset between the local terminal's recovered clock and the master node's system clock;

[0114] It should be noted that the recovered clock refers to the reference clock signal recovered from the network or other synchronization source and used for internal system time synchronization, which is used for comparison with the synchronization clock of the master node; the time deviation refers to the difference between the master node time received by the child node and its own current time.

[0115] When a node needs to synchronize its clock, the node's clock synchronization module can adjust its own system clock according to the time deviation, thereby calculating and compensating for the time difference between different nodes in the network to ensure time accuracy.

[0116] Step S30: Adjust the local clock according to the time deviation.

[0117] It should be noted that the local clock refers to the clock inside each node used to record time. It is usually related to hardware, but can also be adjusted and calibrated through software.

[0118] For example, the master node periodically sends time synchronization messages containing the master node's system clock to all child nodes in the network, following the PTP protocol. Upon receiving the master node's time synchronization messages, the child nodes parse the master node's system clock and compare it with their own recovered clocks to calculate the time offset between the two. Based on this calculated time offset, the child nodes use the clock synchronization module to adjust their local time to synchronize with the master node. This process repeats continuously to ensure consistent time across the entire system.

[0119] In this embodiment, time synchronization is achieved by periodically sending time synchronization messages through the PTP protocol, which effectively reduces delay and jitter in the network, thereby improving the time synchronization accuracy between nodes in the network.

[0120] In a feasible implementation manner, the dual-network synchronous exchange method further includes:

[0121] Step S40: determining the system clock of the local end according to the recovered clock of the local end, and sending the system clock of the local end to the master node;

[0122] Step S50: receiving a clock phase difference sent by the master node, wherein the clock phase difference is a phase difference between the system clock of the local end and the system clock of the master node;

[0123] It should be noted that clock phase difference refers to the time deviation between two clock signals, which may be caused by factors such as hardware delay, fiber delay, clock phase delay and clock drift.

[0124] Step S60: adjusting the system clock of the local end according to the clock phase difference through the clock synchronization module.

[0125] For example, please refer to Figure 4 , Figure 4A schematic diagram of clock synchronization is provided. The GTH module of the master node includes a master node GTH TX111 and a master node GTH RX112. The master node GTH TX111 is used to send a clock signal, and the master node GTH RX112 is used to receive a time signal. The local crystal oscillator 90 can provide a stable clock source. The time phase-locked loop circuit 30 of the master node determines the system clock of the master node based on the local crystal oscillator 90, the external clock source, and the GPS signal, and sends it to the FPGA10 module of the master node. The child node determines the recovered clock from the time phase-locked loop circuit, regards the recovered clock as the system clock of the child node, and sends it to the master node GTH RX112 via the child node GTH TX114. After receiving it, the master node sends the system clock of the child node to the clock synchronization module 104 of the master node to calculate the phase difference between the system clocks of the master node and the child node. The phase difference is then sent to the child node GTH RX113 via the master node GTH TX111. The clock synchronization module of the child node adjusts the system clock of the child node based on the phase difference. The steps of sending the system clock of the child node to the master node and subsequent steps are repeated until the phase difference is zero or remains unchanged, indicating that clock synchronization is achieved between the master node and the child node.

[0126] For example, the phase difference between the system clock of the master node and the recovered clock (system clock) of the slave node is measured to be 100ns. Using phase-locked loop technology, the phase of the system clock of the slave node is adjusted backward by 50ns. The system clock of the slave node is sent to the master node again through the GTH module, and the phase difference between the master node and the slave node is measured. If the phase difference still exists or is constantly changing, the phase adjustment value is continued to be adjusted, and feedback and correction are performed until the phase difference is zero or the phase difference remains unchanged.

[0127] In this embodiment, by continuously adjusting and calibrating the system clocks of the subnodes, the time synchronization accuracy of the entire network can be significantly improved; furthermore, by achieving time synchronization, data synchronization problems caused by time differences can be reduced.

[0128] In a feasible implementation manner, the dual-network synchronous exchange method further includes:

[0129] Step A10: When receiving the MAC frame data, the MAC processing module checks whether the MAC frame data has any errors.

[0130] It should be noted that checking refers to verifying the integrity and correctness of the captured MAC frame data to ensure the accuracy of the data, including checking whether there are frame length errors, non-byte alignment, CRC errors, etc.

[0131] Step A20: If the MAC frame data is not erroneous, the MAC frame data is sent to the data exchange module.

[0132] Before sending MAC data frames to the data exchange module, MAC data frames with the same MAC address can be merged and uploaded, which makes it easier for the data exchange module to distribute data with the same MAC address, reduces the search time of the distribution outlet, and thus improves the efficiency of data exchange.

[0133] For example, the MAC processing module receives MAC frame data from the high-speed interface processing module 101, performs a checksum check on the frame data to ensure it is free of corruption or errors, and then sends the MAC frame data to the data exchange module. The data exchange module then accurately distributes the data packets to the corresponding network devices or network interfaces based on the destination address information in each MAC frame.

[0134] In this embodiment, by checking and verifying the MAC frame data, errors in the data can be discovered and corrected in a timely manner, thereby improving the reliability of data exchange.

[0135] For example, in order to help understand the implementation process of the dual network synchronous switching method obtained by combining this embodiment with the above embodiment 1, please refer to Figure 5 , Figure 5 A schematic diagram of the internal process of a dual-network synchronous switch is provided, specifically:

[0136] Figure 5 The red lines in the figure indicate the transmission of clock synchronization information, the green lines indicate the transmission of clock synchronization information and time data, the blue lines indicate the transmission of MAC frame data, the black lines indicate the transmission of external data, the purple lines indicate the transmission of custom Ethernet frames, and the orange lines indicate the transmission of address mapping table information.

[0137] The dual-network synchronous switch communicates with different local area networks through the synchronous switching interface 70 and the Ethernet port 80, including data exchange and clock synchronization.

[0138] The dual-network synchronous switch includes an FPGA 10, a CPU 20, a time phase-locked loop circuit 30, a local clock 40, a GPS signal processing circuit 50, and a storage module 60. The local clock 40 and the GPS signal processing circuit 50 provide a time reference signal for the time phase-locked loop circuit 30. The time phase-locked loop circuit 30 ultimately outputs stable synchronous clock information synchronized with the reference signal and supplies it to the FPGA 10 for clock synchronization. The storage module 60 provides an address mapping table for the data exchange module 107, making it easier for the data exchange module 107 to find the target exit for data exchange.

[0139] FPGA 10 includes a high-speed interface processing module 101, a time frame module 102, a MAC processing module 103, a clock synchronization module 104, a time maintenance module 105, an FPGA time interaction module 106, a data exchange module 107, and a GPS processing module 108. The high-speed interface processing module 101 is configured to receive external data transmitted from the synchronous exchange interface 70, extract time data and MAC frame data therefrom, and transmit the data to the time frame module 102 and the MAC processing module 103, respectively. The MAC processing module 103 can check the MAC frame data and, after confirming that it is correct, pass the MAC frame data to the data exchange module 107. The data exchange module 107 uses an address mapping table to locate the target outlet for the MAC frame data. The outlet can be the synchronous exchange interface 70, the Ethernet port 80, or another device interface. If the corresponding outlet is an Ethernet port, the MAC frame data is sent to the data processing module 201 for further processing.

[0140] The clock synchronization module 104 primarily performs clock synchronization through phase adjustment based on the clock signal provided by the time phase-locked loop circuit 30 and the time information sent by the high-speed processing module 102. It then synchronizes the synchronized clock information with the time maintenance module 105. The time maintenance module 105 can function as a timing node, receiving the Coordinated Universal Time information provided by the GPS processing module 108 and performing clock synchronization. The time maintenance module 105 can also function as a functional node, communicating with the CPU time interaction module 202 via the FPGA time interaction module 106, synchronizing the clock signal to maintain the CPU's local time maintenance module 204. The time data provided by the time frame module 102 can also be transmitted to the Ethernet MAC module 203 via other modules. The time phase-locked loop circuit 30 can also provide synchronized clock information to the time maintenance module 105, allowing it to transmit this synchronized clock information between various modules.

[0141] The CPU 20 includes a data processing module 201, a CPU time interaction module 202, a local time maintenance module 204, an NTP service module 205, and an Ethernet MAC module 203. The data processing module 201 is responsible for exchanging data with the data exchange module 107 of the FPGA 10 and sending the obtained MAC frame data to the Ethernet MAC module 203. The CPU time interaction module 202 is used to obtain the synchronous clock information and time data of the FPGA 10 and send the synchronous clock information and time data to the local time maintenance module 204, so that the local time maintenance module 204 updates and synchronizes the local time of the current device. Furthermore, after obtaining the synchronous clock information, the NTP service module 205 performs time synchronization within the Ethernet LAN and sends the synchronous clock information and time data to the Ethernet MAC module 203. The Ethernet MAC module 203 fills the time synchronization frame and Ethernet MAC data frame into a custom Ethernet frame based on the obtained synchronous clock information, time data, and MAC frame data, and transmits the custom Ethernet frame to the Ethernet LAN through the Ethernet port 80, thereby achieving clock synchronization and data exchange between the two networks.

[0142] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the dual-network synchronous switching method of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

Claims

1. A dual-network synchronous switch, characterized in that: The dual-network synchronous switch spans a high-precision synchronous switching LAN and an Ethernet LAN. The dual-network synchronous switch includes: a field programmable gate array (FPGA) and a central processing unit (CPU). The FPGA includes a high-speed interface processing module, a time frame module, a media access control (MAC) processing module, a clock synchronization module, a time maintenance module, an FPGA time interaction module, and a data exchange module. The CPU includes a data processing module, a CPU time interaction module, and an Ethernet MAC module. The high-speed interface processing module is used to process the acquired external data to obtain time data and MAC frame data, and send them to the time frame module and the MAC processing module respectively; The time maintenance module is connected to the time frame module, the clock synchronization module and the FPGA time interaction module respectively, and is used to transmit synchronous clock information to each module; The clock synchronization module is used to realize clock synchronization between devices connected to the local end according to the received synchronization clock information; The FPGA time interaction module is used to transmit the synchronous clock information and the time data to the CPU time interaction module; The CPU time interaction module is used to send the synchronous clock information and the time data to the Ethernet MAC module; The data exchange module is configured to receive the MAC frame data sent by the MAC processing module and send the MAC frame data to a target interface, wherein the target interface is determined according to a destination address of the MAC frame data; The data processing module is configured to receive the MAC frame data sent by the data exchange module and transfer the received MAC frame data to the Ethernet MAC module; The Ethernet MAC module is used to encapsulate the synchronous clock information, the time data and the MAC frame data into a custom Ethernet frame, wherein the custom Ethernet frame includes a custom protocol frame header, a time synchronization frame, an Ethernet MAC data frame and a reserved frame definition, and is used for communication in an Ethernet local area network. The custom protocol frame header is used to determine the type of frame, the time synchronization frame is used to achieve clock synchronization, the Ethernet MAC data frame is used to achieve data exchange, and the reserved frame definition is used to expand the purpose of the custom protocol frame.

2. The dual-network synchronous switch according to claim 1, wherein: The dual-network synchronous switch includes a clock phase-locked loop circuit, a local clock and a global positioning system GPS signal processing circuit; The local clock and the GPS signal processing circuit are used to provide a reference clock signal for the clock phase-locked loop circuit; The clock phase-locked loop circuit is used to provide synchronous clock information for the FPGA according to the reference clock signal.

3. The dual-network synchronous switch according to claim 2, wherein: The FPGA includes a GPS processing module, and the GPS processing module is connected to the GPS signal processing circuit and the time maintenance module respectively; The GPS processing module is configured to receive the Coordinated Universal Time provided by the GPS signal processing circuit, and send the Coordinated Universal Time as synchronous clock information to the time maintenance module.

4. The dual-network synchronous switch according to claim 1, wherein: The dual-network synchronous switch includes a storage module; The storage module is used to provide an address mapping table for the data exchange module, wherein the address mapping table is used by the data exchange module to determine a target interface for the MAC frame data.

5. The dual-network synchronous switch according to claim 1, wherein: The CPU includes a local time maintenance module, and the local time maintenance module is used to maintain the local time of the dual-network synchronous switch.

6. The dual-network synchronous switch according to claim 1, wherein: The CPU includes a Network Time Protocol (NTP) service module, and the NTP service module is used for performing time synchronization within the Ethernet local area network.

7. A dual network synchronous switching method, characterized in that: The method is applied to the dual-network synchronous switch according to any one of claims 1 to 6, and the method comprises: Receive the master node system clock sent by the master node in the local area network based on the precision time protocol; Determine the time offset between the local node's recovered clock and the master node's system clock; Adjust the local clock according to the time deviation.

8. The dual network synchronous switching method according to claim 7, wherein: The method further comprises: Determining a system clock of the local end according to the recovered clock of the local end, and sending the system clock of the local end to the master node; Receiving a clock phase difference sent by the master node, wherein the clock phase difference is a phase difference between the system clock of the local end and the system clock of the master node; The system clock of the local end is adjusted according to the clock phase difference through the clock synchronization module.

9. The dual network synchronous switching method according to claim 7, wherein: The method further comprises: When receiving MAC frame data, checking whether the MAC frame data has errors by the MAC processing module; If the MAC frame data is not erroneous, the MAC frame data is sent to the data exchange module.

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