Field effect transistor with recrystallized source / drain and method

Abstract

The invention relates to a field effect transistor with recrystallized source / drain and a method. A method includes forming a nanostructure stack over a substrate; forming a source / drain opening adjacent to the nanostructure stack; forming a semiconductor layer in the source / drain opening; forming an amorphous semiconductor layer by performing ion implantation on the semiconductor layer; and forming a recrystallized source / drain by annealing the amorphous semiconductor layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to a field effect transistor with a recrystallized source / drain and a method thereof. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. In the process of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaled-down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaled-down process also increases the complexity of processing and manufacturing ICs. Summary of the invention

[0003] According to an embodiment of the present application, a method is provided, comprising: forming a nanostructure stack above a substrate; forming a source / drain opening adjacent to the nanostructure stack; forming a semiconductor layer in the source / drain opening; forming an amorphous semiconductor layer by performing ion implantation on the semiconductor layer; and forming a recrystallized source / drain by annealing the amorphous semiconductor layer.

[0004] In some implementations, annealing the amorphous semiconductor layer includes performing the annealing while an upper surface of the amorphous semiconductor layer is exposed.

[0005] In some implementations, performing the annealing includes performing at least two different anneals.

[0006] In some implementations, performing the annealing stops after the amorphous semiconductor layer is completely regrown.

[0007] In some implementations, annealing the amorphous semiconductor layer includes annealing the amorphous semiconductor layer after performing at least one of the following operations: forming a contact etch stop layer on the amorphous semiconductor layer; forming an interlayer dielectric on the contact etch stop layer; or forming a replacement gate, the replacement gate wrapping around a nanostructure of a nanostructure stack.

[0008] In some implementations, the method further includes: before annealing the amorphous semiconductor layer, performing solid phase epitaxial regrowth on the amorphous semiconductor layer via a second annealing.

[0009] In some implementations, performing the solid phase epitaxial regrowth is terminated before the amorphous semiconductor layer is completely regrowthed.

[0010] According to an embodiment of the present application, a method is provided, comprising: forming a nanostructure stack above a substrate; forming a source / drain opening adjacent to the nanostructure stack; forming a semiconductor layer in the source / drain opening; forming an amorphous semiconductor layer by amorphizing the semiconductor layer; and forming a source / drain by performing solid phase epitaxial regrowth on the amorphous semiconductor layer.

[0011] In some implementations, amorphizing the semiconductor layer includes implanting ions, the ions being a Group IV substance, a Group III substance, a Group V substance, or a Group VIII substance.

[0012] In some implementations, implanting ions includes: 13 cm -2 The ions are implanted at a dose.

[0013] In some implementations, implanting the ions includes implanting the ions at an energy in a range of 1 kiloelectronvolts (keV) to 60 keV.

[0014] In some implementations, implanting the ions includes implanting the ions at a temperature in a range of -150°C to 500°C.

[0015] In some implementations, performing solid phase epitaxial regrowth includes performing at least one of: rapid thermal annealing, furnace annealing, millisecond annealing, microsecond annealing, flash annealing, laser annealing, or melt laser annealing.

[0016] In some implementations, performing solid phase epitaxial regrowth includes performing annealing at a temperature in a range of 400° C. to 800° C. for 10 minutes to 12 hours.

[0017] According to an embodiment of the present application, a device is provided, comprising: a substrate; a first semiconductor channel stack on the substrate; a second semiconductor channel stack on the substrate; a first recrystallized source / drain of a first type, adjacent to the first semiconductor channel stack; and a second recrystallized source / drain of a second type different from the first type, adjacent to the second semiconductor channel stack, the first recrystallized source / drain having a first stacking fault number, which exceeds the second stacking fault number of the second recrystallized source / drain.

[0018] In some implementations, the first recrystallized source / drain includes ion-implanted first material; and the second recrystallized source / drain includes ion-implanted second material, the second material being different from the first material.

[0019] In some implementations, the device further includes: a dielectric layer between a second recrystallized source / drain and the substrate, wherein a bottom surface of the second recrystallized source / drain is at a level offset by a thickness of the dielectric layer relative to a bottom surface of the first recrystallized source / drain.

[0020] In some implementations, a visible interface exists between a first portion of the first recrystallized source / drain and a second portion of the first recrystallized source / drain.

[0021] In some implementations, the dopant concentration in the first portion is different than the dopant concentration in the second portion.

[0022] In some implementations, a crystal defect density in the visible interface exceeds a crystal defect density in the first portion and exceeds a crystal defect density in the second portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood from the following specific implementations. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0024] Figure 1A and Figure 1B is a schematic cross-sectional side view of a portion of an IC device according to an embodiment of the present disclosure.

[0025] Figures 2A to 12 are diagrams of various embodiments of an IC device at various stages of fabrication in accordance with various aspects of the present disclosure.

[0026] Fig.13 is a flow chart of a method of forming an IC device according to various embodiments.

[0027] Fig.14 is a flow chart of a method of forming an IC device with regrown source / drain according to various embodiments. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0029] Additionally, spatially relative terms (e.g., "below," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation other than the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0030] Terms expressing relative degrees, such as "about", "substantially", etc., should be interpreted as understood by one of ordinary skill in the art in view of the current technical specification.

[0031] The terms "first", "second", "third", etc. may be used herein to describe a sequence of events or a sequential order of elements, but may be interchangeable or varied in some contexts. For example, the second layer may be formed on (e.g., sequentially after) the first layer, but in some contexts, the first layer may be referred to as the "second layer", "third layer", "fourth layer", etc., and the second layer may be referred to as the "first layer", "third layer", "fourth layer", etc.

[0032] The term "surrounding" may be used herein to describe a structure (e.g., in three dimensions) that completely or partially surrounds another element or structure. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left side, right side, front side, and back side) without surrounding the second structure on two vertical sides (e.g., top side and bottom side). In other examples, a first structure may partially surround a second structure, for example, by surrounding three sides (e.g., top side, front side, and back side) while leaving other sides (e.g., left side, right side, and bottom side) exposed.

[0033] The present disclosure relates generally to semiconductor devices, and more specifically to field effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured FETs (e.g., nanosheet FETs (NSFETs), nanowire FETs (NWFETs)), gate all-around FETs (GAAFETs), etc.

[0034] Defects may relax the source-drain epitaxial stress, which may lead to a significant difference in the on-current versus off-current (e.g., I on -I off ) degradation. One observed defect source is (111) or other directional stacking faults. The source / drain material may also have high resistance due to insufficient dopant activation. The process used to form the source / drain may lack selectivity for process conditions that can restore source / drain stress and improve dopant activation.

[0035] Embodiments of the present disclosure form an amorphized source / drain epitaxy followed by solid phase epitaxial regrowth (SPER), which causes the amorphous source / drain epitaxy to regrow or recrystallize to form the source / drain. Amorphization of the source / drain epitaxy can be performed via ion implantation or via a post-source-drain epitaxial material that introduces a substantially completely amorphous source-drain material. A subsequent annealing process results in SPER, which causes the amorphous source / drain material to regrow or recrystallize. SPER can be performed in a single anneal or multiple anneals prior to the formation of a contact etch stop layer (CESL), the formation of an interlayer dielectric (ILD), and / or the formation of a replacement gate. Alternatively or additionally, SPER can be performed during or after the formation of the CESL, ILD, and replacement gate as part of a thermal budget.

[0036] These embodiments are associated with benefits. The SPER operation is selected to eliminate defects and restore stress in the source / drain material. This is at least due to the fact that SPER is an order of magnitude faster along the (100) direction than along the (111) direction. Performing SPER on amorphous source / drain material to regrow or recrystallize the amorphous source / drain material can restore stress in the source / drain material on the adjacent channel due to reduced stacking faults. Recovery can be selected through a combination of an amorphizing ion implantation and an annealing process. The amorphizing ion implantation can eliminate or reduce defects (such as (111) stacking fault defects) generated during epitaxial growth prior to the annealing process. Performing SPER can improve dopant activation, which can be useful for improving I on -I off Amorphization ion implantation and annealing processes can enhance the stress in the source / drain region, thereby improving the electrical performance of the channel.

[0037] Figure 1A A schematic cross-sectional side view of a portion of a nanostructured device 10 is shown according to various embodiments. Figure 1A A view in the XZ plane is shown. Figure 1A The nanostructured device 10 is provided to provide a method for understanding Figures 2A to 12Context of technical features and benefits of various embodiments depicted. Nanostructured device 10 includes source / drain regions (or "source / drains") 82P, 82N, which may be substantially free of stacking fault defects or have a reduced number of stacking fault defects due to SPER performed during and / or after forming the source / drain regions. (One or more) source / drain regions may be referred to as a source or a drain individually, or may be referred to collectively as a source and a drain, depending on the context. Although nanostructured device 10 is described with reference to nanosheet transistors (or "nanostructured devices" 20A, 20B), it should be understood that these embodiments may also include planar field effect transistors (FETs), fin FETs (or FinFETs), etc., each of which may include source / drain regions that have undergone SPER, as will be referred to in reference to Figures 1A to 12 As described.

[0038] refer to Figure 1A , the nanostructure devices 20A, 20B may be or include one or more N-type FETs (NFETs) or P-type FETs (PFETs). The nanostructure devices 20A, 20B are formed on and / or in the substrate 110 and generally include a gate structure 200 that spans and / or surrounds the semiconductor channels 22A, 22B, 22C (also referred to as "nanostructures"), the gate structure 200 being located on the semiconductor fins 32 that protrude from and are separated by the isolation structures 36 (see Figure 3B The gate structure 200 controls the flow of current through the channels 22A, 22B, 22C.

[0039] The nanostructured devices 20A, 20B shown include three channels 22A, 22B, 22C, which are laterally adjacent to source / drain regions 82N, 82P and are covered and surrounded by a gate structure 200. Typically, the number of channels 22 is two or more, such as three or four or more. The gate structure 200 controls the flow of current through the channels 22A, 22B, 22C to the source / drain regions 82N, 82P and from the source / drain regions 82N, 82P through the channels 22A, 22B, 22C based on the voltage applied to the gate structure 200 and the source / drain regions 82N, 82P. The source / drain regions 82N, 82P are alternatively referred to as source / drain regions 82.

[0040] In some embodiments, the fin structure 32 comprises silicon. In some embodiments, the nanostructure device 20B comprises an NFET and its source / drain regions 82N comprise silicon phosphorus (SiP), SiAs, SiSb, SiPAs, SiP:As:Sb, combinations of the foregoing, or the like. In some embodiments, the nanostructure device 20A comprises a PFET and its source / drain regions 82P comprise silicon germanium (SiGe), which is undoped or doped to form, for example, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or another suitable semiconductor material. In general, the source / drain regions 82N, 82P may comprise any combination of (one or more) suitable semiconductor materials and (one or more) suitable dopants. In some embodiments, the source / drain regions 82N, 82P comprise Si x C y 、Si x Ge y 、Si x Sb y 、Si x P y 、Si x As y , where 0<x<1 and 0<y<1, as appropriate.

[0041] In some embodiments, the source / drain regions 82N, 82P may include one or more implanted ions, which may be or include one or more substances, such as group III substances (including B, Al, Ga), group IV substances (including C, Si, Ge), group V substances (including P, As, Sb), group VIII substances (including He, Ar, Xe), combinations of the foregoing, etc. FIG. 8A to FIG. 8H As described above, the ions may be implanted using an implantation energy in the range of about 1 kiloelectron volt (keV) to about 60 keV. In some embodiments, the ion implantation dose exceeds about 1×10 13 cm -2 , for example, at about 1×10 13 cm -2 About 1×10 22 cm -2 In some embodiments, the dosage of the group III and / or group V substances is about 1×10 19 cm -2 About 1×10 22 cm -2 This is beneficial to improve the SPER rate. 22 cm -2, which may reduce the SPER rate. The implantation temperature may be in the range of about -150°C to about 500°C. In some embodiments, the implantation temperature is room temperature. Higher temperatures (e.g., greater than about 500°C) may reduce the generation of defects in the implantation process. Temperatures in the cryogenics range may improve the formation of amorphous source / drain materials. "High temperature cryogenics" may refer to a range of about -50°C to about -195.79°C, and "low temperature cryogenics" may refer to a temperature below about -195.79°C. The cryogenic range may include high temperature cryogenics, low temperature cryogenics, or a combination thereof.

[0042] Channels 22A, 22B, 22C each include a semiconductor material, such as silicon or a silicon compound (e.g., silicon germanium, etc.). Channels 22A, 22B, 22C are nanostructures (e.g., having a size in the range of several nanometers) and may also each have an elongated shape and extend in the X direction. In some embodiments, channels 22A, 22B, 22C each have a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shapes. The cross-sectional profile of channels 22A, 22B, 22C may be rectangular, circular, square, annular, elliptical, hexagonal, or a combination of the foregoing.

[0043] In some embodiments, the lengths of the channels 22A, 22B, 22C (eg, measured in the X direction) may be different from each other, for example due to tapering during a fin etching process (see FIG. Figure 3A , Figure 3B ). In some embodiments, the length of channel 22C may be less than the length of channel 22B, and the length of channel 22B may be less than the length of channel 22A. For example, due to a channel trimming process used to expand the spacing between channels 22A, 22B, and 22C (e.g., measured in the Z-axis direction) to increase the gate structure manufacturing process window, channels 22A, 22B, and 22C may not each have a uniform thickness (e.g., along the X-axis direction). For example, the middle of each of channels 22A, 22B, and 22C may be thinner than the ends of each of the channels 22A, 22B, and 22C. This shape may be collectively referred to as a "dog-bone" shape.

[0044] In some embodiments, the spacing between channels 22A, 22B, 22C (e.g., between channels 22B and 22A or between channels 22B and 22C) is in a range between about 8 nanometers (nm) and about 12 nm, although ranges above or below the range may also be advantageous. In some embodiments, the thickness of each of channels 22A, 22B, 22C (e.g., measured in the Z direction) is in a range between about 5 nm and about 8 nm, although ranges above or below the range may also be advantageous. In some embodiments, the width of each of channels 22A, 22B, 22C (e.g., measured in the Z direction) is in a range between about 5 nm and about 8 nm, although ranges above or below the range may also be advantageous. Figure 3B The width of the optical fiber 20 is shown as measured in the Y direction perpendicular to the XZ plane) is at least about 8 nm, but in some embodiments, the width can be less than 8 nm.

[0045] A gate structure 200 is disposed on and between the channels 22A, 22B, and 22C, respectively. In some embodiments, the gate structure 200 is disposed on and between the channels 22A, 22B, and 22C, and the channels 22A, 22B, and 22C are silicon channels for N-type devices or silicon germanium channels for P-type devices. In some embodiments, the gate structure 200 includes an interfacial layer (IL) 210, one or more gate dielectric layers 600 on the interfacial layer 210, and optionally one or more work function tuning layers 900 (see FIG. 1 ) on the gate dielectric layer 600. Fig.12 ), and a metal core layer 290 on the gate dielectric layer 600 and optionally on the work function tuning layer 900 .

[0046] The interface layer 210 may be an oxide of the material of the channels 22A, 22B, 22C, which is formed on the exposed areas of the channels 22A, 22B, 22C and the top surface of the fin 32. The interface layer 210 promotes the adhesion of the gate dielectric layer 600 to the channels 22A, 22B, 22C. In some embodiments, the interface layer 210 has a thickness of about 5 angstroms (A) to about 50 angstroms (A). In some embodiments, the interface layer 210 has a thickness of about 10A. An interface layer 210 having too thin a thickness may exhibit voids or insufficient adhesion properties. An interface layer 210 that is too thick may consume the gate fill window, which is related to threshold voltage tuning and resistance. In some embodiments, the interface layer 210 is doped with a dipole (e.g., lanthanum) for threshold voltage tuning.

[0047] In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Example high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or a combination of the foregoing. In some embodiments, the gate dielectric layer 600 has a thickness of about 5 Å to about 100 Å. The gate dielectric layer 600 may be a single layer or a multilayer.

[0048] The gate structure 200 also includes a metal core layer 290. The metal core layer 290 may include a conductive material, such as Co, W, Ru, combinations thereof, etc. In some embodiments, the metal core layer 290 is or includes a compound or alloy based on Co, W, or Ru, which includes one or more elements, such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations of the foregoing, etc. Between the channels 22A, 22B, 22C, the metal core layer 290 is circumferentially surrounded (in the cross-sectional view) by one or more work function metal layers 900, which in turn are circumferentially surrounded by a gate dielectric layer 600, which is circumferentially surrounded by an interface layer 210. The gate structure 200 may also include a glue layer formed between the one or more work function layers 900 and the metal core layer 290 to increase adhesion. For simplicity, in Figure 1A The glue layer is not specifically shown.

[0049] The nanostructured device 20A, 20B may also include a source / drain contact 120, which is formed on the source / drain region 82N, 82P. The source / drain contact 120 may include a core layer, which is or includes a conductive material, such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or a combination of the foregoing. The core layer may be surrounded by one or more liner (or "barrier") layers (e.g., SiN or TiN), which help prevent or reduce material from diffusing from the source / drain contact 120 or prevent or reduce material from diffusing into the source / drain contact 120. In some embodiments, the height of the source / drain contact 120 may be in the range of about 1 nm to about 50 nm.

[0050] The silicide layer 118 is located between the source / drain regions 82N, 82P and the source / drain contacts 120 to at least reduce the source / drain contact resistance. In some embodiments, the silicide layer 118 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, Ysi, HoSi, TbSI, GdSi, LuSi, DySi, ErSi, YbSi, etc. In some embodiments, the silicide layer 118 is or includes NiSi, CoSi, MnSi, Wsi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc. The silicide layer 118 may have a thickness in the range of about 1nm to about 10nm. A thickness lower than about 1nm may result in insufficient reduction of the contact resistance. A thickness greater than about 10nm may result in an electrical short circuit with the nanostructure 22. In some embodiments, the silicide layer 118 is present below the etch stop layer 131 and in contact with it.

[0051] The nanostructured devices 20A, 20B may also include an interlayer dielectric 130 (ILD; see Fig.9A , Fig. 9B ). The ILD 130 provides electrical isolation between various components of the nanostructured devices 20A, 20B described above, for example, between adjacent pairs of source / drain contacts 120. The etch stop layer 131 (see Fig.11 ) may be formed before forming the ILD 130, and may be laterally located between the ILD 130 and the gate spacer 41, and vertically located between the ILD 130 and the source / drain regions 82N, 82P. In some embodiments, the etch stop layer 131 is or includes SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO x 、HfAlO x 、HfSiO x , Al2O3, or other suitable materials. In some embodiments, the thickness of the etch stop layer is in the range of about 1 nm to about 5 nm. In some embodiments, in the absence of ILD 130 (e.g., completely removed before forming the source / drain contact 120), the etch stop layer 131 may contact the source / drain contact 120. Before forming the source / drain contact 120, the etch stop layer 131 may be trimmed, for example, in the X-axis direction, to improve the filling quality of the source / drain contact 120.

[0052] Nanostructured devices 20A and 20B include gate spacers 41 and internal spacers 74. Gate spacers 41 are disposed on the sidewalls of metal core layer 290, gate dielectric layer 600 and IL 210 above channel 22A. Internal spacers 74 are disposed on the sidewalls of IL 210 and / or gate dielectric layer 600 between channels 22A, 22B, and 22C. Internal spacers 74 are also disposed between channels 22A, 22B, and 22C. Figure 1A In the depicted embodiment, the gate spacer 41 includes a first spacer layer 41A and a second spacer layer 41B on the first spacer layer 41A. The first spacer layer 41A and the second spacer layer 41B may each include a dielectric material, such as a low-k material, such as SiOCN, SiON, SiN, SiCN, SiOC, etc. In some embodiments, the second spacer layer 41B does not exist. The materials of the first spacer layer 41A and the second spacer layer 41B may be the same or different from each other. In some embodiments, the upper portion of the second spacer layer 41B (or the first spacer layer 41A when the second spacer layer 41B does not exist) may be partially or completely removed to increase the aspect ratio of the opening through which the source / drain regions 82N, 82P are formed. Figure 1A An embodiment is depicted in which the upper portion of the second spacer layer 41B is not thinned.

[0053] The isolation structure 90 may be located on either side of the respective nanostructure device 20A, 20B. In some embodiments, the isolation structure 90 extends from a level below the bottom surface of the source / drain 82N, 82P to a level above the upper surface of the source / drain 82N, 82P. The isolation structure 90 may include one or more dielectric layers that provide physical and / or electrical isolation between the nanostructure device 20A, 20B and adjacent devices. In some embodiments, the isolation structure 90 is not present.

[0054] exist Figure 1A In the embodiment of the present invention, nanostructure devices 20A, 20B are depicted as being located on the same substrate 110 and being located on different regions of the substrate 110, for example offset from each other on the substrate 110. In some embodiments, nanostructure device 20A is a p-type field effect transistor (PFET) and nanostructure device 20B is an n-type field effect transistor (NFET). In some embodiments, nanostructure device 20B includes a dielectric layer 800 that isolates source / drain 82N from the underlying substrate 110 or fin 32. Dielectric layer 800 may be referred to as a flexible bottom insulator (FBI), bottom dielectric isolation (BDI), etc.

[0055] exist Figure 1A, the source / drain 82P may include a first source / drain portion 82P1 and a second source / drain portion 82P2 on the first source / drain portion 82P1. The first source / drain portion 82P1 is adjacent to the undoped semiconductor layer 110A below the source / drain 82P and the channel 22. The second source / drain portion 82P2 is located on the first source / drain portion 82P1. A visible interface may exist between the first source / drain portion 82P1 and the second source / drain portion 82P2. In some embodiments, the first source / drain portion 82P1 and the second source / drain portion 82P2 are different in one or more aspects. For example, the first source / drain portion 82P1 and the second source / drain portion 82P2 may have different materials from each other, such as different dopant concentrations from each other. In some embodiments, the first source / drain portion 82P1 and the second source / drain portion 82P2 are substantially the same material, but have different crystal orientations due to being formed in different epitaxial growth operations.

[0056] The source / drain 82N may include a first source / drain portion 82N1 and a second source / drain portion 82N2 on the first source / drain portion 82N1. The first source / drain portion 82N1 is adjacent to the channel 22. The second source / drain portion 82N2 is located on the first source / drain portion 82N1 and the dielectric layer 800. A visible interface may exist between the first source / drain portion 82N1 and the second source / drain portion 82N2. In some embodiments, the first source / drain portion 82N1 and the second source / drain portion 82N2 are different in one or more aspects. For example, the first source / drain portion 82N1 and the second source / drain portion 82N2 may have different materials from each other, such as different dopant concentrations from each other. In some embodiments, the first source / drain portion 82N1 and the second source / drain portion 82N2 are substantially the same material, but have different crystal orientations due to being formed in different epitaxial growth operations.

[0057] Figure 1B A simplified diagram depicts a process 400 for regrowing or recrystallizing source / drain 82 according to various embodiments.

[0058] exist Figure 1B In the embodiment, the source / drain 82 includes a first portion 82_1 and a second portion 82_2 on the first portion 82_1. The first portion 82_1 may be an embodiment of a first source / drain portion 82N1, 82P1, and the second portion 82_2 may be an embodiment of a second source / drain portion 82N2, 82P2. Figure 1B Dielectric layer 800 is depicted in FIG. 8 , but may be omitted in some embodiments.

[0059] The source / drain 82 may include one or more stacking faults 82F, which may be (111) oriented stacking faults 82F. The stacking faults 82F may be oriented at an offset angle θ, which may be about 54.7° from the horizontal direction or about 35.3° from the vertical direction.

[0060] In process 400 , the source / drain 82 may be amorphized and then solid phase epitaxial regrowth (SPER) may be performed via one or more anneals that recrystallize the source / drain 82 to remove the stacking faults 82F.

[0061] refer to Fig.13 and Fig.14 The methods 1000, 2000 and Figures 2A to 12 An embodiment of process 400 is described in more detail with reference to a diagram of device 10 at an intermediate processing stage depicted in FIG.

[0062] Fig.13 and Fig.14 Flowcharts of methods 1000, 2000 for forming an IC device or portion thereof from a workpiece according to one or more aspects of the present disclosure are depicted. Methods 1000, 2000 are merely examples and are not intended to limit the present disclosure to what is explicitly shown in methods 1000, 2000. Additional actions may be provided before, during, and after methods 1000, 2000, and some of the actions described may be replaced, eliminated, or moved for use in additional embodiments of the methods. For simplicity, not all actions are described in detail herein. Figures 2A to 12 Methods 1000, 2000 are described with reference to partial perspective views and / or cross-sectional views of a workpiece at different stages of manufacture according to embodiments of methods 1000, 2000 as shown in . For the avoidance of doubt, in all figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X direction and the Y direction. It should be noted that because the workpiece can be manufactured into a semiconductor device, the workpiece can be referred to as a semiconductor device as the context requires.

[0063] Figures 2A to 12 is a diagram of an intermediate stage in the fabrication of a FET (eg, a nanostructure FET) according to some embodiments.

[0064] exist Figure 2A and Figure 2BIn the invention, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate (e.g., a bulk semiconductor, etc.), which may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The semiconductor material of the substrate 110 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination of the foregoing. Other substrates may be used, such as single-layer, multi-layer, or gradient substrates.

[0065] In addition, Figure 2A and Figure 2B In the embodiment, a multilayer stack 25 or "lattice" of alternating layers of first semiconductor layers 21A, 21B (collectively referred to as first semiconductor layers 21) and second semiconductor layers 23 is formed on a substrate 110. In some embodiments, the first semiconductor layer 21 can be formed of a first semiconductor material suitable for n-type nanoFETs, such as silicon, silicon carbide, etc., and the second semiconductor layer 23 can be formed of a second semiconductor material suitable for p-type nanoFETs, such as silicon germanium, etc. Each of the layers 21, 23 of the multilayer stack 25 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0066] Three layers of each of the first semiconductor layer 21 and the second semiconductor layer 23 are shown. In some embodiments, the multilayer stack 25 may include fewer or more pairs of the first semiconductor layer 21 and the second semiconductor layer 23. Although the multilayer stack 25 is shown to include the second semiconductor layer 23 as the bottom layer, in some embodiments, the bottom layer of the multilayer stack 25 may be the first semiconductor layer 21.

[0067] Due to the high etching selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form the channel region of the nanoFET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form the channel region. The high etching selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form the channel region of the nanoFET.

[0068] exist Figure 3A and Figure 3B In the embodiment, fins are formed in the substrate 110, and nanostructures 22, 24 are formed in the multilayer stack 25. Fig.13, which corresponds to action 1100. In some embodiments, the nanostructures 22, 24 and the fins 32 may be formed by etching grooves in the multilayer stack 25 and the substrate 110. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. The first nanostructures 22A, 22B, 22C (hereinafter also referred to as "channels 22") are formed by the first semiconductor layer 21, and the second nanostructure 24 is formed by the second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 may be from about 18 nm to about 100 nm, but in some embodiments a distance CD1 less than 18 nm may be beneficial. To simplify the description, in Figure 3A and 3B A portion of a device 10 is shown in FIG. 1 , which includes two fins 32 . Fig.13 The process 1000 shown can be extended to any number of fins and is not limited to Figures 3A to 12 Two fins 32 are shown.

[0069] The fins 32 and nanostructures 22, 24 may be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multi-patterning processes) may be used to form the fins 32 and nanostructures 22, 24. Typically, the double patterning or multi-patterning process combines lithography and self-alignment processes, allowing for a pitch that is smaller than that obtainable using a single direct lithography process. As an example of a multi-patterning process, a sacrificial layer may be formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 32.

[0070] Figure 3A and Figure 3B The fin 32 is shown with tapered sidewalls such that the width of the fin 32 and / or the respective nanostructures 22, 24 continuously increases in a direction toward the substrate 110. In such an embodiment, each of the nanostructures 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered) such that the widths of the fin 32 and the nanostructures 22, 24 are substantially similar, and each of the nanostructures 22, 24 is rectangular in shape.

[0071] exist Figure 3A and Figure 3BIn the embodiment of the present invention, an isolation region or feature 36 (which may be a shallow trench isolation (STI) region or feature) is formed adjacent to the fin 32. The isolation region 36 may be formed by depositing an insulating material over the substrate 110, the fin 32, and the nanostructures 24, 26, and between adjacent fins 32 and nanostructures 22, 24. The insulating material may be an oxide, such as silicon oxide, nitride, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof, etc. In some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 110, the fin 32, and the nanostructures 22, 24. Thereafter, a core material such as discussed above may be formed over the liner.

[0072] The insulating material undergoes a removal process (eg, chemical mechanical polishing (CMP), an etch back process, a combination thereof, etc.) to remove excess insulating material above the nanostructures 22, 24. After the removal process is completed, the top surfaces of the nanostructures 22, 24 may be exposed and flush with the insulating material.

[0073] The insulating material is then recessed to form isolation regions 36. After the recessing, the upper portions of the nanostructures 22, 24 and the fins 32 may protrude from between adjacent isolation regions 36. The insulating regions 36 may have a top surface that is flat, convex, concave, or a combination of the foregoing as shown. In some embodiments, the isolation regions 36 are recessed by an acceptable etching process (e.g., oxide removal using, for example, dilute hydrofluoric acid (dHF)), which is selective to the insulating material and does not substantially alter the fins 32 and nanostructures 22, 24.

[0074] FIG. 2A to FIG. 3B One embodiment of forming the fin 32 and nanostructures 22, 24 is shown (e.g., etched last). In some embodiments, the fin 32 and / or nanostructures 22, 24 are epitaxially grown in trenches in the dielectric layer (e.g., etched first). The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material.

[0075] exist Figure 3A and Figure 3BIn the embodiment of the present invention, appropriate wells (not shown separately) may be formed in the fins 32, nanostructures 22, 24, and / or isolation regions 36. Using a mask, n-type impurity implantation may be performed in the p-type region of the substrate 110, and p-type impurity implantation may be performed in the n-type region of the substrate 110. Example n-type impurities may include phosphorus, arsenic, antimony, etc. Example p-type impurities may include boron, boron fluoride, indium, etc. Annealing may be performed after implantation to repair implant damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the fins 32 and nanostructures 22, 24 may avoid separate implantations, but in-situ and implantation doping may be used together.

[0076] exist FIG. 4A to FIG. 4C In the embodiment, a dummy or sacrificial gate structure 40 is formed over the fin 32 and / or the nanostructures 22, 24, and Fig.13 The dummy gate layer 45 is formed on the fin 32 and / or the nanostructure 22, 24. The dummy gate layer 45 may be or include a material having a high etching selectivity relative to the isolation region 36. The dummy gate layer 45 may be a conductive material or a non-conductive material, and may be or include amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 45 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. A mask layer 47 is formed on the dummy gate layer 45, and the mask layer 47 may include, for example, silicon nitride, silicon oxynitride, etc. In some embodiments, before the dummy gate layer 45, a gate dielectric layer 43 is formed between the dummy gate layer 45 and the fin 32 and / or the nanostructure 22, 24. In some embodiments, the mask layer 47 includes a first mask layer 47A and a second mask layer 47B, wherein the first mask layer 47A contacts the dummy gate layer 45 and the second mask layer 47B overlies and contacts the first mask layer 47A. The first mask layer 47A may be or include the same or different material as the second mask layer 47B.

[0077] A spacer layer 41 is formed on the sidewalls of the mask layer 47 and the dummy gate layer 45. According to some embodiments, the spacer layer 41 is or includes an insulating material, such as SiOCN, SiOC, SiCN, etc. (or reference numerals). Figure 1A 4 and 4. The spacer layer 41 may be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the dummy gate layer 45. According to some embodiments, an anisotropic etching process is used to remove portions of the spacer material layer between the dummy gate structures 40. In some embodiments, as shown in FIG. Figure 4B and Figure 4CAs shown in detail in FIG. 1 , the spacer layer 41 includes a first spacer layer 41A, and the first spacer layer 41A contacts the nanostructure 22C, the gate dielectric layer 43, the dummy gate layer 45, and the first mask layer 47A and the second mask layer 47B. The second spacer layer 41B of the spacer layer 41 may contact the first spacer layer 41A. The first spacer layer 41A may be or include the same or different material as the second spacer layer 41B.

[0078] exist Figure 5A and Figure 5B In the embodiment, the source / drain opening 59 is formed by performing an etching process to etch the protruding fin 32 and / or the portion of the nanostructures 22, 24 not covered by the dummy gate structure 40, and Fig.13 The recess may be anisotropic, so that the portion of the fin 32 directly below the dummy gate stack 40 and the gate spacer 41 is protected and substantially not etched. According to some embodiments, the top surface of the recessed fin 32 may be substantially coplanar with the top surface of the isolation region 36. According to some other embodiments, such as Figure 5B As depicted in FIG. 1 , the top surface of the recessed fin 32 may be lower than the top surface of the isolation region 36. For simplicity, Figure 5A Three vertical stacks of nanostructures 22, 24 are depicted after the etching process. In general, the etching process may be used to form fewer or additional vertical stacks of nanostructures 22, 24 over the fins 32 than those depicted. In some embodiments, after the etching process, the second mask layer 47B is exposed, e.g., due to removal of upper portions of the spacer layers 41A, 41B during the etching process. Figure 5B Fin spacers 41F are depicted, which are portions of the first spacer layer 41A and / or the second spacer layer 41B overlying the isolation regions 36 adjacent to respective fins 32 .

[0079] 6A to 7B The formation of the internal spacer 74 is depicted according to various embodiments.

[0080] exist Fig. 6A , Figure 6B In the process, a selective etching process is performed to recess the end of the nanostructure 24 exposed through the opening in the spacer layer 41 without substantially attacking the nanostructure 22. After the selective etching process, a recess is formed in the nanostructure 24 where the removed end was once. Then, after the recess is formed, the inner spacer layer 74L is formed to (partially or entirely) fill the recess in the nanostructure 22 formed by the previous selective etching process. The inner spacer layer 74L can be a suitable dielectric material formed by a suitable deposition method such as PVD, CVD, ALD, etc., such as silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), etc.

[0081] exist Fig. 7A and Figure 7B In the embodiment, after forming the inner spacer layer 74L, an etching process (anisotropic etching process) is performed to remove the portion of the inner spacer layer 74 disposed outside the recess, for example, the portion on the sidewalls of the nanostructure 22 and the fin 32. The remaining portion of the inner spacer layer 74L (for example, the portion disposed within the recess in the nanostructure 24) forms the inner spacer layer 74. The resulting structure is as shown in FIG. Fig. 7A shown.

[0082] FIG. 8A to FIG. 8H The formation of a recrystallized source / drain 82 is depicted according to various embodiments.

[0083] exist Fig. 8A , Figure 8B , Figure 8C , Fig.8D In the embodiment, a first material layer 110A is formed in the source / drain opening 59, and Fig.13 The first material layer 110A may be or include an undoped semiconductor, such as undoped silicon. The deposition may include one or more operations (e.g., CVD), which may be ultra-high vacuum chemical vapor deposition (UHV-CVD), which allows for improved control of the deposition rate and purity of the first material layer 110A. The first material layer 110A may extend to a level at or slightly above the upper surface of the fin 32. In some embodiments, the first material layer 110A is not formed.

[0084] Then, an optional bottom insulator 800 and source / drain layer 82L are formed, with Fig.13 The operations 1500 and 1600 correspond to each other. A bottom insulator 800 may be formed on the first material layer 110A. In some embodiments, the bottom insulator 800 is formed in a region of the substrate 110 associated with the n-type source / drain 82N. Fig. 8A , Figure 8B The formation of a single type of source / drain 82 is described, but in action 1600, a similar structure as in reference Figure 1A The first source / drain 82N and the second source / drain 82P are depicted. For example, a device including an n-type source / drain 82N may benefit from including a bottom insulator 800 , while a device including a p-type source / drain 82P may benefit from not including a bottom insulator 800 .

[0085] The first source / drain 82N and the second source / drain 82P may be formed in different operations. For example, when forming the first source / drain 82N, the (one or more) regions of the substrate 110 where the second source / drain 82P is to be formed may be masked. Then, when forming the second source / drain 82P, the (one or more) regions of the substrate 110 where the first source / drain 82N has been formed are masked. The order of forming the first source / drain 82N and the second source / drain 82P may be opposite to the order just described. That is, the second source / drain 82P may be formed before the first source / drain 82N. In some embodiments, a first source / drain layer to be recrystallized to form the first source / drain 82N may be formed, and then a second source / drain layer to be recrystallized to form the second source / drain 82P may be formed, and vice versa.

[0086] In some embodiments, before or after forming the source / drain regions 82P, an optional bottom insulator 800 may be formed in the source / drain openings 59 associated with the n-type nanostructure device. The formation of the bottom insulator 800 may include a suitable deposition operation, such as LPCVD, PECVD, ALD, etc. The bottom insulator 800 may be or include SiN or another suitable dielectric material. The thickness of the bottom insulator 800 may be in the range of about 2 nm to about 4 nm.

[0087] After forming the bottom insulator 800, the source / drain region 82N (or n-type source / drain layer) is epitaxially grown from (one or more) epitaxial materials. Due to the bottom insulator 800, the source / drain layer 82L can be grown from the channel 22 without growing from the first semiconductor layer 110A. For example, Figure 8C As depicted, the source / drain layer 82L may have a first portion 82_1 that grows outward from the channel 22 and a second portion 82_2 that may grow from the first portion 82_1 .

[0088] exist Fig.8D In the embodiment of the present invention, a source / drain layer 82L that may be associated with a p-type nanostructure device may be epitaxially grown from (one or more) epitaxial materials. Since there is no bottom insulator 800, the source / drain layer 82L may be grown from the channel 22 and the undoped silicon layer 110A. For example, a first portion 82_1 of the source / drain layer 82L may be grown outward from the channel 22 and upward from the undoped silicon layer 110A, and a second portion 82_2 of the source / drain layer 82L may be grown from the first portion 82_1.

[0089] In some embodiments, a source / drain layer 82L associated with an n-type nanostructure device and a p-type nanostructure device may be formed directly on the first material layer 110A. That is, the bottom insulator 800 may be omitted from the n-type nanostructure device. For example, the source / drain layer 82L may be formed in both the n-type nanostructure device and the p-type nanostructure device in the same operation. Because one or more masking and patterning operations may be omitted, this may be beneficial in simplifying the process. In other embodiments, it may be beneficial to perform amorphization and SPER operations in an existing process including forming the bottom insulator 800. That is, the existing process may be only slightly modified to include additional amorphization and SPER operations without changing the underlying structure (e.g., including the bottom insulator 800).

[0090] The source / drain layer 82L is formed such that each dummy gate structure 40 is disposed between corresponding adjacent pairs of source / drain layers 82L. In some embodiments, the spacer layer 41 separates the source / drain layer 82L from the dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to a subsequently formed gate of the resulting device. The source / drain layer 82L may have a surface that protrudes from the corresponding surface of the fin 32 and may have a facet. In some embodiments, adjacent source / drain layers 82L may merge to form a single source / drain layer 82L adjacent to two adjacent fins 32.

[0091] exist Fig. 8E and Fig.8F In the embodiment, the amorphous source / drain layer 82A is formed by amorphizing the source / drain layer 82L. Fig.13 Action 1700 and Fig.14 Corresponding to action 2100.

[0092] The formation of the amorphous source / drain layer 82A or "amorphized source / drain layer 82A" may include one or more operations. The amorphization of the source / drain layer 82A may be via one or more ion implantation operations. In some embodiments, the (one or more) ion implantation operations include implanting one or more ions from implanted materials, which may include group III, group IV, group V, group VIII, and combinations of the foregoing. For example, group III ions may include ions of B, Al, or Ga, group IV ions may include ions of C, Si, or Ge, group V ions may include ions of P, As, or Sb, and group VIII ions may include ions of He, Ar, or Xe. The ions may be implanted at an implantation energy in the range of about 1 keV to about 60 keV. An implantation energy of more than about 1×10 13 cm -2 In some embodiments, the concentration of the ion dopant in the source / drain layer 82A is about 1×1019 cm -3 To about 1×1x10 22 cm -3 The SPER rate can be increased (or adjusted) by introducing group III and group V species in concentrations within the described range. Within this range, the SPER rate can be increased. Above about 1×10 22 cm -3 The SPER rate may be reduced. The ions may be implanted at an implantation temperature in the range of about -150°C to about 500°C (e.g., room temperature). A higher temperature (e.g., greater than about 400°C) may reduce the generation of defects during the implantation process, while a low temperature may enhance the amorphization of the source / drain layer 82L.

[0093] Amorphization may be performed in two or more separate operations, for example, to subsequently form the source / drain 82P, 82N of the p-type and n-type nanostructure devices, respectively. That is, a first ion implantation operation may be performed on the source / drain layer 82A associated with the p-type nanostructure device, and then a second ion implantation operation may be performed on the source / drain layer 82A associated with the n-type nanostructure device, or vice versa. In some embodiments, a first ion implantation operation may be performed to implant Group III ions in a p-type region of the substrate 110 associated with the p-type nanostructure device. Before or after the first ion implantation operation, a second ion implantation operation may be performed to implant Group V ions in an n-type region of the substrate 110 associated with the n-type nanostructure device.

[0094] In some embodiments, group IV and / or group VIII materials are simultaneously implanted in the source / drain layer 82A associated with the p-type and n-type nanostructure devices. For example, because group IV and / or group VIII materials do not substantially generate excess carriers in the lattice of the source / drain layer 82A, their ion implantation can be performed simultaneously on the n-type and p-type regions without masking any region. This is beneficial in simplifying the process when achieving amorphization of the source / drain layer 82L.

[0095] exist FIG. 8A to FIG. 8F In the description of FIG. 1 , the source / drain layer 82L is described as being formed in a crystalline state and then amorphized. In some embodiments, as shown in FIG. FIG. 8A to FIG. 8D The source / drain layer 82L formed as described is formed in an amorphous state, which can avoid the Fig. 8E and Fig.8F That is, in some embodiments, actions 1600 and 1700 may be performed simultaneously. In some embodiments, the source / drain layer 82L is formed in an amorphous state, and then ion implantation is performed on the source / drain layer 82L, as described in reference Fig. 8E , Fig.8FAs described, this is helpful.

[0096] Figure 8G , Figure 8H , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B is a diagram depicting the formation of a recrystallized or regrown source / drain 82 according to various embodiments. FIG. 8G to FIG. 10B Embodiments described. It should be understood that "recrystallization" and "regrowth" do not necessarily mean that the initial crystallization or growth is followed by a second (or third, etc.) crystallization or growth. For example, when the source / drain layer 82L is initially formed in an amorphous state, the "recrystallized" source / drain 82 may be crystallized for the first time. That is, "recrystallization" includes the meaning of "first crystallization".

[0097] exist Figure 8G , Figure 8H In the embodiment, the amorphized source / drain layer 82A may be recrystallized to form a recrystallized source / drain 82. Fig.13 Operation 1800 and Fig.14 The operation 2200 and the optional operation 2300 correspond to each other. The recrystallization may be performed by an operation including one or more solid phase epitaxial regrowth (SPER). The thermal budget of the (one or more) SPER may be the original thermal budget in the process flow, or may include (one or more) additional anneals, which is beneficial for increasing the flexibility of implementing (one or more) SPER in the existing process flow. For example, the original thermal budget may include the thermal budget for forming the CESL 131, the ILD 130, the gate structure 200, etc. For example, the (one or more) SPER may be performed after forming the CESL 131, the ILD 130, the gate structure 200, etc. In some embodiments, the thermal budget for forming the CESL 131 and / or the ILD 130 may include a temperature in the range of about 400° C. to about 800° C., for an interval in the range of about 10 minutes to about 12 hours. In some embodiments, the thermal budget for forming the gate structure 200 or the "replacement gate" 200 may include a temperature in the range of about 600° C. to about 1100° C., for an interval in the range of about 0.5 minutes to about 20 minutes.

[0098] The thermal budget after forming the gate structure 200 can be more limited (e.g., lower temperature) to improve threshold voltage (Vt) control. In some embodiments, instead of or in addition to the original thermal budget, one or more anneals can be performed before forming the CESL 131 (e.g., when the source / drain layer 82A is exposed in the source / drain opening 59).

[0099] In some embodiments, Figure 8G , Figure 8H As depicted, SPER(s) may be performed via additional anneal(s) when the source / drain layer 82A is exposed (e.g., before forming the CESL 131). The one or more anneals may include one or more of rapid thermal annealing (RTA), furnace annealing, millisecond annealing, microsecond annealing, flash annealing, laser annealing, melt laser annealing, combinations of the foregoing, and the like. For example, since the SPER is about 1 order of magnitude faster along the (100) direction than along the (111) direction, performing anneal(s) may repair or prevent (111) or other directional stacking faults and restore or improve the stress of the recrystallized source / drain 82. Some annealing operations (e.g., laser annealing) including higher temperatures and shorter times may dissolve interstitial clusters to increase dopant activation levels, for example, by dopant substitution. In some embodiments, performing anneal(s) includes a temperature range of about 600° C. to about 1200° C. for about 1×10 -10 seconds to about 1×10 6 The dopant solubility limit is the maximum concentration that can reach equilibrium with the host lattice. Performing one or more SPERs can result in an active concentration well above the dopant solubility limit, which can reduce the resistance of the recrystallized source / drain 82.

[0100] In some embodiments, the anneal(s) performed prior to forming the CESL 131 may partially or fully recrystallize the source / drain 82 . Figure 8G , Figure 8H Depicted is the partial formation of recrystallized source / drain 82 via one or more anneals performed while source / drain layer 82A is exposed. In some embodiments, the formation of recrystallized source / drain 82 is accomplished by SPER(s) performed while source / drain layer 82A is exposed.

[0101] like Figure 8G , Figure 8H As depicted, overlying the bottom insulator 800 ( Figure 8G ) can be recrystallized without the bottom insulator 800 ( Figure 8H) is completed before the recrystallization of the source / drain layer 82A without the bottom insulator 800. This may be due to the extra height of the source / drain layer 82A without the bottom insulator 800. That is, the source / drain layer 82A without the bottom insulator 800 may have an extra height approximately equal to the thickness of the bottom insulator 800. Therefore, the recrystallization of the source / drain layer 82A having the extra height may be completed after the recrystallization of the source / drain layer 82A overlying the bottom insulator 800. In some embodiments, the recrystallized source / drain 82 above the bottom insulator 800 may be completed by a first SPER, while the recrystallized source / drain 82 omitting the bottom insulator 800 may be completed by a second SPER after the first SPER.

[0102] Partial or complete formation of the recrystallized source / drain 82 may include a single SPER or two or more SPERs performed prior to forming the CESL 131 (eg, when the source / drain layer 82A is exposed).

[0103] In some embodiments, reference is omitted Figure 8G , Figure 8H The SPER(s) described herein may correspond to performing recrystallization of the source / drain layer 82A within the original thermal budget as previously described. Fig.14 This is depicted by the dashed boxes of actions 2200 and 2300.

[0104] Fig.9A and Fig. 9B The formation of CESL 131 and ILD 130 is described. ILD 130 can be formed to cover source / drain layer 82A and / or recrystallize source / drain 82 and abut (one or more) spacer layer 41. In some embodiments, CESL 131 is formed before forming ILD 130. CESL 131 can be formed by depositing a conformal thin layer of a dielectric material different from ILD 130, such as SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO x 、HfAlO x 、HfSiO x, Al2O3 or other suitable materials. After depositing CESL 131, ILD 130 may be deposited by a suitable process, such as a blanket deposition process including PVD, CVD, ALD, etc. The material of ILD 130 may include silicon dioxide or a low-k dielectric material (e.g., a material having a dielectric constant (k value) lower than the k value of silicon dioxide (about 3.9)). The low-k dielectric material may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiO x C y ), spin-on glass (SOG), or a combination of the foregoing. The ILD can be deposited by spin coating, CVD, flowable CVD (FCVD), PECVD, PVD, or another deposition process.

[0105] In some embodiments, completing the recrystallization of the source / drain layer 82A to form the recrystallized source / drain 82 may be performed simultaneously with and / or after forming the CESL 131 and the ILD 130, for example, using a thermal budget associated with each process. Fig.14 In some embodiments, source / drain layer 82A is not completely recrystallized during the formation of CESL 131 and / or ILD 130, but is partially recrystallized. In some embodiments, the thermal budget for forming CESL 131 and / or ILD 130 may include a temperature in the range of about 400° C. to about 800° C. for an interval in the range of about 10 minutes to about 12 hours. Act 2400 may be optional, such as Fig.14 For example, in embodiments where the recrystallized source / drain 82 is completed before forming the CESL 131, act 2400 may be omitted.

[0106] exist Fig. 10A , Fig. 10B In the process, the actual gate structure 200 is formed. A planarization process such as a chemical mechanical polishing (CMP) process is performed on the ILD 130 and the ESL 131. The hard masks 47A, 47B and a portion of the gate spacer 41 are also removed in the planarization process. After the planarization process, the dummy gate layer 45 is exposed. The top surfaces of the ILD 130 and the ESL 131 may be coplanar with the top surfaces of the dummy gate layer 45 and the gate spacer 41.

[0107] Next, the dummy gate layer 45 is removed in an etching process, thereby forming a recess. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate layer 45 without etching the spacer layer 41. When etching the dummy gate layer 45, the dummy gate dielectric 43 (when present) can be used as an etch stop layer. The dummy gate dielectric 43 can then be removed after removing the dummy gate layer 45.

[0108] The nanostructures 24 are removed to release the nanostructures 22. After the nanostructures 24 are removed, the nanostructures 22 form a plurality of nanosheets extending horizontally (e.g., parallel to the main upper surface of the substrate 110). In some embodiments, the nanostructures 24 are removed by a selective etching process using an etchant that is selective to the material of the nanostructures 24, thereby removing the nanostructures 24 without substantially attacking the nanostructures 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and an optional carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas, such as Ar, He, N2, a combination thereof, and the like.

[0109] In some embodiments, nanostructures 24 are removed and nanostructures 22 are patterned to form channel regions for both PFETs and NFETs. However, in some embodiments, nanostructures 24 may be removed and nanostructures 22 may be patterned to form channel regions for NFETs, and nanostructures 22 may be removed and nanostructures 24 may be patterned to form channel regions for PFETs. In some embodiments, nanostructures 22 may be removed and nanostructures 24 may be patterned to form channel regions for NFETs, and nanostructures 24 may be removed and nanostructures 22 may be patterned to form channel regions for PFETs. In some embodiments, nanostructures 22 may be removed and nanostructures 24 may be patterned to form channel regions for both PFETs and NFETs.

[0110] In some embodiments, the nanosheet 22 is reshaped (e.g., thinned) by a further etching process to improve the gate fill window. The reshaping may be performed by an isotropic etching process that is selective to the nanosheet 22. After the reshaping, the nanosheet 22 exhibits a dog-bone shape, wherein the middle portion of the nanosheet 22 is thinner than the peripheral portion of the nanosheet 22 along the X direction.

[0111] Then, a replacement gate 200 is formed. The gate structure 200 may be formed by a series of deposition operations, such as ALD cycles, which deposit various layers of the gate structure 200 in the opening, as described below with reference to Fig.12 As described.

[0112] In some embodiments, the thermal budget for forming the gate structure 200 or “replacement gate” 200 may include a temperature in a range of about 600° C. to about 1100° C. for an interval in a range of about 0.5 minutes to about 20 minutes.

[0113] Fig.12 is a detailed view of a portion of the gate structure 200. The gate structure 200 generally includes an interfacial layer (IL or "first IL" below) 210, at least one gate dielectric layer 600, a work function metal layer 900, and a gate fill layer 290. In some embodiments, each replacement gate 200 further includes at least one of a second interfacial layer 240 or a second work function layer 700.

[0114] refer to Fig.12 In some embodiments, the first IL 210 includes an oxide of the semiconductor material of the substrate 110, such as silicon oxide. In other embodiments, the first IL 210 may include another suitable type of dielectric material. The first IL 210 has a thickness in a range between about 5 angstroms and about 50 angstroms.

[0115] Still reference Fig.12 , a gate dielectric layer 600 is formed on the first IL 210. In some embodiments, an atomic layer deposition (ALD) process is used to form the gate dielectric layer 600 to precisely control the thickness of the deposited gate dielectric layer 600. In some embodiments, the ALD process is performed using between about 40 and 80 deposition cycles at a temperature range between about 200 degrees Celsius and about 300 degrees Celsius. In some embodiments, the ALD process uses HfCl4 and / or H2O as a precursor. Such an ALD process can form a first gate dielectric layer 220 having a thickness in a range between about 10 angstroms and about 100 angstroms.

[0116] In some embodiments, the gate dielectric layer 600 includes a high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or a combination of the foregoing. In other embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, wherein at least one high-k dielectric layer includes a dopant (e.g., lanthanum, magnesium, yttrium, etc.), which can be driven in by an annealing process to change the threshold voltage of the nanostructured device 20A, 20B.

[0117] Further references Fig.12, a second IL 240 is formed on the gate dielectric layer 600, and a second work function layer 700 is formed on the second IL 240. The second IL 240 promotes better adhesion of the metal gate on the gate dielectric layer 600. In many embodiments, the second IL 240 also provides improved thermal stability for the gate structure 200, and is used to limit the diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, the formation of the second IL 240 is achieved by first depositing a high-k cap layer (not shown for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k cap layer includes one or more of the following: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO or other suitable materials. In a specific embodiment, the high-k cap layer includes titanium silicon nitride (TiSiN). In some embodiments, the high-k cap layer is deposited by ALD at a temperature of about 400° C. to about 450° C. using about 40 to about 100 cycles. A thermal anneal is then performed to form the second IL 240, which in some embodiments may be or include TiSiNO. After the second IL 240 is formed by the thermal anneal, an atomic layer etch (ALE) with artificial intelligence (AI) control may be performed cyclically to remove the high-k cap layer without substantially removing the second IL 240. Each cycle may include a first pulse of WCl5, followed by an Ar purge, followed by a second pulse of O2, followed by another Ar purge. The high-k cap layer is removed by metal gate patterning to increase the gate fill window for further multi-threshold voltage tuning. In some embodiments, the thermal anneal includes a SPER that partially or completely completes the recrystallization of the source / drain layer 82A.

[0118] In addition, Fig.12 In some embodiments, after forming the second IL 240 and removing the high-k capping layer, a work function blocking layer 700 is optionally formed on the gate structure 200. The work function blocking layer 700 is or includes a metal nitride, such as TiN, WN, MoN, TaN, etc. In a specific embodiment, the work function blocking layer 700 is TiN. The work function blocking layer 700 can have a thickness ranging from about 5 to about 20. Including the work function blocking layer 700 provides additional threshold voltage tuning flexibility. Generally, the work function blocking layer 700 increases the threshold voltage of NFET transistor devices and reduces the threshold voltage (magnitude) of PFET transistor devices.

[0119] In some embodiments, a work function metal layer 900 is formed on the work function barrier layer 700, and the work function metal layer 900 may include at least one of an N-type work function metal layer, an in-situ capping layer, or an oxygen barrier layer. The N-type work function metal layer is or includes an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The N-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, electroplating, and / or other suitable methods, and the N-type work function metal layer has a thickness between about 10A and 20A. An in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN, or other suitable materials, and has a thickness between about 10A and 20A. An oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen from diffusing into the N-type work function metal layer, otherwise the diffusion of oxygen into the N-type work function metal layer may cause an undesirable shift in the threshold voltage. The oxygen barrier layer is formed of a dielectric material that can prevent oxygen from penetrating into the N-type work function metal layer and can protect the N-type work function metal layer from further oxidation. The oxygen barrier layer may include silicon, germanium, SiGe or other suitable materials. In some embodiments, the oxygen barrier layer is formed using ALD and has a thickness between about 10 Å and about 20 Å.

[0120] Fig.12 A metal core layer 290 is also shown. In some embodiments, a glue layer (not shown separately) is formed between the oxygen barrier layer of the work function metal layer and the metal core layer 290. The glue layer can promote and / or enhance the adhesion between the metal core layer 290 and the work function metal layer 900. In some embodiments, the glue layer can be formed by a metal nitride (e.g., TiN, TaN, MoN, WN) or another suitable material using ALD. In some embodiments, the thickness of the glue layer is between about 10A and about 25A. The metal core layer 290 can be formed on the glue layer, and the metal core layer 290 can include a conductive material, such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination of the foregoing. In some embodiments, the metal core layer 290 can be deposited using methods such as CVD, PVD, electroplating, and / or other suitable processes. In some embodiments, a seam 510 (which can be an air gap) is vertically formed between the channels 22A, 22B, and 22C in the metal core layer 290. In some embodiments, metal core layer 290 is conformally deposited on work function metal layer 900. Seams 510 may be formed due to merging of sidewall deposited films during conformal deposition. In some embodiments, seams 510 do not exist between adjacent channels 22A, 22B, 22C.

[0121] Reference again Fig. 10A , Fig. 10BAfter forming the gate structure 200, a source / drain contact opening may be formed in the ILD 130, and a source / drain contact 120 may be formed in the source / drain contact opening. Fig.14 The resulting structure is as shown in 10A, Fig. 10B A silicide region 118 is formed on the source / drain regions 82N and 82P (see Figure 1A and Fig.11 ) and source / drain contacts 120.

[0122] In some embodiments, a silicide layer 118 is formed before forming the source / drain contacts 120. For example, an n-type or p-type metal layer may be formed as a conformal thin layer over the exposed portions of the source / drain regions 82N, 82P. The metal layer may be or include one or more of the following: Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, etc. In some embodiments, the metal layer may be or include one or more of the following: Ti, Cr, Ta, Mo, Zr, Hf, Sc, Ys, Ho, Tb, Gd, Lu, Dy, Er, Yb, or another suitable material. After forming the metal layer, the silicide layer 118 may be formed by annealing the device 10. After annealing, the silicide layer 118 may be or include one or more of the following: NiSi, CoSi, MnSi, Wsi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, Ysi, HoSi, TbSI, GdSi, LuSi, DySi, ErSi, YbSi, etc. The silicide of the silicide layer 118 may diffuse into the area below the ESL 131. The thickness of the silicide layer 118 may be in the range of about 1 nm to about 10 nm. Below about 1 nm, the contact resistance may be too high. Above about 10 nm, the silicide layer 118 may be shorted with the channel 22B. In some embodiments, the annealing to form the silicide layer 118 includes a SPER that partially or completely completes the recrystallization of the source / drain layer 82A.

[0123] After forming the silicide layer 118, a source / drain contact 120 is formed by filling the openings above the source / drain regions 82N, 82P with, for example, a liner layer and a filler layer. In some embodiments, the source / drain contact 120 is formed by depositing a material that is or includes a conductive material such as Co, W, Ru, and combinations thereof. In some embodiments, the source / drain contact 120 is or includes a compound or alloy based on Co, W, or Ru, which includes one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations of the foregoing, and the like. The source / drain contact 120 falls on the silicide layer 118 and contacts the ESL 131. The description of the device 10 and its illustration in many of the figures are given with reference to a vertically stacked GAAFET including the nanostructure 22. In some embodiments, a silicide layer 118 and source / drain contacts 120 are formed in and over the source / drain regions 82N, 82P of a FinFET or planar device.

[0124] Fig.11 A schematic cross-sectional view of an IC device 10 including nanostructure devices 20A, 20B, 20C according to various embodiments is depicted. The IC device 10 may be Figure 1A and 10A , Fig. 10B Embodiments of the device are depicted, and like reference numerals denote like features.

[0125] exist Fig.11 , the IC device 10 includes a recrystallized source / drain 82. In some embodiments, one or more visible interfaces 82I1, 82I2 exist between a first portion 820A, a second portion 820B, and a third portion 820C of the recrystallized source / drain 82. For example, a first visible interface 82I1 may exist between the first portion 820A and the second portion 820B, and a second visible interface 82I2 may exist between the second portion 820B and the third portion 820C. The visible interfaces 82I1, 82I2 may exist due to stopping the SPER midway through the recrystallization of the source / drain layer 82A.

[0126] When the SPER of a continuous amorphous layer (e.g., source / drain layer 82A) is stopped midway through the process and then continued, several characteristics around the interfaces between the various recrystallized portions may be affected. The measurable characteristics that may be affected may include one or more of the following: crystal defect density, dopant distribution, stress and / or pressure, electrical properties, interface sharpness, material composition, optical properties, mechanical properties. For example, there may be an increased crystal defect density at the interface where the process stops and then restarts. For example, the crystal defect density in the visible interfaces 82I1, 82I2 may exceed the crystal defect density in the first portion 820A, the second portion 820B, and / or the third portion 820C. Defects may include dislocations, stacking faults, point defects, etc. The concentration of dopants may be different on both sides of the visible interfaces 82I1, 82I2, resulting in one or more dopant accumulation or depletion regions. For example, the dopant concentration in the first portion 820A may be different from the dopant concentration in the second portion 820B, or the dopant concentration in the second portion 820B may be different from the dopant concentration in the third portion 820C. Thermal cycling may cause stress or pressure around the visible interfaces 82I1, 82I2, which may cause lattice deformation. Changes in dopant distribution and defect density may lead to changes in electrical properties, such as changes in carrier mobility, carrier lifetime, and resistivity. The abruptness of the interface can be seen using a transmission electron microscope (TEM) or high-resolution X-ray reflectivity (XRR), which may show an interface that is not too sharp due to a stop in the process. During the stop, impurities or secondary phases may be formed at the visible interfaces 82I1, 82I2. Changes in defect density and stress at the interface may change the optical properties of the material. The visible interfaces 82I1, 82I2 may have mechanical properties different from the first, second, and third portions 820A, 820B, 820C, such as hardness or brittleness.

[0127] Additional SPER(s) may be performed after forming the gate structure 200 and / or the source / drain contacts 120, as described above. Fig.14 2600. In many embodiments, the thermal budget after forming the gate structure 200 is more limited (eg, lower temperature) to improve Vt control.

[0128] In the above, there may be differences between the recrystallized source / drain 82 of the p-type device and the recrystallized source / drain 82 of the n-type device. For example, differences in dopant materials and / or ion implantation processes for implanting different dopant materials may result in different concentrations or numbers of stacking faults in the recrystallized source / drain 82. For example, a first recrystallized source / drain 82 associated with a p-type device and including a group III dopant may have a stacking fault number that exceeds a second recrystallized source / drain 82 associated with an n-type device and including a group V dopant. In another example, the second recrystallized source / drain 82 may have a stacking fault number that exceeds the first recrystallized source / drain 82. Other such differences may include a concentration and / or distribution of stacking faults, a concentration, number and / or distribution of dislocations, etc. In this way, the device may include a substrate (e.g., substrate 110 or fin 32), a first semiconductor channel stack 22 on the substrate, and a second semiconductor channel stack 22 on the substrate. A first recrystallized source / drain 82 of a first type (e.g., p-type) may abut the first semiconductor channel stack 22, and a second recrystallized source / drain 82 of a second type (e.g., n-type) different from the first type may abut the second semiconductor channel stack 22. As described above, the second recrystallized source / drain 82 may have a first stacking fault number that exceeds a second stacking fault number of the second recrystallized source / drain 82.

[0129] After forming the source / drain contacts 120, a gate contact (or gate via; not separately shown) can be formed to be electrically coupled to the gate structure 200. An interconnect structure can then be formed over the source / drain contacts 120 and the gate contacts. The interconnect structure can include a plurality of dielectric layers (including, for example, a second ILD) having metal features embedded therein, including conductive traces and conductive vias. The metal features can form (one or more) electrical connections between devices on the substrate 110 (e.g., nanostructure devices 20A, 20B, 20C) and IC devices external to the IC device 10.

[0130] Embodiments may provide advantages. Amorphization via ion implantation and subsequent one or more SPERs allow for reduction of dislocation and / or stacking fault defects and improvement of dopant activation, which may reduce source / drain resistance and increase stress in the channel. The selection of ion implantation type and number of anneals, as well as the sequence of SPER operations, is flexible, which facilitates inclusion of these embodiments in existing processes.

[0131] According to at least one embodiment, a method includes: forming a nanostructure stack above a substrate; forming a source / drain opening adjacent to the nanostructure stack; forming a semiconductor layer in the source / drain opening; forming an amorphous semiconductor layer by performing ion implantation on the semiconductor layer; and forming a recrystallized source / drain by annealing the amorphous semiconductor layer.

[0132] According to at least one embodiment, a method includes: forming a nanostructure stack above a substrate; forming a source / drain opening adjacent to the nanostructure stack; forming a semiconductor layer in the source / drain opening; forming an amorphous semiconductor layer by amorphizing the semiconductor layer; and forming a source / drain by performing solid phase epitaxial regrowth on the amorphous semiconductor layer.

[0133] According to at least one embodiment, a device includes: a substrate; a first semiconductor channel stack on the substrate; a second semiconductor channel stack on the substrate; a first recrystallized source / drain of a first type, adjacent to the first semiconductor channel stack; and a second recrystallized source / drain of a second type different from the first type, adjacent to the semiconductor channel of the second stack, the first recrystallized source / drain having a first stacking fault number that exceeds a second stacking fault number of the second recrystallized source / drain.

[0134] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method comprising: forming a nanostructure stack on a substrate; forming a source / drain opening adjacent to the nanostructure stack; forming a semiconductor layer in the source / drain opening; forming an amorphous semiconductor layer by performing ion implantation on the semiconductor layer; as well as Recrystallized source / drain electrodes are formed by annealing the amorphous semiconductor layer.

2. The method according to claim 1, wherein: Annealing the amorphous semiconductor layer includes performing annealing while an upper surface of the amorphous semiconductor layer is exposed.

3. The method according to claim 2, wherein: The performing annealing includes performing at least two different anneals.

4. The method according to claim 2, wherein: The performing annealing is terminated after the amorphous semiconductor layer is completely regrown.

5. The method according to claim 1, wherein: Annealing the amorphous semiconductor layer includes: annealing the amorphous semiconductor layer after performing at least one of the following operations: forming a contact etch stop layer on the amorphous semiconductor layer; forming an interlayer dielectric on the contact etch stop layer; or A replacement gate is formed that surrounds the nanostructures of the nanostructure stack.

6. The method according to claim 5, further comprising: Before annealing the amorphous semiconductor layer, solid phase epitaxial regrowth is performed on the amorphous semiconductor layer through a second annealing.

7. The method according to claim 6, wherein: The performing of the solid phase epitaxial regrowth is terminated before the amorphous semiconductor layer is completely regrowthed.

8. A method comprising: forming a nanostructure stack on a substrate; forming a source / drain opening adjacent to the nanostructure stack; forming a semiconductor layer in the source / drain opening; forming an amorphous semiconductor layer by amorphizing the semiconductor layer; as well as Source / drain electrodes are formed by performing solid phase epitaxial regrowth on the amorphous semiconductor layer.

9. The method according to claim 8, wherein: Amorphizing the semiconductor layer includes implanting ions, the ions being a Group IV substance, a Group III substance, a Group V substance, or a Group VIII substance.

10. A device comprising: substrate; a first semiconductor channel stack on the substrate; a second semiconductor channel stack on the substrate; a first recrystallized source / drain of a first type adjacent to the first semiconductor channel stack; and A second recrystallized source / drain of a second type different from the first type adjoins the second semiconductor channel stack, the first recrystallized source / drain having a first stacking fault number that exceeds a second stacking fault number of the second recrystallized source / drain.

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