Semiconductor component and method of manufacturing the same

Abstract

The invention discloses a semiconductor component and a manufacturing method thereof. The manufacturing method of the semiconductor component comprises the following steps. A plurality of grooves are formed in a substrate. A first gate dielectric material is formed on the substrate and in the plurality of grooves. The first gate dielectric material on the substrate between the plurality of grooves is at least partially removed to form a trench. A second gate dielectric material is formed in the trench. A gate conductor layer is formed on the second gate dielectric material, and a plurality of spacers are formed on sidewalls of the gate conductor layer. And removing a part of the first gate dielectric material to enable the left first gate dielectric material and the second gate dielectric material to form a gate dielectric layer. The gate dielectric layer includes a body portion and a first hump portion. The first hump part is located on the first edge of the main body part, and the thickness of the first hump part is larger than that of the main body part. A plurality of doped regions are formed in the substrate on both sides of the plurality of spacers.

Description

Technical Field

[0001] The present invention relates to an integrated circuit and a method for forming the same, and in particular to a semiconductor component and a method for forming the same. Background Art

[0002] Transistors are very important components in integrated circuits. The ability to drive current (saturation current) and gate induced drain leakage (GIDL) are important factors affecting transistor performance. The ability to drive current can be improved by reducing the thickness of the gate dielectric layer. However, if the thickness of the gate dielectric layer is too thin, it is easy to cause gate induced drain leakage current to occur at the overlap of the gate and drain regions. Summary of the invention

[0003] The invention provides a semiconductor component and a manufacturing method thereof. The semiconductor component has a low starting voltage, can reduce gate-induced drain leakage current, and allows a higher source / drain voltage.

[0004] According to an embodiment of the present invention, a method for manufacturing a semiconductor component includes the following steps. A plurality of grooves are formed in a substrate. A first gate dielectric material is formed on the substrate and in the plurality of grooves. The first gate dielectric material on the substrate between the plurality of grooves is at least partially removed to form a groove. A second gate dielectric material is formed in the groove. A gate conductor layer is formed on the second gate dielectric material, and a plurality of spacers are formed on the sidewalls of the gate conductor layer. A portion of the first gate dielectric material is removed so that the remaining first gate dielectric material and the second gate dielectric material form a gate dielectric layer. The gate dielectric layer includes a main body and a first hump portion. The first hump portion is located at a first edge of the main body, wherein the thickness of the first hump portion is greater than the thickness of the main body. A plurality of doped regions are formed in the substrate on both sides of the plurality of spacers.

[0005] According to an embodiment of the present invention, a method for manufacturing a semiconductor component includes the following steps. A first gate dielectric material is formed on a substrate. The first gate dielectric material is patterned to form a groove. A second gate dielectric material is formed in the groove. A gate conductor layer is formed on the second gate dielectric material and the first gate dielectric material, and a plurality of spacers are formed on the sidewalls of the gate conductor layer. A portion of the second gate dielectric material and the first gate dielectric material is removed to form a gate dielectric layer, wherein the gate dielectric layer includes a main body and a first hump portion. The first hump portion is located at a first edge of the main body, wherein the thickness of the first hump portion is greater than the thickness of the main body. A plurality of doped regions are formed in the substrate on both sides of the plurality of spacers.

[0006] According to an embodiment of the present invention, a semiconductor component includes a gate structure and a plurality of doped regions. The gate structure includes a gate conductor layer and a gate dielectric layer. The gate conductor layer is located above the substrate. The gate dielectric layer is located between the gate conductor layer and the substrate. The gate dielectric layer includes a main body and a first hump portion. The main body is located on a flat surface of the substrate. The first hump portion is located on a portion of the flat surface at a first edge of the main body. The thickness of the first hump portion is greater than the thickness of the main body. The plurality of doped regions are located in the substrate on both sides of the gate structure.

[0007] Based on the above, the gate dielectric layer of the semiconductor component of the embodiment of the present invention has different thicknesses. The thickness of the main body in the central area of ​​the gate dielectric layer is thinner, which can reduce the threshold voltage. The thickness of the hump portion in the edge area of ​​the gate dielectric layer is thicker, which can reduce the gate induced drain leakage current and allow a higher source / drain voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1J is a cross-sectional schematic diagram of a method for manufacturing a semiconductor component according to an embodiment of the present invention;

[0009] FIG. 2A to FIG. 2C is a cross-sectional schematic diagram of a method for manufacturing a semiconductor component according to another embodiment of the present invention;

[0010] Figures 3 to 5 are cross-sectional schematic diagrams of various semiconductor components according to several embodiments of the present invention;

[0011] 6A to 6F It is a cross-sectional schematic diagram of a method for manufacturing a semiconductor component according to other embodiments of the present invention. DETAILED DESCRIPTION

[0012] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0013] Figures 1A to 1J It is a cross-sectional schematic diagram of a method for manufacturing a semiconductor component according to an embodiment of the present invention.

[0014] Reference Figure 1A , providing a substrate 10. The substrate 10 includes a semiconductor substrate, a semiconductor compound substrate, such as a silicon substrate, a silicon germanium substrate. The substrate 10 may also be a silicon-on-insulator (SOI) substrate. A mask layer 16 is formed on the substrate 10. The mask layer 16 may include a silicon oxide layer 12 and a silicon nitride layer 14. The mask layer 16 has a plurality of openings OP1, exposing the surface of the substrate 10. Afterwards, a thermal oxidation process is performed to form an oxide layer 18 on the surface of the substrate 10 exposed by the openings OP1.

[0015] Reference Figure 1B , an etching process, such as a wet etching process, is performed to remove the mask layer 16 and the thermal oxide layer 18 to expose the surface of the substrate 10 and form a plurality of grooves 20 in the substrate 10. The grooves 20 may be formed in various ways, not limited to the above.

[0016] Reference Figure 1C , a mask layer 26 is formed on the substrate 10. The mask layer 26 may include a silicon oxide layer 22 and a silicon nitride layer 24. The mask layer 26 is patterned by photolithography and etching processes to have a plurality of openings OP2 exposing the surface of the substrate 10. Next, an etching process, such as an anisotropic etching process, is performed to remove a portion of the substrate 10, and a plurality of trenches 27 are formed in the substrate 10. The depth of the trench 27 is greater than the depth of the recess 20.

[0017] Reference Figure 1D , an isolation structure 28 is formed in the groove 27. The isolation structure 28 can be a single layer or a multi-layer. The material of the isolation structure 28 is, for example, silicon oxide, silicon nitride or a combination thereof. The method for forming the isolation structure 28 is, for example, to form an isolation material on the substrate 10 and in the groove 20 and the groove 27, and then, perform an etch-back or chemical mechanical polishing process to remove excess isolation material in the substrate 10 and the groove 20. The isolation structure 28 defines an active area AA in the substrate 10. Thereafter, the mask layer 26 is removed to expose the groove 20.

[0018] Reference Figure 1E , a well region 30 is formed in the substrate 10, and a plurality of doped regions 32 are formed in the well region 30. The plurality of doped regions 32 are located in the well region 30 and are separated from each other, and the sidewalls and the bottom of each doped region 32 are covered by the well region 30. The method for forming the well region 30 and the plurality of doped regions 32 can be to form a mask layer (not shown) on the substrate 10, respectively, and then perform an ion implantation process. In some embodiments, the well region 30 has a first conductive type dopant, and the plurality of doped regions 32 have a second conductive type dopant. The first conductive type dopant can be a P-type dopant, such as boron or boron trifluoride. The second conductive type dopant can be an N-type dopant, such as phosphorus or arsenic.

[0019] Reference Figure 1F , a first gate dielectric material 34 is formed on the substrate 10 and in the plurality of grooves 20. The first gate dielectric material 34 is, for example, silicon oxide. The first gate dielectric material 34 is formed by, for example, thermal oxidation.

[0020] Reference Figure 1G, a mask layer (not shown) is formed on the first gate dielectric material 34, and then an etching process, such as an anisotropic etching process, is performed to at least partially remove the first gate dielectric material 34 on the substrate 10 between the plurality of recesses 20 to form a trench 36. In some embodiments, the bottom of the trench 36 exposes the surface of the substrate 10. In other embodiments, a portion of the first gate dielectric material 34 remains at the bottom of the trench 36, as shown by the dotted line 35.

[0021] Reference Figure 1H , a second gate dielectric material 38 is formed in the trench 36. The second gate dielectric material 38 is, for example, silicon oxide, and is formed by, for example, thermal oxidation. In other embodiments, the second gate dielectric material 38 is, for example, a high dielectric constant material. In other embodiments, regardless of whether a portion of the first gate dielectric material 34 is left at the bottom of the trench 36, the gate dielectric material at the trench 36 is collectively referred to as the second gate dielectric material 38.

[0022] Reference Fig. 1I , a gate conductor layer 40 is formed on the second gate dielectric material 38 and the first gate dielectric material 34, and a plurality of spacers 42 are formed on the sidewalls of the gate conductor layer 40. The gate conductor layer 40 may be a semiconductor gate or a metal gate. The semiconductor gate may be a doped semiconductor material. The metal gate may be, for example, a metal (e.g., a non-composite metal), a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a conductive metal oxynitride or a conductive metal oxide, a metal silicide, or a combination thereof. The metal gate may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN) , tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof.

[0023] The gate conductor layer 40 can be formed by photolithography and etching, or by gate replacement. The gate replacement method can form a dummy gate conductor layer, such as a polysilicon layer, on the second gate dielectric material 38 and the first gate dielectric material 34, and then form a spacer 42 on the sidewall of the dummy gate conductor layer. After forming an inner dielectric layer on the substrate 10, the dummy gate conductor layer is removed to form a gate trench in the inner dielectric layer. Then, a metal material is backfilled in the gate trench to form a metal gate. The spacer 42 can be a single layer or a multilayer. The material of the spacer 42 is, for example, silicon oxide, silicon nitride or a combination thereof.

[0024] Reference Figure 1J , using the spacer 42 as a mask, an etching process is performed to remove a portion of the first gate dielectric material 34. The remaining first gate dielectric material 34 and the second gate dielectric material 38 form a gate dielectric layer 50. The gate dielectric layer 50 and the gate conductor layer 40 are collectively referred to as a gate structure 60.

[0025] Reference Figure 1J , multiple doping regions 44 are formed in the doping regions 32 of the substrate 10. Each doping region 44 is located in the corresponding doping region 32, and the sidewall and bottom of each doping region 44 are covered by the corresponding doping region 32. The multiple doping regions 44 can be formed by forming a mask layer (not shown) on the substrate 10, and then performing an ion implantation process to form them. In some embodiments, the multiple doping regions 44 and the multiple doping regions 32 have a second conductive type dopant. The second conductive type dopant can be an N-type dopant, such as phosphorus or arsenic. The doping concentration of the multiple doping regions 44 is greater than the doping concentration of the multiple doping regions 32. Therefore, the doping region 44 is also called a strongly doped region, and the doping region 32 is also called a lightly doped region. The multiple doping regions 44 can be used as source / drain regions.

[0026] Next, a metal silicide process is performed to form a metal silicide layer 46 on each doped region 44. In some other embodiments, a metal silicide layer (not shown) is also formed on the gate conductor layer 40. The metal silicide layer 46 is, for example, titanium silicide, cobalt silicide, nickel silicide, molybdenum silicide, ruthenium silicide or tungsten silicide. Thus, the semiconductor device 100A is formed.

[0027] In this embodiment, the gate dielectric layer 50 is located between the gate conductor layer 40 and the substrate 10, and between the spacer 42 and the substrate 10. The sidewall of the gate dielectric layer 50 is substantially flush with the outer sidewall 42SW of the spacer 42. The thickness of the gate dielectric layer 50 is thinner at the center, and thicker at the edge of the gate dielectric layer 50. The gate dielectric layer 50 may include a main body 50M, a first hump 50H1, and a second hump 50H2.

[0028] The main body 50M is located approximately at the center of the active area AA. The bottom surface BS1 and the top surface BS2 of the main body 50M have approximately flat surfaces. The bottom surface BS1 of the main body 50M contacts the well region 30 and the doped region 32. The top surface BS2 of the main body 50M contacts the gate conductor layer 40. The cross section of the main body 50M is approximately trapezoidal. The width W of the bottom surface BS1 of the main body 50M is approximately B1 Greater than the width W of the top surface BS2 B2 .

[0029] The first hump portion 50H1 is located at the first edge E1 of the main body portion 50M. The second hump portion 50H2 is located at the second edge E2 of the main body portion 50M. The first hump portion 50H1 and the second hump portion 50H2 may be symmetrical or asymmetrical. The first hump portion 50H1 and the second hump portion 50H2 may have similar shapes. The bottom surface SS1 of the first hump portion 50H1 is an inclined surface, which contacts the doping region 32 and the doping region 44. The bottom surface SS2 of the second hump portion 50H2 is an inclined surface, which contacts another doping region 32 and another doping region 44.

[0030] The top surface SS3 of the first hump portion 50H1 contacts the spacer 42. The top surface SS3' of the first hump portion 50H1 contacts the gate conductor layer 40. The top surface SS3 and the top surface SS3' form an inverted V shape. The top surface (top surface SS3 and top surface SS3') of the first hump portion 50H1 is mountain-shaped. The top surface SS3 and the bottom surface SS1 are inclined in the same direction, and the top surface SS3' and the bottom surface SS1 are inclined in different directions. The top surface SS3 and the bottom surface SS1 have a negative slope, and the top surface SS3' has a positive slope. The top surface SS3 and the bottom surface SS1 can be roughly parallel. The side wall of the first hump portion 50H1 is roughly flush with the outer side wall 42SW of the spacer 42. The side wall of the first hump portion 50H1 contacts the metal silicide layer 46.

[0031] Similarly, the top surface SS4 of the second hump portion 50H2 contacts the spacer 42. The top surface SS4' of the second hump portion 50H2 contacts the gate conductor layer 40. The top surface SS4 and the top surface SS4' form an inverted V shape. The top surface (top surface SS4 and top surface SS4') of the second hump portion 50H2 is mountain-shaped. The top surface SS4 and the bottom surface SS2 are inclined in the same direction, and the top surface SS4' and the bottom surface SS2 are inclined in different directions. The top surface SS4 and the bottom surface SS2 have a positive slope, and the top surface SS4' has a negative slope. The top surface SS4 and the bottom surface SS2 can be roughly parallel. The side wall of the second hump portion 50H2 is roughly flush with the outer side wall 42SW of the spacer 42. The side wall of the second hump portion 50H2 contacts the metal silicide layer 46.

[0032] The bottom surface BS1 of the main body 50M, the bottom surface SS1 of the first hump 50H1, and the bottom surface SS2 of the second hump 50H2 form a bottom surface 50U1. The bottom surface 50U1 is an inverted U-shaped surface. The top surface BS2 of the main body 50M, the top surface SS3' of the first hump 50H1, and the top surface SS4' of the second hump 50H2 form a top surface 50U2. The top surface 50U2 is a positive U-shaped surface. In some embodiments, the positive U-shaped surface is asymmetric to the inverted U-shaped surface.

[0033] The width W of the bottom surface BS1 of the main body 50M is B1 The width W of the bottom surface SS1 of the first hump portion 50H1 may be greater than or equal to the width W of the bottom surface SS1 of the first hump portion 50H1. H1 , and is greater than or equal to the width W of the bottom surface SS2 of the second hump portion 50H2 H2 Similarly, the width W of the top surface BS2 of the main body 50M is B2 Greater than or equal to the width W of the top surface of the first hump portion 50H1 H3 , and is greater than or equal to the width W of the top surface of the second hump portion 50H2 H4 In short, the width of the main body portion 50M is greater than or equal to the width of the first hump portion 50H1 , and greater than or equal to the width of the second hump portion 50H2 .

[0034] The thickness t of the first hump portion 50H1 H1 Greater than the thickness t of the main body 50M B The thickness t of the second hump portion 50H2 is H2 Greater than the thickness t of the main body 50M B The thickness t of the second hump portion 50H2 and the first hump portion 50H1 is H1 The thickness t of the second hump portion 50H2 is H1 Can be roughly equal. Thickness t B , thickness t H1 With thickness t H2 In the embodiment where the semiconductor device 100A is a low voltage device, the thickness t of the main body 50M is B The thickness t of the first hump portion 50H1 is 1 angstrom to 50 angstroms. H1 The thickness t of the second hump portion 50H2 is H1 In the embodiment where the semiconductor device 100A is a medium voltage device, the thickness t of the main body 50M is 100 angstroms to 300 angstroms. B The thickness t of the first hump portion 50H1 is 50 angstroms to 250 angstroms. H1 The thickness t of the second hump portion 50H2 is H1 The thickness t of the main body 50M is 100 angstroms to 300 angstroms. B The thickness of the first hump portion 50H1 is thinner, so the starting voltage can be reduced. H1The thickness t of the second hump portion 50H2 is H2 A thicker thickness can increase the voltage applied to the source / drain regions and reduce the gate induced drain leakage current.

[0035] In the above embodiment, the sidewall of the gate dielectric layer 50 is substantially aligned with the outer sidewall 42SW of the spacer 42 . However, the present invention is not limited thereto. In other embodiments, the gate dielectric layer 50 extends laterally and protrudes beyond the outer sidewall 42SW of the spacer 42 . FIG. 2A to FIG. 2C A schematic cross-sectional view shows a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0036] Reference Figure 2A , refer to FIG. 1A to FIG. 1I The recess 20 is formed in the substrate 10 by a method until a spacer 42 is formed on the sidewall of the gate conductor layer 40. The spacer 42 exposes the first gate dielectric material 34. A plurality of doped regions 44 are formed in the doped region 32 of the substrate 10. The doped regions 44 are covered by the first gate dielectric material 34.

[0037] Reference Figure 2B , a mask layer (not shown) is formed on the substrate 10. Then, a photolithography and patterning process is performed to pattern the first gate dielectric material 34 to expose the doped region 44. The remaining first gate dielectric material 34 and the second gate dielectric material 38 form a gate dielectric layer 50B. The gate dielectric layer 50B is located between the gate conductor layer 40 and the substrate 10, between the spacer 42 and the substrate 10, and extends laterally to protrude from the outer sidewall 42SW of the spacer 42. In this embodiment, the gate dielectric layer 50B may include a main body 50M, a first hump portion 50H1 and a second hump portion 50H2, and further includes extension portions 50e1 and 50e2. The extension portions 50e1 and 50e2 extend laterally to protrude from the outer sidewall 42SW of the spacer 42.

[0038] Reference Figure 2C , a metal silicide process is performed to form a metal silicide layer 46 on each doping region 44. During the metal silicide process, the extensions 50e1 and 50e2 can serve as a self-aligned barrier layer SAB, and no additional self-aligned barrier layer needs to be formed. Thus, the semiconductor device 100B is formed.

[0039] In the semiconductor device 100B, the gate dielectric layer 50B includes extensions 50e1 and 50e2. One side of the extensions 50e1 and 50e2 is respectively connected to the first hump 50H1 and the second hump 50H2, and the sidewalls of the extensions 50e1 and 50e2 are respectively in contact with the metal silicide layer 46. The bottom surface ES11 of the extension 50e1 and the bottom surface ES21 of the extension 50e2 are in contact with the doped region 44. The top surface ES12 of the extension 50e1 and the top surface ES22 of the extension 50e2 can be lower than, equal to, or higher than the top surface BS2 of the main body 50M. In addition, after forming the metal silicide layer 46, the extensions 50e1 and 50e2 can be retained (e.g., Figure 2C ) or removed (as Figure 5 shown).

[0040] The present invention can be applied to various semiconductor components and is not limited to the above semiconductor components 100A and 100B.

[0041] For example, refer to Figure 3 , the semiconductor component 100C is similar to the semiconductor component 100A. The semiconductor component 100C also includes an additional doping region 132. The additional doping region 132 is only on one side of the gate structure 60. The additional doping region 132 covers the sidewalls and a portion of the bottom surface of the doping region 32a. The doping region 32b is not covered by the additional doping region 132, but is in contact with the well region 132. The additional doping region 132 and the doping regions 32a and 30b have a second conductivity type dopant. The second conductivity type dopant can be an N-type dopant, such as phosphorus or arsenic. The doping concentration of the additional doping region 132 is lower than the doping concentration of the doping regions 32a and 30b.

[0042] Reference Figure 4 , the semiconductor device 100D is similar to the semiconductor device 100A. The gate dielectric layer 50D of the semiconductor device 100D is different from the gate dielectric layer 50 of the semiconductor device 100A. The shape of the main body 50M of the gate dielectric layer 50D is still, for example, a trapezoid. The bottom surface BS1 and the top surface BS2 of the main body 50M have substantially flat surfaces. However, the width W of the top surface BS2 of the main body 50M is B2 Smaller, with the width W of the bottom surface BS1 B1 The difference is even greater.

[0043] The first hump portion 50H1 and the second hump portion 50H2 of the gate dielectric layer 50D are closer to the center of the active area AA, so as to be closer to each other. The first hump portion 50H1 also includes a top surface SS5, which is connected to the top surfaces SS3 and SS3'. The second hump portion 50H2 also includes a top surface SS6, which is connected to the top surfaces SS4 and SS4'. The top surfaces SS5 and SS6 can be substantially parallel to the bottom surface BS1. The top surface SS5 and the bottom surface BS1 of the gate dielectric layer 50D have a maximum thickness t' H1 The top surface SS6 and the bottom surface BS1 of the gate dielectric layer 50D have a maximum thickness t' H2 . Maximum thickness t' H1 With t' H2 The well region 30 is located between the doped regions 32 .

[0044] Reference Figure 5 and Figure 1J The semiconductor device 100E is similar to the semiconductor device 100A. The gate dielectric layer 50E of the semiconductor device 100E is different from the gate dielectric layer 50 of the semiconductor device 100A. The gate dielectric layer 50E includes a main body portion 50M and a first hump portion 50H1, but does not include a second hump portion 50H2 (shown in FIG. Figure 1J In other words, the gate dielectric layer 50E includes only a single hump portion (the first hump portion 50H1 ) located on a single side ( E1 ) of the main body portion 50M.

[0045] The metal silicide layer 46 is not in contact with the gate dielectric layer 50E. The metal silicide layer 46a is spaced apart from the first hump portion 50H1 of the gate dielectric layer 50E by a non-zero distance. In some embodiments, an extension portion 50e1 (e.g., Figure 2C ), the extension portion 50e1 can serve as a self-aligned barrier during the metal silicide process of forming the metal silicide layer 46, and can be removed after the metal silicide layer 46 is formed.

[0046] In the above embodiments, a plurality of grooves are formed in the substrate before forming the gate dielectric layer. However, the present invention is not limited thereto. In other embodiments, the step of forming the grooves may also be omitted. 6A to 6F is a cross-sectional schematic diagram of a method for manufacturing a semiconductor component according to other embodiments of the present invention.

[0047] Reference Fig. 6A According to the above method, an isolation structure 28 is formed in the substrate 10 to define an active area AA. A well region 30 is formed in the substrate 10, and a plurality of doping regions 32 are formed in the well region 30. The conductivity type and formation method of the well region 30 and the plurality of doping regions 32 may be the same as those of the well region 30 and the plurality of doping regions 32 in the above embodiment.

[0048] Reference Figure 6B , a first gate dielectric material 34 is formed on the substrate 10. The material and the forming method of the first gate dielectric material 34 of this embodiment may be the same as the material and the forming method of the first gate dielectric material 34 of the above embodiment.

[0049] Reference Figure 6C A mask layer (not shown) is formed on the first gate dielectric material 34, and then an etching process, such as an anisotropic etching process, is performed to at least partially remove the first gate dielectric material 34 on the well region 30 to form a trench 36. In some embodiments, the bottom of the trench 36 exposes the surface of the well region 30.

[0050] Reference Fig.6D , a second gate dielectric material 38 is formed in the trench 36. The material and the forming method of the second gate dielectric material 38 of this embodiment may be the same as the material and the forming method of the second gate dielectric material 38 of the above embodiment.

[0051] Reference Fig. 6E , a gate conductor layer 40 is formed on the second gate dielectric material 38 and the first gate dielectric material 34, and a plurality of spacers 42 are formed on the sidewalls of the gate conductor layer 40. The gate conductor layer 40 and the plurality of spacers 42 of this embodiment may be made of the same materials and formed by the same method as those of the gate conductor layer 40 and the plurality of spacers 42 of the above-mentioned embodiment.

[0052] Reference Fig. 6F , using the spacer 42 as a mask, an etching process is performed to remove a portion of the first gate dielectric material 34. The remaining first gate dielectric material 34 and the second gate dielectric material 38 form a gate dielectric layer 50F.

[0053] A plurality of doping regions 44 are formed in the doping region 32 of the substrate 10 . The plurality of doping regions 44 and the plurality of doping regions 32 have second conductivity type dopants. Next, a metal silicide process is performed to form a metal silicide layer 46 on each of the doping regions 44 .

[0054] The gate dielectric layer 50F of this embodiment is similar to the above-mentioned gate dielectric layer 50. The gate dielectric layer 50F of this embodiment has a flat bottom surface. The gate dielectric layer 50F includes a main body 50M, a first hump portion 50H1 and a second hump portion 50H2. The first hump portion 50H1 and the second hump portion 50H2 are located on both sides of the main body 50M and connected to the main body 50M.

[0055] The cross section of the main body 50M is substantially trapezoidal. The width W of the bottom surface BS1 of the main body 50M is B1 Greater than the width W of the top surface BS2 B2 The width W of the top surface BS2 of the main body 50M is B2is greater than or equal to the width WH3 of the top surface of the first hump portion 50H1, and greater than or equal to the width WH4 of the top surface of the second hump portion 50H2. B1 The width WH1 may be greater than or equal to the width WH1 of the bottom surface SS1 of the first hump portion 50H1 , and greater than or equal to the width WH2 of the bottom surface SS2 of the second hump portion 50H2 .

[0056] The bottom surface BS1 of the main body 50M, the bottom surface SS1 of the first hump 50H1, and the bottom surface SS2 of the second hump 50H2 have substantially flat surfaces. In the present embodiment, the bottom surface BS1 of the main body 50M, the bottom surface SS1 of the first hump 50H1, and the bottom surface SS2 of the second hump 50H2 are coplanar, so that the gate dielectric layer 50F has a flat bottom surface.

[0057] The top surface BS2 of the main body 50M, the top surface SS3' of the first hump portion 50H1, and the top surface SS4' of the second hump portion 50H2 are positive U-shaped surfaces. The top surface SS3 of the first hump portion 50H1 and the top surface SS4 of the second hump portion 50H2 have substantially flat surfaces, and their heights are higher than the top surface BS2 of the main body 50M. The top surface BS2 of the main body 50M, the top surfaces SS3' and SS3 of the first hump portion 50H1 are stepped. The top surface BS2 of the main body 50M, the top surfaces SS4' and SS4 of the second hump portion 50H2 are stepped. The sidewalls of the first hump portion 50H1 and the second hump portion 50H2 are substantially flush with the outer sidewall 42SW of the spacer 42, and are in contact with the metal silicide layer 46.

[0058] The gate dielectric layer of the embodiment of the present invention has a thinner central region, which can reduce the threshold voltage. The gate dielectric layer has a thicker edge region, which can reduce the gate induced drain leakage current and allow a higher voltage to be applied to the source / drain region.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor component, characterized in that: include: providing a substrate; forming a plurality of grooves in the substrate; forming a first gate dielectric material on the substrate and in the plurality of recesses; at least partially removing the first gate dielectric material on the substrate between the plurality of recesses to form trenches; forming a second gate dielectric material in the trench; forming a gate conductor layer on the second gate dielectric material, and forming a plurality of spacers on the sidewalls of the gate conductor layer; removing a portion of the first gate dielectric material so that the remaining first gate dielectric material and the second gate dielectric material form a gate dielectric layer, wherein the gate dielectric layer comprises: the main body; and a first hump portion located at a first edge of the main body portion, wherein a thickness of the first hump portion is greater than a thickness of the main body portion; and A plurality of doped regions are formed in the substrate on both sides of the plurality of spacers. 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein a width of the main body portion is greater than or equal to a width of the first hump portion.

3. The method for manufacturing a semiconductor component according to claim 1, wherein the gate dielectric layer further comprises: The second hump portion is located at the second edge of the main body portion, wherein the thickness of the second hump portion is greater than the thickness of the main body portion. 4 . The method for manufacturing a semiconductor device according to claim 3 , wherein a width of the main body portion is greater than or equal to a width of the second hump portion. 5 . The method for manufacturing a semiconductor device according to claim 4 , wherein the first hump portion and the second hump portion of the gate dielectric layer extend and protrude from outer sidewalls of the plurality of spacers.

6. The method for manufacturing a semiconductor component according to claim 5, further comprising: The first hump portion and the second hump portion of the gate dielectric layer are used as insulating barrier layers to perform a metal silicide process to form a plurality of metal silicide layers on the plurality of doped regions. 7 . The method for manufacturing a semiconductor device according to claim 1 , wherein the first gate dielectric material on the substrate between the plurality of grooves is at least partially removed so that the bottom surface of the trench is exposed to the substrate. 8 . The method for manufacturing a semiconductor component according to claim 1 , wherein the first gate dielectric material on the substrate between the plurality of grooves is at least partially removed, so that a portion of the first gate dielectric material is exposed at a bottom surface of the trench.

9. A method for manufacturing a semiconductor component, characterized in that: include: providing a substrate; forming a first gate dielectric material on the substrate; patterning the first gate dielectric material to form a trench; forming a second gate dielectric material in the trench; forming a gate conductor layer on the second gate dielectric material and the first gate dielectric material, and forming a plurality of spacers on the sidewalls of the gate conductor layer; removing a portion of the second gate dielectric material and the first gate dielectric material to form a gate dielectric layer, wherein the gate dielectric layer comprises: the main body; and a first hump portion located at a first edge of the main body portion, wherein a thickness of the first hump portion is greater than a thickness of the main body portion; and A plurality of doped regions are formed in the substrate on both sides of the plurality of spacers.

10. The method for manufacturing a semiconductor component according to claim 9, wherein the gate dielectric layer further comprises: The second hump portion is located at the second edge of the main body portion, wherein the thickness of the second hump portion is greater than the thickness of the main body portion. 11 . The method for manufacturing a semiconductor device according to claim 10 , wherein a width of the main body portion is greater than or equal to a width of the first hump portion, and greater than or equal to a width of the second hump portion.

12. The method for manufacturing a semiconductor component according to claim 11, further comprising: A metal silicide process is performed to form a plurality of metal silicide layers on the plurality of doped regions. 13 . The method for manufacturing a semiconductor device according to claim 9 , wherein the first gate dielectric material is patterned to form a trench, such that a bottom surface of the trench exposes the substrate. 14 . The method for manufacturing a semiconductor device according to claim 9 , wherein the first gate dielectric material is patterned to form a trench, so that a portion of the first gate dielectric material is exposed at a bottom surface of the trench.

15. A semiconductor component, characterized in that: include: A gate structure is located on the substrate, wherein the gate structure comprises: A gate conductor layer, located above the substrate; A gate dielectric layer, located between the gate conductor layer and the substrate, comprises: a main body portion located on the flat surface of the substrate; and a first hump portion located on a portion of the flat surface of the first edge of the main body portion, wherein a thickness of the first hump portion is greater than a thickness of the main body portion; and A plurality of doped regions are located in the substrate on both sides of the gate structure.

16. The semiconductor component according to claim 15, wherein the gate dielectric layer further comprises: The second hump portion is located at the second edge of the main body portion, wherein the thickness of the second hump portion is greater than that of the main body portion. 17 . The semiconductor device according to claim 16 , wherein sidewalls of the first hump portion and the second hump portion are flush with outer sidewalls of the plurality of spacers. 18 . The semiconductor device according to claim 16 , wherein the gate dielectric layer further comprises a plurality of extension portions, respectively connected to the first hump portion and the second hump portion, and extending and protruding from outer sidewalls of the plurality of spacers. 19 . The semiconductor device according to claim 18 , wherein a top surface of the gate dielectric layer has a positive U-shaped surface, and a bottom surface of the gate dielectric layer has a negative U-shaped surface, wherein the positive U-shaped surface is asymmetric to the negative U-shaped surface. 20 . The semiconductor device according to claim 18 , wherein a top surface of the gate dielectric layer has a positive U-shaped surface, and a bottom surface of the gate dielectric layer has a flat surface.

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