Vertical cavity surface emitting laser and preparation method thereof

Abstract

The invention discloses a vertical cavity surface emitting laser and a preparation method thereof. The preparation method of the vertical cavity surface emitting laser comprises the following steps: growing a semiconductor epitaxial structure with a lower reflecting mirror layer, an active layer and an upper reflecting mirror layer which are sequentially arranged from bottom to top on a substrate to form a wafer; depositing an ohmic metal layer, and etching the semiconductor epitaxial structure until the lower reflector layer is exposed to form a plurality of grooves; performing ion implantation on the side wall and the bottom of each groove to form a plurality of insulating regions; the insulating region comprises a side wall insulating region in contact with the side wall of the groove and a bottom insulating region in contact with the bottom of the groove; the depth of the side wall insulation region is greater than that of the groove; the semiconductor epitaxial structure is jointly divided into a plurality of semiconductor units which are mutually isolated on the active layer by the grooves and the insulating regions; and each semiconductor unit comprises a lower reflecting mirror, an active region, an upper reflecting mirror and an ohmic electrode which are sequentially arranged from bottom to top. According to the embodiment of the invention, the robustness of the vertical cavity surface emitting laser can be improved.

Description

Technical Field

[0001] The present invention relates to the field of laser technology, and in particular to a vertical cavity surface emitting laser and a preparation method thereof. Background Art

[0002] Vertical-Cavity Surface-Emitting Laser (VCSEL) refers to a semiconductor laser that forms a resonant cavity in the vertical direction of the substrate and emits laser in the vertical direction. With the development of VCSEL technology, VCSEL lasers are widely used in smart transportation, health care, biological detection, military security and other fields.

[0003] When VCSEL lasers are used in long-distance sensing applications, they require higher luminous power. Especially in applications such as LiDAR, VCSEL lasers are usually driven by narrow pulses, such as pulse widths of 3-8ns. Compared with DC working conditions, the lasers need to withstand larger driving voltages or currents. However, Figure 1 As shown, the existing VCSEL laser includes a stacked substrate 01, a lower reflector layer 02, an active layer 03, an upper reflector layer 04, an ohmic metal layer 05 and a passivation layer 07. In the prior art, the electrical isolation between adjacent light-emitting units 08 is achieved by setting a groove 06 ( Figure 1 The position of the groove 06 is mainly shown in the figure, and only part of the structure of each light-emitting unit 08 is shown). However, due to surface defects of the passivation layer 07, or uneven etching surface, or uneven metal, the voltage resistance of the existing VCSEL laser is poor. When the driving voltage or driving current is large, the leakage current will increase. In severe abnormal conditions, the passivation layer 07 may be broken down, causing device failure. Therefore, the robustness of the existing VCSEL laser is poor, especially difficult to work normally under narrow pulse driving conditions. Summary of the invention

[0004] The present invention provides a vertical cavity surface emitting laser and a preparation method thereof, so as to improve the voltage resistance and current bearing capacity of the vertical cavity surface emitting laser, improve the robustness of the vertical cavity surface emitting laser, and expand its application range.

[0005] In a first aspect, an embodiment of the present invention provides a method for preparing a vertical cavity surface emitting laser, comprising:

[0006] Growing a semiconductor epitaxial structure on a substrate to form a wafer; wherein the semiconductor epitaxial structure comprises a lower reflector layer, an active layer and an upper reflector layer arranged in sequence from bottom to top;

[0007] Depositing an ohmic metal layer on the semiconductor epitaxial structure, and etching the semiconductor epitaxial structure until the lower reflector layer is exposed to form a plurality of grooves;

[0008] Ion implantation is performed on the sidewalls and bottom of each of the trenches to form a plurality of insulating regions; wherein the insulating regions include a sidewall insulating region in contact with the corresponding trench sidewalls, and a bottom insulating region in contact with the corresponding trench bottom; the depth of the sidewall insulating region is greater than the depth of the trench; the trenches and the insulating regions are used together to separate the semiconductor epitaxial structure into a plurality of semiconductor units isolated from each other on the active layer, so that each of the semiconductor units includes a lower reflector, an active region, an upper reflector and an ohmic electrode arranged in sequence from bottom to top.

[0009] Optionally, the width of the sidewall insulation region is greater than or equal to 0.2 microns.

[0010] Optionally, ion implantation is performed on the sidewalls and bottom of each of the trenches to form a plurality of insulating regions, including:

[0011] forming a photoresist layer on the upper surface of the semiconductor epitaxial structure;

[0012] Patterning the photoresist layer to form an ion implantation pattern; wherein a vertical projection of the ion implantation pattern on the substrate covers a vertical projection of the groove on the substrate;

[0013] Corresponding to the ion implantation pattern, ion implantation is performed on the semiconductor epitaxial structure to form a plurality of the insulating regions.

[0014] Optionally, the sidewall of the groove is perpendicular to the bottom of the groove;

[0015] Performing ion implantation on the semiconductor epitaxial structure comprises:

[0016] Ion implantation is performed on the semiconductor epitaxial structure along a first direction using a variety of implantation energies and / or a variety of implantation ions; wherein the first direction is a normal direction of an upper surface of the substrate.

[0017] Optionally, the cross-sectional shape of the groove is an inverted trapezoid, and the angle between the sidewall of the groove and the bottom of the groove is in the range of 93-145 degrees;

[0018] Performing ion implantation on the semiconductor epitaxial structure comprises:

[0019] At least one implantation energy and at least one implantation ion are used to perform ion implantation on the semiconductor epitaxial structure along a first direction; wherein the first direction is parallel to a normal direction of an upper surface of the substrate.

[0020] Optionally, the sidewall of the groove is perpendicular to the bottom of the groove, or the cross-sectional shape of the groove is an inverted trapezoid, and the angle between the sidewall of the groove and the bottom of the groove is in the range of 93-145 degrees;

[0021] Performing ion implantation on the semiconductor epitaxial structure comprises:

[0022] Controlling the wafer to rotate at least once; before the first rotation and after each rotation, using the same implantation energy and the same implantation ion beam to perform regional ion implantation on the semiconductor epitaxial structure along a direction with a preset angle to the first direction; wherein the range of each regional ion implantation corresponds to a partial area of ​​the insulating area; after multiple regional ion implantations, the range of ion implantation covers the entire area of ​​the insulating area;

[0023] Wherein, the first direction is parallel to the normal direction of the upper surface of the substrate; the angle range of the preset angle is: 3-20 degrees.

[0024] Optionally, the depth of the bottom insulating region is greater than or equal to 1 micron.

[0025] Optionally, the wafer is controlled to rotate on a horizontal plane, the ion beam is controlled to have a preset angle with a normal direction of the horizontal plane, and the ion beam is controlled to be fixed; wherein the horizontal plane is parallel to the upper surface of the substrate;

[0026] In the process of forming the plurality of insulating regions, the wafer is rotated n times, and each rotation angle is 360 / (n+1) degrees; n is a positive integer.

[0027] Optionally, the groove is an annular groove surrounding the semiconductor unit;

[0028] Alternatively, a plurality of spaced-apart grooves are disposed at the periphery of each semiconductor unit, and the plurality of spaced-apart grooves and a plurality of insulating regions corresponding to the plurality of spaced-apart grooves constitute an annular insulating structure surrounding the semiconductor unit.

[0029] Optionally, after forming the plurality of grooves, the method further comprises:

[0030] Corresponding to the plurality of trenches, forming an oxidation restriction layer having an oxidation aperture in each of the semiconductor units by an oxidation process;

[0031] Wherein, the active region includes: at least one active layer;

[0032] When the active region includes multiple active layers, the multiple active layers are arranged in sequence from bottom to top, and adjacent active layers are connected via tunnel junctions.

[0033] Optionally, before or after forming the plurality of insulating regions, the method further includes:

[0034] forming a passivation layer on the upper surface of the semiconductor epitaxial structure;

[0035] After forming the passivation layer and each of the insulating regions, the preparation method further comprises:

[0036] Etching the passivation layer until the ohmic metal layer is exposed to form a plurality of electrical connection openings corresponding to the ohmic electrodes of each semiconductor unit;

[0037] Forming a first electrode corresponding to each of the semiconductor units on the upper surface of the passivation layer, wherein the first electrode is connected to the ohmic electrode through the electrical connection opening;

[0038] The substrate is thinned, and second electrodes corresponding to the semiconductor units are formed on the lower surface of the thinned substrate.

[0039] In a second aspect, an embodiment of the present invention further provides a vertical cavity surface emitting laser, which is prepared using the method for preparing a vertical cavity surface emitting laser provided by any embodiment of the present invention.

[0040] The method for preparing a vertical cavity surface emitting laser provided in an embodiment of the present invention can form a high impedance insulating region completely enveloping the groove around the groove by performing ion implantation on the sidewall and bottom of the groove after etching the groove, which helps to isolate surface defects formed during oxidation, etching, or deposition of the passivation layer, reduce the leakage current of the device, and improve the voltage resistance of the device, so that the device can be applied to short pulse and high current narrow pulse driving conditions. In addition, by setting the sidewall insulating region, the current distribution area within the semiconductor unit can be limited, which helps to adjust the current density and divergence angle of the light-emitting unit to a certain extent. Therefore, compared with the prior art, the embodiment of the present invention can improve the voltage resistance and current carrying capacity of the vertical cavity surface emitting laser, so as to improve the robustness of the vertical cavity surface emitting laser and expand its scope of application.

[0041] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 It is a schematic diagram of the cross-sectional structure of an existing vertical cavity surface emitting laser;

[0044] Figure 2 It is a schematic flow chart of a method for preparing a vertical cavity surface emitting laser provided by an embodiment of the present invention;

[0045] Figure 3 It is a structural schematic diagram of a method for preparing a vertical cavity surface emitting laser in S110-S130 provided in an embodiment of the present invention;

[0046] Figure 4 yes Figure 3 A magnified schematic diagram of the middle area A1;

[0047] Figure 5 is a schematic diagram of a cross-sectional structure of a light-emitting unit provided in an embodiment of the present invention;

[0048] Figure 6-8 It is a structural schematic diagram of a method for preparing a vertical cavity surface emitting laser in S210-S280 provided in an embodiment of the present invention;

[0049] Fig. 9 is a schematic diagram of the cross-sectional structure of another light-emitting unit provided in an embodiment of the present invention;

[0050] Fig.10 is a schematic cross-sectional structure diagram of another light-emitting unit provided in an embodiment of the present invention;

[0051] Figure 11-12 It is a structural schematic diagram of an ion implantation process in S310-S330 provided by an embodiment of the present invention;

[0052] Fig.13 is a structural schematic diagram of S330 in the ion implantation process provided by an embodiment of the present invention;

[0053] Fig.14 is a schematic diagram of an ion implantation process provided by an embodiment of the present invention;

[0054] Fig.15 is another structural schematic diagram of S330 in the ion implantation process provided by an embodiment of the present invention;

[0055] Fig.16 is a schematic diagram of a top view of a vertical cavity surface emitting laser provided by an embodiment of the present invention;

[0056] Fig.17 It is a schematic diagram of a top view of the structure of another vertical cavity surface emitting laser provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0059] An embodiment of the present invention provides a method for preparing a vertical cavity surface emitting laser. The vertical cavity surface emitting laser prepared based on the preparation method has a high tolerance to extreme working conditions such as high voltage and large current, and is particularly suitable for narrow pulse driving conditions (such as narrow pulse, large current and high power density conditions). Figure 2 It is a schematic flow chart of a method for preparing a vertical cavity surface emitting laser provided by an embodiment of the present invention; Figure 3 1 is a schematic diagram of the structure of a method for preparing a vertical cavity surface emitting laser in S110-S130 provided in an embodiment of the present invention. Figure 2 and Figure 3 , the preparation method comprises the following steps:

[0060] S110, growing a semiconductor epitaxial structure on a substrate to form a wafer; wherein the semiconductor epitaxial structure comprises a lower reflector layer, an active layer and an upper reflector layer arranged in sequence from bottom to top.

[0061] Specifically, the substrate 10 may be a conductive substrate, a semi-insulating substrate or an insulating substrate, depending on the design. The lower reflector layer 20 may be an N-type distributed Bragg reflector (N-DBR), which may be made of N-doped Al x Ga 1-x As (x = 1 to 0) / GaAs material. The active layer 30 may include a quantum well. The upper reflector layer 40 may be a P-type distributed Bragg reflector (P-Distributed Bragg Reflector, P-DBR), which may be made of P-doped Al xGa 1-x As (x = 1 ~ 0) / GaAs material. Among them, the active layer 30 is sandwiched between the upper reflector layer 40 and the lower reflector layer 20 to form a resonant cavity. Different types of carriers are recombined in the quantum well of the active layer 30 to generate photons. After being excited, the photons can be reflected back and forth in the resonant cavity and repeatedly amplified to form lasers. The lower reflector layer 20, the active layer 30, and the upper reflector layer 40 can be deposited on the substrate 10 by epitaxial growth.

[0062] S120, depositing an ohmic metal layer above the semiconductor epitaxial structure, and etching the semiconductor epitaxial structure until the lower reflector layer is exposed, thereby forming a plurality of grooves.

[0063] Among them, the ohmic metal layer 50 can be prepared by using a conductive material such as metal, and deposited on the semiconductor epitaxial structure by evaporation, sputtering, etc. Also, after the conductive material is deposited on the semiconductor epitaxial structure in an entire layer, it can be patterned as required to obtain the patterned ohmic metal layer 50. Furthermore, an ohmic contact layer (not shown in the drawings) may also be included between the ohmic metal layer 50 and the upper reflector layer 40 to reduce the ohmic contact resistance between the metal and the semiconductor. Exemplarily, the upper surface of the semiconductor epitaxial structure at the etching position of the groove 100 is not covered by the conductive material of the ohmic metal layer 50. The bottom of the groove 100 may be flush with the upper surface of the lower reflector layer 20, or the groove 100 may be etched to the inside of the lower reflector layer 20, or even to the inside of the substrate 10. The specific etching depth can be set according to actual needs, and is not limited here, as long as the active areas between adjacent semiconductor units 200 can be separated, physical isolation on the active layer 30 can be achieved, and the active areas of the light-emitting units on both sides of the groove are not connected.

[0064] S130. Perform ion implantation on the sidewalls and bottom of each trench to form a plurality of insulating regions; wherein the insulating region comprises a sidewall insulating region in contact with the corresponding trench sidewall, and a bottom insulating region in contact with the corresponding trench bottom; the depth of the sidewall insulating region is greater than the depth of the trench; the trench and the insulating region are used together to separate the semiconductor epitaxial structure into a plurality of semiconductor units isolated from each other on the active layer, so that each semiconductor unit comprises a lower reflector, an active region, an upper reflector and an ohmic electrode arranged in sequence from bottom to top.

[0065] Among them, ion implantation can destroy the crystal structure of the material in the implanted area, so that the impedance of the implanted area is increased, thereby forming an insulating area 70 with high impedance, making it difficult for current to pass through the area, thereby ensuring the insulation effect between the structures on both sides of the trench 100. In order to clearly show the structure of the insulating area 70, Figure 4 It is given in Figure 3 Enlarged view of area A1 in the middle. Figure 4, the portion of the insulating region 70 located around the side wall 101 of the trench 100 is defined as the side wall insulating region 71. The depth h of the side wall insulating region 71 refers to the vertical distance from the top to the bottom of the side wall insulating region 71, or the length of the side wall insulating region 71 in the thickness direction of the vertical cavity surface emitting laser. Setting the depth h of the side wall insulating region 71 to be greater than the depth h0 of the trench can ensure that the side wall of the trench 100 is completely wrapped by the side wall of the trench 100, thereby reliably blocking the lateral current transfer between the two sides of the trench 100. And, the portion of the insulating region 70 located below the bottom 102 of the trench 100 is defined as the bottom insulating region 72. As Figure 4 , illustratively, the depth h11 of the bottom insulating region 72 may be equal to the depth h of the sidewall insulating region 71. By forming the bottom insulating region 72, leakage and other problems caused by surface defects at the bottom 102 of the trench 100 can be effectively blocked. Among them, after the formation of the trench 100, before or after ion implantation, a passivation layer (not shown in the figure) may also be formed on the surface of the semiconductor epitaxial structure and the ohmic metal layer 50. The provision of the insulating region 70 is equivalent to further passivation, thereby improving the durability and anti-destruction performance of the device, making the overall robustness of the device stronger, and not easy to be burned or fail when working under extreme conditions.

[0066] The trench 100 and the insulating region 70 are used together to separate the semiconductor epitaxial structure into a plurality of semiconductor units 200 isolated from each other on the active layer 30, forming a plurality of light-emitting units of the vertical cavity surface emitting laser. The structure of the light-emitting unit can be seen in Figure 5 , the semiconductor unit 200 can serve as the main light-emitting part of the light-emitting unit. The semiconductor unit 200 includes a lower reflector 21 (located in the lower reflector layer), an active area 31 (located in the active layer), an upper reflector 41 (located in the upper reflector layer) and an ohmic electrode 51 (located in the ohmic metal layer) arranged in sequence from bottom to top. The lower end of the semiconductor unit 200 can be connected to the second electrode through the substrate structure 11 (that is, the portion of the substrate 10 corresponding to the semiconductor unit 200) (when the substrate structure 11 is an insulating substrate, the second electrode and the first electrode are both located on the same side of the substrate, and the present application does not limit the location of the second electrode, which depends on the specific design), and the upper end of the semiconductor unit 200 can be connected to the first electrode through the ohmic electrode 51. When an operating voltage / current is applied to the first electrode and the second electrode, a current will be generated in the semiconductor unit 200. See Figure 5 It can be seen that, since the sidewall insulation region has a certain width, it will limit the transmission range of the current and change the current distribution between the first electrode and the second electrode, which is conducive to increasing the current density of the light-emitting unit and improving the divergence angle of the light-emitting unit. Exemplarily, multiple light-emitting units are integrated on the same wafer, and the substrate structure 11 of the multiple light-emitting units can constitute a substrate 10 of an integrated structure.

[0067] The method for preparing a vertical cavity surface emitting laser provided in an embodiment of the present invention, after etching the groove 100, by performing ion implantation on the sidewall 101 and the bottom 102 of the groove 100, a high impedance insulating region 70 completely enveloping the groove 100 can be formed around the groove 70, which helps to isolate the surface defects formed during oxidation, etching, or deposition of the passivation layer, reduce the leakage current of the device, and improve the voltage resistance of the device, so that the device can be applied to short pulses and narrow pulse driving conditions of large currents. In addition, by setting the sidewall insulating region 71, the current distribution area within the semiconductor unit 200 can be limited, which helps to adjust the current density and divergence angle of the light-emitting unit to a certain extent. Therefore, compared with the prior art, the embodiment of the present invention can improve the voltage resistance and current carrying capacity of the vertical cavity surface emitting laser, so as to improve the robustness of the vertical cavity surface emitting laser and expand its scope of application.

[0068] Continue to see Figure 4 , based on the above embodiments, optionally, the width w of the sidewall insulating region 71 is greater than or equal to 0.2 microns, preferably greater than 0.5 microns, to ensure that the high impedance region has sufficient thickness to reliably block leakage current. Also, the vertical projection of the sidewall insulating region 71 on the substrate 10 has no overlap or partially overlaps with the vertical projection of the ohmic electrode 51 on the substrate 10, that is, the width w of the sidewall insulating region 71 is less than the vertical distance w0 between the edge of the ohmic electrode 51 away from the groove 100 and the sidewall 101 of the groove 100, so that the ion implantation process does not completely act on the semiconductor material under the ohmic electrode 51, and the semiconductor material under the ohmic electrode 51 is avoided as much as possible from being modified by the ion implantation, so as to avoid affecting the normal electrical transmission process in the light-emitting unit. Among them, the width w of the sidewall insulating region 71 can be understood as the shortest distance of the sidewall insulating region 71 in the horizontal direction (i.e., the direction parallel to the upper surface of the substrate 10). For example, when the cross-sectional shape of the sidewall insulating region 71 is as follows Figure 4 When the sidewall insulating region 71 is a rectangle as shown, the width w of the sidewall insulating region 71 is the width of the rectangle, and the depth h of the sidewall insulating region 71 is the length of the rectangle.

[0069] Preferably, during the ion implantation process, the vertical projection of the ion implantation range on the substrate 10 can be limited to not overlap with the vertical projection of the ohmic electrode 51 on the substrate 10. In this way, even if the implanted material partially diffuses to the bottom of the ohmic electrode 51 due to diffusion after the ion implantation, the overlapping area between the sidewall insulating region 71 and the vertical projection of the ohmic electrode 51 on the substrate 10 is relatively small, which basically does not affect the normal electrical transmission process in the light-emitting unit. Alternatively, during the ion implantation process, the influence of diffusion can be considered in advance, and the ion implantation range is not set close to the ohmic electrode 51 near the edge of the groove 100, so that the implanted material will not diffuse to the bottom of the ohmic electrode 51.

[0070] The above embodiments mainly describe the steps for preparing structures related to the insulating region 70 . The following describes a complete preparation process that may be used for a vertical cavity surface emitting laser.

[0071] Figure 6-Figure 8 1 is a schematic diagram of the structure of a method for preparing a vertical cavity surface emitting laser in S210-S280 provided in an embodiment of the present invention. Figure 6-8 The light-emitting unit formed by the process steps can be seen in Fig. 9 . Combined Figure 6-Figure 9 , the preparation method comprises the following steps:

[0072] S210 , forming a semiconductor epitaxial structure on the substrate 10 to form a wafer.

[0073] S220 , depositing an ohmic metal layer 50 , and etching the semiconductor epitaxial structure until the lower reflector layer 20 is exposed, thereby forming a plurality of grooves 100 .

[0074] S230 , corresponding to the plurality of trenches 100 , forming an oxidation restriction layer 80 having an oxidation aperture in each semiconductor unit 200 by using an oxidation process.

[0075] The oxidation restriction layer 80 can be formed by oxidizing a portion of the upper reflector layer in the groove 100 using an oxidation process (e.g., a wet oxidation process) to form a non-conductive oxidation restriction layer 80 above the active layer 30, and the light-emitting aperture in the light-emitting unit can be defined by the oxidation aperture in the oxidation restriction layer 80. Since the oxidation restriction layer 80 is a high-impedance film layer, when the light-emitting unit is applied with an operating voltage / current, the current distribution in the light-emitting unit is concentrated in the middle area of ​​the semiconductor 200 due to the lateral restriction of the oxidation restriction layer 80, so that the light-emitting unit generates laser light in the middle area of ​​the active region. In this way, when the same operating voltage / current is applied, the current density and luminous efficiency of the light-emitting unit can be effectively improved.

[0076] The above embodiment exemplifies that the oxidation restriction layer 80 is located above the active layer 30, but it is not intended to limit the present invention. In other embodiments, the oxidation restriction layer 80 may also be located in the active layer 30, and the specific position of the oxidation restriction layer 80 may be selected according to the specific materials of each film layer in the semiconductor epitaxial structure and the materials.

[0077] S240 , forming a passivation layer 60 on the upper surface of the semiconductor epitaxial structure.

[0078] The passivation layer 60 covers the upper surfaces of all exposed parts of the semiconductor epitaxial structure and the ohmic metal layer 50, for example, covers the upper surface of the upper reflector layer 40, the upper surface of the ohmic metal layer 50, and the sidewalls and bottom of the trench 100. Exemplarily, the passivation layer 60 can be prepared by deposition or other processes, and the passivation layer 60 can include materials such as silicon nitride and / or silicon oxide.

[0079] S250 , performing ion implantation on the sidewalls and bottom of each trench 100 to form a plurality of insulating regions 70 .

[0080] The ion implantation may specifically include the steps of depositing photoresist-patterning photoresist-ion implantation; after the ion implantation is completed, the vertical cavity surface emitting laser may be cleaned in order to proceed to the next step.

[0081] S260 , etching the passivation layer 60 until the ohmic metal layer 50 is exposed, forming a plurality of electrical connection openings 600 corresponding to the ohmic electrodes of the semiconductor units.

[0082] S270 , forming a first electrode 91 corresponding to each semiconductor unit on the upper surface of the passivation layer 60 , and the first electrode 91 is connected to the ohmic electrode through the electrical connection opening 600 .

[0083] Specifically, the preparation process of the first electrode 91 may include multiple steps such as conductive material deposition and patterning, which will not be elaborated in detail here.

[0084] S280 , thinning the substrate 10 , and forming second electrodes 92 corresponding to the semiconductor units on the lower surface of the thinned substrate 10 .

[0085] Among them, when the substrate structure is an insulating substrate, the second electrode 92 and the first electrode 91 can be located on the same side of the substrate to form a VCSEL device in which the first and second electrodes are coplanar. The present application is not limited to the setting position of the second electrode 92, which depends on the specific design.

[0086] Illustratively, after the first electrode 91 and the second electrode 92 are prepared, the wafer may be diced and tested to eventually form a vertical cavity surface emitting laser that meets the requirements.

[0087] This embodiment realizes the preparation of a vertical cavity surface emitting laser through S210-S280. It should be noted that the above preparation process and the contents of each step are only for exemplary description and are not intended to limit the present invention. In actual application, the preparation steps can be increased, decreased and adjusted according to needs. For example, ion implantation can be performed first to prepare an insulating region 70, and then a passivation layer 60 can be formed on the upper surface of the semiconductor epitaxial structure. Among them, when ion implantation is performed at different times, the ion type, energy and dose required for ion implantation can be adjusted according to the film material to be penetrated and the target implantation depth.

[0088] Figure 6-8 The film structure near the groove is mainly shown in FIG. The structure of the light-emitting unit obtained based on this preparation step can be seen in FIG. Fig. 9 Specifically, the active region of the semiconductor unit may include: at least one active layer 311; the oxidation restriction layer 80 may be formed inside the corresponding active layer 311 or above the corresponding active layer 311. The active layer 311 may be a multi-layer stacked structure, for example, including a lower cladding layer, a quantum well, and an upper cladding layer arranged in sequence from bottom to top, wherein the upper cladding layer and the lower cladding layer are semiconductor film layers with different carrier types.

[0089] Next, several specific structures of the active region of the semiconductor unit 200 are described.

[0090] See also Fig. 9 In one embodiment, optionally, the active region includes an active layer 311 and an oxidation restriction layer 80 , and the oxidation restriction layer 80 may be formed above the active layer 311 .

[0091] See also Fig.10 In another embodiment, optionally, the active region includes a plurality of active layers 311 arranged in sequence from bottom to top to increase the slope efficiency of the light-emitting unit. Adjacent active layers 311 may be connected via tunnel junctions 312, so that current can flow and transmit between adjacent active layers 311. In this case, illustratively, the oxidation restriction layer 80 may be formed inside the corresponding active layer 311, or between the corresponding active layer 311 and the tunnel junction 312. At least one oxidation restriction layer 80 may be provided in the active region, which is located in the active layer 311. In this embodiment, an oxidation restriction layer 80 is provided for each active layer 311, but the present application is not limited thereto, and the number of oxidation restriction layers 80 depends on the specific design.

[0092] The specific process of ion implantation in the preparation step is described below.

[0093] Figure 11-12 Schematic diagram of the structure of an ion implantation process in S310-S330 provided by an embodiment of the present invention. Figure 11-12 , the specific process of ion implantation includes:

[0094] S310 , forming a photoresist layer 301 on the upper surface of the semiconductor epitaxial structure.

[0095] The photoresist layer 301 can protect the non-ion implantation area from being affected by the ion implantation process by covering the non-ion implantation area (ie, the area outside the target implantation area).

[0096] S320 , patterning the photoresist layer 301 to form an ion implantation pattern 302 .

[0097] The ion implantation pattern 302, i.e., the photoresist layer 301 is removed to expose the part of the semiconductor epitaxial structure. The ion implantation pattern 302 can be realized by performing exposure and development on the photoresist layer 301. The vertical projection of the ion implantation pattern 302 on the substrate 10 covers the vertical projection of the groove 100 on the substrate 10, so that the insulating region 70 formed after the ion implantation includes a sidewall insulating region 71 surrounding the sidewall of the groove 100. The ion implantation pattern 302 can be used to limit the range of ion implantation, and the size of the sidewall insulating region 71 is related to the range of the ion implantation pattern 302 outside the groove 100. Exemplarily, the ion implantation pattern 302 can be set to have no overlap with the vertical projection of the ohmic electrode on the substrate 10.

[0098] S330 , corresponding to the ion implantation pattern 302 , ion implantation is performed on the semiconductor epitaxial structure to form a plurality of insulating regions 70 .

[0099] The ion type and implantation energy required for the ion implantation can be selected according to the depth of the sidewall insulating region 71 .

[0100] In this embodiment, the insulating region 70 is prepared through S310 - S330 .

[0101] Based on the above implementations, there are optionally multiple specific methods for ion implantation in S330, and a few of them are described below.

[0102] Continue to see Fig.12 In one embodiment, optionally, the sidewall 101 of the trench 100 is perpendicular to the bottom 102 of the trench 100. In this case, the ion implantation can be set to be performed along the first direction Z. The first direction Z is the normal direction of the upper surface of the substrate 10, that is, the thickness direction of the vertical cavity surface emitting laser. Exemplarily, the ion implantation of the sidewall insulating region and the bottom insulating region are performed simultaneously along the first direction Z, then the depth of the sidewall insulating region and the bottom insulating region is the same. Then, if Fig.12 As shown, in this case, the depth required for ion implantation is equal to the depth h of the sidewall insulation region. The implantation depth is relatively deep, for example, 6 microns, and it is difficult to achieve the implantation depth using the same implantation ion at the same implantation energy. Therefore, under this condition, it is necessary to use multiple implantation energies and / or multiple implantation ions to perform ion implantation on the semiconductor epitaxial structure along the first direction Z. Among them, the implanted ions can be H+, B+, etc., and different energies and doses cover different implantation depths. The target implantation depth is achieved by superposition of multiple implantation processes.

[0103] Furthermore, in this method, the thickness h1 of the photoresist layer 301 can be set to be sufficient to resist the ion implantation process, so that all ions that deviate from the ion implantation pattern 302 enter the photoresist, and will not pass through the photoresist layer 301 and be implanted into the functional film layer of the light-emitting unit, thereby ensuring that the film layer in the non-implantation area will not be modified by ion bombardment. Exemplarily, the thickness h1 of the photoresist layer 301 can be set specifically according to the ion implantation depth of the insulating region 70 and the blocking ability of the photoresist material to ion implantation.

[0104] In order to simplify the preparation steps, the inventors have improved the ion implantation process; several of the improvements are exemplified below.

[0105] Fig.13 FIG. 1 is a schematic diagram of a structure in S330 during the ion implantation process provided by an embodiment of the present invention. Fig.13 In another embodiment, optionally, the sidewall 101 of the trench 100 is still perpendicular to the bottom 102 of the trench 100. By adjusting the injection direction of the ion injection, the injection depth can be reduced on the basis of providing a sufficient width w of the sidewall insulation region, so that the preparation of the insulation region 70 can be achieved by using at least one injection energy and at least one injection ion. For example, by reasonably adjusting the injection angle and reasonably setting the width w of the sidewall insulation region, only one injection energy and one injection ion can be used to prepare the insulation region 70, so as to effectively simplify the preparation process.

[0106] Specifically, ion implantation can be performed on the semiconductor epitaxial structure along a direction that is at a preset angle α to the first direction Z. Then, the required ion implantation depth is converted into the depth of the sidewall insulating region in the ion implantation direction, and the ion implantation depth * sinα is the width w of the sidewall insulating region. This method can greatly reduce the implantation depth. Correspondingly, the ion implantation depth * cosα is the depth of the bottom insulating region. Exemplarily, the depth of the bottom insulating region can be set to be greater than or equal to 1 micron. It should be noted that in the insulating region formed by this method, a portion protruding compared to the target width may appear near the top of the sidewall insulating region. This portion is not included in the width w of the sidewall insulating region. The width w of the sidewall insulating region is still based on the width of the main part of the sidewall insulating region, or the minimum width of the sidewall insulating region is used as its width w.

[0107] In this method, after each ion implantation, the wafer can be controlled to rotate once. Before the first rotation, and after each rotation, the same implantation energy and the same ion beam of implanted ions are used to perform regional ion implantation on the semiconductor epitaxial structure along a direction at a preset angle α with the first direction Z, that is, the same ion beam incident angle is used. Among them, since the ion beam bombards the groove 100 along a direction at a preset angle α with the first direction Z, the range of each regional ion implantation only corresponds to a part of the insulating region. Therefore, by rotating the wafer to adjust the ion beam bombardment position, the ion implantation range can cover the entire insulating region after multiple regional ion implantations, ensuring that each position of the groove 100 can receive ion bombardment, thereby forming a uniform and complete insulating region 70.

[0108] On the basis of the above embodiments, optionally, during the ion implantation process, n rotations may be performed so that the ion implantation range covers the entire insulating region. Wherein n is a positive integer, which may be set according to actual needs. For example, n is 1, 2, 3 or 4. Exemplarily, each rotation may adopt the same or different rotation angles as required. Preferably, the same angle is rotated each time to ensure that each regional ion implantation is performed uniformly. Then, each rotation angle is 360 / (n+1) degrees.

[0109] Fig.14 1 is a schematic diagram of an ion implantation process provided by an embodiment of the present invention. Fig.14 , taking three rotations, each of which is 90 degrees, as an example, the ion implantation process is described in detail. Fig.14 In one embodiment, optionally, the wafer can be controlled to rotate on a horizontal plane, and the relative position of the ion beam can be controlled to be fixed, that is, the ion beam and the normal direction of the horizontal plane are at a preset angle; wherein the horizontal plane is parallel to the upper surface of the substrate. Then, the ion beam incident position can be adjusted by rotating the wafer. It is difficult to adjust the exit angle of the ion beam, and the rotation process and angle of the wafer on the horizontal plane are easier to control. Since there is no need to adjust the angle of the ion beam multiple times, the ion implantation process can be simplified, and the consistency of the thickness of the insulating region 70 can be ensured. Exemplarily, the wafer can be fixed on a machine table, and the rotation of the wafer can be achieved by controlling the rotation process of the machine table.

[0110] Fig.14 For example, the solid arrow indicates the incident direction of the ion beam, the disk indicates the wafer, and the shaded fill indicates the range of the ion implanted wafer (ie, each ion implantation covers the entire wafer). Fig.14 The small circle in the middle disk can be understood as the ion implantation area corresponding to a groove 100. For the sake of convenience, only one small circle is shown here. It should be noted that the size shown here does not represent the actual size ratio of the wafer and the groove. Figure 13-14Due to the blocking effect of the trench sidewall 101 and the photoresist layer 301, when the ion beam is tilted for implantation, although the ion implantation covers the entire wafer, the following may occur: Fig.13 In the case where the right side wall of the middle trench is blocked, the surface of the trench side wall 101 in the blocked area and even part of the trench bottom 102 are not bombarded by the ion beam. Fig.14 As shown in , before the first rotation, the shielded area cannot be ion-implanted. After each rotation, the shielded portion before the first rotation is gradually exposed in the ion implantation area. Specifically, taking area B1 as an example, before the first rotation, area B1 is located in the shielded area (for example, in the fourth quadrant, which can correspond to Fig.13 The right side wall of the middle groove 100 is not covered by the first regional ion implantation. However, the region B1 rotates with the rotation of the wafer. For example, after the first rotation, the shielding area covers the region B2; after the second rotation, the shielding area covers the region B3; after the third rotation, the shielding area covers the region B4. It can be seen that after two rotations, the region B1 has become as follows relative to the ion beam: Fig.13 The left side wall portion of the middle groove (for example, located in the second quadrant) can be unobstructed and fully covered by the ion beam. The ion beam performs ion implantation on the groove 100 after the two rotations in a direction with a preset angle α with the first direction Z. The range of the two rotations and the secondary regional ion implantation has completely covered the area B1, that is, through the rotation of the wafer, the ion implantation of the area B1 is completed (similarly, the front and rear left and right side walls of the groove are all ion implanted). It can be seen that by rotating the wafer multiple times for regional ion implantation, the range of ion implantation can cover the entire area of ​​the insulating area, forming a uniform and complete insulating area.

[0111] On the basis of the above-mentioned embodiment, optionally, the angle range of the preset angle α is: 3-20 degrees, preferably 5-15 degrees, for example 7 degrees. Specifically, the preset angle α can be set according to the target width and target depth of the sidewall insulation region, and the depth of the groove 100. Exemplarily, since the relative position of the ion beam and the groove 100 is far, the upper limit of the preset angle is the smaller of the angle β and the angle γ to avoid the defect that the bottom insulation region cannot be completely formed. Among them, the angle β is the angle between the line connecting the vertex of the groove sidewall 101 and the center position of the groove bottom 102, and the groove sidewall 101; the angle γ is the angle between the line connecting the vertex of the inner wall of the photoresist layer 301 close to the groove 100 and the center position of the groove bottom 102, and the inner wall of the photoresist layer 301 close to the groove 100.

[0112] Fig.15 FIG. 1 is another structural diagram of S330 in the ion implantation process provided by an embodiment of the present invention. Fig.15In another embodiment, the implantation depth can be reduced by adjusting the shape of the trench 100. In this way, under the vertical implantation condition, at least one implantation energy and at least one implantation ion can be used to prepare the insulating region 70, thereby simplifying the preparation process.

[0113] Specifically, the cross-sectional shape of the groove 100 can be set to an inverted trapezoid, and the angle (obtuse angle) δ between the sidewall 101 of the groove and the bottom 102 of the groove 100 is in the range of 93-145 degrees, preferably 95-135 degrees, for example 100 degrees. Then, when the semiconductor epitaxial structure is ion-implanted along the first direction Z, the implantation depth is adjusted to the distance between the groove sidewall 101 and the outer boundary of the sidewall insulating region in the first direction Z. The implantation depth is also less than the depth when the vertical sidewall is implanted vertically. Therefore, at least one implantation energy and at least one implantation ion can be used to prepare the insulating region 70. For example, by reasonably adjusting the angle δ between the groove sidewall 101 and the bottom 102 and the width of the sidewall insulating region, only one implantation energy and one implantation ion can be used to prepare the insulating region 70, so as to effectively simplify the preparation process. It should be noted that at this time, the width w of the sidewall insulating region can be understood as the minimum width of the sidewall insulating region in the direction perpendicular to the first direction Z.

[0114] On the basis of preparing the inverted trapezoidal groove 100, optionally, an inclined ion implantation method can be adopted to increase the width w of the sidewall insulating region under the same implantation energy and the same implanted ions; or on the basis of ensuring the same width w of the sidewall insulating region, expand the selection range of ion types and energy of ion implantation.

[0115] On the basis of the above embodiments, optionally, in the case of vertical ion implantation, the device may not be rotated and only one ion implantation may be performed. Alternatively, the device may be rotated and multiple ion implantations may be performed to eliminate the influence of the non-vertical and sloped section of the photoresist layer 301 on the ion implantation process; and to eliminate the influence of the ion implantation not being completely vertical due to environmental and other influencing factors.

[0116] The isolation structure between adjacent semiconductor units 200 is described below.

[0117] Fig.16 is a schematic diagram of a top view of a vertical cavity surface emitting laser provided by an embodiment of the present invention. Fig.16 In one embodiment, optionally, taking the case where the cross section of the semiconductor unit is circular when viewed from above, the groove 100 itself is a ring-shaped groove surrounding the semiconductor unit. Then, the groove 100 itself can cut off the electrical connection between adjacent semiconductor units, and the insulating region can assist the groove 100 to further ensure the electrical isolation function.

[0118] Fig.17 FIG. 1 is a schematic diagram of a top view of another vertical cavity surface emitting laser provided by an embodiment of the present invention. Fig.17 In another embodiment, the grooves 100 around each semiconductor unit may not be continuous grooves, but may be discretely arranged, with multiple grooves 100 spaced apart around the semiconductor unit. Then, the grooves 100 themselves cannot cut off the electrical connection between adjacent semiconductor units, but by preparing insulating regions 70 around the grooves 100 and connecting the insulating regions 70 around adjacent grooves 100, multiple spaced apart grooves 100 and their corresponding multiple insulating regions 70 may together form a ring-shaped insulating structure 303 around the semiconductor unit, which may also ensure the isolation between adjacent semiconductor units on the active layer.

[0119] It should be noted that the cross-sectional shape of the above-mentioned insulating structure in top view is not intended to limit the present invention. In other embodiments, optionally, the cross-sectional shape of the insulating structure formed by the trench 100 and its corresponding insulating region 70 in top view may also be a quadrilateral, hexagon or other polygon, or an irregular shape. Also, the cross-sectional shape of the discrete trench 100 in top view may be a circle, an ellipse, a rectangle, a hexagon or other polygon, or an irregular shape.

[0120] The embodiment of the present invention also provides a vertical cavity surface emitting laser, which is prepared by the method for preparing the vertical cavity surface emitting laser provided by any embodiment of the present invention, and has corresponding beneficial effects. Exemplarily, the vertical cavity surface emitting laser includes a substrate, a semiconductor epitaxial structure and an ohmic metal layer stacked from bottom to top. Among them, the semiconductor epitaxial structure includes a lower reflector layer, an active layer and an upper reflector layer arranged in sequence from bottom to top. The semiconductor epitaxial structure also includes a plurality of grooves, and the bottom of the groove exposes the lower reflector layer. In addition, the sidewalls and bottom of each groove are provided with a plurality of insulating regions; wherein the insulating region includes a sidewall insulating region contacting the corresponding groove sidewall, and a bottom insulating region contacting the corresponding groove bottom; the depth of the sidewall insulating region is greater than the depth of the groove; the groove and the insulating region jointly separate the semiconductor epitaxial structure into a plurality of semiconductor units isolated from each other on the active layer. Each semiconductor unit includes a lower reflector, an active region, an upper reflector and an ohmic electrode arranged in sequence from bottom to top. A semiconductor unit, combined with the substrate portion at its bottom, and the first electrode and the second electrode, constitute a light-emitting unit. A plurality of light emitting units are arranged in an array to form a vertical cavity surface emitting laser.

[0121] The vertical cavity surface emitting laser provided by the embodiment of the present invention forms an insulating region with high impedance around the groove, which helps to isolate surface defects formed during oxidation, etching, or deposition of the passivation layer, reduce the leakage current of the device, and improve the voltage resistance of the device, so that the device can be applied to short pulses and narrow pulse driving conditions with large currents. In addition, by setting the sidewall insulating region, the current distribution area within the semiconductor unit can be limited, which helps to adjust the current density and divergence angle of the light-emitting unit to a certain extent. Therefore, compared with the prior art, the embodiment of the present invention can improve the voltage resistance and current carrying capacity of the vertical cavity surface emitting laser, so as to improve the robustness of the vertical cavity surface emitting laser and expand its scope of application.

[0122] It should be noted that in each embodiment of the preparation method, specific descriptions are given for different structures of vertical cavity surface emitting lasers. These specific structures can all be considered as the structures of the vertical cavity surface emitting laser provided in the embodiments of the present invention, and the repeated contents will not be repeated here.

[0123] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0124] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a vertical cavity surface emitting laser, characterized in that: include: Growing a semiconductor epitaxial structure on a substrate to form a wafer; wherein the semiconductor epitaxial structure comprises a lower reflector layer, an active layer and an upper reflector layer arranged in sequence from bottom to top; Depositing an ohmic metal layer on the semiconductor epitaxial structure, and etching the semiconductor epitaxial structure until the lower reflector layer is exposed to form a plurality of grooves; Ion implantation is performed on the sidewalls and bottom of each of the trenches to form a plurality of insulating regions; wherein the insulating regions include a sidewall insulating region in contact with the corresponding trench sidewalls, and a bottom insulating region in contact with the corresponding trench bottom; the depth of the sidewall insulating region is greater than the depth of the trench; the trenches and the insulating regions are used together to separate the semiconductor epitaxial structure into a plurality of semiconductor units isolated from each other on the active layer, so that each of the semiconductor units includes a lower reflector, an active region, an upper reflector and an ohmic electrode arranged in sequence from bottom to top.

2. The method for preparing a vertical cavity surface emitting laser according to claim 1, characterized in that: The width of the sidewall insulating region is greater than or equal to 0.2 microns.

3. The method for preparing a vertical cavity surface emitting laser according to claim 1, characterized in that: Ion implantation is performed on the sidewalls and bottom of each of the trenches to form a plurality of insulating regions, including: forming a photoresist layer on the upper surface of the semiconductor epitaxial structure; Patterning the photoresist layer to form an ion implantation pattern; wherein a vertical projection of the ion implantation pattern on the substrate covers a vertical projection of the groove on the substrate; Corresponding to the ion implantation pattern, ion implantation is performed on the semiconductor epitaxial structure to form a plurality of the insulating regions.

4. The method for preparing a vertical cavity surface emitting laser according to claim 3, characterized in that: The sidewall of the groove is perpendicular to the bottom of the groove; Performing ion implantation on the semiconductor epitaxial structure comprises: Ion implantation is performed on the semiconductor epitaxial structure along a first direction using a variety of implantation energies and / or a variety of implantation ions; wherein the first direction is a normal direction of an upper surface of the substrate.

5. The method for preparing a vertical cavity surface emitting laser according to claim 3, characterized in that: The cross-sectional shape of the groove is an inverted trapezoid, and the angle between the side wall of the groove and the bottom of the groove is in the range of 93-145 degrees; Performing ion implantation on the semiconductor epitaxial structure comprises: At least one implantation energy and at least one implantation ion are used to perform ion implantation on the semiconductor epitaxial structure along a first direction; wherein the first direction is parallel to a normal direction of an upper surface of the substrate.

6. The method for preparing a vertical cavity surface emitting laser according to claim 3, characterized in that: The sidewall of the groove is perpendicular to the bottom of the groove, or the cross-sectional shape of the groove is an inverted trapezoid, and the angle between the sidewall of the groove and the bottom of the groove is in the range of 93-145 degrees; Performing ion implantation on the semiconductor epitaxial structure comprises: Controlling the wafer to rotate at least once; before the first rotation and after each rotation, using the same implantation energy and the same implantation ion beam to perform regional ion implantation on the semiconductor epitaxial structure along a direction with a preset angle to the first direction; wherein the range of each regional ion implantation corresponds to a partial area of ​​the insulating area; after multiple regional ion implantations, the range of ion implantation covers the entire area of ​​the insulating area; Wherein, the first direction is parallel to the normal direction of the upper surface of the substrate; the angle range of the preset angle is: 3-20 degrees.

7. The method for preparing a vertical cavity surface emitting laser according to claim 6, characterized in that: The depth of the bottom insulating region is greater than or equal to 1 micron.

8. The method for preparing a vertical cavity surface emitting laser according to claim 6, characterized in that: Controlling the wafer to rotate on a horizontal plane, controlling the ion beam to have a preset angle with a normal direction of the horizontal plane, and controlling the ion beam to be fixed; wherein the horizontal plane is parallel to the upper surface of the substrate; In the process of forming the plurality of insulating regions, the wafer is rotated n times, and each rotation angle is 360 / (n+1) degrees; n is a positive integer.

9. The method for preparing a vertical cavity surface emitting laser according to claim 1, characterized in that: The groove is an annular groove surrounding the semiconductor unit; Alternatively, a plurality of spaced-apart grooves are disposed at the periphery of each semiconductor unit, and the plurality of spaced-apart grooves and a plurality of insulating regions corresponding to the plurality of spaced-apart grooves constitute an annular insulating structure surrounding the semiconductor unit.

10. The method for preparing a vertical cavity surface emitting laser according to claim 1, characterized in that: After forming a plurality of grooves, the method further comprises: Corresponding to the plurality of trenches, forming an oxidation restriction layer having an oxidation aperture in each of the semiconductor units by an oxidation process; Wherein, the active region includes: at least one active layer; When the active region includes multiple layers of active layers, the multiple layers of active layers are arranged in sequence from bottom to top, and adjacent active layers are connected via tunnel junctions.

11. The method for preparing a vertical cavity surface emitting laser according to claim 1, characterized in that: Before or after forming the plurality of insulating regions, further comprising: forming a passivation layer on the upper surface of the semiconductor epitaxial structure; After forming the passivation layer and each of the insulating regions, the preparation method further comprises: Etching the passivation layer until the ohmic metal layer is exposed to form a plurality of electrical connection openings corresponding to the ohmic electrodes of each semiconductor unit; Forming a first electrode corresponding to each of the semiconductor units on the upper surface of the passivation layer, wherein the first electrode is connected to the ohmic electrode through the electrical connection opening; The substrate is thinned, and second electrodes corresponding to the semiconductor units are formed on the lower surface of the thinned substrate.

12. A vertical cavity surface emitting laser, characterized in that: The vertical cavity surface emitting laser is prepared by the preparation method of any one of claims 1 to 11.

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