Write request arbitration circuit and method

Abstract

The invention discloses an arbitration circuit and method for a write-in request. The arbitration circuit comprises a plurality of request channels, request storage modules corresponding to the request channels, an arbiter and a DMA (Direct Memory Access) module, each request channel comprises a plurality of request modules, and each request module at least corresponds to one data storage module; each request module initiates a data writing request; each request storage module stores data writing requests of all the request modules in the corresponding request channel; the arbiter carries out arbitration to obtain a current target request channel; and the DMA module obtains a data write-in request in a target request storage module corresponding to the target request channel, determines a target data storage module according to the control write-in information carried in the data write-in request, reads the to-be-written data from the target data storage module and writes the to-be-written data into the external equipment. According to the embodiment of the invention, the problem of arbitration of a large number of write requests is avoided, the arbitration result generation speed of the write requests is accelerated, and the data write-in speed is improved.

Description

Technical Field

[0001] The present invention relates to data storage technology, and more particularly to an arbitration circuit and method for writing a request. Background Art

[0002] In the design of storage control chips, a multi-channel design is more common. Peripherals of multiple channels simultaneously access shared resources inside the chip. Therefore, an arbitrator is required to arbitrate the requests of each channel so that only one channel can access at a time.

[0003] When multiple request modules in multiple channels initiate write requests at the same time, there are two common practices in the related technology: one is to input each request into the arbitrator and let the arbitrator arbitrate the request to be responded to; the other is to perform a first-level arbitration on the request within each channel, and then perform a second-level arbitration on the request between channels.

[0004] However, the arbitration method of the related art requires arbitration for a large number of requests, which results in low efficiency in generating arbitration results, thereby affecting the data writing speed. Summary of the invention

[0005] The present application provides an arbitration circuit and method for write requests, which can avoid arbitrating a large number of write requests, thereby accelerating the speed of generating arbitration results of write requests and improving data writing speed.

[0006] In a first aspect, the present application provides an arbitration circuit for write requests, comprising: a plurality of request channels, a request storage module corresponding to each request channel, an arbitrator, and a DMA module; wherein each of the request channels comprises: a plurality of request modules, each request module corresponds to at least one data storage module; Each request module is used to initiate a data writing request; Each request storage module is used to store data write requests initiated by all request modules in the corresponding request channel; wherein the data write request carries at least control write information corresponding to the data to be written; wherein the control write information includes: identification information of the data storage module to which the data to be written belongs; The arbitrator is used to arbitrate all request channels with data write requests to obtain the target request channel to which the data write request to be responded to belongs; The DMA module is used to obtain a data write request in a target request storage module corresponding to the target request channel, determine a target data storage module for storing the data to be written in the corresponding request module according to control write information carried by the obtained data write request, and read the data to be written from the target data storage module and write it to the external device.

[0007] In a second aspect, the present application provides an arbitration method for a write request, which is applied to the arbitration circuit as described above, and the method includes: Each request module initiates a data write request; Each request storage module stores the data write request initiated by all request modules in the corresponding request channel; wherein the data write request carries at least control write information corresponding to the data to be written; The arbitrator arbitrates all request channels with data write requests to obtain the target request channel to which the data write request to be responded to belongs; The DMA module obtains a data write request in a target request storage module corresponding to the target request channel, determines a target data storage module for storing the data to be written in the corresponding request module according to control write information carried by the obtained data write request, and reads the data to be written from the target data storage module and writes it into the external device; wherein the control write information includes: identification information of the data storage module to which the data to be written belongs.

[0008] Compared with the related art, in the embodiment of the present application, each request storage module stores the data write requests initiated by all request modules in the corresponding request channel, the arbitrator arbitrates all request channels with data write requests to obtain the target request channel to which the data write request to be responded belongs, the DMA module obtains the data write request in the target request storage module corresponding to the target request channel, determines the target data storage module for storing the data to be written in the corresponding request module according to the control write information carried by the obtained data write request, and reads the data to be written from the target data storage module and writes it to the external device. The embodiment of the present application can use the request storage module to store the data write requests initiated by all request modules in the corresponding request channel, and use the arbitrator to arbitrate all request channels to obtain the target request channel to which the data write request to be responded belongs, thereby avoiding the problem of arbitrating a large number of write requests, thereby speeding up the speed of generating arbitration results of write requests and improving the data writing speed.

[0009] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0011] Figure 1 This is a structural diagram of an arbitration circuit for a write request according to an embodiment of the present application; Figure 2 A schematic diagram of the structure of another arbitration circuit for write request according to an embodiment of the present application; Figure 3 This is a structural diagram of another arbitration circuit for write requests according to an embodiment of the present application; Figure 4 The figure is a flowchart of an arbitration method for writing a request according to an embodiment of the present application. DETAILED DESCRIPTION

[0012] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0013] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0014] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation for the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0015] In the related art, large-scale system-on-chip (SoC) often has very high requirements for data transmission rate and transmission efficiency. At the same time, there are generally a large number of designs in SoC that multiple modules simultaneously access the same shared resource (such as random access memory (RAM)). How to ensure sufficient throughput in the design while minimizing the scale of logic circuits poses a great challenge to the design of DMA control and arbitration. In the design of storage control chips, due to the demand for large capacity and high parallelism, the particle characteristics of flash, etc., it is currently more common to adopt a multi-channel design, and the peripherals of multiple channels simultaneously access the shared resources inside the chip. This requires the arbitrator to arbitrate the requests of each channel so that only one channel can access a shared resource at the same time. When multiple channels have multiple modules that initiate requests at the same time, there are usually two ways: one is to input each request into the arbitrator and let the arbitrator arbitrate the request to be responded to; the other is to first perform a first-level arbitration on the request within each channel, and then perform a second-level arbitration on the request between channels.

[0016] However, the arbitration method of the related art requires arbitration for a large number of requests, which results in low efficiency in generating arbitration results, thereby affecting the data writing speed.

[0017] To this end, the embodiment of the present application provides an arbitration circuit for a write request, such as Figure 1 As shown, it includes: multiple request channels 101, request storage modules 102 corresponding to each request channel 101, an arbitrator 103, and a DMA module 104; wherein each of the request channels 101 includes: multiple request modules 105, and each request module 105 corresponds to at least one data storage module 106; Each request module 105 is used to initiate a data write request; Each request storage module 102 is used to store data write requests initiated by all request modules 105 in the corresponding request channel; wherein the data write request at least carries control write information corresponding to the data to be written; The arbitrator 103 is used to arbitrate all request channels with data write requests to obtain the target request channel to which the data write request to be responded to belongs; The DMA module 104 is used to obtain the data write request in the target request storage module 102 corresponding to the target request channel, determine the target data storage module 106 for storing the data to be written in the corresponding request module 105 according to the control write information carried by the obtained data write request, and read the data to be written from the target data storage module 106 and write it to the external device; wherein the control write information includes: identification information of the data storage module 106 to which the data to be written belongs.

[0018] In this embodiment, the request channel having a data write request refers to a request channel having a data request initiating module for initiating a data write request.

[0019] In this embodiment, the objects of arbitration by the arbitrator are all request channels. When the arbitrator obtains a request channel through arbitration, it indicates that the data write request to be responded to this time is the data write request in the request storage module corresponding to the request channel, that is, the data write request initiated by a request module in the request channel.

[0020] Since the control write information includes the identification information of the data storage module to which the data to be written belongs, the target data storage module for storing the data to be written in the corresponding request module can be determined based on the identification information of the data storage module to which the data to be written belongs in the control write information carried by the obtained data write request.

[0021] The arbitration circuit for write requests provided in the embodiment of the present application can utilize the request storage module to store the data write requests initiated by all request modules in the corresponding request channel, and utilize the arbitrator to arbitrate all request channels to obtain the target request channel to which the data write request to be responded to belongs, thereby avoiding the problem of arbitrating a large number of write requests, thereby speeding up the speed of generating arbitration results for write requests and improving the data writing speed.

[0022] The arbitration circuit for write requests provided in the embodiment of the present application can solve the request arbitration problem when there are multiple channels at the same time and each channel has multiple requests, and has the characteristics of simple structure, small circuit scale and high transmission efficiency.

[0023] In an exemplary embodiment, the control writing information further includes: a starting address of the data to be written and a length of the data to be written.

[0024] In an exemplary embodiment, the request storage module includes: a synchronous FIFO module 107 .

[0025] In this embodiment, the synchronous FIFO module 107 is a first-in-first-out module, and the data writing request initiated first will be output first.

[0026] In an exemplary embodiment, when the request storage module is a synchronous FIFO module 107, the arbitrator 103 is further used to send a data write request output instruction to the target synchronous FIFO module 107 corresponding to the target request channel obtained by this arbitration; The target synchronization FIFO module 107 is used to output a write data request to the DMA module 104 according to a data write request output instruction; The DMA module 104 obtains a data write request in a target request storage module, including: The DMA module 104 receives the data write request output by the target synchronous FIFO module.

[0027] In this embodiment, the arbitrator arbitrates a target request channel once in a round of arbitration, and sends a data write request output instruction to the target synchronous FIFO module corresponding to the target request channel obtained in this arbitration, so that the target synchronous FIFO module outputs a write data request to the DMA module, and the DMA module receives the data write request output by the target synchronous FIFO module, determines the target data storage module for storing the data to be written in the corresponding request module according to the control write information carried by the obtained data write request, reads the data to be written from the target data storage module and writes it to the external device, and then feeds back the writing completion information to the arbitrator, and the arbitrator performs the next round of arbitration.

[0028] In an exemplary embodiment, before the target synchronous FIFO module outputs a write data request to the DMA module 104 according to the data write request output instruction, the target synchronous FIFO module is further used to determine whether there is an outputtable data write request according to the received data write request output instruction; The target synchronous FIFO module outputs a write data request to the DMA module 104 according to a data write request output instruction, including: In response to the determination result that there is an outputtable data write request in the target synchronous FIFO module, the target synchronous FIFO module outputs a write data request to the DMA module 104 according to a data write request output instruction.

[0029] In this embodiment, the determination of whether there is a data write request that can be output in the target synchronous FIFO module is actually the determination of whether the target synchronous FIFO module is empty. In practical applications, the target synchronous FIFO module can respond to the write control signal and output the write data request to the DMA module according to the data write request output instruction. The write control signal can be (a pulse signal of the arbitrator arbitration completion) and not (the target synchronous FIFO module empty signal) and (the grant[i] signal of the arbitrator arbitration to the request channel i).

[0030] In an exemplary embodiment, the depth of the synchronous FIFO module is set according to an actual throughput rate in the corresponding request channel.

[0031] In practical applications, the depth of the synchronous FIFO module can be set to 4, taking into account the frequency of data write requests initiated by all request modules in the request channel and the arbitration frequency of the arbitrator.

[0032] In an exemplary embodiment, each request storage module stores data write requests initiated by all request modules 105 in the corresponding request channel, including: Each request storage module performs the following operations for each data write request initiated by each request module 105 in the corresponding request channel: It is determined whether there is available storage space, and in response to the determination result that there is available storage space, the data write request is stored.

[0033] In this embodiment, the judgment of whether there is an output data write request in the target synchronous FIFO module of each request storage module is actually the judgment of whether the target synchronous FIFO module is empty.

[0034] In an exemplary embodiment, the arbiter 103 is further configured to perform a logical OR operation on the data write request in each request channel respectively, so as to obtain all request channels having data write requests.

[0035] In this embodiment, the data write request in each request channel refers to the data write request initiated by all request modules in each request channel. For example, assuming that there are 4 request channels, a logical OR operation is performed on the data write requests initiated by all request modules in the first request channel and a logical OR operation result is obtained, a logical OR operation is performed on the data write requests initiated by all request modules in the second request channel and a logical OR operation result is obtained, a logical OR operation is performed on the data write requests initiated by all request modules in the third request channel and a logical OR operation result is obtained, and a logical OR operation is performed on the data write requests initiated by all request modules in the fourth request channel and a logical OR operation result is obtained, wherein the request channel corresponding to the logical OR operation result that is not empty is the request channel with the data write request.

[0036] In an exemplary embodiment, the DMA module 104 is further configured to send a request initiation pause instruction to the target request module 105 when the target request storage module is in the process of reading the data to be written and writing the data to the external device, so that the target request module 105 pauses initiating new data write requests; The DMA module 104 is further configured to send a request to initiate a recovery instruction to the target request module 105 after the data to be written has been written into the external device, so that the target request module 105 initiates a new data writing request when necessary.

[0037] In an exemplary embodiment, Figure 2 As shown, it also includes: a data cache module 108; The data cache module 108 is used to store the data read by the DMA module 104 from the target data storage module 106; The DMA module 104 reads the data to be written from the target data storage module 106 and writes the data to the external device, including: The DMA module 104 determines the data corresponding to the starting address of the data to be written in the target data storage module 106, and sequentially obtains the data and subsequent data starting from the determined data and stores them in the data cache module 108 until the length of the obtained data is equal to the length of the data to be written; The DMA module 104 writes the data stored in the data cache module 108 to the external device.

[0038] In this embodiment, the DMA module 104 sequentially reads part of the data to be written in the target data storage module. Whenever part of the data is read, the read part of the data is temporarily placed in the data cache module 108. After all the data to be written is read, the data to be written in the data cache module 108 is written to the external device.

[0039] In practical applications, the data cache module may be a random access memory (RAM).

[0040] The embodiment of the present application also provides an arbitration circuit for a write request, such as Figure 3 As shown, it includes: multiple request channels 101 ( Figure 3 Taking four request channels as an example), a synchronous FIFO module 107, an arbiter 103, and a DMA module 104 corresponding to each request channel 101 respectively; wherein each of the request channels 101 includes: multiple request modules 105, and each request module 105 corresponds to a RAM 108.

[0041] The four synchronous FIFO modules 107 are used to cache the data write request of each request channel and the information of each request (REQ_INFO). The structure and control signal of each FIFO are similar. As shown in the figure, the write control signal of the FIFO is the pulse P_r generated by the data write request of the internal module of each request channel and the non-FIFO write full signal, and the read control signal of the FIFO is (the pulse signal of the arbitration completion of the arbitrator 103) and non (FIFO empty signal) and (the grant[i] signal arbitrated to the channel i). The depth of the FIFO is set according to the actual throughput of the channel, for example, the depth can be set to 4.

[0042] The arbiter 103 is used to arbitrate the requests REQ1-REQ4 of the four channels. The input signals of the arbiter are REQ1-REQ4, and REQi (1<=i<=4) is the logical OR of all requests in each channel. Since there are four request channels in the arbitration circuit in this embodiment, the arbiter is actually a 4-1 arbiter.

[0043] DMA module 104 is used to transfer the corresponding data source obtained to peripheral 1 according to the arbitration result and REQ_INFO. Assuming that the output data of request channel FIFO1 is REQ_INFO1, and the content of REQ_INFO1 is module 1 in request channel 1, then the module will parse out the corresponding source data as the data in RAM1 of module 1, and then control the execution of DMA read operation of RAM1 to transfer the corresponding data to peripheral 1.

[0044] DMA module 104 also generates a finishi (1<=i<=16) signal ( Figure 3 Take each request channel including 4 request modules as an example, therefore), the request is transmitted to each internal module of each request channel, so that the request of each internal module of each request channel is released after obtaining arbitration and execution. In this example, after the data transmission of RAM1 is completed, a finish1 signal is sent back to module 1 inside channel 1 to release its corresponding internal request.

[0045] In this embodiment, a data cache module may also be provided to cache data during the process of transmitting data from the internal module to the external device.

[0046] The embodiment of the present application provides an arbitration method for a write request, which is applied to the arbitration circuit described in the above embodiment. Figure 4 As shown, the method includes: Step 201, each request module initiates a data write request; Step 202: Each request storage module stores the data write request initiated by all request modules in the corresponding request channel; wherein the data write request at least carries control write information corresponding to the data to be written; Step 203: The arbitrator arbitrates all request channels with data write requests to obtain the target request channel to which the data write request to be responded belongs. Step 204, the DMA module obtains a data write request in the target request storage module corresponding to the target request channel, determines a target data storage module for storing the data to be written in the corresponding request module according to the control write information carried by the obtained data write request, and reads the data to be written from the target data storage module and writes it to the external device; wherein the control write information includes: identification information of the data storage module to which the data to be written belongs.

[0047] In an exemplary embodiment, the control writing information further includes: a starting address of the data to be written and a length of the data to be written.

[0048] In an exemplary embodiment, the request storage module includes: a synchronous FIFO module. When the request storage module is a synchronous FIFO module, the method further includes: The arbitrator sends a data write request output instruction to the target synchronous FIFO module corresponding to the target request channel obtained in this arbitration; The target synchronous FIFO module outputs a write data request to the DMA module according to a data write request output instruction.

[0049] In an exemplary embodiment, the DMA module obtains a data write request in a target request storage module, including: The DMA module receives a data write request output by the target synchronous FIFO module.

[0050] In an exemplary embodiment, before the target synchronous FIFO module outputs a write data request to the DMA module according to a data write request output instruction, the method further includes: The target synchronous FIFO module determines whether there is an outputtable data write request according to the received data write request output instruction.

[0051] In an exemplary embodiment, the target synchronous FIFO module outputs a write data request to the DMA module according to a data write request output instruction, including: In response to a determination result that there is an outputtable data write request in the target synchronous FIFO module, the target synchronous FIFO module outputs a write data request to the DMA module according to a data write request output instruction.

[0052] In an exemplary embodiment, the depth of the synchronous FIFO module is set according to an actual throughput rate in the corresponding request channel.

[0053] In an exemplary embodiment, each request storage module stores data write requests initiated by all request modules 105 in the corresponding request channel, including: Each request storage module performs the following operations for each data write request initiated by each request module in the corresponding request channel: It is determined whether there is available storage space, and in response to the determination result that there is available storage space, the data write request is stored.

[0054] In an exemplary embodiment, the arbitrator performs a logical OR operation on the data write request in each request channel to obtain all request channels having data write requests.

[0055] In an exemplary embodiment, the method further comprises: When the DMA module is in the process of reading the data to be written from the target request storage module and writing it to the external device, the DMA module sends a request initiation pause instruction to the target request module, so that the target request module pauses initiating new data writing requests; After the data to be written has been written into the external device, the DMA module sends a request to initiate a recovery instruction to the target request module, so that the target request module initiates a new data writing request when necessary.

[0056] In an exemplary embodiment, the arbitration circuit further includes: a data cache module.

[0057] In an exemplary embodiment, the method further comprises: The data cache module stores the data read by the DMA module from the target data storage module.

[0058] In an exemplary embodiment, the DMA module reads the data to be written from the target data storage module and writes the data to the external device, including: The DMA module determines data corresponding to the starting address of the data to be written in the target data storage module, and sequentially obtains the data and subsequent data starting from the determined data and stores them in the data cache module until the length of the obtained data is equal to the length of the data to be written; The DMA module writes the data stored in the data cache module into the external device.

[0059] The arbitration method for write requests provided in the embodiment of the present application can utilize the request storage module to store the data write requests initiated by all request modules in the corresponding request channel, and utilize the arbitrator to arbitrate all request channels to obtain the target request channel to which the data write request to be responded to belongs, thereby avoiding the problem of arbitrating a large number of write requests, thereby speeding up the speed of generating arbitration results for write requests and improving the data writing speed.

[0060] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. An arbitration circuit for a write request, characterized in that: include: Multiple request channels, request storage modules, arbitrators, and DMA modules corresponding to each request channel; wherein each of the request channels comprises: multiple request modules, each request module corresponds to at least one data storage module; Each request module is used to initiate a data writing request; Each request storage module is used to store data write requests initiated by all request modules in the corresponding request channel; wherein the data write request at least carries control write information corresponding to the data to be written; The arbitrator is used to arbitrate all request channels with data write requests to obtain the target request channel to which the data write request to be responded to belongs; The DMA module is used to obtain a data write request in a target request storage module corresponding to the target request channel, determine a target data storage module for storing the data to be written in the corresponding request module according to control write information carried by the obtained data write request, and read the data to be written from the target data storage module and write it into the external device; wherein the control write information includes: identification information of the data storage module to which the data to be written belongs.

2. The arbitration circuit according to claim 1, characterized in that: The control writing information also includes: the starting address of the data to be written and the length of the data to be written.

3. The arbitration circuit according to claim 1, characterized in that: The request storage module includes: a synchronous FIFO module. When the request storage module is a synchronous FIFO module, the arbitrator is further used to send a data write request output instruction to the target synchronous FIFO module corresponding to the target request channel obtained by this arbitration; The target synchronous FIFO module is used to output a write data request to the DMA module according to a data write request output instruction; The DMA module obtains a data write request in a target request storage module, including: The DMA module receives a data write request output by the target synchronous FIFO module.

4. The arbitration circuit according to claim 3, characterized in that: Before the target synchronous FIFO module outputs a write data request to the DMA module according to the data write request output instruction, the target synchronous FIFO module is further used to determine whether there is an outputtable data write request according to the received data write request output instruction; The target synchronous FIFO module outputs a write data request to the DMA module according to a data write request output instruction, including: In response to a determination result that there is an outputtable data write request in the target synchronous FIFO module, the target synchronous FIFO module outputs a write data request to the DMA module according to a data write request output instruction.

5. The arbitration circuit according to claim 3, characterized in that: The depth of the synchronous FIFO module is set according to the actual throughput rate in the corresponding request channel.

6. The arbitration circuit according to claim 1, characterized in that: Each request storage module stores the data write requests initiated by all request modules in the corresponding request channel, including: Each request storage module performs the following operations for each data write request initiated by each request module in the corresponding request channel: It is determined whether there is available storage space, and in response to the determination result that there is available storage space, the data write request is stored.

7. The arbitration circuit according to claim 1, characterized in that: The arbiter is further used to perform a logical OR operation on the data write request in each request channel respectively, so as to obtain all request channels having data write requests.

8. The arbitration circuit according to claim 1, characterized in that: The DMA module is further configured to send a request initiation pause instruction to the target request module when the target request storage module is in the process of reading the data to be written and writing it to the external device, so that the target request module pauses initiating new data writing requests; The DMA module is further used to send a request to initiate a recovery instruction to the target request module after the data to be written has been written into the external device, so that the target request module initiates a new data writing request when necessary.

9. The arbitration circuit according to claim 2, characterized in that: Also includes: Data cache module; The data cache module is used to store the data read by the DMA module from the target data storage module; The DMA module reads the data to be written from the target data storage module and writes the data to the external device, including: The DMA module determines data corresponding to the starting address of the data to be written in the target data storage module, and sequentially obtains the data and subsequent data starting from the determined data and stores them in the data cache module until the length of the obtained data is equal to the length of the data to be written; The DMA module writes the data stored in the data cache module into the external device.

10. A write request arbitration method, characterized in that: Applied to the arbitration circuit according to any one of claims 1 to 9, the method comprises: Each request module initiates a data write request; Each request storage module stores the data write request initiated by all request modules in the corresponding request channel; wherein the data write request carries at least control write information corresponding to the data to be written; The arbitrator arbitrates all request channels with data write requests to obtain the target request channel to which the data write request to be responded to belongs; The DMA module obtains a data write request in a target request storage module corresponding to the target request channel, determines a target data storage module for storing the data to be written in the corresponding request module according to control write information carried by the obtained data write request, and reads the data to be written from the target data storage module and writes it into the external device; wherein the control write information includes: identification information of the data storage module to which the data to be written belongs.

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