Memory and module equipment

Abstract

The invention discloses a memory and module equipment. The memory comprises K groups of memory modules, each group of memory modules comprises at least two sub-memory modules which are adjacently arranged, and each sub-memory module comprises a memory array, a first-stage amplifier, a local data line and a selection unit which are connected in sequence; wherein in each group of storage modules, the local data lines of the at least two sub-storage modules are connected in a penetrating manner so as to be shared, and the selection units of the at least two sub-storage modules are arranged in adjacent areas between the sub-storage modules. According to the invention, the requirements of reducing prefetch and ensuring speed of the memory are considered.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a memory and a module device. Background Art

[0002] With the development of various electronic products, the performance requirements for memory are getting higher and higher. The data reading and writing speed is one of the important performance parameters of memory.

[0003] In some cases where it is necessary to reduce memory prefetching, it is often difficult to balance the reduction of prefetching with the control of data transmission delay, which has an adverse effect on the data reading and writing speed of the memory. Summary of the invention

[0004] In view of the above problems, the present invention is proposed to provide a memory and module device that overcomes the above problems or at least partially solves the above problems.

[0005] In a first aspect, a memory is provided, comprising:

[0006] K groups of storage modules, each group of storage modules includes at least two adjacent sub-storage modules, each of which includes a storage array, a first-stage amplifier, a local data line, and a selection unit connected in sequence;

[0007] In each group of the storage modules, the local data lines of the at least two sub-storage modules are connected through and shared, and the selection units of the at least two sub-storage modules are arranged in adjacent areas between the sub-storage modules.

[0008] Optionally, in each group of the storage modules, any first-stage amplifier is connected to the selection units of the at least two sub-storage modules.

[0009] Optionally, in each group of the storage modules, the maximum transmission delay of data from the first-stage amplifier to the selection unit is less than or equal to the difference between the total delay of the local data line and the first-segment delay; wherein the total delay of the local data line is the delay of data crossing all the first-stage amplifiers sharing the local data line along the direction from the first-stage amplifier to the selection unit; and the first-segment delay is the delay of data crossing a single first-stage amplifier along the direction from the first-stage amplifier to the selection unit.

[0010] Optionally, in each group of the storage modules: the number of the sub-storage modules is 2; the local data lines of two of the sub-storage modules are connected through, so that any one of the first-stage amplifiers is connected to the selection units of both of the sub-storage modules; and the selection units of the two sub-storage modules are arranged in an adjacent area between the two sub-storage modules.

[0011] Optionally, in each group of the storage modules, the maximum transmission delay of data from the first-stage amplifier to the selection unit is less than or equal to a first-stage delay; wherein the first-stage delay is the delay of data crossing a single first-stage amplifier in the direction from the first-stage amplifier to the selection unit.

[0012] Optionally, each group of the storage modules further includes: a main data line and a second-stage amplifier, the selection units are connected to the second-stage amplifier via the main data line, and the second-stage amplifier is connected to the input and output channels of the memory to transmit data.

[0013] Optionally, in each group of the storage modules, the number of the sub-storage modules is A, and the second-stage amplifiers are divided into A groups, where A is an integer greater than 1; wherein the second-stage amplifiers in group A are connected one-to-one with the selection units of A sub-storage modules, and wherein each group of the second-stage amplifiers corresponds to the sub-storage module that is closest to it.

[0014] Optionally, each of the sub-storage modules includes two first-stage amplifiers, namely an odd amplifier and an even amplifier, and the two first-stage amplifiers are respectively located on both sides of the storage array and are respectively connected to the corresponding selection units via the local data lines; wherein, in each group of the storage modules, the local data lines of the odd amplifiers of the at least two sub-storage modules are connected through and shared, and the local data lines of the even amplifiers of the at least two sub-storage modules are connected through and shared; wherein, in each group of the storage modules, the selection units connected to the odd amplifiers are all arranged in adjacent areas between the odd amplifiers; and the selection units connected to the even amplifiers are all arranged in adjacent areas between the even amplifiers.

[0015] Optionally, each group of the storage modules further includes: a main data line and a second-stage amplifier, and the selection units are connected to the second-stage amplifier through the main data line; in each group of the storage modules, the number of the sub-storage modules is A, including a total of 2*A first-stage amplifiers, and the second-stage amplifiers are divided into 2*A groups, and A is an integer greater than 1; wherein, the 2*A groups of the second-stage amplifiers are connected to the 2*A first-stage amplifiers in a one-to-one correspondence through the selection units; wherein, each group of the second-stage amplifiers corresponds to the first-stage amplifier that is closest to it.

[0016] In a second aspect, a module device is provided, which includes a communication module, a power module and a storage module, wherein: the power module is used to provide power to the module device; the storage module is used to store data and instructions; the communication module is used for internal communication within the module device, or for the module device to communicate with external devices; the storage module includes any memory described in the first aspect.

[0017] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages:

[0018] The memory and module device provided by the embodiment of the present invention are arranged in each group of storage modules, and the local data lines of multiple sub-storage modules are connected through, so that the first-stage amplifiers in each sub-storage module share the local data lines with each other, thereby reducing the pre-fetch by increasing the load of the local data lines while maintaining the number of word lines in the first-stage amplifier unchanged. In addition, the selection units of the multiple sub-storage modules that share the local data lines are all arranged in the adjacent areas between the sub-storage modules, thereby avoiding the situation where the data transmission of the remote storage unit needs to cross all the first-stage amplifiers to reach the selection unit, effectively reducing the delay on the data transmission path and improving the speed of data reading and writing.

[0019] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0021] Figure 1 A schematic diagram of the structure of an existing memory in an embodiment of the present invention;

[0022] Figure 2 In the embodiment of the present invention Figure 1 Enlarged schematic diagram of the middle ellipse area;

[0023] Figure 3 A schematic diagram of a memory structure provided in an embodiment of the present invention Figure 1 ;

[0024] Figure 4 A schematic diagram of a memory structure provided in an embodiment of the present invention Figure 2 ;

[0025] Figure 5 A schematic diagram of a memory structure provided in an embodiment of the present invention Figure 3 ;

[0026] Figure 6 A schematic diagram of a memory structure provided in an embodiment of the present invention Figure 4 ;

[0027] Figure 7 A schematic diagram of a memory structure provided in an embodiment of the present invention Figure 5 ;

[0028] Figure 8 A schematic diagram of a memory structure provided in an embodiment of the present invention Figure 6 ;

[0029] Fig. 9 A schematic diagram of the structure of a module device is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0031] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0032] See also Figure 1, which is a schematic diagram of the structure of an existing memory. The memory array 1 of the memory is controlled by the bit line (WL) and the word line (BL). Among them, the word line (BL) of the memory array 1 is connected to the second stage amplifier (SSA) 6 through the first stage amplifier (SA) 2, the local data line (LDQ) 3, the selection unit (SWITCH) 4 and the main data line (MDQ) 5 in sequence. The first stage amplifier (SA) 2 is mainly responsible for the first stage amplification of the data, and the second stage amplifier (SSA) 6 is mainly responsible for the second stage amplification of the data, and transmits the data to the input and output circuit (I / O) and the calculation unit on the logic chip and other logical functional units through the read and write data line (RWDL).

[0033] See also Figure 2 ,for Figure 1 Enlarged schematic diagram of the elliptical area in the middle. When the WL of the storage cell in the storage array 1 is turned on, the charge in the capacitor is shared with the charge of BL to change the voltage of BL. After the BL voltage is amplified by the first-stage amplifier 2, the data is transmitted to the second-stage amplifier 6 for amplification through the local data line 3, the selection unit 4, and the main data line 5 in sequence, and finally the data is sent to the input and output circuit.

[0034] Figure 2 The elliptical trajectory in the middle represents the transmission path of the data of the farthest storage unit from BL to the second-stage amplifier 6 (i.e., the farthest transmission path), and the arrow in the dotted line is the direction of data flow. The delay of the data of the farthest storage unit on the transmission path from BL to the second-stage amplifier 6 is the sum of the first delay T1, the second delay T2, and the third delay T3, wherein T1 is the delay of the data crossing a single first-stage amplifier 2 along the direction from the first-stage amplifier 2 to the selection unit 4, i.e., the maximum delay from BL to the selection unit 4 (according to the conventional layout, T1 is the maximum load delay of the LDQ parallel to the WL direction). T2 is the delay of data transmission on the main data line 5 (according to the conventional layout, T2 is the metal line delay of the MDQ parallel to the BL direction). T3 is the maximum delay of data transmission in the layout area of ​​the second-stage amplifier 6 (according to the conventional layout, T3 is the maximum delay of the metal line parallel to the WL direction).

[0035] See also Figure 3 The present application provides a memory, comprising: K groups of storage modules 301, each group of storage modules 301 comprising at least two adjacent sub-storage modules 302, each sub-storage module 302 comprising a storage array 1, a first-stage amplifier 2, a local data line 3 and a selection unit 4 connected in sequence; wherein, in each group of storage modules 301, the local data lines 3 of the at least two sub-storage modules 302 are connected through for sharing, and the selection units 4 of the at least two sub-storage modules 302 are all arranged in adjacent areas between the sub-storage modules 302.

[0036] Specifically, in the case where the memory prefetch needs to be reduced (for example, the prefetch of LDDR3 X32 mode is 8*N, and the prefetch of LPDDR2 X32 mode is 4*N, where N is the number of data pins), in each group of storage modules 301, local data lines 3 of multiple sub-storage modules 302 are set to be connected through, so that the first-stage amplifiers 2 in each sub-storage module 302 share the local data lines 3, thereby reducing the prefetch by increasing the load of the local data lines 3 while maintaining the number of word lines in the first-stage amplifier 2 unchanged. Assuming that the prefetch when the sub-storage modules 302 do not share the local data lines is M, then if there are A sub-storage modules 302 in each group of storage modules 301, A is an integer greater than 1, and the local data lines 3 of the A sub-storage modules 302 are connected through for sharing, then the prefetch is That is, when A is equal to 2, the prefetch is When A is equal to 4, the prefetch is

[0037] It should be noted that the local data lines 3 between the sub-storage modules 302 are connected through each other, so that in each group of storage modules 301, any first-stage amplifier 2 is connected to the selection units 4 of all sub-storage modules 302 that share the local data line 3. In other words, the transmission path of the data of the farthest storage unit from the BL to the selection unit 4 may span multiple sub-storage modules 302, resulting in a longer delay in this part.

[0038] See also Figure 4 , Figure 4 The elliptical trajectory in the middle represents the transmission path of the data of the farthest storage unit from BL to the second-stage amplifier 6 (i.e., the farthest transmission path), and the arrow in the dotted line is the direction of data flow. It can be seen that if the setting position of the selection unit 4 is not improved and it is set on the same side of the first-stage amplifier 302, the delay of the data transmission path of the farthest storage unit will be increased. Taking the number of sub-storage modules 302 in each group of storage modules 301 as 2 as an example, for the farthest storage unit, the delay on the transmission path of its data from BL to the second-stage amplifier 6 is 2*T1+T2+2*T3, where T1 is the aforementioned first delay, T2 is the aforementioned second delay, and T3 is the aforementioned third delay, which is specifically related to Figure 2The T1, T2 and T3 marked in are the same. It can be seen that when two sub-storage modules 302 share the local data line 3, although pre-fetching can be reduced, since the data may cross multiple first-stage amplifiers 2 to reach the selection unit 4, the maximum delay of data transmission from BL to the selection unit 4 will be increased by at least 2*T1. In addition, due to the reduction of pre-fetching, the same number of second-stage amplifiers 6 need to be arranged in the areas of multiple sub-storage modules 302, so the gaps between the second-stage amplifiers 6 will be increased, which will also cause the maximum delay of data transmission in the arrangement area of ​​the second-stage amplifiers 6 to increase to 2*T3.

[0039] See also Figure 5 In the present application, the selection units 4 of the multiple sub-storage modules 302 that share the local data line 3 are all arranged in the adjacent areas between the sub-storage modules 302, thereby avoiding the situation where the data transmission of the remote storage unit needs to cross the first-stage amplifier 2 of all the shared local data lines 3 before reaching the selection unit 4, effectively reducing the delay on the data transmission path and improving the speed of data reading and writing.

[0040] Specifically, using the solution provided by the present application, in each group of storage modules 301, the maximum transmission delay of data from the first-stage amplifier 2 to the selection unit 4 is less than or equal to the difference between the total delay on the local data line 4 and the first-segment delay. The total delay of the local data line is the delay of the data crossing all the first-stage amplifiers 2 that share the local data line 4 in the storage module 302 along the direction from the first-stage amplifier 2 to the selection unit 4. The first-segment delay is the delay of the data crossing a single first-stage amplifier 2 along the direction from the first-stage amplifier 2 to the selection unit 4. In other words, since the selection units 4 are all set in the adjacent areas between the sub-storage modules 302, for the farthest storage unit, its data does not need to cross all the first-stage amplifiers 2 that share the local data line 4 when it goes from BL to the selection unit 4, compared with Figure 4 The solution can at least reduce the delay across a first-stage amplifier 2, that is, it can at least reduce the delay of T1.

[0041] For example, Figure 5As shown, it is assumed that the number of sub-storage modules 302 in each group of storage modules 301 is 2. The local data lines 3 of the two sub-storage modules 302 are connected through, so that any first-stage amplifier 2 is connected to the selection units 4 of the two sub-storage modules 302. And the selection units 4 of the two sub-storage modules 302 are both arranged in the adjacent area between the two sub-storage modules 302. In this way, placing the two selection units 4 in the middle of the two first-stage amplifiers 2 on the layout can optimize the delay on the data transmission path. Specifically, after the improvement, in each group of storage modules 302, the maximum transmission delay of data from the first-stage amplifier 2 to the selection unit 4 is less than or equal to the first delay. Among them, the first delay is the delay of the data crossing a single first-stage amplifier 2 along the direction from the first-stage amplifier 2 to the selection unit 4, that is, T1. It can be seen that compared to Figure 4 According to the scheme, the maximum transmission delay of data from the first-stage amplifier 2 to the selection unit 4 is reduced from 2*T1 to T1.

[0042] In an alternative embodiment, if Figure 5 As shown, each group of storage modules 301 also includes: a main data line 5 and a second-stage amplifier 6, and the selection unit 4 is connected to the second-stage amplifier 6 through the main data line 5, and the second-stage amplifier 6 is connected to the input and output channels of the memory to transmit data. After adopting the solution provided by the present application, taking the number of sub-storage modules 302 in each group of storage modules 301 as 2 as an example, for the farthest storage unit, the delay of its data on the transmission path from BL to the second-stage amplifier 6 is T1+T2+2*T3, where T1 is the aforementioned first delay, T2 is the aforementioned second delay, and T3 is the aforementioned third delay, which is specifically related to Figure 2 The T1, T2 and T3 in the figure are the same. Figure 4 The solution can reduce the delay of T1.

[0043] In an optional implementation, the second-stage amplifiers 6 can also be grouped to reduce delay. That is, it can be set that in each group of storage modules 301, the number of sub-storage modules 302 is A (each sub-storage module 302 has a selection unit, and there are A selection units in total), and the corresponding second-stage amplifiers 6 are also divided into A groups, where A is an integer greater than 1. Among them, A groups of second-stage amplifiers 6 are connected to A selection units 4 in a one-to-one correspondence, and each group of second-stage amplifiers 6 corresponds to the sub-storage module 302 that is closest to it. For example, Figure 5 As shown, the second-stage amplifier 6 on the lower right side is connected to the selection unit 4 of the sub-storage module 302 on the lower left side, and the second-stage amplifier 6 on the upper right side is connected to the selection unit 4 of the sub-storage module 302 on the upper left side. In this way, data will only be transmitted to the group of second-stage amplifiers 6 that are closest to it, and will not cross to other second-stage amplifiers 6 in more distant areas, thereby further reducing transmission delay.

[0044] In an optional embodiment, the number A of sub-storage modules 302 included in each group of storage modules 301 can be an even number such as 2, 4 or 6, which is not limited here. Figure 3 The layout shown can be used when A is equal to 4 Figure 6 The layout shown only requires that the selection units 4 that share the local data lines 3 are all arranged in adjacent areas between the sub-storage modules 302 .

[0045] In an optional embodiment, the connection between the storage array 1 and the first-stage amplifier 2 in the memory may also have an open bitline structure, in which the input end of the first-stage amplifier 2 comes from two different storage arrays 1, and one storage array 1 is connected to two first-stage amplifiers 2 located on the left and right sides, respectively. That is, each sub-storage module 302 includes two first-stage amplifiers 2, namely an odd-numbered amplifier 21 and an even-numbered amplifier 22, and the two first-stage amplifiers 2 are located on both sides of the storage array 1, and are connected to the corresponding selection units 4 via the local data lines 3, respectively.

[0046] Specific as Figure 7 As shown, Figure 7 The elliptical track in the middle represents the transmission path (i.e., the farthest transmission path) of the data of the farthest storage unit from BL to the second-stage amplifier 6, the dotted arrow is the data flow direction of the odd amplifier 21, and the solid arrow is the data flow direction of the even amplifier 22. In each group of storage modules 301, the local data lines 3 of the odd amplifiers 21 of multiple sub-storage modules 302 are connected through and shared, and the local data lines 3 of the even amplifiers 22 of multiple sub-storage modules 302 are connected through and shared. In addition, in each group of storage modules 301, the selection units 4 connected to the odd amplifiers 21 are all arranged in the adjacent areas between the odd amplifiers 21; the selection units 4 connected to the even amplifiers 22 are all arranged in the adjacent areas between the even amplifiers 22. In this way, the selection units 4 are all set in the adjacent areas between the corresponding odd amplifiers 21 or even amplifiers 22. For the farthest storage unit, its data does not need to cross all the odd amplifiers 21 or even amplifiers 22 that share the local data line 4 when it goes from BL to the selection unit 4. Compared with the conventional solution of setting the selection units on the same side, at least the delay across an odd amplifier 21 or even amplifier 22 can be reduced, that is, at least the delay of T1 can be reduced.

[0047] In an optional implementation scheme, for the open bitline structure, similarly, each group of storage modules 301 also includes: a main data line 5 and a second-stage amplifier 6, the selection unit 4 is connected to the second-stage amplifier 6 through the main data line 5, and the second-stage amplifier 6 is connected to the input and output channels of the memory to transmit data. Further, the second-stage amplifier 6 can also be grouped to reduce delay. That is, it can be set in each group of storage modules 301 that the number of sub-storage modules 302 is A, and each sub-storage module 302 has 2 first-stage amplifiers 2, then each group of storage modules 301 has a total of 2*A first-stage amplifiers 2, and A is an integer greater than 1. Correspondingly, the second-stage amplifier 6 is also divided into 2*A groups. Among them, 2*A groups of second-stage amplifiers 6 are connected to 2*A first-stage amplifiers 2 through the selection unit in a one-to-one correspondence, and each group of second-stage amplifiers 6 corresponds to the nearest first-stage amplifier 2. In this way, data will only be transmitted to the group of second-stage amplifiers 6 that is closest, and will not cross to other second-stage amplifiers 6 in more distant areas, further reducing transmission delay.

[0048] For example, Figure 8 As shown, it is assumed that the number of sub-storage modules 302 in each group of storage modules 301 is 2. The second-stage amplifier 6 marked with a is connected to the selection unit 4 corresponding to the odd-numbered amplifier 21 marked with a, the second-stage amplifier 6 marked with b is connected to the selection unit 4 corresponding to the odd-numbered amplifier 21 marked with b, the second-stage amplifier 6 marked with c is connected to the selection unit 4 corresponding to the even-numbered amplifier 22 marked with c, and the second-stage amplifier 6 marked with d is connected to the selection unit 4 corresponding to the even-numbered amplifier 22 marked with d.

[0049] Based on the same inventive concept, the embodiment of the present invention further provides a module device 900, such as Fig. 9 As shown, the module device 900 includes a communication module 901, a power module 902 and a storage module 903, wherein: the power module 902 is used to provide power to the module device; the storage module 903 is used to store data and instructions; the communication module 901 is used for internal communication of the module device, or for the module device to communicate with external devices; the storage module 903 includes any memory provided by the embodiments of the present invention.

[0050] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages:

[0051] The memory and module device provided by the embodiment of the present invention are arranged in each group of storage modules, and the local data lines of multiple sub-storage modules are connected through, so that the first-stage amplifiers in each sub-storage module share the local data lines with each other, thereby reducing the pre-fetch by increasing the load of the local data lines while maintaining the number of word lines in the first-stage amplifier unchanged. In addition, the selection units of the multiple sub-storage modules that share the local data lines are all arranged in the adjacent areas between the sub-storage modules, thereby avoiding the situation where the data transmission of the remote storage unit needs to cross all the first-stage amplifiers to reach the selection unit, effectively reducing the delay on the data transmission path and improving the speed of data reading and writing.

[0052] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the description of the above specific languages ​​is for disclosing the best mode of the present invention.

[0053] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0054] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the intention that the claimed invention requires more features than those explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0055] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0056] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0057] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "one" or "an" preceding a component does not exclude the presence of a plurality of such components. The present invention may be implemented by means of hardware comprising a number of different components and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

Claims

1. A memory, characterized in that: include: K groups of storage modules, each group of storage modules includes at least two adjacent sub-storage modules, each of which includes a storage array, a first-stage amplifier, a local data line, and a selection unit connected in sequence; In each group of the storage modules, the local data lines of the at least two sub-storage modules are connected through and shared, and the selection units of the at least two sub-storage modules are arranged in adjacent areas between the sub-storage modules.

2. The memory according to claim 1, wherein: In each group of the storage modules, any first-stage amplifier is connected to the selection units of the at least two sub-storage modules.

3. The memory according to claim 1, wherein: In each group of the storage modules, the maximum transmission delay of data from the first-stage amplifier to the selection unit is less than or equal to the difference between the total delay of the local data line and the first-stage delay; Among them, the total delay of the local data line is the delay of data crossing all the first-stage amplifiers sharing the local data line along the direction from the first-stage amplifier to the selection unit; the first-segment delay is the delay of data crossing a single first-stage amplifier along the direction from the first-stage amplifier to the selection unit.

4. The memory according to claim 1, wherein: In each set of said storage modules: The number of the sub-storage modules is 2; The local data lines of the two sub-storage modules are connected through, so that any one of the first-stage amplifiers is connected to the selection units of the two sub-storage modules; The selection units of the two sub-storage modules are both arranged in an adjacent area between the two sub-storage modules.

5. The memory according to claim 4, wherein: In each group of the storage modules, the maximum transmission delay of data from the first-stage amplifier to the selection unit is less than or equal to the first delay; The first delay is the delay of data crossing a single first-stage amplifier in the direction from the first-stage amplifier to the selection unit.

6. The memory according to claim 1, wherein: Each group of storage modules also includes: A main data line and a second-stage amplifier, the selection units are connected to the second-stage amplifier through the main data line, and the second-stage amplifier is connected to the input and output channels of the memory to transmit data.

7. The memory according to claim 6, wherein: In each group of the storage modules, the number of the sub-storage modules is A, the second-stage amplifiers are divided into A groups, and A is an integer greater than 1; A groups of the second-stage amplifiers are connected to the selection units of A sub-storage modules in a one-to-one correspondence, and each group of the second-stage amplifiers corresponds to the sub-storage module that is closest to it.

8. The memory according to claim 1, wherein: Each of the sub-storage modules comprises two first-stage amplifiers, namely an odd-number amplifier and an even-number amplifier, the two first-stage amplifiers are respectively located at two sides of the storage array and are respectively connected to the corresponding selection units via the local data lines; Wherein, in each group of the storage modules, the local data lines of the odd-numbered amplifiers of the at least two sub-storage modules are connected through and shared, and the local data lines of the even-numbered amplifiers of the at least two sub-storage modules are connected through and shared; Wherein, in each group of the storage modules, the selection units connected to the odd amplifiers are all arranged in adjacent regions between the odd amplifiers; and the selection units connected to the even amplifiers are all arranged in adjacent regions between the even amplifiers.

9. The memory according to claim 8, wherein: Each group of the storage modules further includes: a main data line and a second-stage amplifier, and the selection units are connected to the second-stage amplifier via the main data line; In each group of the storage modules, the number of the sub-storage modules is A, including 2*A first-stage amplifiers in total, and the second-stage amplifiers are divided into 2*A groups, where A is an integer greater than 1; Among them, 2*A groups of the second-stage amplifiers are connected to 2*A first-stage amplifiers in a one-to-one correspondence through the selection unit; and each group of the second-stage amplifiers corresponds to the first-stage amplifier that is closest to it.

10. A module device, characterized in that: The module device includes a communication module, a power module and a storage module, wherein: the power module is used to provide power to the module device; the storage module is used to store data and instructions; the communication module is used for internal communication within the module device, or for the module device to communicate with external devices; the storage module includes the memory described in any one of claims 1 to 9.

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