Memory system and operating method thereof, computer readable storage medium
By setting up user-space storage blocks as write-accelerated caches in the memory system and expanding the cache capacity using free storage blocks in hidden space, the problem of limited write performance is solved, achieving more efficient write acceleration and wear leveling.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2023-10-26
- Publication Date
- 2026-05-26
Smart Images
Figure CN119902690B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the semiconductor field, and includes, but is not limited to, a memory system and its operation method, and a computer-readable storage medium. Background Technology
[0002] Memory controllers and memory can be integrated into various types of storage devices, such as solid-state drives (SSDs), universal flash storage (UFS), and embedded multi-media cards (eMMC). The memory controller controls the operation of the memory, such as reading, writing, or erasing.
[0003] With the increase in memory integration and bit density, more data can be stored in memory. However, there is still considerable room for improvement in memory performance, especially write performance. Summary of the Invention
[0004] This disclosure provides a memory system and its operation method, as well as a computer-readable storage medium.
[0005] According to a first aspect of the present disclosure, a memory system is provided, comprising:
[0006] The memory, whose physical space is divided into user space and hidden space;
[0007] A memory controller, coupled to the memory, is configured to:
[0008] The first storage block of the user space is set as a write acceleration cache; wherein, the first storage block is in the first-level storage unit mode; the write acceleration cache is configured to cache data;
[0009] The free storage block of the hidden space is set as the write acceleration cache area; wherein the free storage block is the first level storage unit mode.
[0010] In some embodiments, the hidden space includes a reserved subspace for garbage collection; the memory controller is specifically configured to:
[0011] Set the free storage block of the reserved subspace as the write acceleration cache area.
[0012] In some embodiments, the memory controller is further configured to:
[0013] When the hidden space needs to use the free storage block of the reserved subspace, the free storage block occupied by the write acceleration cache is returned to the reserved subspace.
[0014] In some embodiments, the memory controller is specifically configured to:
[0015] The data cached in the free storage block occupied by the write acceleration cache is written to the second storage block in the user space; wherein, the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode;
[0016] After writing the data cached in the free storage block into the second storage block, the free storage block is erased, so that the free storage block is returned to the reserved subspace.
[0017] In some embodiments, the hidden space needs to use the free storage block of the reserved subspace in at least one of the following situations: the available capacity of the hidden space is less than or equal to the preset capacity, or garbage collection.
[0018] In some embodiments, the memory controller is further configured to:
[0019] When the number of erase / write cycles of the free storage block in the hidden space is greater than or equal to a preset value, the setting of the free storage block in the hidden space as the write acceleration cache area is stopped.
[0020] In some embodiments, the memory controller is further configured to:
[0021] When the number of erase / write cycles of the free storage block in the hidden space is greater than or equal to a preset value, the data to be cached in the free storage block is cached in the first storage block.
[0022] In some embodiments, the memory controller is specifically configured to:
[0023] The physical addresses of the free storage block and the first storage block are swapped.
[0024] In some embodiments, the memory controller is further configured to:
[0025] The data cached in the first storage block is written to the second storage block in the user space; wherein the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode.
[0026] After writing the data cached in the first storage block to the second storage block, the first storage block is erased.
[0027] In some embodiments, the memory controller is further configured to:
[0028] Set the first storage block in the user space to the first-level storage unit mode;
[0029] Set the storage block of the hidden space to the first-level storage unit mode;
[0030] The second storage block of the user space is set to a second-level storage unit mode; wherein the second storage block is configured to store the data.
[0031] In some embodiments, the memory system includes: a solid-state drive, an embedded multimedia card, and general-purpose flash memory.
[0032] According to a second aspect of the present disclosure, a method for operating a memory system is provided, the memory system including a memory and a memory controller coupled to the memory, wherein the physical space of the memory is divided into a user space and a hidden space; the method includes:
[0033] The first storage block of the user space is set as a write acceleration cache; wherein, the first storage block is in the first-level storage unit mode; the write acceleration cache is configured to cache data;
[0034] The free storage block of the hidden space is set as the write acceleration cache area; wherein the free storage block is the first level storage unit mode.
[0035] In some embodiments, the hidden space includes a reserved subspace for waste recycling;
[0036] Setting the free storage block of the hidden space as the write acceleration cache includes:
[0037] Set the free storage block of the reserved subspace as the write acceleration cache area.
[0038] In some embodiments, the operating method further includes:
[0039] When the hidden space needs to use the free storage block of the reserved subspace, the free storage block occupied by the write acceleration cache is returned to the reserved subspace.
[0040] In some embodiments, returning the free storage block occupied by the write acceleration cache to the reserved subspace includes:
[0041] The data cached in the free storage block occupied by the write acceleration cache is written to the second storage block in the user space; wherein, the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode;
[0042] After writing the data cached in the free storage block into the second storage block, the free storage block is erased, so that the free storage block is returned to the reserved subspace.
[0043] In some embodiments, the operating method further includes:
[0044] When the number of erase / write cycles of the free storage block in the hidden space is greater than or equal to a preset value, the setting of the free storage block in the hidden space as the write acceleration cache area is stopped.
[0045] In some embodiments, the operating method further includes:
[0046] When the number of erase / write cycles of the free storage block in the hidden space is greater than or equal to a preset value, the data to be cached in the free storage block is cached in the first storage block.
[0047] In some embodiments, caching the data to be cached in the free storage block to the first storage block includes:
[0048] The physical addresses of the free storage block and the first storage block are swapped.
[0049] In some embodiments, the operating method further includes:
[0050] Set the first storage block in the user space to the first-level storage unit mode;
[0051] Set the storage block of the hidden space to the first-level storage unit mode;
[0052] The second storage block of the user space is set to a second-level storage unit mode; wherein the second storage block is configured to store the data.
[0053] According to a third aspect of the present disclosure, a computer-readable storage medium is provided, wherein instructions are stored on the computer-readable storage medium, and when executed, the instructions implement the operation method as described in any embodiment of the second aspect of the present disclosure.
[0054] In this embodiment of the disclosure, by setting the first storage block of the user space as the write acceleration cache, the write speed can be improved; by setting the free storage block of the hidden space as the write acceleration cache, the capacity of the write acceleration cache can be increased; and even in dirty scenarios, the write acceleration cache can still use the free storage block of the hidden space, which is beneficial to improving the write performance in dirty scenarios. Attached Figure Description
[0055] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.
[0056] Figure 1 This is a schematic diagram of a system according to an embodiment of the present disclosure;
[0057] Figure 2a This is a schematic diagram of a memory card according to an embodiment of the present disclosure;
[0058] Figure 2b This is a schematic diagram of a solid-state drive according to an embodiment of the present disclosure;
[0059] Figure 3 This is a schematic diagram of the physical space of a memory according to an embodiment of the present disclosure. Figure 1 ;
[0060] Figure 4 This is a second schematic diagram of the physical space of a memory according to an embodiment of the present disclosure;
[0061] Figure 5 This is a flowchart illustrating an operation method of a memory system according to an embodiment of the present disclosure. Detailed Implementation
[0062] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.
[0063] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.
[0064] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.
[0065] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0066] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.
[0067] Figure 1 This is a schematic diagram illustrating a system 100 according to an embodiment of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.
[0068] Memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital Memory Card (SD Card), Compact Flash Card (CF Card), Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments in solid state disks (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.
[0069] The memory controller 106 can be configured to control the operation of the memory 104, such as read, write, and erase operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with a host (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCIE), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced System Device Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.
[0070] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a general-purpose flash memory package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Reduced-Size MMC (RS-MMC), a Multimedia Card Micro (MMCmicro), an SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108 is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202. The memory 104 may include volatile and non-volatile memory, such as NAND flash memory, dynamic random access memory, ferroelectric random access memory, magnetic random access memory, phase-change random access memory, resistive random access memory, nano-random access memory, etc.
[0071] Figure 3 This is a schematic diagram of the physical space of a memory 300 according to an embodiment of the present disclosure. Figure 1 . Reference Figure 3 As shown, the physical space of memory 300 can be divided into user space 310 and hidden space 320; user space 310 is used to store data, and hidden space 320 is used to store parameter information or status information of user space 310. Both user space 310 and hidden space 320 need to reserve a certain number of storage blocks for garbage collection operations. The space formed by the reserved storage blocks is called the reserved subspace (Over Provisioning, OP). For example, Figure 3The diagram shows the reserved subspace 311 of user space 310 and the reserved subspace 321 of hidden space 320. Here, the number of storage blocks in the reserved subspace can be one or more, and this disclosure does not impose any special restrictions on this. In practical applications, the capacity of the reserved subspace is generally calculated and cannot be arbitrarily changed; for example, decreasing the capacity of the reserved subspace 321 of hidden space 320 to increase the capacity of the reserved subspace 311 of user space 310, etc.
[0072] To improve the write performance of the storage device, a portion of the storage blocks in user space 310 can be configured as a write booster cache 330. For example, the storage cells of a portion of the storage blocks in user space 310 can be configured in Single-Level Cell mode and used for data caching. The capacity of the write booster cache 330 is closely related to write performance, and the larger the capacity of the write booster cache 330 that a manufacturer's product can provide, the more competitive it will undoubtedly be in the market.
[0073] However, the capacity of the write acceleration cache 330 is limited by the capacity of the user space 310. The capacity of the write acceleration cache 330 will decrease as the available capacity of the user space 310 decreases. Specifically, the capacity of the write acceleration cache 330 is derived from the user space 310. To prevent the write acceleration cache 330 from consuming SLC mode storage blocks too quickly, a threshold line is usually set, such as... Figure 3 As shown by the dashed line, when the write acceleration cache 330 is in a dirty scenario—for example, when the available storage blocks in the write acceleration cache 330 drop to a threshold—the capacity of the write acceleration cache 330 will become zero. Subsequent storage blocks will be in a multi-level storage cell mode, such as a triple-level cell (TLC) mode. In this case, the write speed will significantly slow down, and write performance will degrade. Therefore, increasing the capacity of the write acceleration cache to improve write performance has become a pressing technical problem.
[0074] Based on this, in order to solve one or more of the above-mentioned technical problems, this disclosure provides a memory system.
[0075] Figure 4 This is a second schematic diagram of the physical space of a memory 400 according to an embodiment of this disclosure. The following will be combined with... Figure 4 The memory system provided in the embodiments of this disclosure will be described. (Refer to...) Figure 4 As shown, the memory system includes:
[0076] The memory 400 has its physical space divided into user space 410 and hidden space 420.
[0077] The memory controller, coupled to the memory 400, is configured as follows:
[0078] The first storage block of user space 410 is set as write acceleration cache 430; wherein, the first storage block is in first-level storage unit mode; and write acceleration cache 430 is configured to cache data.
[0079] Set the free storage block of hidden space 420 as write acceleration cache 430; where the free storage block is in first-level storage unit mode.
[0080] Memory systems include solid-state drives (SSDs), general-purpose flash memory, and embedded multimedia cards. For details on the specific structure and composition of memory systems, please refer to the aforementioned section. Figure 1 , Figure 2a , Figure 2b The details of the memory system are described in detail above, and other details are similar to those described above, so for the sake of brevity, they will not be repeated here.
[0081] The memory 400 includes SLC memory, MLC (Multi-Level Cell) memory, TLC (Trinary-Level Cell) memory, or QLC (Quad-Level Cell) memory, etc.; wherein, one storage cell of SLC memory stores one bit, one storage cell of MLC memory stores two bits, one storage cell of TLC memory stores three bits, and one storage cell of QLC memory stores four bits. For ease of understanding, this disclosure will use TLC memory as an example for explanation.
[0082] The memory 400 includes multiple memory blocks, each memory block includes multiple memory pages, and each memory page includes multiple memory cells. Taking NAND flash memory as an example, the smallest unit for performing an erase operation in NAND flash memory is a memory block, and the smallest unit for performing a write operation in NAND flash memory is a memory page. In practical applications, the multiple memory blocks can be partitioned. Specifically, the physical space corresponding to the multiple memory blocks can be divided into user space 410 and hidden space 420. User space 410 is used to store data, and hidden space 420 is used to store parameter information or status information of user space 410.
[0083] The memory controller is coupled to and can control the memory 400. More specifically, the memory controller may include a processor for controlling the overall operation of the memory controller. The processor can drive firmware to control the overall operation of the memory controller to implement various functions of the memory controller, such as bad block management, garbage collection, logical-to-physical address translation, wear leveling, and data error correction. The processor can also manage and maintain multiple memory blocks in the memory 400. For example, the firmware manages free memory blocks through arrays or block bitmaps. In this example, the firmware may be stored in the memory controller or in the memory. When the firmware is stored in the memory, it may be loaded into the memory controller upon power-up.
[0084] The memory controller sets the first storage block of user space 410 as the write acceleration cache 430 and the free storage block of hidden space 420 as the write acceleration cache 430. Both the first storage block and the free storage block are in first-level memory cell mode, thus increasing the capacity of the write acceleration cache 430. Here, the first-level memory cell mode includes SLC mode, MLC mode, or TLC mode, etc. For example, when memory 400 is TLC memory, the first-level memory cell mode can be SLC mode or MLC mode. In this example, at least a portion of the first storage block of the reserved subspace 411 of user space 410 can be set as the write acceleration cache 430.
[0085] It should be noted that the first storage block and the free storage block can be set as the write acceleration cache 430 simultaneously, or sequentially; this disclosure does not impose any special restrictions on this. The number of free storage blocks in the hidden space 420 set as the write acceleration cache 430 can be one or more. In practical applications, the number of free storage blocks set as the write acceleration cache 430 can be dynamically adjusted according to the current capacity of the write acceleration cache 430 and / or the current size of the data to be written to the user space 410.
[0086] In one specific embodiment, the first-level storage unit mode is SLC mode, and the write acceleration cache 430 is an SLC cache. The SLC cache is used for temporary or permanent data caching. By setting a portion of the memory's storage blocks as SLC caches, write requests can be processed with lower latency, improving write speed and overall write performance. In practical applications, the data cached in the SLC cache can be flushed to the user space data storage area via host commands or when the firmware is idle, for example, the space in user space other than the write acceleration cache 430.
[0087] In this embodiment of the disclosure, by setting the first storage block of the user space as the write acceleration cache, the write speed can be improved; by setting the free storage block of the hidden space as the write acceleration cache, the capacity of the write acceleration cache can be increased; and even in dirty scenarios, the write acceleration cache can still use the free storage block of the hidden space, which is beneficial to improving the write performance in dirty scenarios.
[0088] In some embodiments, the processor may include a partitioning module, which has functions such as creating partitions, deleting partitions, merging partitions, and extending partitions. Through the combination of functions related to the partitioning module, multiple storage blocks of the memory 400 can be partitioned. It should be noted that the processor may also include other functional modules known in the art. The various modules of the processor may be software modules running on a processor (e.g., a microcontroller unit (MCU)) that is part of the processor, or hardware modules of a finite state machine (FSM) (e.g., integrated circuits (ICs, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs)), or a combination of software modules and hardware modules.
[0089] In some embodiments, the hidden space 420 includes a reserved subspace 421 for garbage collection; the memory controller is specifically configured to set free storage blocks of the reserved subspace 421 as write acceleration cache 430.
[0090] For example, when the capacity of the write acceleration cache 430 is small or the available capacity is insufficient, free storage blocks in the reserved subspace 421 can be set as the write acceleration cache 430. For instance, a portion of the free storage blocks from the reserved subspace 421 can be included in the scope of the write acceleration cache 430, thereby expanding the capacity of the write acceleration cache 430. It should be noted that the free storage blocks included in the write acceleration cache 430 still belong to the hidden space 420 in terms of ownership.
[0091] In other embodiments, when there are unoccupied free storage blocks in the hidden space 420 other than the reserved subspace 421, some of the free storage blocks in that space can be set as the write acceleration cache 430. This disclosure does not impose any special restrictions on this.
[0092] In some embodiments, the memory controller is further configured to: when the hidden space 420 needs to use a free storage block in the reserved subspace 421, return the free storage block occupied by the write acceleration cache 430 to the reserved subspace 421. Here, the situations in which the hidden space 420 needs to use a free storage block in the reserved subspace 421 include at least one of the following: the available capacity of the hidden space 420 is less than or equal to a preset capacity, or garbage collection occurs. It is understood that when the hidden space 420 needs to use a free storage block in the reserved subspace, the write acceleration cache 430 needs to promptly return the occupied free storage block.
[0093] In one example, when the available capacity of the hidden space 420 is less than or equal to the preset capacity, the free storage block occupied by the write acceleration cache 430 can be returned to the reserved subspace 421 for use by the hidden space 420. Here, the preset capacity can be reasonably set according to the actual memory capacity, and this disclosure does not have any special limitations on it. In a specific embodiment, the preset capacity is less than the capacity of the hidden space 420.
[0094] In another example, when the hidden space 420 needs garbage collection, the free storage blocks occupied by the write acceleration cache 430 can be returned to the reserved subspace 421, thus allowing the hidden space 420 to perform garbage collection operations. Garbage collection refers to transferring valid data from one or more storage blocks to a free storage block and erasing the one or more storage blocks, after which the erased storage blocks can be used to write new data.
[0095] In some embodiments, the memory controller is specifically configured as follows:
[0096] The data cached in the free storage block occupied by the acceleration cache 430 is written to the second storage block of the user space 410; wherein, the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode.
[0097] After writing the cached data in the free storage block to the second storage block, the free storage block is erased, so that the free storage block is returned to the reserved subspace 421.
[0098] For example, the cached data in the free storage block is written to the data storage area in user space, and the free storage block is erased. Since the free storage block still belongs to the hidden space 420, the erased free storage block does not need to be repartitioned before being returned to the reserved subspace 421. In this example, the data storage area includes one or more second storage blocks, and the second-level storage unit mode includes MLC mode, TLC mode, or QLC mode, etc. When the memory 400 is a TLC memory, the second-level storage unit mode can be TLC mode.
[0099] In some embodiments, the memory controller is further configured to: stop setting the free memory blocks of the hidden space 420 as the write acceleration cache 430 when the number of erase / write cycles of the free memory blocks of the hidden space 420 is greater than or equal to a preset value.
[0100] Since the write acceleration cache 430 uses free storage blocks of the hidden space 420, it may accelerate the wear of the hidden space 420. In order to make the wear of the user space 410 and the hidden space 420 as even as possible, the free storage blocks of the hidden space 420 can be stopped from being set as the write acceleration cache 430 when the number of erase counts (EC) of the free storage blocks of the hidden space 420 is greater than or equal to a preset value. In this way, the wear of the user space 410 and the hidden space 420 can be balanced. Here, those skilled in the art can reasonably set the preset value according to the characteristics of the storage cells in the actual memory, and this disclosure does not impose any limitations.
[0101] In some embodiments, the memory controller is further configured to cache data to be cached to the free storage block to the first storage block when the number of erase / write cycles of the free storage block in the hidden space 420 is greater than or equal to a preset value. By caching the data to be cached to the free storage block to the first storage block, the positions of the storage blocks in the hidden space 420 and the user space 410 can be swapped. That is, the storage blocks in the user space that do not store data are reassigned to the hidden space 420, and the free storage blocks in the hidden space 420 that are more severely worn are reassigned to the user space 410, thereby ensuring wear balance between the user space 410 and the hidden space 420.
[0102] In some embodiments, the memory controller is specifically configured to swap the physical address of a free memory block and the physical address of a first memory block. In this example, the free memory block being swapped may be a memory block in the hidden space 420 that is severely worn, and the first memory block being swapped may be a memory block in user space that does not store data. By swapping the physical addresses of the free memory block and the first memory block, the positions of the free memory block and the first memory block can be interchanged.
[0103] In some embodiments, the memory controller is further configured to:
[0104] The data cached in the first storage block is written to the second storage block in user space 410; wherein, the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode.
[0105] After writing the cached data in the first storage block to the second storage block, the first storage block is erased.
[0106] For example, the data cached in the first storage block is written to the data storage area in user space, and the first storage block is erased; the erased first storage block can be swapped with a free storage block in the hidden space. The second-level storage cell mode includes MLC mode, TLC mode, or QLC mode, etc. When the memory 400 is a TLC memory, the second-level storage cell mode can be TLC mode.
[0107] In some embodiments, the memory controller is further configured to:
[0108] Set the first storage block of user space 410 to the first-level storage unit mode;
[0109] Set the storage block of hidden space 420 to the first-level storage unit mode;
[0110] The second storage block of user space 410 is set to the second-level storage unit mode; wherein the second storage block is configured to store data.
[0111] For example, the memory controller sets the first storage block of user space 410 to SLC mode, the second storage block of user space 410 to TLC mode, and the storage blocks of hidden space 420 to SLC mode; wherein, the first storage block of user space 410 is used to cache data, and one or more pieces of data cached in the first storage block can be refreshed to the second storage block of user space 410; the portion of the storage blocks in hidden space 420 set to SLC mode is used to store parameter information or status information of user space 410, and the portion of the free storage blocks in hidden space 420 set to SLC mode can be dynamically included in the scope of write acceleration cache 430.
[0112] In this embodiment of the disclosure, by setting the first storage block of the user space to the first-level storage unit mode, the first storage block can be set as a write acceleration cache, thereby improving the write speed; by setting the storage block of the hidden space to the first-level storage unit mode, the free storage block of the hidden space can be set as a write acceleration cache, thereby increasing the capacity of the write acceleration cache, which is beneficial to improving write performance.
[0113] Based on the above-described memory system, this disclosure also provides a method for operating the memory system.
[0114] Figure 5 This is a flowchart illustrating an operation method of a memory system according to an embodiment of the present disclosure. The memory system includes a memory and a memory controller coupled to the memory. The physical space of the memory is divided into user space and hidden space. (Refer to...) Figure 5 As shown, the operation method includes:
[0115] S510: Set the first storage block in user space as a write acceleration cache; wherein, the first storage block is in first-level storage unit mode; the write acceleration cache is configured to cache data;
[0116] S520: Set the free storage block of the hidden space as a write acceleration cache; where the free storage block is in the first-level storage unit mode.
[0117] In some embodiments, the hidden space includes a reserved subspace, which is used for garbage collection; step S520 above includes: setting the free storage block of the reserved subspace as a write acceleration cache.
[0118] In some embodiments, the above operation method further includes: when the hidden space needs to use the free storage block of the reserved subspace, returning the free storage block occupied by the write acceleration cache to the reserved subspace.
[0119] In some embodiments, the above-mentioned method of returning the free storage block occupied by the write acceleration cache to the reserved subspace includes:
[0120] The data cached in the free storage block occupied by the acceleration cache is written to the second storage block in user space; wherein, the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode.
[0121] After writing the cached data in the free storage block to the second storage block, the free storage block is erased, so that the free storage block is returned to the reserved subspace.
[0122] In some embodiments, the above operation method further includes: when the number of erase / write operations of the free storage block in the hidden space is greater than or equal to a preset value, stopping the setting of the free storage block in the hidden space as a write acceleration cache.
[0123] In some embodiments, the above operation method further includes: when the number of erase / write operations of the free storage block in the hidden space is greater than or equal to a preset value, caching the data to be cached to the free storage block to the first storage block.
[0124] In some embodiments, caching the data to be cached in the free storage block to the first storage block includes: swapping the physical address of the free storage block and the physical address of the first storage block.
[0125] In some embodiments, the above-described operation method further includes:
[0126] Set the first storage block in user space to the first-level storage unit mode;
[0127] Set the storage block of the hidden space to the first-level storage unit mode;
[0128] Set the second storage block in user space to the second-level storage unit mode; wherein, the second storage block is configured to store data.
[0129] The above operating methods have been described in detail on the memory system side, and will not be repeated here for the sake of brevity.
[0130] This disclosure also provides a computer-readable storage medium storing instructions that, when executed, implement the operation method as described in any of the above embodiments.
[0131] Here, implementing all or part of the processes in the methods of the above embodiments can be accomplished by a computer program instructing relevant hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive, etc.; the storage medium can also include combinations of the above types of memory.
[0132] This disclosure also provides an electronic device, including a memory system as described in any of the above embodiments.
[0133] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.
[0134] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.
[0135] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0136] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0137] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A memory system, characterized in that, include: The memory, whose physical space is divided into user space and hidden space; A memory controller, coupled to the memory, is configured to: The first storage block of the user space is set as a write acceleration cache; wherein, the first storage block is in the first-level storage unit mode; the write acceleration cache is configured to cache data; The free storage block of the hidden space is set as the write acceleration cache area; wherein the free storage block is the first level storage unit mode; When the hidden space needs to use the free storage block, the free storage block occupied by the write acceleration cache is returned to the hidden space; wherein, the free storage block occupied by the write acceleration cache belongs to the hidden space in terms of partition.
2. The memory system according to claim 1, characterized in that, The hidden space includes a reserved subspace, which is used for waste recycling; The memory controller is specifically configured as follows: Set the free storage block of the reserved subspace as the write acceleration cache area.
3. The memory system according to claim 2, characterized in that, The memory controller is further specifically configured to: When the hidden space needs to use the free storage block of the reserved subspace, the free storage block occupied by the write acceleration cache is returned to the reserved subspace.
4. The memory system according to claim 3, characterized in that, The memory controller is further specifically configured to: The data cached in the free storage block occupied by the write acceleration cache is written to the second storage block in the user space; wherein, the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode; After writing the data cached in the free storage block into the second storage block, the free storage block is erased, so that the free storage block is returned to the reserved subspace.
5. The memory system according to claim 2, characterized in that, The hidden space needs to use the free storage block of the reserved subspace in at least one of the following situations: the available capacity of the hidden space is less than or equal to the preset capacity, or garbage collection.
6. The memory system according to claim 1, characterized in that, The memory controller is also configured to: When the number of erase / write cycles of the free storage block in the hidden space is greater than or equal to a preset value, the setting of the free storage block in the hidden space as the write acceleration cache area is stopped.
7. The memory system according to claim 1, characterized in that, The memory controller is also configured to: When the number of erase / write cycles of the free storage block in the hidden space is greater than or equal to a preset value, the data to be cached in the free storage block is cached in the first storage block.
8. The memory system according to claim 7, characterized in that, The memory controller is specifically configured as follows: The physical addresses of the free storage block and the first storage block are swapped.
9. The memory system according to claim 7, characterized in that, The memory controller is also configured to: The data cached in the first storage block is written to the second storage block in the user space; wherein the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode. After writing the data cached in the first storage block to the second storage block, the first storage block is erased.
10. The memory system according to claim 1, characterized in that, The memory controller is also configured to: Set the first storage block in the user space to the first-level storage unit mode; Set the storage block of the hidden space to the first-level storage unit mode; The second storage block of the user space is set to a second-level storage unit mode; wherein the second storage block is configured to store the data.
11. The memory system according to claim 1, characterized in that, The memory system includes: solid-state drives, embedded multimedia cards, and general-purpose flash memory.
12. A method for operating a memory system, characterized in that, The memory system includes a memory and a memory controller coupled to the memory, and the physical space of the memory is divided into user space and hidden space; The operation method includes: The first storage block of the user space is set as a write acceleration cache; wherein, the first storage block is in the first-level storage unit mode; the write acceleration cache is configured to cache data; The free storage block of the hidden space is set as the write acceleration cache area; wherein the free storage block is the first level storage unit mode; When the hidden space needs to use the free storage block, the free storage block occupied by the write acceleration cache is returned to the hidden space; wherein, the free storage block occupied by the write acceleration cache belongs to the hidden space in terms of partition.
13. The operating method according to claim 12, characterized in that, The hidden space includes a reserved subspace, which is used for waste recycling; Setting the free storage block of the hidden space as the write acceleration cache includes: Set the free storage block of the reserved subspace as the write acceleration cache area.
14. The operating method according to claim 13, characterized in that, When the hidden space needs to use the free storage block, returning the free storage block occupied by the write acceleration cache to the hidden space includes: When the hidden space needs to use the free storage block of the reserved subspace, the free storage block occupied by the write acceleration cache is returned to the reserved subspace.
15. The operating method according to claim 14, characterized in that, Returning the free storage block occupied by the write acceleration cache to the reserved subspace includes: The data cached in the free storage block occupied by the write acceleration cache is written to the second storage block in the user space; wherein, the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode; After writing the data cached in the free storage block into the second storage block, the free storage block is erased, so that the free storage block is returned to the reserved subspace.
16. The operating method according to claim 12, characterized in that, The operation method further includes: When the number of erase / write cycles of the free storage block in the hidden space is greater than or equal to a preset value, the setting of the free storage block in the hidden space as the write acceleration cache area is stopped.
17. The operating method according to claim 12, characterized in that, The operation method further includes: When the number of erase / write cycles of the free storage block in the hidden space is greater than or equal to a preset value, the data to be cached in the free storage block is cached in the first storage block.
18. The operating method according to claim 17, characterized in that, The step of caching the data to be cached in the free storage block to the first storage block includes: The physical addresses of the free storage block and the first storage block are swapped.
19. The operating method according to claim 12, characterized in that, The operation method further includes: Set the first storage block in the user space to the first-level storage unit mode; Set the storage block of the hidden space to the first-level storage unit mode; The second storage block of the user space is set to a second-level storage unit mode; wherein the second storage block is configured to store the data.
20. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed, implement the operation method as described in any one of claims 12 to 19.