Memory and compression reading method

Abstract

The invention provides a memory and a compression reading method, the memory comprises a plurality of memory blocks, each memory block comprises two memory halves, aiming at a compression reading instruction, a first memory half in the selected memory block generates a plurality of first data groups, and a second memory half generates a plurality of second data groups; the first compression module compresses the first half of the first data set and the second half of the second data set to generate low-order compressed data; the second compression module compresses the second half of the first data set and the second half of the second data set to generate high-order compressed data.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a memory and a compression reading method. Background Art

[0002] In the process of testing a memory (such as a dynamic random access memory), test data is written to each memory block therein, and then the data of each memory block is read out through a read instruction to determine whether the memory cells in the memory block can work normally. It should be understood that for each read instruction, the selected memory block will read multiple bit line groups therein to obtain multiple groups of data signals. Generally speaking, each bit line group includes 8 bit lines, and each group of data signals includes 8 data signals, that is, the burst length is 8.

[0003] In order to improve the efficiency of the test, the test data written is generally designed. For example, the same data is written to the bit lines with the same number in each bit line group that is read out at the same time, that is, the level state of the data signal at the same position in each group of data signals should be the same. Based on this, the multiple groups of data signals output by the storage block can be compressed through XOR processing, so as to better observe the test results. However, this compression method cannot reduce the number of cycles required for traversal reading, and the test efficiency is relatively low. Summary of the invention

[0004] The present disclosure provides a memory and a compression reading method.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a memory, the memory comprising a plurality of memory blocks, the memory performing compression reading on selected memory blocks based on a compression read instruction, and each selected memory block outputs low-order compressed data and high-order compressed data;

[0007] Each of the storage blocks includes two storage halves, and each of the storage blocks has a control circuit, a first compression module and a second compression module; wherein,

[0008] The control circuit is connected to the corresponding storage block and is configured to read the first storage half in the storage block to generate a plurality of first data groups, and read the second storage half in the storage block to generate a plurality of second data groups;

[0009] The first compression module is connected to the control circuit and is configured to receive and compress the first half of the first data group and the first half of the second data group to form the low-bit compressed data;

[0010] The second compression module is connected to the control circuit and is configured to receive and compress the second half of the first data group and the second half of the second data group to form the high-bit compressed data.

[0011] In some embodiments, each of the storage halves includes M storage column groups, each storage column group includes a plurality of bit line groups, the number of the first data groups is M, and the number of the second data groups is M;

[0012] The control circuit is specifically configured to read a selected bit line group in each storage column group in the first storage half to generate M first data groups when the target word line is turned on; and read a selected bit line group in each storage column group in the second storage half to generate M second data groups;

[0013] Each bit line group has N bit lines, the first data group includes N-bit data, the second data group includes N-bit data, and N and M are both positive integers.

[0014] In some embodiments, the first compression module includes:

[0015] A first compression submodule is configured to receive and compress the first M / 2 first data groups, and output first intermediate data; a second compression submodule is configured to receive and compress the first M / 2 second data groups, and output second intermediate data; a third compression submodule is connected to both the first compression submodule and the second compression submodule, and is configured to receive the first intermediate data and the second intermediate data, compress the first intermediate data and the second intermediate data, and output the low-order compressed data;

[0016] The second compression module comprises:

[0017] a fourth compression submodule, configured to receive and compress the last M / 2 of the first data groups, and output third intermediate data;

[0018] a fifth compression submodule, configured to receive and compress the last M / 2 second data groups, and output fourth intermediate data;

[0019] The sixth compression submodule is connected to both the fourth compression submodule and the fifth compression submodule, and is configured to receive the third intermediate data and the fourth intermediate data, compress the third intermediate data and the fourth intermediate data, and output the high-bit compressed data.

[0020] In some embodiments, the first compression submodule includes N first operation units and 1 second operation unit, and the second compression submodule includes N third operation units and 1 fourth operation unit;

[0021] In the case of M=8, the i-th first operation unit is configured to compare the i-th data signal of the 0th first data group with the i-th data signal of the 1st first data group to generate the i-th first result signal; and compare the i-th data signal of the 2nd first data group with the i-th data signal of the 3rd first data group to generate the i-th second result signal; i is a positive integer, and i≤N; the second operation unit is connected to the N first operation units, and is configured to receive the N first result signals and the N second result signals; perform logic operations on the N first result signals and the N second result signals to generate the first intermediate data; the i-th third operation unit is configured to compare the i-th data signal of the 0th second data group with the i-th data signal of the 1st second data group to generate an i-th third result signal; and compare the i-th data signal of the 2nd second data group with the i-th data signal of the 3rd second data group to generate an i-th fourth result signal; i is a positive integer, and i≤N; the fourth operation unit is connected to the N third operation units, and is configured to receive N third result signals and N fourth result signals; perform logic operations on the N third result signals and the N fourth result signals to generate the second intermediate data.

[0022] In some embodiments, each of the first operation units includes a first logic device and a second logic device; in the ith first operation unit: the ith first logic device is configured to receive the ith data bit signal of the 0th first data group and the ith data bit signal of the 1st first data group; if the received data signal levels are the same, the ith first result signal of the first state is output; if the received data signal levels are different, the ith first result signal of the second state is output; the ith second logic device is configured to receive the ith data bit signal of the 2nd first data group and the ith data bit signal of the 3rd first data group; if the received data signal levels are different, the ith second result signal of the second state is output; the second operation unit is configured to output the first intermediate data of the third state if N first result signals and N second result signals are all in the first state; if the N first result signals and N second result signals are not all in the first state, the first intermediate data of the fourth state is output.

[0023] In some embodiments, each of the third operation units includes a third logic device and a fourth logic device; in the ith third operation unit: the ith third logic device is configured to receive the ith data bit signal of the 0th second data group and the ith data bit signal of the 1st second data group; if the received data signal levels are the same, the ith third result signal of the first state is output; if the received data signal levels are different, the ith third result signal of the second state is output; the ith fourth logic device is configured to receive the ith data bit signal of the 2nd second data group and the ith data bit signal of the 3rd second data group; if the received data signal levels are the same, the ith fourth result signal of the first state is output; if the received data signal levels are different, the ith fourth result signal of the second state is output; the fourth operation unit is configured to output the second intermediate data of the third state if N of the third result signals and N of the fourth result signals are all in the first state; if the N of the third result signals and N of the fourth result signals are not all in the first state, the second intermediate data of the fourth state is output.

[0024] In some embodiments, the third compression submodule is configured to output the low-bit compressed data in the fifth state if the first intermediate data and the second intermediate data are both in the third state; if the first intermediate data and the second intermediate data are not both in the third state, output the low-bit compressed data in the sixth state.

[0025] In some embodiments, the fourth compression submodule includes N fifth operation units and 1 sixth operation unit, and the fifth compression submodule includes N seventh operation units and 1 eighth operation unit; when M=8, the i-th fifth operation unit is configured to compare the i-th data signal of the fourth first data group with the i-th data signal of the fifth first data group to generate the i-th fifth result signal; and compare the i-th data signal of the sixth first data group with the i-th data signal of the seventh first data group to generate the i-th sixth result signal; the sixth operation unit is connected to the N fifth operation units, and is configured to receive the N fifth result signals and the N sixth result signals; The fifth result signal and the N sixth result signals are logically operated to generate the third intermediate data; the i-th seventh operation unit is configured to compare the i-th data signal of the fourth second data group with the i-th data signal of the fifth second data group to generate the i-th seventh result signal; and compare the i-th data signal of the sixth second data group with the i-th data signal of the seventh second data group to generate the i-th eighth result signal; the eighth operation unit is connected to the N fifth operation units, and is configured to receive the N seventh result signals and the N eighth result signals; and perform a logical operation on the N seventh result signals and the N eighth result signals to generate the fourth intermediate data.

[0026] In some embodiments, each of the fifth operation units includes a fifth logic device and a sixth logic device; in the i-th fifth operation unit: the fifth logic device is configured to receive the i-th data signal of the fourth first data group and the i-th data signal of the fifth first data group; if the received data signal levels are the same, the i-th fifth result signal of the first state is output; if the received data signal levels are different, the i-th fifth result signal of the second state is output; the sixth logic device is configured to receive the i-th data signal of the sixth first data group and the i-th data signal of the seventh first data group; if the received data signal levels are the same, the i-th sixth result signal of the first state is output; if the received data signal levels are different, the i-th sixth result signal of the second state is output; the sixth operation unit is configured to output the third intermediate data of the third state if N of the fifth result signals and N of the sixth result signals are all in the first state; if the N of the fifth result signals and N of the sixth result signals are not all in the first state, the third intermediate data of the fourth state is output.

[0027] In some embodiments, each of the seventh operation units includes a seventh logic device and an eighth logic device; in the ith seventh operation unit: the ith seventh logic device is configured to receive the ith bit data signal of the 4th second data group and the ith bit data signal of the 5th second data group; if the received data signal levels are the same, the ith seventh result signal of the first state is output; if the received data signal levels are different, the ith seventh result signal of the second state is output; the ith eighth logic device is configured to receive the ith bit data signal of the 6th second data group and the ith bit data signal of the 7th second data group; if the received data signal levels are the same, the ith eighth result signal of the first state is output; if the received data signal levels are different, the ith eighth result signal of the second state is output; the eighth operation unit is configured to output the fourth intermediate data of the third state if N of the seventh result signals and N of the eighth result signals are all in the first state; if the N of the seventh result signals and N of the eighth result signals are not all in the first state, the fourth intermediate data of the fourth state is output.

[0028] In some embodiments, the sixth compression submodule is configured to output the high-bit compressed data in the fifth state if the third intermediate data and the fourth intermediate data are both in the third state; if the third intermediate data and the fourth intermediate data are not both in the third state, output the high-bit compressed data in the sixth state.

[0029] In some embodiments, the memory further comprises a decoding circuit; the decoding circuit is configured to decode the compressed read instruction to generate a row address signal group for each of the storage blocks and a column address signal group for each of the storage blocks; wherein, for the selected storage block, the corresponding partial selection signal and partial selection complementary signal in the row address signal group are both valid, the valid partial selection signal is used to select the first storage half, and the valid partial selection complementary signal is used to select the second storage half.

[0030] In a second aspect, an embodiment of the present disclosure provides a compression reading method, which is applied to a memory, and the memory includes multiple storage blocks, each storage block includes two storage halves, and the method includes:

[0031] When a compression read instruction is received, for each selected storage block, its first storage half is read to generate multiple first data groups; its second storage half is read to generate multiple second data groups; for each selected storage block, the first data group in the first half and the second data group in the first half are compressed to form low-order compressed data corresponding to the storage block; and the first data group in the second half and the second data group in the second half are compressed to form high-order compressed data corresponding to the storage block.

[0032] The disclosed embodiments provide a memory and a compressed reading method. For each compressed reading instruction, two storage halves in a selected storage block are selected to output multiple first data groups and multiple second data groups, which can reduce the number of read times required for traversal reading (i.e., the number of compressed reading instructions) by half. At the same time, the multiple first data groups and the multiple second data groups are compressed into high-order compressed data and low-order compressed data, thereby improving the data compression ratio and improving the overall test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of data output of a storage block;

[0034] Figure 2 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0035] Figure 3 A schematic diagram of data output of a storage block provided in an embodiment of the present disclosure;

[0036] Figure 4 A schematic diagram of the structure of a first compression module and a second compression module provided in an embodiment of the present disclosure;

[0037] Figure 5 A schematic diagram of the structure of a first compression module provided in an embodiment of the present disclosure;

[0038] Figure 6 A schematic diagram of the structure of a second compression module provided in an embodiment of the present disclosure;

[0039] Figure 7 A flowchart of a compression reading method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, rather than to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0042] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0043] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0044] Dynamic Random Access Memory (DRAM);

[0045] Synchronoμs Dynamic Random Access Memory (SDRAM);

[0046] Double Data Rate SDRAM (DDR);

[0047] Low power (Lower Power, LPDDR);

[0048] 6th generation LPDDR standard (LPDDR6 Specification, LPDDR6 SPEC);

[0049] Currently, DRAM includes multiple memory blocks (Bank). Figure 1As shown, each Bank is divided into two storage halves (half Banks) along the word line direction, each half Bank includes 8 storage column groups (i.e., the 0th storage column group to the 7th storage column group), each storage column group is further divided into multiple bit line groups, each bit line group includes 8 bit lines, and these 8 bit lines are controlled by a column selection signal (CSL). Each storage block includes a row decoding module (XDEC) and a column decoding module (YDEC), XDEC is used to decode and generate a row selection signal according to an externally transmitted operation instruction (such as a read instruction, a write instruction, a refresh instruction, an activation instruction, etc.), and the row selection signal is used to select one of the storage halves and turn on the target word line in the selected storage half, and the column decoding module (YDEC) is used to decode and generate a column selection signal according to an externally transmitted operation instruction, and the column selection signal is used to select a bit line group in each storage column group to perform subsequent operations.

[0050] Taking the compression read mode (Para mode read) as an example, based on the received compression read instruction, for the selected storage block, first, one of the storage halves in the storage block is selected, and the target word line is further opened in the selected storage half; secondly, one of the bit line groups in each storage column group in the storage block is selected, so as to output a group of data signals. That is to say, for each selected storage block, one of the storage halves corresponds to outputting 8 groups of data signals DQ0[7:0], DQ1[7:0]...DQ7[7:0], and each group of data signals has 8 bits (that is, the burst length is 8), totaling 64 bits of data signals. In order to improve the reading efficiency, these 64 bits of data signals are compressed into 2 bits, and the compression ratio is 32:1.

[0051] It should be understood that during the test process of the memory, after writing the test data, it is necessary to perform a traversal reading of all the storage cells in all the storage blocks to detect whether each storage cell can work normally. However, although the compression process makes each storage block output only 2 bits of data signal each time, the number of readings required for the traversal reading is not reduced, so the test time is still long.

[0052] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0053] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the structure of a memory 10 provided by an embodiment of the present disclosure. Figure 2 As shown, the memory 10 includes a plurality of storage blocks 20 ( Figure 1Only one of them is shown), the memory 10 performs compression reading on the selected storage block 20 based on the compression read instruction, and each selected storage block 20 outputs low-order compressed data and high-order compressed data. Here, the memory 10 can be DRAM, SDRAM, DDR, LPDDR, etc., the low-order compressed data is only embodied as a 1-bit signal, and the high-order compressed data is also only embodied as a 1-bit signal.

[0054] like Figure 2 As shown, each storage block 20 includes two storage halves, and each storage block 20 has a control circuit 11, a first compression module 12 and a second compression module 13; wherein,

[0055] The control circuit 11 is connected to the corresponding storage block 20 and is configured to read the first storage half in the storage block 20 to generate a plurality of first data groups, and read the second storage half in the storage block 20 to generate a plurality of second data groups;

[0056] The first compression module 12 is connected to the control circuit 11 and is configured to receive and compress the first half of the first data group and the first half of the second data group to form low-bit compressed data;

[0057] The second compression module 13 is connected to the control circuit 11 and is configured to receive and compress the second half of the first data group and the second half of the second data group to form high-bit compressed data.

[0058] In this way, for each selected storage block 20, two storage halves thereof are selected to output multiple first data groups and multiple second data groups, which is equivalent to doubling the burst length of each read, and can halve the number of reads required for traversal reading (i.e., the number of compressed read instructions); at the same time, multiple first data groups and multiple second data groups are compressed into high-order compressed data and low-order compressed data, the data compression ratio is improved, and the overall test efficiency is improved.

[0059] In some embodiments, see Figure 3 Each storage half includes M storage column groups ( Figure 3 Taking M=8 as an example), each storage column group includes a plurality of bit line groups, the number of the first data groups is M, and the number of the second data groups is M;

[0060] The control circuit 11 is specifically configured to read a selected bit line group in each storage column group in the first storage half to generate M first data groups when the target word line is turned on; and read a selected bit line group in each storage column group in the second storage half to generate M second data groups; wherein each bit line group has N bit lines ( Figure 3Taking N=8 as an example, the first data group includes N-bit data, the second data group includes N-bit data, and N and M are both positive integers. At this time, the M first data groups can be expressed as DQ0_A[N-1:0], DQ1_A[N-1:0]...DQ(M-1)_A[N-1:0], and the M second data groups can be expressed as DQ0_B[N-1:0], DQ1_B[N-1:0]...DQ(M-1)_B[N-1:0].

[0061] It should be noted that the target word line, the selected storage block 20, and the selected bit line group are all information carried in the compressed read instruction, but the information originally carried in the compressed read instruction for selecting one of the storage halves in the selected storage block 20 is masked, so that the two storage halves in the selected storage block 20 are selected at the same time. Here, the number of word lines and the word line addresses in the two storage halves are the same; for the same word line address, if only one storage half is selected, then only the word line corresponding to the word line address is opened in the storage half, and the word line corresponding to the word line address in the unselected storage half will not be opened; however, if both storage halves are selected, then the word line corresponding to the word line address is opened in each of the two storage halves, and the opened word line is also called the target word line.

[0062] That is, based on the address information carried by the read instruction, the target word line is opened in each storage half of the selected storage block 20, and then a selected bit line group is opened in each storage column group, generating a total of M first data groups and M second data groups.

[0063] In some embodiments, Figure 4 As shown, the first compression module 12 includes:

[0064] The first compression submodule 121 is configured to receive and compress the first M / 2 first data groups, and output the first intermediate data, that is, DQ0_A[N-1:0], DQ1_A[N-1:0]...DQ(M / 2-1)_A[N-1:0] are compressed to generate the first intermediate data; the second compression submodule 122 is configured to receive and compress the first M / 2 second data groups, and output the second intermediate data, that is, DQ0_B[N-1:0], DQ1_B[N-1:0]...DQ(M / 2-1)_B[N-1:0] are compressed to generate the second intermediate data; the third compression submodule 123 is connected to both the first compression submodule 121 and the second compression submodule 122, and is configured to receive the first intermediate data and the second intermediate data, compress the first intermediate data and the second intermediate data, and output low-bit compressed data.

[0065] Similar, such as Figure 4 As shown, the second compression module 13 includes:

[0066] The fourth compression submodule 131 is configured to receive and compress the last M / 2 first data groups, and output the third intermediate data, that is, DQ(M / 2)_A[N-1:0], DQ(M / 2+1)_A[N-1:0]…DQ(M-1)_A[N-1:0] are compressed to generate the third intermediate data; the fifth compression submodule 132 is configured to receive and compress the last M / 2 second data groups, and output the fourth intermediate data, that is, DQ(M / 2)_B[N-1:0], DQ(M / 2+1)_B[N-1:0]…DQ(M-1)_B[N-1:0] are compressed to generate the fourth intermediate data; the sixth compression submodule 133 is connected to both the fourth compression submodule 131 and the fifth compression submodule 132, and is configured to receive the third intermediate data and the fourth intermediate data, compress the third intermediate data and the fourth intermediate data, and output high-bit compressed data.

[0067] It should be noted that the compressed read instruction is generally used to test the memory 10. In short, during the test, the memory 10 is first written through a write instruction, and the write rule is: the same data sequence is written to the bit line group with the same number in each storage column group in the same storage block 20. In other words, when the memory 10 works normally, for the same storage block, the level value of the i-th data signal of each first data group and the i-th data signal of each second data group should be the same.

[0068] Under this premise, the following exemplary compression rules for low-order compressed data and high-order compressed data are provided. Of course, if the write rules change during the test process, the compression rules for low-order compressed data and high-order compressed data can be adaptively modified based on the write rules, as long as the low-order compressed data and high-order compressed data can reflect whether the corresponding part of the storage block is reading and writing data normally.

[0069] In some embodiments, taking M=8 and N=8 as an example, Figure 5 FIG. 1 shows a schematic diagram of a specific structure of the first compression module 12. Figure 5 As shown, the first compression submodule 121 includes N first operation units 21 and 1 second operation unit 22 , and the second compression submodule 122 includes N third operation units 23 and 1 fourth operation unit 24 .

[0070] The i-th first operation unit 21 is configured to compare the i-th data signal DQ0_A[i] of the 0th first data group with the i-th data signal DQ1_A[i] of the 1st first data group to generate an i-th first result signal; and compare the i-th data signal DQ2_A[i] of the 2nd first data group with the i-th data signal DQ3_A[i] of the 3rd first data group to generate an i-th second result signal; i is a positive integer, and i≤N; the second operation unit 22 is connected to the N first operation units 21, and is configured to receive N first result signals and N second result signals; perform logic operations on the N first result signals and the N second result signals to generate first intermediate data.

[0071] The i-th third operation unit 23 is configured to compare the i-th data signal DQ0_B[i] of the 0th second data group with the i-th data signal DQ1_B[i] of the 1st second data group to generate the i-th third result signal; and compare the i-th data signal DQ2_B[i] of the 2nd second data group with the i-th data signal DQ3_B[i] of the 3rd second data group to generate the i-th fourth result signal; i is a positive integer, and i≤N; the fourth operation unit 24 is connected to the N third operation units 23, and is configured to receive N third result signals and N fourth result signals; perform logic operations on the N third result signals and the N fourth result signals to generate second intermediate data.

[0072] In some embodiments, Figure 5 As shown, each first operation unit 21 includes a first logic unit 211 and a second logic unit 212. Figure 5 Only one of the first logic units and one of the second logic units 212 are labeled.

[0073] In the i-th first operation unit 21: the i-th first logic device 211 is configured to receive the i-th data signal DQ0_A[i] of the 0-th first data group and the i-th data signal DQ1_A[i] of the 1st first data group; if the received data signal levels are the same, the i-th first result signal of the first state is output; if the received data signal levels are different, the i-th first result signal of the second state is output; the i-th second logic device 212 is configured to receive the i-th data signal DQ2_A[i] of the 2nd first data group and the i-th data signal DQ3_A[i] of the 3rd first data group; if the received data signal levels are the same, the i-th second result signal of the first state is output; if the received data signal levels are different, the i-th second result signal of the second state is output;

[0074] The second operation unit 22 is configured to output the first intermediate data of the third state if the N first result signals and the N second result signals are all in the first state; and to output the first intermediate data of the fourth state if the N first result signals and the N second result signals are not all in the first state.

[0075] It should be noted that the first logic device 211 may be one or more of the following logic devices: XOR gate, XNOR gate, NOT gate, and the second logic device 212 has the same structure as the first logic device 211. The second operation unit 22 may be one or more of the following logic devices: AND gate, OR gate, NAND gate, NOR gate, XNOR gate, XOR gate, NOT gate. Figure 5 This is only an example and does not constitute a corresponding limitation.

[0076] In some embodiments, each third operation unit 23 includes a third logic unit 231 and a fourth logic unit 232. Figure 5 Only one of the third logic units 231 and one of the fourth logic units 232 are labeled.

[0077] In the i-th third operation unit 23: the i-th third logic device 231 is configured to receive the i-th data signal DQ0_B[i] of the 0-th second data group and the i-th data signal DQ1_B[i] of the 1st second data group; if the received data signal levels are the same, the i-th third result signal of the first state is output; if the received data signal levels are different, the i-th third result signal of the second state is output; the i-th fourth logic device 232 is configured to receive the i-th data signal DQ2_B[i ] and the i-th data signal DQ3_B[i] of the third second data group; if the received data signal levels are the same, the i-th fourth result signal of the first state is output; if the received data signal levels are different, the i-th fourth result signal of the second state is output; the fourth operation unit 24 is configured to output the second intermediate data of the third state if the N third result signals and the N fourth result signals are all in the first state; if the N third result signals and the N fourth result signals are not all in the first state, the second intermediate data of the fourth state is output.

[0078] It should be noted that the third logic unit 231 and the fourth logic unit 232 have the same structure as the first logic unit 211 , and the fourth operation unit 24 has the same structure as the second operation unit 22 .

[0079] In some embodiments, the third compression submodule 123 is configured to output low-order compressed data in the fifth state if both the first intermediate data and the second intermediate data are in the third state; if both the first intermediate data and the second intermediate data are not in the third state, output low-order compressed data in the sixth state.

[0080] Here, the third compression submodule 123 may be one or more of the following devices: an AND gate, an OR gate, a NAND gate, a NOR gate, a NOT gate, an XNOR gate, and an XOR gate.

[0081] In this way, during the test process, if the low-order compressed data is in the fifth state, the circuit part representing the low-order data signal of the corresponding data block is read and written normally; if the low-order compressed data is in the sixth state, the circuit part representing the low-order data signal of the corresponding data block is not read and written normally.

[0082] against Figure 5 , taking the first logic 211, the second logic 212, the third logic 231, and the fourth logic 232 as XOR gates, the second operation unit 22 as an OR gate, the fourth operation unit 24 as an OR gate, and the third compression submodule 123 as an OR gate as an example. At this time, the first state, the third state, and the fifth state are all low levels, and the second state, the fourth state, and the sixth state are all high levels. Specifically, if DQ0_A[0] and DQ1_A[0] correspond differently, the corresponding first logic 211 outputs a high level, the second operation unit 22 outputs a high level, and the low-order compressed data is a high level. In other words, if the low-order compressed data is a high level, it indicates that there is a read / write error in the circuit portion corresponding to the storage block; otherwise, it indicates that there is no read / write error in the circuit portion corresponding to the storage block.

[0083] It should be understood that the structures of the second compression module 13 and the first compression module 12 are similar. Taking M=8, N=8 as an example, Figure 6 A specific structural schematic diagram of the second compression module 13 is shown.

[0084] like Figure 6 As shown, the fourth compression submodule 131 includes N fifth operation units 25 and 1 sixth operation unit 26 , and the fifth compression submodule 132 includes N seventh operation units 27 and 1 eighth operation unit 28 .

[0085] The i-th fifth operation unit 25 is configured to compare the i-th data signal DQ4_A[i] of the fourth first data group with the i-th data signal DQ5_A[i] of the fifth first data group to generate an i-th fifth result signal; and compare the i-th data signal DQ6_A[i] of the sixth first data group with the i-th data signal DQ7_A[i] of the seventh first data group to generate an i-th sixth result signal; the sixth operation unit 26 is connected to the N fifth operation units 25, and is configured to receive the N fifth result signals and the N sixth result signals; perform logic operations on the N fifth result signals and the N sixth result signals to generate third intermediate data;

[0086] The i-th seventh operation unit 27 is configured to compare the i-th data signal DQ4_B[i] of the fourth second data group with the i-th data signal DQ5_B[i] of the fifth second data group to generate the i-th seventh result signal; and compare the i-th data signal DQ6_B[i] of the sixth second data group with the i-th data signal DQ7_B[i] of the seventh second data group to generate the i-th eighth result signal; the eighth operation unit 28 is connected to the N fifth operation units 25, and is configured to receive N seventh result signals and N eighth result signals; perform logic operations on the N seventh result signals and the N eighth result signals to generate fourth intermediate data.

[0087] In some embodiments, Figure 6 As shown, each fifth operation unit 25 includes a fifth logic unit 251 and a sixth logic unit 252;

[0088] In the i-th fifth operation unit 25: the fifth logic device 251 is configured to receive the i-th data signal DQ4_A[i] of the fourth first data group and the i-th data signal DQ5_A[i] of the fifth first data group; if the received data signal levels are the same, the i-th fifth result signal of the first state is output; if the received data signal levels are different, the i-th fifth result signal of the second state is output; the sixth logic device 252 is configured to receive the i-th data signal DQ6_A[i] of the sixth first data group and the i-th data signal DQ7_A[i] of the seventh first data group; if the received data signal levels are the same, the i-th sixth result signal of the first state is output; if the received data signal levels are different, the i-th sixth result signal of the second state is output.

[0089] Correspondingly, the sixth operation unit 26 is configured to output the third intermediate data of the third state if the N fifth result signals and the N sixth result signals are all in the first state; if the N fifth result signals and the N sixth result signals are not all in the first state, output the third intermediate data of the fourth state.

[0090] In some embodiments, each seventh operation unit 27 includes a seventh logic device 271 and an eighth logic device 272. In the i-th seventh operation unit 27: the i-th seventh logic device 271 is configured to receive the i-th data signal DQ4_B[i] of the fourth second data group and the i-th data signal DQ5_B[i] of the fifth second data group; if the received data signal levels are the same, the i-th seventh result signal of the first state is output; if the received data signal levels are different, the i-th seventh result signal of the second state is output; the i-th eighth logic device 272 is configured to receive the i-th data signal DQ6_A[i] of the sixth second data group and the i-th data signal DQ7_A[i] of the seventh second data group; if the received data signal levels are the same, the i-th eighth result signal of the first state is output; if the received data signal levels are different, the i-th eighth result signal of the second state is output.

[0091] Correspondingly, the eighth operation unit 28 is configured to output fourth intermediate data of the third state if the N seventh result signals and the N eighth result signals are all in the first state; and to output fourth intermediate data of the fourth state if the N seventh result signals and the N eighth result signals are not all in the first state.

[0092] It should be noted that the fifth logic unit 251 , the sixth logic unit 252 , the seventh logic unit 271 , and the eighth logic unit 272 have the same structure as the first logic unit 211 , and the sixth operation unit 26 and the eighth operation unit 28 have the same structure as the second operation unit 22 .

[0093] In some embodiments, the sixth compression submodule 133 is configured to output high-bit compressed data of the fifth state if the third intermediate data and the fourth intermediate data are both in the third state; if the third intermediate data and the fourth intermediate data are not both in the third state, output high-bit compressed data of the sixth state.

[0094] It should be noted that the sixth compression submodule 133 has the same structure as the third compression submodule 123 .

[0095] In the above description, the first state is different from the second state, for example, the first state is a high level and the second state is a low level; or, the first state is a low level and the second state is a high level. Similarly, the third state is different from the fourth state, and the fifth state is different from the sixth state.

[0096] In this way, during the test process, if the high-order compressed data is in the fifth state, the circuit part representing the high-order data signal of the corresponding data block is working normally; if the high-order compressed data is in the sixth state, the circuit part representing the high-order data signal of the corresponding data block is not working normally.

[0097] against Figure 6 , taking the fifth logic 251, the sixth logic 252, the seventh logic 271, and the eighth logic 272 as XOR gates, the sixth operation unit 26 as an OR gate, the eighth operation unit 28 as an OR gate, and the sixth compression submodule 133 as an OR gate as an example. At this time, the first state, the third state, and the fifth state are all low levels, and the second state, the fourth state, and the sixth state are all high levels. Specifically, if DQ4_A[0] and DQ5_A[0] correspond differently, the corresponding fifth logic 251 outputs a high level, the sixth operation unit 26 outputs a high level, and the high-order compressed data is a high level. In other words, if the high-order compressed data is a high level, it indicates that there is a read / write error in the circuit portion corresponding to the storage block; otherwise, it indicates that there is no read / write error in the circuit portion corresponding to the storage block.

[0098] In some embodiments, the memory 10 further includes a decoding circuit;

[0099] A decoding circuit configured to decode the compressed read instruction to generate a row address signal group of each storage block 20 and a column address signal group of each storage block 20;

[0100] Among them, for the selected storage block 20, the corresponding part selection signal (X15) and the part selection complementary signal (X15B) in the row address signal group are both valid, the valid part selection signal is used to select the first storage half, and the valid part selection complementary signal is used to select the second storage half, so as to further enable the target word line in the selected storage half.

[0101] Specifically, in normal mode, the information carried by the row instruction is decoded to obtain the partial selection signal in the selected storage block 20, and the partial selection signal (X15) is level-inverted to generate the partial selection complementary signal (X15B), that is, at most only one of the partial selection signal (X15) and the partial selection complementary signal (X15B) is valid, that is, at most only one storage half in the same storage block 20 is selected, so 8 groups of data signals with a burst length of 8 are output, totaling 64-bit data signals; however, in the compressed read mode, for the storage block 20 selected by the compressed read instruction, its partial selection signal (X15) and the partial selection complementary signal (X15B) are both set to valid, that is, both storage halves in the selected storage block 20 are selected, so 16 groups of data signals with a burst length of 8 are output, totaling 128-bit data signals, and these 128-bit data signals are ultimately compressed into 1 low-bit data signal and 1 high-bit data signal, so the compression ratio is 64:1.

[0102] The disclosed embodiment provides a memory, in which, in a compressed read mode, for each selected storage block 20, two storage halves thereof are selected to output a plurality of first data groups and a plurality of second data groups, which is equivalent to doubling the burst length at each read, and can halve the number of read times required for traversal reading (i.e., the number of compressed read instructions), thereby reducing the test time; at the same time, the plurality of first data groups and the plurality of second data groups are compressed into high-order compressed data and low-order compressed data, thereby improving the data compression ratio and improving the overall test efficiency.

[0103] In yet another embodiment of the present disclosure, see Figure 7 , which shows a schematic flow chart of a compression reading method provided by an embodiment of the present disclosure. Figure 7 As shown, the method includes:

[0104] S401: when receiving a compression read instruction, for each selected storage block, read the first storage half thereof to generate a plurality of first data groups; and read the second storage half thereof to generate a plurality of second data groups;

[0105] S402: For each selected storage block, compress the first half of the first data group and the first half of the second data group to form low-order compressed data corresponding to the storage block; and compress the second half of the first data group and the second half of the second data group to form high-order compressed data corresponding to the storage block.

[0106] In this way, during the execution of the compressed read instruction, the two storage halves of the storage block each output a set of data signals, that is, the storage block outputs multiple first data groups and multiple second data groups, which is equivalent to doubling the burst length each time reading, and can halve the number of reads required for traversal reading (that is, the number of compressed read instructions), thereby reducing the test time; at the same time, multiple first data groups and multiple second data groups are compressed into high-order compressed data and low-order compressed data, the data compression ratio is improved, and the overall test efficiency is improved.

[0107] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: The memory comprises a plurality of memory blocks, and the memory performs compression reading on the selected memory blocks based on the compression read instruction, and each of the selected memory blocks outputs low-order compressed data and high-order compressed data; Each of the storage blocks includes two storage halves, and each of the storage blocks has a control circuit, a first compression module and a second compression module; wherein, The control circuit is connected to the corresponding storage block and is configured to read the first storage half in the storage block to generate a plurality of first data groups, and read the second storage half in the storage block to generate a plurality of second data groups; The first compression module is connected to the control circuit and is configured to receive and compress the first half of the first data group and the first half of the second data group to form the low-bit compressed data; The second compression module is connected to the control circuit and is configured to receive and compress the second half of the first data group and the second half of the second data group to form the high-bit compressed data.

2. The memory according to claim 1, characterized in that: Each of the storage halves includes M storage column groups, each storage column group includes a plurality of bit line groups, the number of the first data groups is M, and the number of the second data groups is M; The control circuit is specifically configured to read a selected bit line group in each storage column group in the first storage half to generate M first data groups when the target word line is turned on; and read a selected bit line group in each storage column group in the second storage half to generate M second data groups; Wherein, each bit line group has N bit lines, the first data group includes N-bit data, the second data group includes N-bit data, and N and M are both positive integers.

3. The memory according to claim 2, characterized in that: The first compression module comprises: A first compression submodule is configured to receive and compress the first M / 2 first data groups and output first intermediate data; A second compression submodule is configured to receive and compress the first M / 2 of the second data groups, and output second intermediate data; a third compression submodule, connected to both the first compression submodule and the second compression submodule, configured to receive the first intermediate data and the second intermediate data, perform compression processing on the first intermediate data and the second intermediate data, and output the low-bit compressed data; The second compression module comprises: a fourth compression submodule, configured to receive and compress the last M / 2 first data groups, and output third intermediate data; a fifth compression submodule, configured to receive and compress the last M / 2 second data groups, and output fourth intermediate data; The sixth compression submodule is connected to both the fourth compression submodule and the fifth compression submodule, and is configured to receive the third intermediate data and the fourth intermediate data, compress the third intermediate data and the fourth intermediate data, and output the high-bit compressed data.

4. The memory according to claim 3, characterized in that: The first compression submodule includes N first operation units and 1 second operation unit, and the second compression submodule includes N third operation units and 1 fourth operation unit; When M=8, The i-th first operation unit is configured to compare the i-th data signal of the 0th first data group with the i-th data signal of the 1st first data group to generate an i-th first result signal; and compare the i-th data signal of the 2nd first data group with the i-th data signal of the 3rd first data group to generate an i-th second result signal; i is a positive integer, and i≤N; The second operation unit is connected to the N first operation units and is configured to receive the N first result signals and the N second result signals; Performing a logic operation on the N first result signals and the N second result signals to generate the first intermediate data; The i-th third operation unit is configured to compare the i-th data signal of the 0-th second data group with the i-th data signal of the 1st second data group to generate an i-th third result signal; and compare the i-th data signal of the 2nd second data group with the i-th data signal of the 3rd second data group to generate an i-th fourth result signal; i is a positive integer, and i≤N; The fourth operation unit is connected to the N third operation units, and is configured to receive N third result signals and N fourth result signals; perform logic operations on the N third result signals and the N fourth result signals to generate the second intermediate data.

5. The memory according to claim 4, characterized in that: Each of the first operation units includes a first logic device and a second logic device; In the i-th first operation unit: The i-th first logic device is configured to receive the i-th data signal of the 0-th first data group and the i-th data signal of the 1st first data group; If the received data signals have the same level, outputting the i-th first result signal in the first state; If the received data signal levels are different, outputting the i-th first result signal in the second state; The i-th second logic device is configured to receive the i-th data signal of the second first data group and the i-th data signal of the third first data group; If the received data signal levels are the same, outputting the i-th second result signal of the first state; If the received data signal levels are different, outputting the i-th second result signal of the second state; The second operation unit is configured to output the first intermediate data in a third state if the N first result signals and the N second result signals are all in the first state; If the N first result signals and the N second result signals are not all in the first state, the first intermediate data in the fourth state is output.

6. The memory according to claim 5, characterized in that: Each of the third operation units includes a third logic device and a fourth logic device; In the i-th third operation unit: The i-th third logic device is configured to receive the i-th data signal of the 0-th second data group and the i-th data signal of the 1st second data group; If the received data signal levels are the same, outputting the i-th third result signal of the first state; If the received data signal levels are different, outputting the i-th third result signal of the second state; The i-th fourth logic device is configured to receive the i-th data signal of the second second data group and the i-th data signal of the third second data group; if the received data signal levels are the same, then output the i-th fourth result signal of the first state; if the received data signal levels are different, then output the i-th fourth result signal of the second state; The fourth operation unit is configured to output the second intermediate data in the third state if the N third result signals and the N fourth result signals are all in the first state; and to output the second intermediate data in the fourth state if the N third result signals and the N fourth result signals are not all in the first state.

7. The memory according to claim 6, characterized in that: The third compression submodule is configured to output the low-order compressed data in the fifth state if both the first intermediate data and the second intermediate data are in the third state; and to output the low-order compressed data in the sixth state if both the first intermediate data and the second intermediate data are not in the third state.

8. The memory according to claim 3, characterized in that: The fourth compression submodule includes N fifth operation units and 1 sixth operation unit, and the fifth compression submodule includes N seventh operation units and 1 eighth operation unit; When M=8, the i-th fifth operation unit is configured to compare the i-th data signal of the fourth first data group with the i-th data signal of the fifth first data group to generate an i-th fifth result signal; and compare the i-th data signal of the sixth first data group with the i-th data signal of the seventh first data group to generate an i-th sixth result signal; The sixth operation unit is connected to the N fifth operation units and configured to receive the N fifth result signals and the N sixth result signals; Performing a logic operation on the N fifth result signals and the N sixth result signals to generate the third intermediate data; the i-th seventh operation unit is configured to compare the i-th data signal of the fourth second data group with the i-th data signal of the fifth second data group to generate an i-th seventh result signal; and compare the i-th data signal of the sixth second data group with the i-th data signal of the seventh second data group to generate an i-th eighth result signal; The eighth operation unit is connected to the N fifth operation units, and is configured to receive the N seventh result signals and the N eighth result signals; perform logic operations on the N seventh result signals and the N eighth result signals to generate the fourth intermediate data.

9. The memory according to claim 8, characterized in that: Each of the fifth operation units includes a fifth logic device and a sixth logic device; In the i-th fifth operation unit: The fifth logic device is configured to receive the i-th data signal of the fourth first data group and the i-th data signal of the fifth first data group; if the received data signal levels are the same, output the i-th fifth result signal of the first state; if the received data signal levels are different, output the i-th fifth result signal of the second state; The sixth logic device is configured to receive the i-th bit data signal of the sixth first data group and the i-th bit data signal of the seventh first data group; if the received data signal levels are the same, output the i-th sixth result signal of the first state; if the received data signal levels are different, output the i-th sixth result signal of the second state; The sixth operation unit is configured to output the third intermediate data in the third state if the N fifth result signals and the N sixth result signals are all in the first state; and to output the third intermediate data in the fourth state if the N fifth result signals and the N sixth result signals are not all in the first state.

10. The memory according to claim 9, characterized in that: Each of the seventh operation units includes a seventh logic device and an eighth logic device; In the ith seventh operation unit: The i-th seventh logic device is configured to receive the i-th data signal of the fourth second data group and the i-th data signal of the fifth second data group; If the received data signal levels are the same, outputting the i-th seventh result signal of the first state; If the received data signal levels are different, outputting the i-th seventh result signal of the second state; The i-th eighth logic device is configured to receive the i-th data signal of the sixth second data group and the i-th data signal of the seventh second data group; if the received data signals have the same level, output an i-th eighth result signal of the first state; If the received data signal levels are different, outputting the i-th eighth result signal of the second state; The eighth operation unit is configured to output the fourth intermediate data in the third state if the N seventh result signals and the N eighth result signals are all in the first state; and to output the fourth intermediate data in the fourth state if the N seventh result signals and the N eighth result signals are not all in the first state.

11. The memory according to claim 10, characterized in that: The sixth compression submodule is configured to output the high-bit compressed data in the fifth state if the third intermediate data and the fourth intermediate data are both in the third state; if the third intermediate data and the fourth intermediate data are not both in the third state, output the high-bit compressed data in the sixth state.

12. The memory according to any one of claims 1 to 11, characterized in that: The memory also includes a decoding circuit; The decoding circuit is configured to decode the compressed read instruction to generate a row address signal group of each storage block and a column address signal group of each storage block; Among them, for the selected storage block, the corresponding part selection signal and part selection complementary signal in the row address signal group are both valid, the valid part selection signal is used to select the first storage half, and the valid part selection complementary signal is used to select the second storage half.

13. A compression reading method, characterized in that: Applied to a memory, wherein the memory includes multiple memory blocks, each memory block includes two memory halves, and the method includes: When a compression read instruction is received, for each selected storage block, the first storage half is read to generate a plurality of first data groups; and the second storage half is read to generate a plurality of second data groups; For each selected storage block, the first data group in the first half and the second data group in the first half are compressed to form low-order compressed data corresponding to the storage block; and the first data group in the second half and the second data group in the second half are compressed to form high-order compressed data corresponding to the storage block.

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