Chip packaging method

Abstract

The invention provides a chip packaging method, which comprises a chip positioning step and a chip routing step, and the chip positioning step comprises the following steps: providing a positioning platform provided with a flange structure; assembling a plurality of chips on the elastic part of the carrier plate; the carrier plate drives the chip to move towards the flange structure, when one side of the chip is in contact with the flange structure, the flange structure provides limiting, and the elastic part provides elastic buffering towards the flange structure for the chip so as to reduce the chip edge breakage probability and make up for the chip mounting position error at the same time. Therefore, the routing process error of a plurality of chips subjected to routing through the flange side of the flange structure is reduced, the routing error among all chips produced in a large scale is reduced to the minimum, and the consistency of chip routing is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor packaging, and in particular relates to a chip packaging method. Background Art

[0002] The chip packaging process is a key link in the semiconductor manufacturing process to protect the chip from physical and chemical damage. At present, the mainstream chip (such as image sensor chip, etc.) is usually packaged with COM (Chip on Module) for two-solder-point hanging wire packaging. In the COM packaging process, the positioning of the chip mainly depends on the suction nozzle to absorb the back of the chip. The nozzle is used to pick up and place the chip on the wire bonding platform, and then the push rod is used to fix the limit to complete the chip positioning step.

[0003] However, due to the limited accuracy of the nozzle in picking up and placing the chip, the chip positioning is not accurate enough, which in turn causes poor consistency in wire bonding on both sides of the chip, reducing the linear consistency of the wires led out on both sides of a single chip. At the same time, since the mounting of each chip and the mounting of other chips usually occur at different times (for example, two chips mounted twice in the same position) or in different positions (for example, two chips in the front and back rows of the same column are mounted at the same time), there are errors in the placement positions of different chips. Such position errors will cause wire bonding errors between different chips after subsequent wire bonding. In addition, using a push rod to fix the chip may cause damage to the edge of the chip, resulting in edge collapse. Therefore, it is urgent to introduce a new chip packaging method to improve the positioning consistency of the chip on the wire bonding platform and reduce the risk of chip edge collapse. Summary of the invention

[0004] The purpose of the present invention is to provide a chip packaging method to reduce the probability of chip edge collapse and compensate for chip positioning errors, thereby reducing chip wire bonding process errors and improving the linear stability and consistency of chip wires.

[0005] To achieve the above-mentioned purpose, the present invention provides a chip packaging method, which includes a chip positioning step and a chip bonding step, and the chip positioning step includes: providing a positioning platform provided with a side guard structure; assembling a plurality of chips on the elastic portion of a carrier; the carrier drives the chip to move toward the side guard structure, and when one side of the chip contacts the side guard structure, the side guard structure provides a limit, and the elastic portion provides an elastic buffer for the chip toward the side guard structure to reduce the probability of chip edge collapse while compensating for the chip mounting position error, thereby reducing the bonding process error of a plurality of chips that stop at the side guard side of the side guard structure to complete bonding.

[0006] Optionally, the retaining edge structure is provided for a row of chips, so that the carrier gradually moves toward the retaining edge structure to complete the wire bonding process of a number of the chips row by row.

[0007] Optionally, the carrier drives the chip to move toward the sidewall structure, specifically comprising the following steps:

[0008] S11, the positioning platform moves downward to separate the carrier plate from the positioning platform;

[0009] S12, the carrier plate moves toward the sidewall structure at a first speed by a first distance to reach a first position;

[0010] S13, the positioning platform moves upward, so that the bottom surface of the carrier plate and the positioning platform contacting the chip is not higher than the top of the retaining edge structure;

[0011] S14, the carrier moves toward the sidewall structure at a second speed and a second distance, so that one side of the chip contacts the sidewall structure.

[0012] Optionally, step S12 further includes determining whether the carrier plate has reached the first position by identifying a marking portion on the carrier plate.

[0013] Optionally, if the identification portion on the carrier is recognized, it is determined that the carrier has reached the first position and S13 is executed; if the identification portion on the carrier is not recognized, it is determined that the carrier has not reached the first position, and the carrier moves a third distance toward the retaining edge structure at a first speed so that the carrier reaches the first position.

[0014] Optionally, the first speed is greater than the second speed.

[0015] Optionally, after the chip is docked on the sidewall of the sidewall structure, the chip is adsorbed and fixed on the sidewall of the sidewall structure by adsorbing the elastic part through an adsorption device.

[0016] Optionally, after the chip rests on the sidewall of the sidewall structure, a pressing plate located above the carrier plate presses downward to fix the carrier plate.

[0017] Optionally, the carrier plate includes a length direction and a width direction, the elastic parts are evenly arranged along the length direction and the width direction, the length direction is a direction toward the sidewall structure, and the width direction is perpendicular to the length direction.

[0018] Optionally, when the carrier moves along the length direction, the chip positioning process is sequentially performed on a plurality of chips mounted on each column of elastic parts uniformly arranged along the width direction.

[0019] Optionally, in the horizontal plane, the elastic part forms hollow areas arranged in an array, and a number of chips are arranged in rows and / or columns in the non-hollow areas of the elastic part, wherein both sides of the carrier of each chip in the movement direction are the hollow areas.

[0020] Optionally, a first marker is provided on the chip and a second marker is provided on the wire cutting knife. After the wire bonding device identifies the first marker, it leads out a wire with a predetermined direction from the position specified by the first marker until the second marker is identified and the wire cutting knife cuts the wire at the position specified by the second marker, so as to form a wire with one end hanging in the air.

[0021] Optionally, the retaining edge structure includes the retaining edge side and the guide side which are arranged relatively to each other, the retaining edge side is a vertical surface for providing a restraining force to limit the position of the chip; the guide side is an inclined surface for preventing the wire bonding device from pulling the wire to form the wire with one end suspended.

[0022] Optionally, the elastic portion is a high temperature resistant tape.

[0023] Compared with the prior art, a chip packaging method provided by the present invention has at least the following beneficial effects: the core is driven to move toward the side guard structure by a carrier plate, and when one side of the chip contacts the side guard structure, the side guard structure provides a limit, so that the elastic part is deformed and provides elastic force buffering for the chip toward the side guard structure, which reduces the probability of chip edge collapse on the one hand, and compensates for the chip mounting position error on the other hand through the side guard structure.

[0024] Furthermore, by arranging the sidewall structures in a row, the positioning consistency of chips in the same batch is ensured, while the positioning errors of chips in different batches are also reduced, thereby reducing the wire bonding process errors of several chips that stop at the sidewall side of the sidewall structure to complete wire bonding, ensuring that the wire bonding errors between all chips produced in large quantities are minimized, thereby improving the consistency of the wire bonding process and the wire bonding efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a chip packaging method according to an embodiment of the present invention;

[0026] Figure 2 A top view of the structure of a chip packaging system of the present invention that can implement the chip packaging method;

[0027] Figure 3 for Figure 2 An enlarged three-dimensional schematic diagram of the middle frame A;

[0028] Figure 4 for Figure 3 An enlarged cross-sectional schematic diagram of the middle frame B;

[0029] Figure 5 for Figure 2 A top view of a carrier board in a chip packaging system is shown. DETAILED DESCRIPTION

[0030] The following will be combined with the attached embodiment of the present invention Figure 1 ~Attached Figure 5 , the technical solutions, structural features, objectives achieved and effects in the embodiments of the present invention are described in detail.

[0031] It should be noted that the drawings are in a very simplified form and use non-precise proportions. They are only used to conveniently and clearly assist in explaining the embodiments of the present invention, and are not used to limit the conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention.

[0032] It should be noted that, in the present invention, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or equipment including a series of elements includes not only the elements explicitly listed, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment.

[0033] In order to improve the consistency of positioning of chips in the same batch and / or different batches during chip packaging and reduce the risk of chip edge collapse, an embodiment of the present invention provides a chip packaging method, please refer to Figure 1 to Figure 4As shown, the chip packaging method includes a chip positioning step S1 and a chip wire bonding step S2, wherein the chip positioning step S1 includes: providing a positioning platform 101 provided with a retaining edge structure 111, wherein the positioning platform 101 can move upward or downward in a vertical direction; assembling a plurality of chips 200 on an elastic portion 121 of a carrier 102, wherein the carrier 102 can move in a horizontal direction; wherein the carrier 102 drives the chip 200 to move toward the retaining edge structure 111, and when one side of the chip 200 contacts the retaining edge structure 111, the retaining edge structure 111 provides a limit position so that the chip 200 is 200 is docked on the side of the sidewall structure 111. When the chip 200 is limited by the sidewall structure 111, the elastic part 121 is deformed, so that the elastic part 121 can provide elastic buffering to the chip 200 toward the sidewall structure 111, so as to reduce the probability of chip 200 breaking. At the same time, the synergistic effect of the sidewall structure 111 and the elastic part 121 compensates for the mounting position error of the chip 200, thereby reducing the wire bonding process error between the multiple chips 200 that stop at the side of the sidewall structure 111 to complete the wire bonding, and improving the wire bonding consistency of mass-produced chips. Preferably, the elastic part 121 is a high temperature resistant tape; preferably, the high temperature resistant tape used to form the multiple elastic parts 121 can be replaced, for example Figure 5 As shown, the high temperature tape with a plurality of chips 200 mounted thereon is mounted on the lower surface of the carrier 102 , and a plurality of hollow holes of the carrier expose the plurality of chips 200 and a portion of the elastic portion 121 .

[0034] Among them, Figure 2 to Figure 4 As shown, the retaining edge structure 111 is set for a row of chips 200, so that the carrier 102 gradually moves toward the retaining edge structure 111 to complete the wire bonding process of several chips 200 row by row. By arranging the retaining edge structure 111 in a row, the number of chips 200 processed in the same batch is increased, that is, multiple chips 200 can be positioned and wire bonded at the same time, which improves the consistency of positioning and wire bonding of chips in the same batch (i.e., in the same row), and improves the chip processing efficiency. At the same time, due to the synergistic effect of the retaining edge structure 111 and the elastic part 121, the retaining edge structure 111 provides a stable position to provide precise positioning, and the elastic part 121 provides an elastic buffer to adjust the mounting position of the chip, thereby synergistically further ensuring the consistency of positioning and wire bonding of chips in the same batch or even different batches (i.e., in different rows), so that the wire bonding error between all chips 200 produced in large quantities can be minimized, and the consistency of the wire bonding process of the chip 200 can be improved.

[0035] Furthermore, in order to keep consistent with the structure of the sidewall structure 111 arranged in a row and improve the chip bonding efficiency, as shown in FIG. Figure 2 and Figure 5As shown, the carrier 102 includes a length direction L and a width direction W, and the elastic parts 121 are evenly arranged along the length direction L and the width direction W. The length direction L is the direction toward the sidewall structure 111, and the width direction W is perpendicular to the length direction L. Specifically, in this embodiment, the carrier 102 has 4 elastic parts 121 in the width direction W and 12 elastic parts 121 in the length direction L, that is, the carrier 102 can load 48 chips 200 at most at the same time. When the carrier 102 moves along the length direction L, the chip positioning process is sequentially performed on a plurality of chips 200 assembled on the elastic parts 121 evenly arranged in each column along the width direction W, so that the chips 200 in the same column can be docked on the sidewall of the sidewall structure 111, and the positioning error between the chips 200 in the same column is reduced to a minimum, and after each positioning is completed, the 4 chips 200 in the width direction can be wired, which greatly improves the wire bonding efficiency and reduces the wire bonding error. In other embodiments, the number of the elastic portions 121 may be greater than 48, and the arrangement thereof is not limited to the above-mentioned arrangement of 4 in the width direction.

[0036] like Figure 2 , Figure 3 and Figure 5 As shown, on the horizontal plane of the carrier 102, the elastic part 121 is formed with hollow areas 123 arranged in an array, and the hollow areas 123 are used to provide space for the retaining edge structure 111 to move upward or downward, so that the retaining edge structure 111 is higher than the chip 200 or lower than the carrier 102. Further, a plurality of the chips 200 are arranged in rows and / or columns in the non-hollow areas of the elastic part 121, wherein both sides of each chip 200 in the moving direction of the carrier 102 are the hollow areas 123. When the side guard structure 111 passes through the hollow area 123 and moves upward to be higher than the chip 200, the carrier 102 drives the chip 200 to move toward the side guard structure 111, and the side guard side of the side guard structure 111 can provide a limit for the chip 200; when the side guard structure 111 moves downward from the hollow area 123 to be lower than the carrier 102, the side guard mechanism 111 will not affect the horizontal movement of the carrier 102.

[0037] The carrier 102 drives the chip 200 to move toward the edge structure 111, which specifically includes the following steps:

[0038] S11, the positioning platform 101 moves downward to separate the carrier 102 from the positioning platform 101, so as to prevent the retaining edge structure 111 on the positioning platform 101 from hindering the horizontal movement of the carrier 102;

[0039] S12, the carrier 102 moves a first distance at a first speed toward the sidewall structure 111 to reach a first position, i.e., the rough positioning of the chip 200 is completed, so that the chip 200 reaches the vicinity of the sidewall structure 111 to improve the positioning efficiency;

[0040] S13, the positioning platform 101 moves upward, so that the bottom surface of the carrier 102 and the positioning platform 101 contacting the chip 200 is not higher than the top of the retaining edge structure 111, so that the edge of the chip 200 is at least partially opposite to the retaining edge structure 111;

[0041] S14, the carrier 102 moves toward the retaining edge structure 111 at a second speed and a second distance, so that one side of the chip 200 contacts the retaining edge structure 111, so that each chip 200 is parked on one side of the retaining edge structure 111, and the precise positioning of the chip 200 is completed. Figure 4 shown.

[0042] Among them, the first speed in step S12 is greater than the second speed in step S14. This is because the first speed is used to transfer the chip 200 to the vicinity of the retaining edge structure 111, and the chip 200 does not contact the retaining edge structure 111, so setting the first speed faster can improve the chip transmission efficiency; and setting the second speed to be less than the first speed, and setting the second speed as slow as possible under the premise of satisfying the transmission efficiency, can effectively reduce the collision force when the chip 200 contacts the retaining edge structure 111, thereby reducing the possibility of edge collapse at the edge of the chip 200. At the same time, slowing down the second speed can cause the elastic part 121 to deform slowly, thereby providing a more sufficient elastic buffer for the chip 200, reducing the reaction force of the retaining edge structure 111 on the chip 200, and further reducing the risk of edge collapse at the edge of the chip 200.

[0043] Wherein, step S12 also includes determining whether the carrier 102 has reached the first position by identifying the identification portion 122 on the carrier 102. Specifically, if the identification portion 122 on the carrier 102 is identified, it is determined that the carrier 102 has reached the first position, and the step S13 is executed; if the identification portion 122 on the carrier 102 is not identified, it is determined that the carrier 102 has not reached the first position, and the carrier 102 moves toward the retaining edge structure 111 at a first speed for a third distance, so that the carrier 102 reaches the first position. In this embodiment, if Figure 5 As shown, the identification portion 122 is two holes diagonally arranged on both sides of the elastic portion 121. In other embodiments, it can also be other easily identifiable marking patterns, grooves, protrusions or irregular shapes, which is not limited to the present invention.

[0044] Further, if Figure 4 As shown, the positioning platform 101 is provided with an adsorption device 113, which is located on the side of the sidewall structure 111 and below the elastic part 121. When the chip 200 is docked on the sidewall of the sidewall structure 111, the elastic part 121 is adsorbed and fixed on the sidewall of the sidewall structure 111 by the adsorption device 113, so as to prevent the chip from being displaced during the bonding step. The sidewall of the sidewall structure 111 is a vertical surface, which is used to provide a restraining force to limit the position of the chip 200, so that the chip 200 is docked on the same straight line, thereby improving the bonding error between all chips 200 in the same column or different columns.

[0045] Among them, Figure 1 As shown, a pressing plate 103 is further provided above the carrier 102, and the pressing plate 103 can abut against the upper surface of the carrier 102. A window area 131 is also provided on the pressing plate 103. In this embodiment, the window area 131 extends along the width direction W of the carrier 102, and is used to expose the elastic parts 121 equipped with the chips 200 arranged in an array along the width direction on the carrier 102. Specifically, when the chip 200 is docked on the side of the sidewall structure 111, the pressing plate 103 located above the carrier 102 presses and fixes the carrier 102 downward, so that the carrier 102 and the positioning platform 101 remain relatively still.

[0046] like Figure 3 and Figure 4 As shown, after the chip 200 is docked on the side of the sidewall structure 111, the chip bonding step S2 is performed. The chip bonding step S2 refers to leading out at least one wire 300 from the chip. The wire 300 is used to connect with the external substrate circuit. The chip bonding step S2 is implemented by a bonding device (not shown) located above the carrier 102. A wire cutter 112 is also provided on the positioning platform 101 to cut the wire 300 to complete the two-weld point hanging bonding process, that is, one end of the wire 300 is bonded to the chip 200, and the other end of the wire 300 is suspended. Further, since both pairs of edges of the chip 200 need to be bonded, that is, the first edge opposite to the sidewall structure 111 and the second edge arranged parallel to the first edge, the wire cutter 112 is provided on both sides of the adsorption device 113.

[0047] Specifically, the chip 200 is provided with a first mark 201, and the first mark 201 is used to guide the movement of the wire bonding device. The wire cutting knife 112 is provided with a second mark (not shown in the figure). After the wire bonding device recognizes the first mark 201, it leads out a wire with a predetermined direction from the position specified by the first mark 201 until the wire cutting knife 112 cuts the wire at the position specified by the second mark after recognizing the second mark, so as to form a wire 300 with one end suspended. The wire 300 with one end suspended has a certain hardness, and the material of the wire 300 can be a conductive material such as gold, silver or copper, and the suspended end of the wire 300 can be fixed on the substrate containing the circuit by solder paste or other welding methods.

[0048] Further, if Figure 4 As shown, the retaining edge structure 111 also includes a guide side arranged opposite to the retaining edge side, and the guide side is an inclined surface for preventing the wire punching device from pulling the wire 300 so as to form the wire 300 with one end suspended. This is because the diameter of the wire 300 is relatively thin and has one suspended end. Therefore, setting the guide side of the retaining edge structure 111 as an inclined surface can prevent the wire 300 from hitting the retaining edge structure 111 and causing damage to the wire 300.

[0049] In summary, the chip packaging method provided by the present invention drives the chip 200 to move toward the edge structure 111 through the carrier 102. When one side of the chip 200 contacts the edge structure 111, the edge structure 111 provides a limit, so that the elastic part 121 is deformed and provides elastic buffering for the chip 200 toward the edge structure 111, thereby reducing the probability of edge collapse of the chip 200 and compensating for the mounting position error of the chip 200.

[0050] Furthermore, by arranging the sidewall structures in a row, the positioning consistency of the chips in the same batch is ensured, while the positioning errors of the chips in different batches are also reduced, thereby reducing the wire bonding process errors of several chips 200 that have stopped at the sidewall side of the sidewall structure 111 to complete the wire bonding, ensuring that the wire bonding errors between all chips 200 produced in large quantities are minimized, thereby improving the consistency of the wire bonding process and the wire bonding efficiency.

[0051] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A chip packaging method, characterized in that: The method comprises a chip positioning step and a chip bonding step, wherein the chip positioning step comprises: Providing a positioning platform with a retaining edge structure; Mounting a plurality of chips on the elastic portion of the carrier; The carrier drives the chip to move toward the side guard structure. When one side of the chip contacts the side guard structure, the side guard structure provides a limit. The elastic part provides elastic buffering for the chip toward the side guard structure to reduce the probability of chip edge collapse while compensating for the chip mounting position error, thereby reducing the wire bonding process error of several chips that stop at the side guard structure to complete wire bonding.

2. The chip packaging method according to claim 1, characterized in that: The retaining edge structure is arranged for a row of chips, so that the carrier gradually moves toward the retaining edge structure to complete the wire bonding process of a plurality of the chips row by row.

3. The chip packaging method according to claim 1, characterized in that: The carrier drives the chip to move toward the edge structure, which specifically includes the following steps: S11, the positioning platform moves downward to separate the carrier plate from the positioning platform; S12, the carrier plate moves toward the sidewall structure at a first speed by a first distance to reach a first position; S13, the positioning platform moves upward, so that the bottom surface of the carrier plate and the positioning platform contacting the chip is not higher than the top of the retaining edge structure; S14, the carrier moves toward the sidewall structure at a second speed and a second distance, so that one side of the chip contacts the sidewall structure.

4. The chip packaging method according to claim 3, characterized in that: Step S12 also includes determining whether the carrier plate has reached the first position by identifying a marking portion on the carrier plate.

5. The chip packaging method according to claim 4, characterized in that: If the identification portion on the carrier is recognized, it is determined that the carrier has reached the first position, and S13 is executed; If the identification portion on the carrier is not identified, it is determined that the carrier has not reached the first position, and the carrier moves toward the sidewall structure at a first speed for a third distance, so that the carrier reaches the first position.

6. The chip packaging method according to claim 3, characterized in that: The first speed is greater than the second speed.

7. The chip packaging method according to claim 1, characterized in that: When the chip is parked on the side of the sidewall structure, the chip is adsorbed and fixed on the sidewall structure by adsorbing the elastic part through an adsorption device.

8. The chip packaging method according to claim 1 or 7, characterized in that: After the chip is parked on the side of the rib structure, the pressing plate located above the carrier plate is pressed downward to fix the carrier plate.

9. The chip packaging method according to claim 1, characterized in that: The carrier plate includes a length direction and a width direction, and the elastic parts are evenly arranged along the length direction and the width direction. The length direction is a direction toward the sidewall structure, and the width direction is perpendicular to the length direction.

10. The chip packaging method according to claim 9, characterized in that: When the carrier moves along the length direction, the chip positioning process is sequentially performed on a plurality of chips mounted on each column of elastic parts uniformly arranged along the width direction.

11. The chip packaging method according to claim 9, characterized in that: In the horizontal plane, the elastic part forms hollow areas arranged in an array, and a number of chips are arranged in rows and / or columns in the non-hollow areas of the elastic part, wherein both sides of the carrier of each chip in the moving direction are the hollow areas.

12. The chip packaging method according to claim 1, characterized in that: A first mark is provided on the chip, and a second mark is provided on the wire cutting knife. After the wire bonding device identifies the first mark, it leads out a wire with a predetermined direction from the position specified by the first mark until the wire cutting knife cuts the wire at the position specified by the second mark after identifying the second mark, so as to form a wire with one end hanging in the air.

13. The chip packaging method according to claim 12, characterized in that: The retaining edge structure includes the retaining edge side and the guide side which are arranged relatively to each other. The retaining edge side is a vertical surface for providing a restraining force to limit the position of the chip; the guide side is an inclined surface for preventing the wire bonding device from pulling the wire so as to form the wire with one end suspended.

14. The chip packaging method according to claim 1, characterized in that: The elastic part is a high temperature resistant adhesive tape.

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