SPIR-V-based inter-thread shared memory processing method

Abstract

The invention is suitable for the technical field of GPU (Graphics Processing Unit), and provides an SPIR-V-based inter-thread shared memory processing method, which comprises the following steps of: S1, reading a high-level language code source code to a character buffer area, and then converting the source code in the character buffer area into an intermediate code in an SPIR-V form; s2, traversing an instruction sequence of an intermediate code, and for variable declarations in the instruction sequence, accumulating the sum of occupied spaces of all shared memory variables; s3, calculating a one-dimensional index and a shared memory address of the thread group; and S4, traversing the instruction sequence of the intermediate code, and for instructions in the function declaration and the function definition, if processing of a shared memory is involved, calculating a real address and generating different GPU instructions according to instruction types. The invention provides a universal method for translating related codes, used for processing a shared memory of a working group, in SPIR-V codes into basic instructions of all GPU architectures, and the instructions used in the method are basic instructions of all GPU instruction sets, so that the method has hardware platform universality.

Description

Technical Field

[0001] The present invention belongs to the field of GPU technology, and in particular relates to a SPIR-V-based method for processing shared memory between threads. Background Art

[0002] SPIR-V (Standard Portable Intermediate Representation-Vulkan) is an intermediate language developed by the Khronos organization for parallel computing and graphics. SPIR-V can be converted from a variety of high-level language codes, such as codes written in OpenCL (Open Computing Language), OpenGL (OpenGraphics Library), Vulkan (a cross-platform 2D and 3D graphics application programming interface) and other standards.

[0003] With the introduction of SPIR-V, developers no longer need to provide a parser for each language during compiler program development. Instead, they convert high-level language codes into SPIR-V codes and then perform post-processing on the SPIR-V codes, which facilitates cross-language compiler program development. Today, the SPIR-V standard has become an increasingly integral part of the modern GPU software ecosystem.

[0004] SPIR-V supports basic and advanced features of different high-level languages, including compute shaders, parallel computing, and memory management operations. In order to support parallel computing features in different languages, the SPIR-V standard introduces the concept of workgroup, which refers to a group of threads that perform computing tasks simultaneously. In order to facilitate data exchange and communication, threads in a workgroup can share a specific memory area, which is called shared memory. In addition, in order to ensure collaboration and data consistency between threads, the SPIR-V instruction set also provides OpControlBarrier instructions for synchronization between threads. In order to fully support the SPIR-V standard, the SPIR-V code used to process the shared memory of the workgroup needs to be converted into target code supported by the GPU hardware and maintain the same semantics.

[0005] As a standardized intermediate form, SPIR-V cannot be executed directly on the GPU. It needs to be converted into a GPU instruction sequence of a specific hardware architecture before it can be executed in the GPU. In order to make the converted GPU instruction sequence fully support the shared memory characteristics of SPIR-V in the field of parallel computing, it is necessary to complete the allocation of shared memory space and map the SPIR-V instructions that use shared memory variables to GPU instructions. Since the instruction level of the GPU is lower than that of SPIR-V, a one-to-one mapping relationship cannot be formed. During the conversion process, the SPIR-V instructions must be split to generate multiple GPU instructions to achieve consistent functions. At present, no relevant technical solutions have been disclosed. Summary of the invention

[0006] In view of the above problems, the purpose of the present invention is to provide a method for processing shared memory between threads based on SPIR-V, aiming to solve the technical problem of how to translate the instructions for processing shared memory in the SPIR-V code into a GPU instruction sequence with the same semantics after the high-level language code is converted into the SPIR-V code.

[0007] The present invention adopts the following technical solution:

[0008] The SPIR-V-based inter-thread shared memory processing method comprises the following steps:

[0009] Step S1, reading the high-level language code source into the character buffer, and then converting the source code in the character buffer into an intermediate code in the SPIR-V format;

[0010] Step S2, traverse the instruction sequence of the intermediate code, for the variable declaration therein, if the storage class of the variable is a work group, then the current variable is identified as a shared memory variable, the size of the space occupied by the variable is calculated, and the variable offset is recorded at the same time, and finally the total size of the space occupied by all shared memory variables is accumulated;

[0011] Step S3, according to the total size of the occupied space, calculate the size of the shared memory space to be allocated and obtain the base address, by calculating the one-dimensional index of the thread group, and calculating the shared memory address of the thread group according to the one-dimensional index, the total size of the occupied space, and the base address;

[0012] Step S4, traverse the instruction sequence of the intermediate code, and for the instructions in the function declaration and function definition, if they involve the processing of shared memory, calculate the real address and generate different GPU instructions according to the instruction type.

[0013] Furthermore, the specific process of step S2 is as follows:

[0014] S21, traversing the instruction sequence of the intermediate code, wherein the OpVariable instruction is used for variable declaration, for the variable declaration, determining whether the storage class of the OpVariable instruction is a workgroup, if so, it indicates that the variable declared by the variable declaration is a shared memory variable;

[0015] S22. Calculate the space size S of the declared variable according to the type of the operand in the OpVariable instruction i , where if the type declaration is OpTypeVoid, it does not occupy storage space, S i 0 if the type declaration is a primitive type, S i The specific size of the space occupied by this primitive type. If the type declaration is a composite data type, S i The specific space occupied by this composite type;

[0016] S23. Calculate the total size of all shared memory variables n is the number of shared memory variables. In addition, the variable offset of the shared memory variable is recorded synchronously. k , the kth shared memory variable, its variable offset That is, it is equal to the sum of the space occupied by all previous variables of the current shared memory variable.

[0017] Furthermore, the specific process of step S3 is as follows:

[0018] S31. Calculate the size of the shared memory space to be allocated SmTotalSize, SmTotalSize = S total ×GroupNum, where GroupNum is the number of all thread groups. A region of size SmTotalSize is allocated in the GPU memory for shared memory space. The base address of the region is SmBaseAddr.

[0019] S32, by generating a GPU instruction to calculate the one-dimensional index GroupIndex of the thread group, assuming that the index of the thread group in each dimension is i1, i2, ..., i d , and the maximum thread group size in each dimension is n1,n2,…,n d , then the one-dimensional index GroupIndex of the thread group is:

[0020] GroupIndex=i1+n1×(i2+n2×(i3+…+n d-2 ×(i d-1 +n d-1 ×i d )…));

[0021] S33, calculate the shared memory address of the thread group in the shared memory space, that is, the starting address SmAddr = GroupIndex × S total +SmBaseAddr.

[0022] Furthermore, in step S4, different GPU instructions are generated according to the instruction type, including OpLoad instructions, OpStore instructions, and OpControlBarrier instructions, wherein the OpLoad instruction is used for memory reading, the OpStore instruction is used for memory writing, and the OpControlBarrier instruction is used to control the synchronization of memory access and memory barriers:

[0023] For the OpLoad instruction, before generating it, calculate the real address of the instruction realAddr = offset k +SmAddr, the pointer operand of the OpLoad instruction comes directly from the return value of the OpVariable instruction, and the address read by the OpLoad instruction is realAddr; if the pointer operand of the OpLoad instruction comes from the return value of the SPIR-V chain operation instruction, the address offset is recursively calculated through the base address and index of the chain operation instruction, and the address offset plus realAddr is used as the address read by the OpLoad instruction;

[0024] For the OpStore instruction, whether it writes data to the shared memory space is determined by whether the storage class of the pointer operand of the OpStore instruction is a working group. The method of calculating the real address is the same as that of the OpLoad instruction.

[0025] For the OpControlBarrier instruction, according to the execution scope and memory scope synchronized by the OpControlBarrier instruction, the corresponding GPU barrier instruction Barrier is generated to ensure the correct synchronization of the thread group.

[0026] The beneficial effects of the present invention are as follows: the present invention converts the high-level language code source code into SPIR-V code, traverses the variable declaration instructions, and accurately calculates the total amount of shared memory space used according to the data type of each variable, thereby reducing memory waste when accurately allocating space; and at the same time, adds a GPU instruction to the GPU instruction sequence header, so that the shared memory address of the thread group is calculated before the thread executes the operation, which is used to calculate the real address in the subsequent instruction translation, thereby reducing repeated calculations. Since the instructions used in the present invention are all basic instructions in all GPU instruction sets, the method of the present invention has universality of hardware platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a flowchart of a SPIR-V-based inter-thread shared memory processing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] In order to solve the problem of how to convert the SPIR-V code for processing shared memory into a GPU instruction sequence with equivalent functions after converting the high-level language code into the SPIR-V intermediate code. The present invention provides a method for processing shared memory between threads based on SPIR-V. The method first analyzes the variable declaration of the shared memory variables used in the SPIR-V code, then calculates the total size of the occupied space and allocates the shared memory space in the hardware, generates a GPU instruction and places it in the sequence header for calculating the shared memory address, and finally converts the instructions for reading, writing and synchronizing the shared memory in the SPIR-V code into GPU instructions with equivalent semantics. The generated GPU instructions are basic instructions in all GPU instruction sets, including MUL (multiplication), ADD (addition), LOAD (memory read) and STORE (memory write). In order to illustrate the technical solution described in the present invention, it is described below through specific embodiments.

[0030] like Figure 1 As shown, this embodiment provides a method for processing shared memory between threads based on SPIR-V, comprising the following steps:

[0031] Step S1, read the high-level language code source into the character buffer, and then convert the source code in the character buffer into an intermediate code in the SPIR-V format.

[0032] First, the host program reads the high-level language code from a file or other source into a character buffer, and then converts the source code in the character buffer into an intermediate code in the SPIR-V format. SPIR-V instructions must be arranged in a specified order, converting the source code into an intermediate code in the SPIR-V format to form a SPIR-V instruction sequence.

[0033] Step S2, traverse the instruction sequence of the intermediate code, for the variable declaration therein, if the storage class of the variable is a working group, the current variable is identified as a shared memory variable, the size of the space occupied by the variable is calculated, and the variable offset is recorded at the same time, and finally the total size of the space occupied by all shared memory variables is accumulated.

[0034] SPIR-V instructions consist of a series of precisely arranged binary data streams, each word contains 32 bits, follows the little-endian byte order, and each instruction consists of one or more words. Each instruction in SPIR-V contains an opcode (OpCode) and several operands. The opcode defines the type of instruction. Each SPIR-V instruction begins with an opcode, indicating the type and function of the instruction. The opcode is a 16-bit integer that uniquely identifies an operation; the operand provides the specific data required for the instruction to execute. These operands can be direct numerical values, references to values ​​generated by other instructions, or references to other resources, such as buffers or textures.

[0035] This step traverses the SPIR-V instruction sequence, calculates and accumulates the total size of the space occupied by the shared memory variables. The specific process is as follows:

[0036] S21. Traverse the instruction sequence of the intermediate code, wherein the OpVariable instruction is used for variable declaration. For the variable declaration, determine whether the storage class of the OpVariable instruction is a workgroup. If so, it indicates that the variable declared by the variable declaration is a shared memory variable.

[0037] In the intermediate code of SPIR-V format, the OpVariable instruction is used for variable declaration, and the storage class (Storage Class) of the OpVariable instruction specifies the storage type of the variable. The storage class (Storage Class) in SPIR-V defines the storage type of the variable and its access scope. Common storage classes include UniformConstant, Input, Uniform, Output, Workgroup, CrossWorkgroup, Private, Function and Generic. UniformConstant is used for externally shared read-only variables, which can be accessed in all functions called. It is usually used for graphics unified memory and OpenCL constant memory, and can have an initializer, which is specifically based on the provisions of the client API. Therefore, in this step, it is determined whether the storage class of the OpVariable instruction in the instruction sequence is a workgroup Workgroup. If so, it means that the variable declared by the OpVariable instruction is a shared memory variable, and then the subsequent step S22 is continued to calculate the size of the space occupied by the shared variable, otherwise the next OpVariable instruction is traversed.

[0038] S22. Calculate the space size S of the declared variable according to the type of the operand in the OpVariable instruction i , where if the type declaration is OpTypeVoid, it does not occupy storage space, Si 0 if the type declaration is a primitive type, S i The specific size of the space occupied by this primitive type. If the type declaration is a composite data type, S i The exact size of the space occupied by this composite type.

[0039] The result type (Result Type) in the operand (Operand) of the OpVariable instruction is the return value of the OpTypePointer instruction. The OpTypePointer instruction is used to declare a pointer type. The type (Type) in the operand of the OpTypePointer instruction is the type of the object pointed to by the pointer type. The space occupied by the declared variable S is calculated based on the type here. i .

[0040] SPIR-V has a variety of instructions for declaring different types. For example, in this embodiment, if the type declaration is OpTypeVoid, it does not occupy storage space. i is 0; if the type declaration is a primitive type, such as OpTypeBool, OpTypeFloat, OpTypeInt, etc., then S i Is the specific size of the space occupied by this primitive type; if the type declaration is a composite data type, such as OpTypeVector, OpTypeMatrix, OpTypeArray, OpTypeStruct, etc., then S i It is the specific space occupied by the entire composite type.

[0041] S23. Calculate the total size of all shared memory variables n is the number of shared memory variables. In addition, the variable offset of the shared memory variable is recorded synchronously. k , the kth shared memory variable, its variable offset That is, it is equal to the sum of the space occupied by all previous variables of the current shared memory variable.

[0042] Step S3, according to the total occupied space size, calculate the size of the shared memory space to be allocated and obtain the base address, by calculating the one-dimensional index of the thread group, and calculating the shared memory address of the thread group according to the one-dimensional index, the total occupied space size, and the base address.

[0043] This step is mainly to calculate the one-dimensional index. The specific process is as follows:

[0044] S31. Calculate the size of the shared memory space to be allocated SmTotalSize, SmTotalSize = S total×GroupNum, where GroupNum is the number of all thread groups. An area of ​​size SmTotalSize is allocated in the GPU memory for shared memory space, and the base address of the area is SmBaseAddr.

[0045] GroupNum is the number of all thread groups, and its value is passed in by the user when calling the driver's API. A region of size SmTotalSize is allocated in the GPU memory for shared memory space. The base address of this memory region is SmBaseAddr. The shared memory space is used by different thread groups to store the data of shared memory variables.

[0046] S32, by generating a GPU instruction to calculate the one-dimensional index GroupIndex of the thread group, assuming that the index of the thread group in each dimension is i1, i2, ..., i d , and the maximum thread group size in each dimension is n1,n2,…,n d , then the one-dimensional index GroupIndex of the thread group is:

[0047] GroupIndex=i1+n1×(i2+n2×(i3+…+n d-2 ×(i d-1 +n d-1 ×i d )…)).

[0048] The purpose of the present invention is to convert source code into SPIR-V intermediate code, that is, a SPIR-V instruction sequence, and then translate the instruction sequence into GPU instructions, and the translated GPU instructions are also an instruction sequence. The instructions contained in the GPU instructions will vary depending on the architecture and specific implementation of the GPU, and usually include some basic instructions to perform various computing tasks, manage data and control program flow, basic instructions such as arithmetic operation instructions such as addition (add), subtraction (sub), multiplication (mul), division (div), and load and store instructions for memory access, wherein load is used to read data from a memory address, and store is used to write data to a memory address. In an embodiment of the present invention, the translation of the SPIR-V instructions is mainly completed by relying on these instructions.

[0049] Before translation, we need to generate a GPU instruction to calculate the one-dimensional index GroupIndex of the thread group. This instruction is located at the head of the GPU instruction sequence. This instruction is executed first when executing the GPU instruction sequence. Assume that the indexes of the thread group in each dimension are i1, i2, …, i d , and the maximum thread group size in each dimension is n1,n2,…,n d, d is the number of indexes. The one-dimensional index GroupIndex of the thread group is:

[0050] GroupIndex=i1+n1×(i2+n2×(i3+…+n d-2 ×(i d-1 +n d-1 ×i d )…)).

[0051] For example, for the commonly used standards such as OpenCL and Vulkan, the maximum dimension supported by their thread groups is three-dimensional, so GroupIndex = i1+i2×n1+i3×n1×n2. It is expressed in three-address code as follows:

[0052] R1=i2×n1

[0053] R2=i1+R1 / / used to calculate i1+i2*n1

[0054] R3=n2+n1

[0055] R4=R3×i3 / / used to calculate i3*n1*n2

[0056] GroupIndex=R4+R2 / / GroupIndex=i1+i2*n1+i3*n1*n2

[0057] Three-address code is a representation method for intermediate code generation and is widely used in compiler design. Each instruction of three-address code usually contains three operands (addresses), namely two operands and a result address.

[0058] S33, calculate the shared memory address of the thread group in the shared memory space, that is, the starting address SmAddr = GroupIndex × S total +SmBaseAddr.

[0059] Before each thread uses the shared memory space, it needs to calculate the starting address SmAddr of the thread group in which it is located in the shared memory space. In this embodiment, the shared memories used by different thread groups are arranged linearly in the shared memory space, so SmAddr = GroupIndex × S total +SmBaseAddr.

[0060] Therefore, two instructions are added after the GroupIndex instruction used to calculate the one-dimensional index, expressed in three-address code form as follows:

[0061] AddrOffset=GroupIndex×S_total

[0062] SmAddr=AddrOffset+SmBaseAddr.

[0063] Step S4, traverse the instruction sequence of the intermediate code, and for the instructions in the function declaration and function definition, if they involve the processing of shared memory, calculate the real address and generate different GPU instructions according to the instruction type.

[0064] In this step, different GPU instructions are generated according to the instruction type, including OpLoad instructions, OpStore instructions and OpControlBarrier instructions. The OpLoad instruction is used for memory reading, the OpStore instruction is used for memory writing, and the OpControlBarrier instruction is used to control the synchronization of memory access and memory barriers.

[0065] OpLoad instruction in SPIR-V is used to read memory. OpLoad instruction has a return value type operand, which determines whether the storage class of the return value type is WorkGroup. If it is, it means that it is used to read data in shared memory. The pointer operand of OpLoad instruction is the address of memory, which can be traced back to OpVariable instruction. At this time, the offset of the variable recorded before can be obtained. k , then before generating the OpLoad instruction in the GPU instruction sequence, add an addition instruction to calculate the real address realAddr of the instruction. The three-address code form is as follows:

[0066] realAddr = offset k +SmAddr

[0067] If the pointer operand of the OpLoad instruction comes directly from the return value of the OpVariable instruction, it means that no additional memory operation occurs in the middle, and the address read by the OpLoad instruction is realAddr; if the pointer operand of the OpLoad instruction comes from the return value of the SPIR-V chain operation instruction, the address offset is recursively calculated through the base address and index of the chain operation instruction, and the address offset plus realAddr is used as the address read by the OpLoad instruction.

[0068] OpStore instruction in SPIR-V is used for memory writing. Whether it writes data to the shared memory space is determined by whether the storage class of the pointer operand of the OpStore instruction is a working group. The way to calculate the real address is the same as that of the OpLoad instruction.

[0069] For the OpControlBarrier instruction, the OpControlBarrier instruction in SPIR-V is used to control the synchronization of memory access and memory barriers. According to the execution scope and memory scope of the synchronization of the OpControlBarrier instruction, the corresponding GPU barrier instruction Barrier is generated to ensure the correct synchronization of the thread group.

[0070] According to the above S2-S4, all instructions are traversed until the translation is completed. It can be seen from the above steps that the present invention is a method for allocating and calculating shared memory and mapping instructions for processing shared memory in SPIR-V code to GPU instruction sets, specifically recording the size and offset of all shared memory variables in SPIR-V code, and allocating shared memory space of corresponding size; generating instructions in the GPU instruction sequence header to ensure that the thread calculates the shared memory address of the thread group of this thread before executing the operation; translating the remaining SPIR-V instructions for processing shared memory into GPU instructions with the same function.

[0071] In summary, the technical solution of the present invention has the following characteristics:

[0072] Firstly, the present invention uses variable declaration instructions in traversal SPIR-V code to accurately calculate the size of shared memory space required by each thread group, and records the offset of each variable in the shared memory, and finally calculates the total size of shared memory space required by all thread groups; secondly, after allocating shared memory space according to the total size of shared memory space required by all thread groups, a basic instruction is generated in the GPU instruction sequence header, which is used to calculate the one-dimensional index of the thread group, and then the shared memory address of the thread group is calculated according to the one-dimensional index of the thread group, which is used to calculate the real address when the subsequent instructions are translated; thirdly, when translating SPIR-V memory read and write instructions, if the variables in the shared memory are read and written, then an addition instruction is added to calculate the real address, and the SPIR-V memory barrier OpControlBarrier instruction is converted into a GPU barrier instruction with the same semantics to ensure the correct synchronization of the thread group.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for processing shared memory between threads based on SPIR-V, characterized in that: The method comprises the following steps: Step S1, reading the high-level language code source into the character buffer, and then converting the source code in the character buffer into an intermediate code in the SPIR-V format; Step S2, traverse the instruction sequence of the intermediate code, for the variable declaration therein, if the storage class of the variable is a work group, then the current variable is identified as a shared memory variable, the size of the space occupied by the variable is calculated, and the variable offset is recorded at the same time, and finally the total size of the space occupied by all shared memory variables is accumulated; Step S3, according to the total size of the occupied space, calculate the size of the shared memory space to be allocated and obtain the base address, by calculating the one-dimensional index of the thread group, and calculating the shared memory address of the thread group according to the one-dimensional index, the total size of the occupied space, and the base address; Step S4, traverse the instruction sequence of the intermediate code, and for the instructions in the function declaration and function definition, if they involve the processing of shared memory, calculate the real address and generate different GPU instructions according to the instruction type.

2. The SPIR-V-based inter-thread shared memory processing method as claimed in claim 1, characterized in that: The specific process of step S2 is as follows: S21, traversing the instruction sequence of the intermediate code, wherein the OpVariable instruction is used for variable declaration, for the variable declaration, determining whether the storage class of the OpVariable instruction is a workgroup, if so, it indicates that the variable declared by the variable declaration is a shared memory variable; S22. Calculate the space size S of the declared variable according to the type of the operand in the OpVariable instruction i , where if the type declaration is OpTypeVoid, it does not occupy storage space, S i 0 if the type declaration is a primitive type, S i The specific size of the space occupied by this primitive type. If the type declaration is a composite data type, S i The specific space occupied by this composite type; S23. Calculate the total size of all shared memory variables n is the number of shared memory variables. In addition, the variable offset of the shared memory variable is recorded synchronously. k , the kth shared memory variable, its variable offset That is, it is equal to the sum of the space occupied by all previous variables of the current shared memory variable.

3. The SPIR-V-based inter-thread shared memory processing method as claimed in claim 2, characterized in that: The specific process of step S3 is as follows: S31. Calculate the size of the shared memory space to be allocated SmTotalSize, SmTotalSize = S total ×GroupNum, where GroupNum is the number of all thread groups. A region of size SmTotalSize is allocated in the GPU memory for shared memory space. The base address of the region is SmBaseAddr. S32, by generating a GPU instruction to calculate the one-dimensional index GroupIndex of the thread group, assuming that the index of the thread group in each dimension is i1, i2, ..., i d , and the maximum thread group size in each dimension is n1, n2, ..., n d , then the one-dimensional index GroupIndex of the thread group is: GroupIndex=i1+n1×(i2+n2×(i3+…+n d-2 ×(i d-1 +n d-1 ×i d )…)); S33, calculate the shared memory address of the thread group in the shared memory space, that is, the starting address SmAddr = GroupIndex × S total +SmBaseAddr.

4. The SPIR-V-based inter-thread shared memory processing method as claimed in claim 3, characterized in that: In step S4, different GPU instructions are generated according to the instruction type, including OpLoad instructions, OpStore instructions and OpControlBarrier instructions, wherein the OpLoad instruction is used for memory reading, the OpStore instruction is used for memory writing, and the OpControlBarrier instruction is used to control the synchronization of memory access and memory barriers: For the OpLoad instruction, before generating it, calculate the real address of the instruction realAddr = offset k +SmAddr, the pointer operand of the OpLoad instruction comes directly from the return value of the OpVariable instruction, and the address read by the OpLoad instruction is realAddr; if the pointer operand of the OpLoad instruction comes from the return value of the SPIR-V chain operation instruction, the address offset is recursively calculated through the base address and index of the chain operation instruction, and the address offset plus realAddr is used as the address read by the OpLoad instruction; For the OpStore instruction, whether it writes data to the shared memory space is determined by whether the storage class of the pointer operand of the OpStore instruction is a working group. The method of calculating the real address is the same as that of the OpLoad instruction. For the OpControlBarrier instruction, according to the execution scope and memory scope synchronized by the OpControlBarrier instruction, the corresponding GPU barrier instruction Barrier is generated to ensure the correct synchronization of the thread group.

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