Angle-based solution system based on CORDIC instructions

Abstract

This invention belongs to the field of computer technology and relates to an angle calculation system based on CORDIC instructions. The system includes an IFU (Instruction Fetch Unit) and an EXU (Execution Unit). During the instruction fetch phase, the IFU reads CORDIC instructions from the instruction memory according to the address of the PC. The EXU includes a decoding module, an arithmetic logic unit, a load-memory unit, and a write-back unit. This invention extends the CORDIC angle calculation instruction set based on the RISC-V architecture and designs a complete pipelined hardware structure, supporting trigonometric function operations. It has a complete CORDIC operation path hardware circuit structure, reusing the same operation path for different operation processes, improving hardware resource utilization. It overcomes the limitation of convergence of the calculation result range when performing angle calculation based on the CORDIC algorithm by pre-storing special angle results to reduce calculation time and optimize the circuit operating frequency.

Description

Technical Field

[0001] This invention belongs to the field of computer technology, and more specifically, relates to an angle calculation system based on CORDIC instructions. Background Technology

[0002] In fields such as scientific computing, digital signal processing, servo control, and image processing, arctangent calculation is one of the commonly used fundamental operations. Currently, most processors do not support trigonometric function operations. Embedded microprocessors typically use software calls to perform trigonometric calculations such as arctangent function computation. However, using software to calculate arctangent function angles is difficult to meet the real-time requirements of embedded microprocessors. Arctangent angle calculation using general-purpose processors generally uses the basic processor instruction set, often requiring dozens of instructions to perform the calculation, resulting in long computation times. Designing a separate arctangent angle calculation module would increase hardware overhead. To balance computation time, resource consumption, and operating frequency, extending the angle calculation instruction set in general-purpose processors and designing corresponding hardware control circuits to implement arctangent function computation is considered a better solution. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides an angle calculation system based on CORDIC instructions, comprising an IFU instruction fetch unit and an EXU execution unit;

[0004] During the instruction fetch phase, the IFU (Instruction Fetch Unit) reads the CORDIC instruction from the instruction memory based on the address of the PC (Program Counter).

[0005] The EXU execution unit includes a decoding module, an arithmetic logic unit, a load-memory unit, and a write-back unit. During the execution phase, the EXU execution unit decodes CORDIC instructions through the decoding module to decode the corresponding operands and passes the decoded operands to the arithmetic logic unit, and reads the operands from the load-memory unit. After the arithmetic logic unit finishes execution, the write-back unit writes the result back to the register file.

[0006] The arithmetic logic unit includes an ALU logic operation subunit, a CORDIC operation subunit, and an operation data path module. The CORDIC operation subunit initiates a shared operation request to the operation data path module according to the CORDIC perspective calculation instructions, and retrieves the calculation result from the operation data path module. The operation data path module accepts the requests from the ALU logic operation subunit and the CORDIC operation subunit, performs the calculation, and returns the calculation result to the corresponding ALU logic operation subunit and CORDIC operation subunit after the calculation is completed.

[0007] The CORDIC operation subunit includes a quadrant and special angle discrimination module, a CORDIC algorithm serial iteration module, and an angle compensation module. The quadrant and special angle discrimination module performs quadrant pre-judgment on the coordinate values ​​corresponding to the input source operands and discriminates the angle. When the angle is a preset angle value, it outputs the preset angle solution value; otherwise, it enters the CORDIC algorithm serial iteration module. After the operation is completed, the angle compensation module outputs the angle value.

[0008] Based on the above technical solution, the present invention can be further improved as follows.

[0009] Furthermore, the CORDIC instruction consists of 32 bits. Bits 25-31 are the func7 field, containing 0000010, which is defined as the CORDIC instruction set. Bits 20-24 are the second source operand index. Bits 15-19 are the first source operand index. Bits 12-14 are the func3 field, which is the arctangent operation instruction. Bits 7-11 are the result operand index. Bits 0-6 are the opcode.

[0010] Furthermore, the ALU logic operation subunit and the CORDIC operation subunit share the operation data path during instruction execution and computation. The ALU logic operation subunit initiates an operation request to the shared operation path according to the ALU instruction and retrieves the computation result from the shared operation path. The CORDIC operation subunit initiates a shared operation request to the operation data path according to the CORDIC perspective solution instruction and retrieves the computation result from the operation data path. The operation data path accepts the requests from the ALU logic operation subunit and the CORDIC operation subunit, performs the computation process simultaneously, and returns the computation result to the operation data path of the corresponding subunit after the calculation is completed.

[0011] Furthermore, the operand values ​​include the operand register index, write-back register index, and operand that need to be read to execute the CORDIC instruction.

[0012] Furthermore, a dispatch module is set between the decoding module and the computation data path; the CORDIC angle calculation long instruction is first dispatched to the ALU logic operation subunit, and delivered through the interface between the ALU logic operation subunit and the delivery module. At the same time, according to the corresponding indication signal obtained from decoding, the ALU logic operation subunit dispatches the CORDIC angle calculation long instruction to the CORDIC operation subunit.

[0013] Furthermore, the dispatch module is equipped with a FIFO module. When a CORDIC angle calculation long instruction is dispatched, an entry is allocated in the FIFO module to store the source operand register index and result register index of the CORDIC angle calculation long instruction. After the CORDIC angle calculation long instruction is written back, the information in the entry is removed from the cache of the FIFO module. When a subsequent CORDIC angle calculation long instruction is dispatched, the source operand register index and result register index of the CORDIC angle calculation long instruction are compared with each entry in the FIFO module to determine whether the CORDIC angle calculation long instruction has RAW and WAW correlations with CORDIC angle calculation long instructions that have been dispatched but not yet written back.

[0014] Furthermore, in its initial state, the CORDIC operation subunit receives the initial source operand and the source operand, and simultaneously initializes the angle value for the first iteration. Upon receiving the cordic_i_valid signal, it enters the CORDIC angle calculation instruction execution state, and cordic_sta_is_exec becomes valid. Upon receiving the exec_last_cycle signal, it completes the last round of calculation for the CORDIC angle calculation instruction: it exits the angle calculation iteration process, and the cordic_sta_is_done signal becomes valid. After the calculation is completed, it outputs the cordic_o_valid signal and the final calculated 32-bit angle value. When the CORDIC operation subunit receives initialization and refresh commands, it does not perform any operations and remains in an idle state.

[0015] Furthermore, the CORDIC computing subunits reuse and share computing data paths, including:

[0016] In each iteration, the CORDIC operation subunit sends X and Y values ​​to the operation data path, representing the input values ​​for the CORDIC operation, and Z value, representing the output value. X and Y are coordinate information, and Z is the output angle value obtained from the input angle information. The subunit also controls the start, progress, and end of the iteration calculation through output control signals. The control signals include addition, subtraction, and shift signals. Upon receiving the control signals, the operation data path uses its internal adders, subtractors, and shift registers to perform the calculations. The output of each iteration is fed back as the input to the CORDIC operation subunit until the final result is derived.

[0017] Furthermore, the CORDIC operation subunit includes an angle compensation unit and an angle discrimination unit. The angle compensation unit expands the CORDIC angle output range to (0, 2π) through interval conversion. At the same time, the angle discrimination unit judges the CORDIC angle and directly outputs the corresponding function value when the CORDIC angle belongs to the set angle.

[0018] The beneficial effects of this invention are:

[0019] (1) This invention is based on the RISC-V architecture. It extends the CORDIC angle computation instruction set according to the instruction encoding rules of the RISC-V architecture and designs a corresponding pipelined hardware structure. The original RISC-V instruction set uses a fixed 47 instructions RV32I as its core, which are basic integer instructions. The R-type instruction set contains arithmetic operation instructions, including a basic instruction set (funct7 field is 0000000) and a multiplication instruction set (funct7 field is 0000001). This design extends the original instruction set with the CORDIC arithmetic instruction set (funct7 field is 0000010) and has a complete hardware pipeline structure including the fetch and execution stages, enabling the RISC-V architecture to support trigonometric function operations.

[0020] (2) This invention designs a complete hardware circuit structure for the CORDIC arithmetic path. Upon receiving a CORDIC arithmetic instruction from the IFU instruction register, the decoding module decodes it according to the instruction encoding rules of the RISC-V architecture, generating CORDIC arithmetic instruction type information and operand register indexes. After decoding and reading operands from the register set, the CORDIC arithmetic instruction is dispatched to the ALU module for execution. The difference between this design and traditional execution methods lies in the following: the CORDIC instruction is first dispatched to the ALU and delivered through the interface between the ALU and the delivery module. Simultaneously, based on the corresponding indication signal obtained from decoding, the ALU dispatches the instruction to the CORDIC arithmetic subunit. During the dispatch process, the source operand register index and result register index of the long CORDIC instruction are written into a FIFO structure, thereby solving the data dependency problem. All function operations, including angle calculations using the CORDIC algorithm, go through the same core computing unit. This core computing unit includes the data path module that is actually used for calculations and the CORDIC computing subunit, which is a state machine that controls the execution of the calculations. Their actual calculation processes share the actual computing data path, which means that different calculation processes reuse the same set of computing paths, thereby improving the utilization of hardware resources.

[0021] (3) The hardware circuit structure of the traditional CORDIC algorithm is optimized to overcome the limitation of convergence of the calculation result range when calculating the angle based on the CORDIC algorithm. The hardware circuit scheme of the CORDIC arctangent function is optimized to expand the output angle range to the full quadrant. The calculation time is reduced by pre-storing special angle results, thereby optimizing the circuit operating frequency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the angle calculation system based on CORDIC instructions provided in an embodiment of the present invention.

[0023] Figure 2 This is the CORDIC arithmetic instruction format table;

[0024] Figure 3 This is a block diagram of the ALU (Arithmetic Logic Unit).

[0025] Figure 4 This is a block diagram of the principle of the angle calculation system based on CORDIC instructions;

[0026] Figure 5 This is a schematic diagram of the state machine transition process of the CORDIC computing module.

[0027] Figure 6 Timing diagram of the CORDIC operation subunit;

[0028] Figure 7 This is a simulation diagram showing the changes in key signals during the execution of angle calculation instructions. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0030] Example 1

[0031] As an example, see the attached document. Figure 1 As shown, to solve the above-mentioned technical problems, this embodiment provides an angle calculation system based on CORDIC (Coordinated Rotation Digital Computer) instructions, including an IFU (Instruction Fetch Unit) and an EXU (Execution Unit);

[0032] During the instruction fetch phase, the IFU (Instruction Fetch Unit) reads the CORDIC instruction from the instruction memory based on the address of the PC (Program Counter).

[0033] The EXU (Execution Unit) includes a decoding module, an arithmetic logic unit, a load-memory unit, and a write-back unit. During the execution phase, the EXU decodes CORDIC instructions using the decoding module to decode the corresponding operands and passes them to the arithmetic logic unit. It also reads the operands from the load-memory unit. After the arithmetic logic unit finishes execution, the write-back unit writes the result back to the register file.

[0034] The arithmetic logic unit includes an ALU logic operation subunit, a CORDIC operation subunit, and an operation data path module. The CORDIC operation subunit initiates a shared operation request to the operation data path module according to the CORDIC perspective calculation instructions, and retrieves the calculation result from the operation data path module. The operation data path module accepts the requests from the ALU logic operation subunit and the CORDIC operation subunit, performs the calculation, and returns the calculation result to the corresponding ALU logic operation subunit and CORDIC operation subunit after the calculation is completed.

[0035] The CORDIC operation subunit includes a quadrant and special angle discrimination module, a CORDIC algorithm serial iteration module, and an angle compensation module. The quadrant and special angle discrimination module performs quadrant pre-judgment on the coordinate values ​​corresponding to the input source operands and discriminates the angle. When the angle is a preset angle value, it outputs the preset angle solution value; otherwise, it enters the CORDIC algorithm serial iteration module. After the operation is completed, the angle compensation module outputs the angle value.

[0036] The EXU execution unit maintains pipeline resource conflicts and data conflicts during the execution phase.

[0037] The decoding module decodes the instruction according to the RISC-V architecture's instruction encoding rules, generating CORDIC instruction type information and operand register indices. The decoding module receives the 32-bit CORDIC angle calculation instruction from the IFU decoding module, along with the corresponding PC value, to obtain the register index values ​​for source operand 1 and source operand 2. By comparing the register indices in the register file, it obtains the source operand 1 and source operand 2 that need to be read from the corresponding registers. Source operand 1 is the X-coordinate value required for the CORDIC angle calculation, and source operand 2 is the Y-coordinate value required for the CORDIC angle calculation. Simultaneously, it generates control signals for writing the result operand after the CORDIC instruction calculation is completed.

[0038] This invention proposes a hardware pipeline structure for a CORDIC algorithm instruction processor based on the RISC-V architecture. The complete pipeline structure includes a two-stage pipeline structure, comprising an instruction fetch unit (IFU) and an execution unit (EXU). During the fetch stage, the CORDIC instruction is read from the instruction memory based on the address of the program counter (PC). During the execution stage, the CORDIC instruction is first decoded, and operands are read from the register file. After entering the arithmetic stage, the operands are entered into the corresponding functional modules based on the decoding result. The EXU execution unit includes a decoding module, an ALU (Arithmetic Logic Unit) submodule, a load memory unit, and a write-back unit. All arithmetic operations in the ALU submodule reuse arithmetic logic resources. After the execution stage, the result is written back to the register file.

[0039] After fetching the instruction, the IFU instruction fetch unit places the instruction in the instruction register between itself and the EXU execution unit; the PC value of the instruction is also placed in the PC register, and the instruction will be used to perform further operations with the PC during subsequent execution.

[0040] During the execution phase, the decoding module decodes the designed CORDIC instruction to obtain the corresponding operation value, including the operand register index, write-back register index and operand information that the CORDIC instruction needs to read, and passes the above information to the EXU execution unit; the EXU execution unit mainly includes the arithmetic logic unit (ALU) and the CORDIC arithmetic unit.

[0041] The decoding module decodes instructions according to the RISC-V architecture's instruction encoding rules, generating CORDIC instruction type information and operand register indices. In practical applications, the decoding module receives a 32-bit CORDIC angle calculation instruction from the IFU, along with the corresponding PC value, obtaining the register index values ​​for source operand 1 and source operand 2. By comparing the register indices in the register file, it obtains the source operand 1 and source operand 2 that need to be read from the corresponding registers. Source operand 1 is the X-coordinate value of the input number required for the CORDIC angle calculation, and source operand 2 is the Y-coordinate value of the input number required for the CORDIC angle calculation. Simultaneously, it generates control signals for writing the result operand after the CORDIC instruction calculation is completed.

[0042] Optionally, the CORDIC instruction consists of 32 bits. Bits 25-31 are the func7 field, containing 0000010, which is defined as the CORDIC instruction set. Bits 20-24 are the second source operand index. Bits 15-19 are the first source operand index. Bits 12-14 are the func3 field, which is the arctangent operation instruction. Bits 7-11 are the result operand index. Bits 0-6 are the opcode.

[0043] The designed CORDIC instruction consists of 32 bits. Bits 31-25 are the func7 field (Function7 represents the function code field, i.e., the first seven bits of a 32-bit RISC-V architecture instruction), with a content of 0000010, defining it as the CORDIC instruction set. Bits 24-20 are the source operand 2 index; bits 19-15 are the source operand 1 index; bits 14-12 are the func3 field, with a content of 111, indicating that the instruction is included in the CORDIC instruction set and is an arctangent operation instruction; bits 11-7 are the result operand index; and bits 6-0 are the opcode, with a content of 0110011, indicating that the CORDIC-perspective computation instruction type is an arithmetic instruction.

[0044] Let rs represent the source register, and rs1 and rs2 be general-purpose registers in the RISC-V instruction set. The CORDIC instruction format is shown in Table 1.

[0045] Table 1 Examples of CORDIC instructions

[0046]

[0047]

[0048] The information bus required by the CORDIC arithmetic unit is generated according to the designed CORDIC instructions, including the following: group information indicating that the current instruction belongs to the CORDIC instruction set, information indicating that the current instruction is a 32-bit instruction, and information indicating that the current instruction is an arctangent angle calculation instruction belonging to the CORDIC instruction set.

[0049] In practical applications, the custom CORDIC angle calculation instructions are arithmetic instructions and are classified into the R-type instruction set in RISC-V (opcode 0110011), as shown in the attached figure. Figure 2 The CORDIC operation instruction format shown above, since the input source operands cordic_i_rs1 and cordic_i_rs2 are both signed two's complement, the input coordinate values ​​are pre-determined by judging cordic_i_rs1

[31] and cordic_i_rs2

[31] , and the coordinates of the other quadrants outside the first quadrant are respectively added. π Angle compensation is applied, and the angle is normalized to the first quadrant for calculation. The original R-type instruction set includes the basic instruction set (funct7 is 0000000) and the multiplication instruction set (funct7 is 0000001). The newly added CORDIC arithmetic instruction set defines funct7 as 0000010 and funct3 as 111. Since calculating the arctangent function requires two coordinate values ​​(x and y), it is defined as a two-operand instruction and a register-to-register instruction. It needs to read the operand from the register and write the result back to the register after the instruction is executed.

[0050] This invention proposes an angle calculation system based on RISC-V architecture and CORDIC algorithm. It achieves arctangent function angle calculation with a single instruction, solving the problem of the large number of instructions and long computation time required when using basic processor instruction sets for angle calculation. It also fills the gap in the current RISC-V architecture instruction set, which does not support trigonometric function operations. At the same time, the corresponding processor hardware circuit is designed, and the traditional CORDIC circuit structure is optimized. By reusing the computation path, the consumption of hardware resources is reduced, and the output range of angle calculation is expanded.

[0051] The CORDIC algorithm is widely used in engineering. It can perform complex operations such as trigonometric functions using only simple shifting and recursive addition / subtraction operations, making it widely applicable in digital circuit design using arctangent functions. This invention designs a hardware system for a serial iterative CORDIC algorithm, controlled by extended angle calculation instructions, achieving angle calculation with a single instruction.

[0052] RISC-V is an instruction set architecture (ISA) based on the principles of Reduced Instruction Set Computer (RISC). Its advantages lie in its openness and flexibility; as an open standard, it can run on various different architectures. RISC-V's flexibility allows it to meet the needs of different applications; users can customize the instruction set to handle specific tasks, such as encryption, multimedia processing, and artificial intelligence. Furthermore, RISC-V offers advantages in scalability and portability. Because the ISA is modular, users can add extended instruction sets as needed to handle different tasks, making it well-suited for various embedded systems. At the same time, RISC-V's design facilitates portability across different platforms because the ISA design is simple and transparent, adhering to unified specifications and interface standards, thereby improving software and hardware interoperability.

[0053] RISC-V architecture microprocessors have gained increasingly widespread application in the industry. This architecture provides ample instruction code space that is easy to implement and apply, making it increasingly popular in both academic and industrial fields. In resource-constrained RISC-V embedded microprocessors, performing fast and low-power calculations of a large number of trigonometric functions can be accomplished by designing corresponding trigonometric function operation circuits. Since the RISC-V architecture is relatively new, there are currently no extensions for trigonometric function operations based on it. Therefore, designing a corresponding RISC-V architecture trigonometric function operation instruction set and related hardware control circuits is of significant practical importance for further expanding application areas.

[0054] Optionally, the ALU logic operation subunit and the CORDIC operation subunit share the operation data path during instruction execution and operation. The ALU logic operation subunit initiates an operation request to the shared operation path according to the ALU instruction and retrieves the operation result from the shared operation path. The CORDIC operation subunit initiates a shared operation request to the operation data path according to the CORDIC perspective calculation instruction and retrieves the operation result from the operation data path. The operation data path accepts the requests from the ALU logic operation subunit and the CORDIC operation subunit, performs the operation process simultaneously, and returns the calculation result to the operation data path of the corresponding subunit after the calculation is completed.

[0055] As attached Figure 3 The diagram shows the block structure of the ALU (Arithmetic Logic Unit). If there is no resource conflict, the current CORDIC operation subunit issues a cordic_i_ready signal. When a valid cordic_i_valid signal is received, the handshake signal cordic_i_hsked becomes valid, and the CORDIC operation subunit starts working, initiating an operation request to the shared operation data path and retrieving the operation result from the shared operation path. The operation data path module is the actual data path module used for calculation. After the calculation is completed, it returns the calculation result to the operation data path of the corresponding subunit.

[0056] Optionally, the operand values ​​include the operand register index, write-back register index, and operand that need to be read to execute the CORDIC instruction.

[0057] Optionally, a dispatch module is provided between the decoding module and the computation data path; the CORDIC angle calculation long instruction is first dispatched to the ALU logic operation subunit and delivered through the interface between the ALU logic operation subunit and the delivery module. At the same time, according to the corresponding indication signal obtained from decoding, the ALU logic operation subunit dispatches the CORDIC angle calculation long instruction to the CORDIC operation subunit.

[0058] The angle calculation system employs a two-stage pipeline architecture. After decoding, the CORDIC angle calculation instructions read operands from the register set and are then dispatched to the CORDIC arithmetic unit for execution. The dispatch mechanism involves sending the CORDIC instructions to the ALU module, which delivers them through the interface between the ALU and the delivery module. Simultaneously, the ALU performs the actual dispatch, sending the decoded information to the CORDIC arithmetic unit based on the CORDIC instruction indication signal generated during decoding.

[0059] During instruction dispatch, resource and data conflicts in the pipeline are resolved. For example, if the currently executing instruction is a long-cycle instruction and requires the same arithmetic unit as subsequent instructions, a resource conflict arises. CORDIC angle calculation instructions are dispatched from the ALU to the CORDIC arithmetic subunit for execution. At this time, the cor_op signal (indicating the instruction is a CORDIC angle calculation instruction) is high, and the cor_i_ready signal (a handshake signal in the CORDIC module indicating readiness to receive data) is selected. If the current CORDIC submodule has not completed its previous calculation, resulting in a resource conflict, the cor_i_ready signal goes low. This causes the i_ready signal in the upstream dispatch module (i_ready low indicates the dispatch module is not ready to receive data, i_ready high indicates the dispatch module is ready to receive data) to go low. In this case, the current instruction cannot be dispatched and must wait until the cor_i_ready signal goes high. After the previous calculation is completed, the resource conflict is resolved, thus solving the resource conflict problem.

[0060] Optionally, the dispatch module is equipped with a FIFO module. When a CORDIC angle calculation long instruction is dispatched, an entry is allocated in the FIFO module to store the source operand register index and result register index of the CORDIC angle calculation long instruction. After the CORDIC angle calculation long instruction is written back, the information in the entry is removed from the cache of the FIFO module. When a subsequent CORDIC angle calculation long instruction is dispatched, the source operand register index and result register index of the CORDIC angle calculation long instruction are compared with each entry in the FIFO module to determine whether the CORDIC angle calculation long instruction has RAW (Read After Write) and WAW (Write After Write) correlations with CORDIC angle calculation long instructions that have been dispatched but not yet written back.

[0061] Because CORDIC angle resolution instructions are long instructions executed over multiple cycles, they may exhibit RAW and WAW dependencies with other instructions during execution, leading to data conflicts. By adding a FIFO module, when a CORDIC angle resolution long instruction is dispatched, an entry is allocated in the FIFO to store the source operand register index and result register index of that instruction. This information is only removed from the FIFO cache after the instruction has been written back. Subsequent instructions, when dispatched, compare their source operand register index and result register index with the entries in the FIFO to determine if they have RAW and WAW dependencies with dispatched but not yet written back CORDIC angle resolution long instructions.

[0062] Optionally, the CORDIC operation subunit receives the initial source operand and source operand during its initial state, and initializes the angle value for the first iteration. Upon receiving the cordic_i_valid signal (a data validity signal sent to the cordic operation module), it enters the CORDIC angle calculation instruction execution state, and the cordic_sta_is_exec signal (cordic module starts execution signal) becomes valid. Upon receiving the exec_last_cycle signal (an indication signal for the last iteration of the cordic operation), it completes the last round of calculation of the CORDIC angle calculation instruction: exits the angle calculation iteration process, and the cordic_sta_is_done signal (cordic iteration process ends signal) becomes valid. After the calculation is completed, it outputs the cordic_o_valid signal and the finally calculated 32-bit angle value. When the CORDIC operation subunit receives initialization and refresh commands, it does not perform any operation and remains in an idle state.

[0063] The ALU (Arithmetic Logic Unit) logic operation subunit initiates operation requests to the shared computation path based on ALU instructions (such as add, sub, and xor instructions; add performs addition, sub performs subtraction, and xor performs XOR). It then retrieves the results from the shared computation path. Similarly, the CORDIC operation subunit initiates operation requests to the shared computation data path based on CORDIC-based computation instructions and retrieves the results from the shared computation path. The computation data path module is the actual data path module used for computation. Its function is relatively simple: it accepts requests from the ALU logic operation subunit and the CORDIC operation subunit, performs the actual computation process, and returns the result to the corresponding subunit's computation data path after completion. In summary, the ALU logic operation subunit and the CORDIC operation subunit are only responsible for the execution control of specific instructions; their actual computation process shares the actual computation data path. This greatly reduces the area overhead required for CORDIC computation and also reduces the overall hardware resource consumption of the design.

[0064] The specific implementation of the CORDIC operation subunit is as follows: First, as shown in the attached... Figure 4As shown, if there is no resource conflict, the current CORDIC operation subunit sends a cordic_i_ready signal (a handshake signal indicating that the CORDIC operation module is ready to receive data). When a valid cordic_i_valid signal is received, the handshake signal cordic_i_hsked becomes valid, and the CORDIC operation subunit starts working. After instruction dispatch, the CORDIC operation subunit receives the source operand information obtained by decoding the CORDIC angle calculation instruction designed above. After reset, the CORDIC operation subunit is in the initial state, and cordic_sta_is_0th (the first iteration start signal of the CORDIC algorithm) is valid. In this state, it receives the initial source operand 1, i.e., the assignment of the X coordinate value, and the initial source operand 2, i.e., the assignment of the Y coordinate value, and initializes the angle value Z of the first iteration to 0. Upon receiving the `cordic_i_valid` signal (a valid data signal sent to the `cordic` operation module), the CORDIC angle calculation instruction execution state is entered, `cordic_sta_is_exec` (the signal indicating the start of operation by the `cordic` module) becomes valid, and the unit waits for the next status signal. Upon receiving the `exec_last_cycle` signal (an indication signal for the final iteration of the `cordic` operation), the final round of calculation for the CORDIC angle calculation instruction is completed: the angle calculation iteration process is exited, and the `cordic_sta_is_done` signal (the signal indicating the end of the `cordic` iteration process) becomes valid. After the above steps, the CORDIC operation subunit sends information to the EXU execution unit, including the `cordic_o_valid` signal (a valid output signal from the `cordic` module) and the `cordic_o_wbck_wdat` signal (data values ​​written back by the `cordic` module), where `cordic_o_wbck_wdat` is the final calculated 32-bit angle value. Upon receiving other commands, including initialization and refresh commands, no operation is performed, and the state of the CORDIC operation subunit is `IDLE`, i.e., idle.

[0065] Traditional CORDIC calculations of arctangent angles only output angles within a certain range. In this invention, the CORDIC operation subunit is improved to address this limitation. By using interval transformation, the angle range of the algorithm is widened to (0, 2π), while also supporting signed number coordinate input.

[0066] Specifically, when the input coordinate values ​​enter the CORDIC circuit, they are first determined to be specific angles, such as 0°. π And 2π. Function values ​​for special angles are pre-stored. When these angles are encountered, the corresponding angle calculation value is directly output, thus shortening the multiple iteration cycles of the traditional CORDIC circuit to 3 cycles, accelerating instruction execution speed. These optimizations make this hardware structure better suited for engineering practice. When the input data is not a special angle, it enters the iteration module. The CORDIC calculation serial structure is as follows: Figure 5 As shown, the output of each iteration module is fed back to the iteration module as input in the next clock cycle. The CORDIC iteration module contains 3 addition / subtraction units and 2 shift units, all of which reuse the data path to reduce resource consumption. Register 1 is the data register that stores the X value during iteration, Y_reg is the data register that stores the Y value during iteration, adder 1 is the adder that calculates the X result during iteration, adder 2 is the adder that calculates the Y result during iteration, and adder 3 is the adder that calculates the Z result during iteration; register 2 is the data register that stores the Z value during iteration; the adder calculates the Z result during iteration; the sign determination controller controls the operation number according to the magnitude of the Y value. If Y < 0, the Y value is calculated by addition in the next iteration; if Y ≥ 0, the Y value is calculated by subtraction in the next iteration. Shifter 1 is the shift parameter for the X value; shifter 2 is the shift parameter for the Y value.

[0067] The specific implementation of the CORDIC arithmetic subunit and arithmetic data path is as follows:

[0068] The core of the CORDIC operation subunit is the iterative process of angle calculation in the cordic_sta_is_exec state of the state machine. In this state, the CORDIC operation subunit primarily outputs source operand 1 (signed coordinate value X) and source operand 2 (signed coordinate value Y) to the operation data path, and controls the entire iterative process of angle calculation. In each iteration, the operation data path receives the corresponding coordinate values ​​X, Y, and angle value Z, performs corresponding addition, subtraction, and shift operations on each channel, and after completing one iteration, outputs the calculated value to the CORDIC operation subunit as the calculation value for the next iteration.

[0069] The specific calculation process for each operand in each iteration is as follows:

[0070] For coordinate value X, output the current coordinate value X as the minuend to the output calculation path. Let i be the iteration number, multiply the current coordinate value Y by the rotation direction d, and then multiply by 2. i The subtraction output is sent to the arithmetic path, and the difference obtained after the subtraction operation is performed by the arithmetic path is output as the X value of the new round of iteration to the CORDIC arithmetic subunit for the next round of iteration;

[0071] For coordinate value Y, output the current coordinate value Y as the addend to the output calculation path, and multiply the current coordinate value X by the rotation direction d and then multiply by 2. i The sum is output as an addend to the arithmetic path, and the sum obtained after the arithmetic path performs the addition operation is output as the Y value of the new round of iteration to the CORDIC arithmetic subunit for the next round of iteration;

[0072] For the angle value Z, the current angle value Z is output as the minuend to the output calculation path, and the rotation direction d is multiplied by θ. i The subtraction output is sent to the computation path, and the difference obtained after subtraction is used as the Z value for the next iteration and output to the CORDIC computation subunit for the next iteration. The rotation direction d is determined by the current coordinate value Y. When the Y value is less than or equal to 0, d is +1; when the Y value is greater than or equal to 0, d is -1. In the above calculation process, i is the count value of the i-th iteration, and θ is the rotation angle value pre-stored in ROM for the i-th iteration. The angle calculation iteration process ends when the Y value approaches 0.

[0073] Optionally, CORDIC computation subunits can reuse and share computation data paths, including:

[0074] In each iteration, the CORDIC operation subunit sends X and Y values ​​to the operation data path, representing the input values ​​for the CORDIC operation, and Z value, representing the output value. X and Y are coordinate information, and Z is the output angle value obtained from the input angle information. The subunit also controls the start, progress, and end of the iteration calculation through output control signals. The control signals include addition, subtraction, and shift signals. Upon receiving the control signals, the operation data path uses its internal adders, subtractors, and shift registers to perform the calculations. The output of each iteration is fed back as the input to the CORDIC operation subunit until the final result is derived.

[0075] Optionally, the CORDIC operation subunit includes an angle compensation unit and an angle discrimination unit. The angle compensation unit expands the CORDIC angle output range to (0, 2π) through interval conversion. At the same time, the angle discrimination unit judges the CORDIC angle and directly outputs the corresponding function value when the CORDIC angle belongs to the set angle.

[0076] As attached Figure 6 The timing diagram of the CORDIC operation subunit is shown below. Figure 7The diagram shows the simulation of key signal changes during the execution of the angle calculation instruction. clk represents the clock signal. The timing of the CORDIC operation subunit is as follows: the cordic_i_valid signal is pulled high; cordic_i_rs1 and cordic_i_rs2 represent the inputs to the source register; and cordic_o_wbck_wdat[31:0] represents the result input to the destination register. The calculation of a regular angle takes 16 clock cycles; the module has a lookup table for special angle values, so the calculation of special angle values ​​only takes 3 clock cycles, thereby improving the average speed of the angle calculation instruction within the processor pipeline.

[0077] Based on this invention, a complete hardware-based angle calculation system was completed. A test platform was built according to the complete system, and the RISC-V GNU toolchain was downloaded to complete the instruction compilation environment. Assembly code was written to complete the input of CORDIC angle calculation instructions, and C language inline assembly was used to implement the call of the instruction to obtain the CORDIC angle calculation result.

[0078] This invention extends CORDIC arithmetic instructions based on the RISC-V architecture and designs a corresponding processor hardware circuit system, which has the following characteristics:

[0079] (1) When designing CORDIC arithmetic instructions for the RISC-V architecture, the instruction encoding rules of the RISC-V architecture are followed. First, according to the instruction encoding rules of the RISC-V architecture, the CORDIC arithmetic instructions are encoded into 32-bit executable EXU instructions. In the EXU execution unit, the instructions are decoded according to the instruction encoding rules of the RISC-V architecture to generate CORDIC instruction type information and operand register indexes. Next, based on the decoded instruction information, the CORDIC arithmetic subunits are controlled to perform arithmetic operations.

[0080] (2) This design has a complete pipeline structure, including the decoding and dispatch of CORDIC instructions, reading the general-purpose register group through the index of the decoded operand register, maintaining the data dependency of the instructions through the FIFO structure, the complete CORDIC instruction delivery process, and finally writing the angle calculation result of the instruction back to the general-purpose register group.

[0081] (3) The ALU (Arithmetic Logic Unit) includes ALU logic operation subunits, CORDIC operation subunits, and operation data paths. The CORDIC operation subunits, based on CORDIC perspective calculation instructions, initiate operation requests to the shared operation data path and retrieve the calculation results from the shared operation path. The operation data path module is the actual data path module used for calculation. It accepts requests from the ALU logic operation subunits and CORDIC operation subunits, performs the specific calculation process, and returns the calculation results to the corresponding subunit's operation data path after completion. The CORDIC operation subunits specifically control the state machine for operation execution. Their actual operation processes share the actual operation data path, thereby reducing the area overhead required for CORDIC operations and also reducing the overall hardware resource consumption of the design.

[0082] (4) Compared with the traditional CORDIC algorithm hardware circuit, the CORDIC operation subunit hardware circuit in this invention expands the angle range of the algorithm to (0, 2π) through interval conversion, and also supports the coordinate input method of signed numbers. In particular, the CORDIC operation circuit is designed with a special angle discrimination function. The function values ​​of special angles are pre-stored. When these angles are encountered, the corresponding function values ​​are directly output, thereby shortening the multiple iteration cycles of the traditional CORDIC circuit to 3 cycles, which can accelerate the execution speed of instructions.

[0083] The advantages of this invention compared to the prior art are:

[0084] (1) This invention is based on the RISC-V architecture. It extends the CORDIC angle computation instruction set according to the instruction encoding rules of the RISC-V architecture and designs a corresponding pipelined hardware structure. The original RISC-V instruction set uses a fixed 47 instructions RV32I as its core, which are basic integer instructions. The R-type instruction set contains arithmetic operation instructions, including a basic instruction set (funct7 field is 0000000) and a multiplication instruction set (funct7 field is 0000001). This design extends the original instruction set with the CORDIC arithmetic instruction set (funct7 field is 0000010) and has a complete hardware pipeline structure including the fetch and execution stages, enabling the RISC-V architecture to support trigonometric function operations.

[0085] (2) This invention designs a complete hardware circuit structure for the CORDIC arithmetic path. Upon receiving a CORDIC arithmetic instruction from the IFU instruction register, the decoding module decodes it according to the instruction encoding rules of the RISC-V architecture, generating CORDIC arithmetic instruction type information and operand register indexes. After decoding and reading operands from the register set, the CORDIC arithmetic instruction is dispatched to the ALU module for execution. The difference between this design and traditional execution methods lies in the following: the CORDIC instruction is first dispatched to the ALU and delivered through the interface between the ALU and the delivery module. Simultaneously, based on the corresponding indication signal obtained from decoding, the ALU dispatches the instruction to the CORDIC arithmetic subunit. During the dispatch process, the source operand register index and result register index of the long CORDIC instruction are written into a FIFO structure, thereby solving the data dependency problem. All function operations, including angle calculations using the CORDIC algorithm, go through the same core computing unit. This core computing unit includes the data path module that is actually used for calculations and the CORDIC computing subunit, which is a state machine that controls the execution of the calculations. Their actual calculation processes share the actual computing data path, which means that different calculation processes reuse the same set of computing paths, thereby improving the utilization of hardware resources.

[0086] (3) The hardware circuit structure of the traditional CORDIC algorithm is optimized to overcome the limitation of convergence of the calculation result range when calculating the angle based on the CORDIC algorithm. The hardware circuit scheme of the CORDIC arctangent function is optimized to expand the output angle range to the full quadrant. The calculation time is reduced by pre-storing special angle results, thereby optimizing the circuit operating frequency.

[0087] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An angle calculation system based on CORDIC instructions, characterized in that, This includes the IFU instruction fetch unit and the EXU execution unit; During the instruction fetch phase, the IFU (Instruction Fetch Unit) reads the CORDIC instruction from the instruction memory based on the address of the PC (Program Counter). The EXU execution unit includes a decoding module, an arithmetic logic unit, a load-memory unit, and a write-back unit. During the execution phase, the EXU execution unit decodes CORDIC instructions through the decoding module to decode the corresponding operands and passes the decoded operands to the arithmetic logic unit, and reads the operands from the load-memory unit. After the arithmetic logic unit finishes execution, the write-back unit writes the result back to the register file. The arithmetic logic unit includes an ALU logic operation subunit, a CORDIC operation subunit, and an operation data path module. The CORDIC operation subunit initiates a shared operation request to the operation data path module according to the CORDIC perspective calculation instructions, and retrieves the calculation result from the operation data path module. The operation data path module accepts the requests from the ALU logic operation subunit and the CORDIC operation subunit, performs the calculation, and returns the calculation result to the corresponding ALU logic operation subunit and CORDIC operation subunit after the calculation is completed. The CORDIC operation subunit includes a quadrant and special angle discrimination module, a CORDIC algorithm serial iteration module, and an angle compensation module. The quadrant and special angle discrimination module performs quadrant pre-judgment on the coordinate values ​​corresponding to the input source operands and discriminates the angle. When the angle is a preset angle value, it outputs the preset angle solution value; otherwise, it enters the CORDIC algorithm serial iteration module. After the operation is completed, the angle compensation module outputs the angle value.

2. The angle calculation system based on CORDIC instructions according to claim 1, characterized in that, The CORDIC instruction consists of 32 bits. Bits 25-31 are the func7 field, containing 0000010, which is defined as the CORDIC instruction set. Bits 20-24 are the second source operand index. Bits 15-19 are the first source operand index. Bits 12-14 are the func3 field, which is the arctangent operation instruction. Bits 7-11 are the result operand index. Bits 0-6 are the opcode.

3. The angle calculation system based on CORDIC instructions according to claim 1, characterized in that, During instruction execution and computation, the ALU logic operation subunit and the CORDIC operation subunit share the computation data path. The ALU logic operation subunit initiates an operation request to the shared computation path based on the ALU instruction and retrieves the computation result from the shared computation path. The CORDIC operation subunit initiates a shared operation request to the computation data path based on the CORDIC perspective calculation instruction and retrieves the computation result from the computation data path. The computation data path accepts requests from the ALU logic operation subunit and the CORDIC operation subunit, performs the computation process simultaneously, and returns the calculation result to the computation data path of the corresponding subunit after the calculation is completed.

4. The angle calculation system based on CORDIC instructions according to claim 1, characterized in that, The operand values ​​include the operand register index, write-back register index, and operands that need to be read when executing the CORDIC instruction.

5. The angle calculation system based on CORDIC instructions according to claim 1, characterized in that, A dispatch module is set between the decoding module and the computation data path; the CORDIC angle calculation long instruction is first dispatched to the ALU logic operation subunit and delivered through the interface between the ALU logic operation subunit and the delivery module. At the same time, according to the corresponding indication signal obtained from decoding, the ALU logic operation subunit dispatches the CORDIC angle calculation long instruction to the CORDIC operation subunit.

6. The angle calculation system based on CORDIC instructions according to claim 4, characterized in that, The dispatch module is equipped with a FIFO module. When a CORDIC angle calculation long instruction is dispatched, an entry is allocated in the FIFO module to store the source operand register index and result register index of the CORDIC angle calculation long instruction. After the CORDIC angle calculation long instruction is written back, the information in the entry is removed from the FIFO module's cache. When a subsequent CORDIC angle calculation long instruction is dispatched, the source operand register index and result register index of the CORDIC angle calculation long instruction are compared with each entry in the FIFO module to determine whether the CORDIC angle calculation long instruction has RAW and WAW dependencies with a CORDIC angle calculation long instruction that has been dispatched but not yet written back.

7. The angle calculation system based on CORDIC instructions according to claim 1, characterized in that, In its initial state, the CORDIC operation subunit receives the initial source operand and the source operand, and initializes the angle value for the first iteration. Upon receiving the cordic_i_valid signal, it enters the CORDIC angle calculation instruction execution state, and the cordic_sta_is_exec signal becomes valid. Upon receiving the exec_last_cycle signal, it completes the last round of calculation of the CORDIC angle calculation instruction, exits the angle calculation iteration process, and the cordic_sta_is_done signal becomes valid. After the calculation is completed, it outputs the cordic_o_valid signal and the final calculated 32-bit angle value. When the CORDIC operation subunit receives initialization and refresh commands, it does not perform any operation and remains in an idle state.

8. The angle calculation system based on CORDIC instructions according to claim 1, characterized in that, CORDIC computing subunits reuse and share computing data paths, including: In each iteration, the CORDIC arithmetic subunit sends X and Y values ​​to the arithmetic data path, representing the input values ​​and Z values, respectively, and the output values. X and Y are coordinate information, while Z is the output angle value calculated based on the input angle information. The subunit also controls the start, progress, and end of the iteration calculation via output control signals. These control signals include addition, subtraction, and shift signals. Upon receiving these control signals, the arithmetic data path uses its internal adders, subtractors, and shift registers to perform the calculations. The output of each iteration serves as the input to the CORDIC arithmetic subunit until the final result is derived.

9. The angle calculation system based on CORDIC instructions according to claim 1, characterized in that, The CORDIC operation subunit includes an angle compensation unit and an angle discrimination unit. The angle compensation unit expands the CORDIC angle output range to (0, 2π) through interval conversion. At the same time, the angle discrimination unit judges the CORDIC angle and directly outputs the corresponding function value when the CORDIC angle belongs to the set angle.

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