Method and equipment for detecting register of arithmetic device and computer readable medium

Abstract

The invention provides a method for detecting registers of an arithmetic device, and the arithmetic device comprises a plurality of registers. The method comprises at least one sub-detection process, and in each sub-detection process, at least one register is a target register, and at least one other register except the target register is a test accompanying register; each sub-detection process comprises the following steps: writing detection data into the target register; and reading real-time data from the target register and the test accompanying register, and comparing the real-time data with theoretical data. The invention further provides equipment for detecting the register of the arithmetic device and a computer readable medium.

Description

Technical Field

[0001] The present disclosure relates to the technical field of register detection, and in particular to a method and device for detecting a register of a computing device, and a computer-readable medium. Background Art

[0002] There are a large number of registers in the chip, and the status of the registers will directly affect the overall function of the chip, so the detection (verification) of the registers is an important part of chip detection.

[0003] When detecting chip registers in the related technology, after writing data to a register, only the correctness of the data in the register is verified, and the values ​​of other registers are not verified. As a result, the correlation (logic) between registers cannot be measured, and it is also impossible to accurately determine whether the registers and addresses are in a one-to-one correspondence. The detection has loopholes and is insufficient and incomplete, which increases the risk of tape-out. Summary of the invention

[0004] The present disclosure provides a method and device for detecting a register of a computing device, and a computer-readable medium.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for detecting a register of a computing device, wherein the computing device includes a plurality of the registers; the method includes at least one sub-detection process, in each of the sub-detection processes, at least one of the registers is a target register, and at least one other register except the target register is a companion test register; each of the sub-detection processes includes:

[0006] Writing detection data to the target register;

[0007] Real-time data is read from the target register and the companion test register, and the real-time data is compared with theoretical data.

[0008] In a second aspect, an embodiment of the present disclosure provides a method for detecting a register of a computing device, wherein the computing device includes a plurality of the registers; the method includes:

[0009] Establishing a register model according to the information of the register in the computing device; the register model includes the address of each register;

[0010] Setting a random number generation function, and using the random number generation function to generate a random value as detection data;

[0011] According to the order of the addresses from front to back, one of the registers is selected each time as the target register to perform the sub-detection process until the register with the last address is selected as the target register;

[0012] According to the order of the addresses from back to front, one of the registers is selected each time as the target register to perform the sub-detection process until the register with the frontmost address is selected as the target register;

[0013] In each of the sub-detection processes, one register is the target register, and at least one other register except the target register is a companion test register; each of the sub-detection processes includes:

[0014] Writing the detection data into the target register through the front door;

[0015] The real-time data is read from the target register and all the accompanying test registers through a back door, and the real-time data is compared with theoretical data.

[0016] In a third aspect, an embodiment of the present disclosure provides a device for detecting registers of a computing device, which includes a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements any one of the methods for detecting registers of a computing device of the embodiments of the present disclosure.

[0017] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, and when the computer program is executed by a processor, the method for detecting a register of a computing device according to any one of the embodiments of the present disclosure is implemented.

[0018] In the disclosed embodiment, after writing specific data (test data) to the target register, in addition to reading and verifying the data in the target register (real-time data), the data (real-time data) of the register that is not directly written this time (companion test register) is also read and verified; thus, the disclosed embodiment can not only detect errors in a single register itself, but also detect data errors caused by other registers being rewritten due to unknown errors or incorrect associations between registers, thereby avoiding detection loopholes, making detection more sufficient and complete, improving detection results, and reducing tape-out risks. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In the accompanying drawings of the embodiments of the present disclosure:

[0020] Figure 1 A flowchart of a method for detecting a register of a computing device provided by an embodiment of the present disclosure;

[0021] Figure 2 A flowchart of another method for detecting a register of a computing device provided by an embodiment of the present disclosure;

[0022] Figure 3 A flowchart of another method for detecting a register of a computing device provided by an embodiment of the present disclosure;

[0023] Figure 4 A block diagram of a device for detecting a register of a computing device provided in an embodiment of the present disclosure;

[0024] Figure 5 A block diagram of a computer-readable medium provided for an embodiment of the present disclosure;

[0025] Figure 6 A block diagram of a detection system provided in an embodiment of the present disclosure;

[0026] Figure 7 A logical process diagram of another method for detecting a register of a computing device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the method and device for detecting the register of a computing device and the computer-readable medium provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0028] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments set forth below. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete, and will enable those skilled in the art to fully understand the scope of the present disclosure.

[0029] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0030] The present disclosure may be described with reference to plan views and / or cross-sectional views by means of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0031] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0032] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0034] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0035] With the development of integrated circuit (IC) technology, the scale and complexity of chips (computing devices) are increasing day by day, so the workload and difficulty of chip detection (verification) are also increasing rapidly. For example, in the development process of some chips, the time spent on detection may account for 70% of the entire project; but even with such a huge investment of energy, the incompleteness of detection work is still one of the main reasons for tape-out failure, becoming a bottleneck limiting the chip development cycle.

[0036] There are a large number of registers in the chip, which are the core components for realizing the chip's computing functions. Therefore, comprehensive and effective detection of the registers in the chip is an important part of the overall chip detection.

[0037] In some related technologies, the detection method for registers in a chip is to detect each register individually, that is, a predetermined expected value (detection data) is written into a register through a bus (Bus), and then a mirror value (real-time data) is immediately read from the register, and the mirror value is compared with the expected value to see if they are the same. If they are the same, the register is judged to be correct, and if they are different, the register is judged to be faulty.

[0038] However, there are intricate associations (logical relationships) between many registers of the chip, and changes in the values ​​of one or more registers will often cause changes in the values ​​of one or more other registers. The related technology is to read data immediately after writing data to a register, so it can only detect the read and write functions of a single register itself, but cannot detect the association (logic) between registers. There are loopholes, and the detection is insufficient and incomplete, which increases the risk of tape-out.

[0039] In a first aspect, an embodiment of the present disclosure provides a method for detecting a register of a computing device, wherein the computing device includes a plurality of registers.

[0040] In the embodiments of the present disclosure, the computing device is a device with integrated circuit as the main body and has data processing (computing) functions, which can be specifically in the form of a chip (processor, such as a central processing unit), a programmable logic controller (PLC), etc.; the register is a high-speed storage device for temporarily storing a small amount of data; in each computing device, a large number of registers are provided, and some of the registers may have a certain correlation relationship.

[0041] The method of the embodiment of the present disclosure is used to detect (verify) whether the register in the computing device is normal.

[0042] The method of the embodiment of the present disclosure includes at least one sub-detection process (S1).

[0043] In each sub-test process, at least one register is a target register, and at least one register other than the target register is a companion test register.

[0044] Reference Figure 1 , each sub-detection process (S1) includes:

[0045] S101, writing detection data into a target register.

[0046] S102, read out real-time data from the target register and the accompanying test register, and compare the real-time data with the theoretical data.

[0047] In the embodiment of the present disclosure, the detection of the registers of the computing device includes one or more "sub-detection processes", and each sub-detection process is a specific detection operation performed on at least part of the registers.

[0048] That is, in each sub-test process, one or more registers are selected as "target registers", and one or more registers other than the target registers are selected as "co-test registers", so as to operate on these target registers and co-test registers.

[0049] Specifically, in each sub-test process, the known data (test data, such as expected value) is first written into the target register selected this time through the front door, and then the actual stored data (real-time data, such as mirror value) is read out from the target register selected this time and the accompanying test register through the back door, and the real-time data is compared with the theoretical data (such as theoretical value) that the register should theoretically have at this time to see if they are the same:

[0050] (1) If they are the same, it means that the sub-test (verification) process has passed, and the sub-test process has not found any problem with the corresponding register (it does not necessarily mean that the corresponding register is completely free of problems).

[0051] (2) If they are different, it indicates that the sub-test (verification) process has failed and the sub-test process has found a problem in the corresponding register.

[0052] The detection data is predetermined (known) data used to be written into the target register.

[0053] In some embodiments, the detection data is random data generated according to a preset random number generation algorithm.

[0054] As one method of an embodiment of the present disclosure, a preset random number generation algorithm may be used to generate some random data (random values) as the above detection data.

[0055] It should be understood that the specific form of the detection data is not limited thereto, and artificially specified data may also be used as the detection data.

[0056] It should be understood that when there are multiple target registers (including multiple target registers in one sub-detection process, or multiple target registers in different sub-detection processes), their detection data may be the same (such as generating random data with a length equal to the bit width of one target register, and repeatedly using it as the detection data of each target register), or different (such as generating a random data sequence with a length equal to the sum of the bit widths of all target registers, and using different parts of it in turn as the detection data of each target register).

[0057] The theoretical data refers to the data that should be there in theory after the detection data is written into the target register and when there are no errors in each register; the theoretical data of different registers can be determined according to the specific situation.

[0058] For example, during a sub-detection process, the theoretical data of the target register should be the detection data just written.

[0059] For another example, if a companion test register has had data written into it before (such as test data having been written into it as a target register in a previous sub-test process), then its theoretical data should be the data written into it before (such as the previous test data); and if a companion test register has not had data written into it, then its theoretical data should be its default value (initial value).

[0060] For another example, if a companion test register is associated with other registers (such as the target register) (data changes in other registers will cause data changes in the companion test register), and the data in other registers are indeed changed during the sub-test process, then the theoretical data of the companion test register should be the data obtained after the original data is changed.

[0061] Therefore, during the sub-detection process, if the real-time data of the target register (just written) does not match the theoretical data, it indicates that there is an error in the read and write function of the target register; and if the real-time data of the accompanying test register (not written this time) does not match the theoretical data, it indicates that the data of the accompanying test register should not have changed but has been changed due to the influence of other registers, or the data of the accompanying test register should have changed due to the influence of other registers but has not actually changed, both of which indicate that there is an error in the association between the accompanying test register and other registers.

[0062] In the disclosed embodiment, after writing specific data (test data) to the target register, in addition to reading out and verifying the data in the target register (real-time data), the data (real-time data) of the register (companion test register) that is not directly written this time is also read out and verified; thus, the disclosed embodiment can not only detect errors in a single register itself, but also detect data errors caused by other registers being rewritten due to unknown errors or incorrect associations between registers, thereby avoiding detection loopholes, making detection more sufficient and complete, improving detection results, and reducing tape-out risks.

[0063] It should be understood that a read-only register cannot be used as a target register in the embodiments of the present disclosure (because test data cannot be written to it), and a write-only register cannot be used as a companion test register in the embodiments of the present disclosure (because data therein cannot be read out); therefore, a certain register selected in the embodiments of the present disclosure must meet the above requirements, and accordingly, the "all registers" and "traversal registers" mentioned in the embodiments of the present disclosure are also for registers that meet the above requirements, rather than necessarily all registers and hardware.

[0064] In some embodiments, in each sub-test process, one register is a target register, and all registers except the target register are co-test registers.

[0065] It should be understood that the specific methods of the target register and the accompanying test register in each sub-test process are various. For example, in each sub-test process, multiple registers can be used as target registers at the same time, or only registers that are designed to be associated with the target register (associated registers) can be used as accompanying test registers, etc.

[0066] As a specific method of the embodiment of the present disclosure, in each sub-detection process, "only" one register can be selected as the target register, and "all" other registers can be used as co-test registers; that is, each sub-detection process only writes data to one register, and reads and verifies the data of all registers. This is because this method has the following advantages:

[0067] (1) After writing data to the target register, in theory, only the value of its "associated register" will change, that is, the data of the associated register "most needed" to be read in each sub-test process; however, if "only" the associated register is used as the companion test register, it is necessary to determine which registers are the "associated registers" of the target register before each test process. However, there are many registers in the computing device, and the association relationship between them is also very complex. Therefore, compared with the method of directly using all other registers as companion test registers, the process of determining the associated register alone will greatly increase the workload.

[0068] (2) Some errors in associated registers can only be discovered by using the above method.

[0069] For example, the address of a register may be wrong, resulting in a non-one-to-one correspondence between the register name and the address.

[0070] For example, assume that there are three interrelated registers named reg1, reg2, and reg3, with addresses 001, 002, and 003, respectively, and the logical relationship between the values ​​of the three registers is reg3=reg1+reg2, and the default values ​​after reset are all 0; but due to an address error, the addresses of reg1 and reg2 are both 001. When reg1 and reg2 are used as target registers and "1" is written to them respectively as test data, the result is that the values ​​of reg1 and reg2 are both 1, and the value of reg3 is 1+1=2. The result seems to be correct, but in fact, the value of reg2 becomes 1 when data is written to reg1 (address 001), which is incorrect; and the above errors can only be discovered when reg1 is used as the target register alone and all other registers are used as accompanying test registers.

[0071] (3) In addition to associated registers, the values ​​of other "unassociated" registers may also be "erroneously" overwritten. This situation also requires the above method to ensure detection.

[0072] For example, assume that there are two unrelated registers named reg1 and reg2, with addresses 001 and 002 respectively, but due to an address error, the addresses of both are 001; therefore, when reg1 is used as the target register and test data is written into it, the test data is actually written into reg2 as well. If the "unrelated" reg2 is not used as the companion test register at this time, the error cannot be discovered.

[0073] In some embodiments, reference Figure 2 The method of the embodiment of the present disclosure includes: a first detection stage (A1), the first detection stage includes a plurality of sub-detection processes (S1) performed sequentially; the number of sub-detection processes in the first detection stage is equal to the total number of registers in the computing device, and in the plurality of sub-detection processes performed sequentially, all registers are sequentially used as target registers in a predetermined order.

[0074] As one method of the embodiment of the present disclosure, multiple sub-detection processes (S1) may be performed continuously as a "large detection stage", i.e., the first detection stage (A1). In each sub-detection process of the first detection stage, all registers are "traversed" once as target registers in a predetermined order. In other words, a register is selected as the target register for each sub-detection process, and in the entire first detection stage, each register is used as the target register "only" once, and all registers are used as target registers in a predetermined order (predetermined order).

[0075] Therefore, in the first detection stage, each register is once subjected to a sub-detection process as a target register alone, and when each register is written with detection data as a target register, all other registers are read out of real-time data as accompanying test registers; therefore, the above method achieves complete detection.

[0076] In some embodiments, the predetermined order is an ascending or descending order of the addresses of the registers.

[0077] Each register in the computing device has a certain address. As a method of an embodiment of the present disclosure, in the first detection stage, each register can be selected as the target register in sequence according to the ascending order (address from low to high or from front to back) or descending order (address from high to low or from back to front) of the address of each register and perform the corresponding sub-detection process.

[0078] It should be understood that the specific form of the predetermined order is not limited thereto, and the predetermined order may also be generated according to certain algorithms.

[0079] In some embodiments, reference Figure 2 , before the first detection stage (A1), also includes:

[0080] S01. Reset all registers.

[0081] As a method of an embodiment of the present disclosure, before starting the first detection stage, all registers in the computing device can be reset so that the data stored therein are restored to default values, thereby eliminating the impact of previous data on the detection and facilitating the determination of theoretical data.

[0082] For example, if the relationship between the registers is not considered, then in each sub-detection process, the theoretical data of the target register should be the detection data written this time, and the theoretical data of the register that has been the target register in the previous sub-detection process (this time the accompanying test register) should be the detection data written therein in the previous sub-detection process, and the theoretical data of the register that has never been the target register (this time the accompanying test register) should be the default value.

[0083] In some embodiments, reference Figure 2 , after the first detection stage (A1), it also includes: a second detection stage (A2), the second detection stage includes multiple sub-detection processes (S1) performed in sequence; the number of sub-detection processes in the second detection stage is equal to the total number of registers in the computing device, and in the multiple sub-detection processes performed in sequence, all registers are sequentially used as target registers in the reverse order of a predetermined order.

[0084] As one method of an embodiment of the present disclosure, after the first detection stage is completed, the target registers can be selected in sequence in the "reverse order (reverse order of the predetermined order)" and multiple sub-detection processes can be performed until all registers are traversed again, thereby completing the "second detection stage".

[0085] Since the influence between registers may be "one-way" or "two-way", and there may be a situation where multiple registers change before affecting another register, a comprehensive detection of various associations between registers can be achieved by "traversing all registers twice in reverse order" for a sub-detection process.

[0086] In some embodiments, reference Figure 2 , between the first detection stage (A1) and the second detection stage (A2), further comprising:

[0087] S02. Reset all registers.

[0088] As a method of an embodiment of the present disclosure, after the first detection stage is completed and before the second detection stage begins, all registers of the computing device can be reset so that the data stored therein are restored to the default values, thereby eliminating the influence of previous data (data generated in the first detection stage) on the detection in the second detection stage, and facilitating the determination of theoretical data.

[0089] In a second aspect, an embodiment of the present disclosure provides a method for detecting a register of a computing device, wherein the computing device includes a plurality of registers.

[0090] Reference Figure 3 , the method for detecting the register of the computing device according to the embodiment of the present disclosure includes:

[0091] S201. Establish a register model according to the information of the register in the computing device.

[0092] Among them, the register model includes the address of each register.

[0093] S202, setting a random number generation function, and using the random number generation function to generate a random value as detection data.

[0094] S203 , selecting one register as the target register each time to perform a sub-detection process in the order of addresses from front to back, until the register with the last address is selected as the target register.

[0095] S204 , selecting one register as the target register each time to perform a sub-detection process in the order of addresses from back to front, until the register with the frontmost address is selected as the target register.

[0096] In each sub-test process, one register is a target register, and at least one other register other than the target register is a companion test register; each sub-test process includes:

[0097] Write detection data to the target register through the front gate;

[0098] The real-time data is read from the target register and all the accompanying test registers through the backdoor, and the real-time data is compared with the theoretical data.

[0099] As a specific method of an embodiment of the present disclosure, before performing a specific sub-detection process, the information of the registers in the computing device to be detected can be obtained first, and a register model can be established based on this. The register model has at least the address of each register (it can also include the name, bit width, read-write attributes, default value, etc. of each register).

[0100] At the same time, a random number generation function (random number generation algorithm) is customized and used to generate random values ​​as detection data for subsequent use.

[0101] After that, one register can be selected as the target register each time for the sub-detection process in the order of the address from front to back; in this sub-detection process, the selected register is used as the target register, and all other registers are used as accompanying test registers, and the above random value (detection data) is written to the target register through the front door, and then the real-time data is read from all registers through the back door and compared with the theoretical data.

[0102] After all registers have been selected as target registers for the sub-detection process in the order of addresses from front to back (i.e., the first detection stage is completed), the sub-detection process can be reversed and one register can be selected as the target register at a time in the order of addresses from back to front for the sub-detection process until all registers have been selected as target registers for the sub-detection process (i.e., the second detection stage is completed).

[0103] Thirdly, refer to Figure 4 An embodiment of the present disclosure provides a device for detecting the register of a computing device, which includes a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, any method of detecting the register of a computing device in the embodiments of the present disclosure is implemented.

[0104] Fourthly, refer to Figure 5 An embodiment of the present disclosure provides a computer-readable medium on which a computer program is stored. When the computer program is executed by a processor, any method of detecting a register of a computing device in the embodiments of the present disclosure is implemented.

[0105] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, and can realize information exchange between the memory and the processor, including but not limited to the data bus (Bus), etc.

[0106] Example:

[0107] The following is an exemplary introduction to the method and device for detecting the register of a computing device according to an embodiment of the present disclosure.

[0108] The device for detecting the registers of the computing device in the embodiment of the present disclosure is in the form of a "detection system", which includes a detection platform, a register model module, and a register information document module.

[0109] Reference Figure 7 , the process of using the above detection system to perform detection may include:

[0110] B101. Build a testing platform according to needs.

[0111] Reference Figure 6The detection platform includes an environment component (Env), in which a reference model component (Reference model l), a scoreboard component (Scoreboard) and multiple agent components (Agent, such as Tx_agent, Rx_agent) are instantiated. The above components are connected through a transaction level module (TLM, Transaction Level Module) communication; and each agent component instantiates a monitor component (Mon itor), an incentive driver component (Driver), and a data packet component (Sequence item). The monitor component and the incentive driver component are connected to the serial peripheral interface (SPI, Serial Peripheral Interface) bus through an intf interface (such as Tx_intf, Rx_intf), and the SPI is then connected to the computing device (i.e., the device under test DUT, Device Under Test).

[0112] Among them, the above components are conventional components for realizing the control of DUT and will not be described in detail here.

[0113] B102, the register information document module creates a register information document (Reg mode l) according to the information of the registers in the computing device to be tested, which includes the name, bit width, read-write attributes (such as whether the register is read-only, write-only, read-write, etc.), default value, address and other information of each register.

[0114] B103. The register model module reads the information of the register information document, saves the corresponding information as an element into the queue of the register model through a preset script, and implants the corresponding register model into the detection platform.

[0115] B104. The detection platform generates random values ​​(detection data) using a custom function (random number generation algorithm) based on the register model, and determines the register with the smallest address that has not been written to in this stage (target register) based on the register model, writes the random value into the register through front-door access, and then reads the values ​​(real-time data) of all registers (target registers and companion test registers) through back-door access.

[0116] B105. Compare the values ​​of all registers with the expected values ​​(theoretical data) to see if they are consistent.

[0117] If it matches, then return to step B104, reselect the register to be written (target register) and repeat the above process until all registers are traversed (the first detection stage is completed).

[0118] If it does not meet the requirements, it is confirmed that there is an error and the error is reported for the designer to study and modify.

[0119] B106, reset all registers.

[0120] B107. Repeat steps B104 to B105, except that the register with the largest address that has not been written is selected, until all registers are traversed for the second time (the second detection stage is completed), and the detection is completed.

[0121] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0122] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0123] Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-temporary medium) and a communication medium (or temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical disk storage; magnetic cassettes, magnetic tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0124] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for detecting a register of a computing device, wherein: The computing device includes a plurality of the registers; the method includes at least one sub-detection process, in each of the sub-detection processes, at least one of the registers is a target register, and at least one register other than the target register is a companion test register; each of the sub-detection processes includes: Writing detection data to the target register; Real-time data is read from the target register and the companion test register, and the real-time data is compared with theoretical data.

2. The method according to claim 1, wherein: In each of the sub-test processes, one register is the target register, and all registers except the target register are the accompanying test registers.

3. The method according to claim 2, wherein: include: A first detection stage, wherein the first detection stage includes a plurality of sub-detection processes performed sequentially; The number of the sub-detection processes in the first detection stage is equal to the total number of the registers in the computing device. In a plurality of sub-detection processes performed sequentially, all the registers are sequentially used as the target registers in a predetermined order.

4. The method according to claim 3, wherein: The predetermined order is an ascending order or a descending order of the addresses of the registers.

5. The method according to claim 3, wherein: Before the first detection stage, the method further includes: Resets all of the mentioned registers.

6. The method according to claim 3, wherein: After the first detection stage, the method further includes: a second detection stage, wherein the second detection stage includes a plurality of sub-detection processes performed sequentially; The number of the sub-detection processes in the second detection stage is equal to the total number of the registers in the computing device. In a plurality of sub-detection processes performed sequentially, all the registers are sequentially used as the target registers in reverse order of the predetermined order.

7. The method according to claim 6, wherein: Between the first detection stage and the second detection stage, the method further includes: Resets all of the mentioned registers.

8. The method according to claim 1, wherein: The detection data is random data generated according to a preset random number generation algorithm.

9. A method for detecting a register of a computing device, wherein: The computing device includes a plurality of registers; the method includes: Establishing a register model according to the information of the register in the computing device; the register model includes the address of each register; Setting a random number generation function, and using the random number generation function to generate a random value as detection data; According to the order of the addresses from front to back, one of the registers is selected each time as the target register to perform the sub-detection process until the register with the last address is selected as the target register; According to the order of the addresses from back to front, one of the registers is selected each time as the target register to perform the sub-detection process until the register with the frontmost address is selected as the target register; In each of the sub-detection processes, one register is the target register, and at least one other register except the target register is a companion test register; each of the sub-detection processes includes: Writing the detection data into the target register through the front door; The real-time data is read from the target register and all the accompanying test registers through a back door, and the real-time data is compared with theoretical data.

10. A device for detecting the register of a computing device, comprising a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, the method for detecting the register of a computing device described in any one of claims 1 to 9 is implemented.

11. A computer-readable medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the method for detecting a register of a computing device according to any one of claims 1 to 9 is implemented.

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