Thermally aware thread scheduling

Abstract

The invention relates to thermally aware thread scheduling. Devices, systems, and techniques for controlling utilization of a combination of processing cores. In at least one embodiment, utilization of the combination of processing cores is controlled based at least in part on historical thermal characteristics of the combination of processing cores.

Description

Technical Field

[0001] At least one embodiment is directed to processing resources for executing one or more programs. For example, at least one embodiment is directed to a processor or computing system for causing a device to operate based at least in part on the execution of application program instructions. Background Art

[0002] Processors are typically configured to manage heat through a software thermal policy that monitors the average temperature of thermal sensors located in a set of operating cores. Currently, a worst-case hotspot thermal excursion estimate based on the profiled application is added as a safety margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A system including a controller and a processor to optimize processor performance according to at least one embodiment is shown;

[0004] Figure 2 A use case is shown representing optimizing performance of a group of processors by a controller in accordance with at least one embodiment;

[0005] Figure 3 A flow chart showing a relationship between a controller and a plurality of processors when using application-specific thermal information according to at least one embodiment is shown;

[0006] Figure 4 A block diagram illustrating a relationship between a controller and a plurality of processors when using application-specific thermal information according to at least one embodiment is shown;

[0007] Figure 5 illustrates a relationship between a controller and a plurality of processors using application-specific thermal information according to at least one embodiment;

[0008] Figure 6 A process for managing application scheduling to avoid worst case processor utilization patterns in accordance with at least one embodiment is shown;

[0009] Figure 7 illustrates an exemplary data center in accordance with at least one embodiment;

[0010] Figure 8 A processing system according to at least one embodiment is shown;

[0011] Fig. 9 A computer system according to at least one embodiment is shown;

[0012] Fig.10 A system according to at least one embodiment is shown;

[0013] Fig.11 An exemplary integrated circuit according to at least one embodiment is shown;

[0014] Fig.12 A computing system according to at least one embodiment is shown;

[0015] Fig.13 An APU is shown according to at least one embodiment;

[0016] Fig.14 A CPU according to at least one embodiment is shown;

[0017] Fig.15 An exemplary accelerator integrated slice is shown in accordance with at least one embodiment;

[0018] FIG. 16A to FIG. 16B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0019] Fig.17A illustrates a graphics core according to at least one embodiment;

[0020] Fig. 17B A GPGPU is shown according to at least one embodiment;

[0021] Fig.18A illustrates a parallel processor according to at least one embodiment;

[0022] Fig.18B illustrates a processing cluster according to at least one embodiment;

[0023] Fig.18C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0024] Fig.19 A graphics processor according to at least one embodiment is shown;

[0025] Fig. 20 A processor according to at least one embodiment is shown;

[0026] Fig.21 A processor according to at least one embodiment is shown;

[0027] Fig. 22 illustrates a graphics processor core according to at least one embodiment;

[0028] Fig.23 illustrates a PPU according to at least one embodiment;

[0029] Fig.24 shows a GPC according to at least one embodiment;

[0030] Fig.25A streaming multiprocessor is shown according to at least one embodiment;

[0031] Fig.26 A software stack for a programming platform according to at least one embodiment is shown;

[0032] Fig. 27 According to at least one embodiment, Fig.26 CUDA implementation of the software stack;

[0033] Fig.28 According to at least one embodiment, Fig.26 ROCm implementation of the software stack;

[0034] Fig.29 According to at least one embodiment, Fig.26 OpenCL implementation of the software stack;

[0035] Fig.30 illustrates software supported by a programming platform according to at least one embodiment;

[0036] Fig.31 According to at least one embodiment, Figure 26-29 Compiled code executed on the programming platform;

[0037] Fig.32 According to at least one embodiment, Figure 26-29 More detailed coding executed on the programming platform;

[0038] Fig.33 Transforming source code prior to compiling the source code according to at least one embodiment is shown;

[0039] Fig.34A A system configured to compile and execute CUDA source code using different types of processing units according to at least one embodiment is shown;

[0040] Fig.34B A method configured to compile and execute using a CPU and a CUDA-enabled GPU according to at least one embodiment is shown. Fig.34A CUDA source code system;

[0041] Fig.34C A method configured to compile and execute using a CPU and a non-CUDA enabled GPU according to at least one embodiment is shown. Fig.34A CUDA source code system;

[0042] Fig.35 According to at least one embodiment, Fig.34C An example kernel converted by the CUDA to HIP conversion tool;

[0043] Fig.36 In more detail, the Fig.34C A non-CUDA-enabled GPU;

[0044] Fig.37 shows how threads of an exemplary CUDA grid are mapped to Fig.36 different computing units of

[0045] Fig.38 It shows how to migrate existing CUDA code to data parallel C++ code according to at least one embodiment. DETAILED DESCRIPTION

[0046] In the following description, numerous specific details are set forth to provide a more complete understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the concept of the present invention can be practiced without one or more of these specific details.

[0047] In at least one embodiment, the multi-core CPU chip includes a thermal sensor physically positioned according to the hardware design. In at least one embodiment, the multi-core CPU chip is a server chip. In at least one embodiment, the average temperature Taverage measured by the thermal sensor on the chip is calculated by software during operation, and if the average value exceeds a predetermined thermal limit, remedial measures are taken. In at least one embodiment, the remedial measures include limiting the operating frequency. In at least one embodiment, the thermal sensor cannot be guaranteed to be precisely located at the hottest point, and therefore may not capture the worst-case thermal behavior caused by one or more running applications. In at least one embodiment, the application refers to a computing workload. In at least one embodiment, the thermal offset is therefore added to the average temperature calculation as a margin of error. In at least one embodiment, the added thermal offset over-penalizes certain applications (especially applications that do not actually exhibit the worst processor usage pattern) and imposes thermal-based constraints on performance in the pathological use cases utilized by these processors. In at least one embodiment, the pathological use case utilized by the processor is a processor usage pattern or combination that causes problematic thermal behavior. For example, in at least one embodiment, a pathological case of processor utilization may occur when a group of processor cores are highly utilized and located close to each other on the chip, causing the local temperature of that area to exceed a safety margin.

[0048] Figure 1A block diagram 100 of a system including a controller and a processor to optimize processor performance according to at least one embodiment is shown. In at least one embodiment, the system 100 includes one or more processor chips, each processor chip including one or more physical cores. In at least one embodiment, the chip has 2 sockets, each socket has 76 physical cores, for a total of 152 cores. In at least one embodiment, the firmware controller 102 optimizes the overall performance of a group of processor cores 104a-104n. In at least one embodiment, in combination with Figure 1 One or more aspects of one or more embodiments described herein may be combined with one or more aspects of one or more embodiments described herein, including at least one aspect of one or more embodiments described herein. Figures 2 to 6 Described embodiments.

[0049] In at least one embodiment, the measurements from the thermal sensor 106 provide substantially real-time thermal measurements. In at least one embodiment, the profile 108 includes stored information for identifying processor combinations associated with pathological patterns of processor usage. In at least one embodiment, a more complete understanding of the usage patterns of a group of processors (e.g., processors 104a-104n) by an application includes identifying pathological use cases of thermal conditions based on information provided in the profile 108 about the use of the processor by one or more applications, which may lead to pathological patterns of processor usage. In at least one embodiment, the profile 108 is associated with one or more specific applications. In at least one embodiment, the profile 108 is specific to a chip, an operating system, or a computing device. In at least one embodiment, a more complete understanding of the usage patterns of a group of processors (e.g., processors 104a-104n) by an application includes neural network processing.

[0050] Figure 2 Optimization of overall thermal performance of a group of processors associated with a group of processors 104a-104n according to at least one embodiment is shown. In at least one embodiment, a first core assembly of processors displays a thermal image 202a captured by, for example, an infrared sensitive camera. In at least one embodiment, the thermal image indicates temperature or heat radiating from a portion of the image.

[0051] In at least one embodiment, a core combination refers to a subset of processors on a chip that are assigned to handle processing tasks. In at least one embodiment, a core combination that requires thermal limiting before power limiting is required is a pathological mode of processor utilization, which may also be described as a worst-case processor combination, a pathological core combination, a worst-case processor core combination, or other similar terms. In at least one embodiment, a thermal mask (sometimes referred to as a core mask) indicates a processor utilization pattern to be avoided.

[0052] In at least one embodiment, pathological use cases for thermal conditions are identified based on information indicating expected or actual core usage by one or more applications. In at least one embodiment, worst case combinations are indicated in a configuration file read by the firmware. In at least one embodiment, the configuration file identifies combinations of processor core utilization that may cause problematic thermal behavior. In at least one embodiment, these combinations are masked. In at least one embodiment, masking the combinations causes the scheduler to avoid scheduling threads on the masked processors or processor cores. In at least one embodiment, the firmware prevents the operating system scheduler from scheduling threads in a manner that would cause these combinations to occur.

[0053] In at least one embodiment, the core mask is indicated to the kernel to prevent the corresponding thread from being available to the scheduler. In at least one embodiment, the controller (e.g. Figure 1 The controller 102 shown in FIG. 1 updates the allowed processor capacity to the peak capacity by setting Fmax via the ACPI table, which is available to the scheduler.

[0054] In at least one embodiment, thermal image 202b is generated by applying a thermal strategy that implements the shielding, thereby preventing or reducing the occurrence of pathological modes of processor utilization. In at least one embodiment, this is done at least in part based on processor utilization patterns characterized by profiles or other means, such as in conjunction with Figure 1 described.

[0055] In at least one embodiment, thermal image 202a may be generated by a static thermal strategy that features thermal excursions and lacks an expected profile that provides a pathological core combination. In at least one embodiment, a software thermal strategy that manages Taverage is improved by identifying specific processor combinations that cause problematic thermal behavior, which is supplemented by a constant feature hot spot excursion added to the thermal strategy to observe a selected absolute maximum temperature limit (Tjmax). In at least one embodiment, depending on the subset of cores enabled, thermal density and hot spots may begin to increase to problematic levels before the chip is power limited. In at least one embodiment, the chip is power limited when the chip is running at a maximum allowed clock frequency, which corresponds to the maximum allowed supply voltage.

[0056] In at least one embodiment, as shown in thermal image 202a, the core combination is running at a clock frequency (supply voltage) per socket that requires thermal limiting due to hotspot 206, and is therefore actually performance limited. In at least one embodiment, as shown in thermal image 202b, the performance of different core combination selections exhibits relatively mild thermal regions 208 and does not need to be limited according to thermal policy. In at least one embodiment, processors that do not exhibit hotspot 206 can be run at a maximum allowed frequency setting according to performance rather than thermal policy. In at least one embodiment, shielding the sick mode utilized by the processor allows such operation at the maximum allowed frequency.

[0057] Figure 3 is a flow diagram illustrating, in at least one embodiment, the relationship between a controller and multiple processors when using application-specific thermal information.

[0058] In step 302, in at least one embodiment, the worst case thermal combination is read from a file. In at least one embodiment, the file is such as Figure 1 Configuration file 108 is shown.

[0059] In at least one embodiment, at step 304, a controller (e.g. Figure 1 The controller 102 shown in FIG. 10A updates an Advanced Configuration and Power Interface (ACPI) table to indicate to the scheduler the capacity used by each processor core when executing the workload application to be run. In at least one embodiment, the scheduler is an ARM core / scheduler.

[0060] In one embodiment, the controller monitors the processor's thermals according to a software specified thermal policy at step 306. In at least one embodiment, the firmware includes instructions to monitor the processor's thermal behavior while the processor is in use.

[0061] In one embodiment, a core mask is applied based on the thermal constraints at step 308. In at least one embodiment, this includes indicating the core mask to the kernel and causing the kernel to prevent the selected thread from being scheduled on the processor core indicated by the mask. In at least one embodiment, this prevents pathological processor utilization patterns from occurring.

[0062] In at least one embodiment, the controller 102 cooperates with the kernel to cause the shielded core to enter a low power state at step 310. In at least one embodiment, instructions in firmware and software are executed to cooperate with the application kernel to cause the heat shielded processor to enter a low power state when the heat shielded processor is not executing an operating system task or other task that may be classified as having a high priority.

[0063] In at least one embodiment, threads are scheduled onto unshielded cores in step 312. In at least one embodiment, by scheduling threads in a manner that emphasizes the use of unshielded cores, thermal hot spots may be avoided.

[0064] Figure 4 4 is a block diagram illustrating, in at least one embodiment, optimizing the overall performance of a group of processors. In at least one embodiment, worst case processor combination characteristics are provided to the scheduler in a configuration file as a core mask 412 applied to a group of processors, with the result that one or more combinations 404a and 404d of the group of processors are prevented from being scheduled for a task. In at least one embodiment, an operating system (OS) scheduler increases the scheduling of one or more processors 404b and 404c in the group and decreases the scheduling of one or more other processors 404a and 404d in the group. In at least one embodiment, the firmware prevents the OS scheduler from scheduling threads that use these combinations to allow the processors in the group to run cooler for a given application than if no blocking were done.

[0065] In at least one embodiment, schematic 400 includes an OS scheduler 402 and a CPU chip 404 containing processor cores (1-32). In at least one embodiment, OS scheduler 402 is communicatively connected to CPU chip 404 and one or more processor cores (1-32) and also to ARM / core scheduler 406. In at least one embodiment, ARM / core scheduler 406 is communicatively connected to firmware 408. In at least one embodiment, information such as temperature (in conjunction with Figure 1-3 408 and one or more thermal sensors 410. In at least one embodiment, the thermal sensors 410 are such as Figure 1 Thermal sensor 106 is shown.

[0066] In at least one embodiment, the CPU chip 404 is a multi-core CPU chip. In at least one embodiment, the CPU chip 404 is a chip containing 152 physical cores, with two sockets each having 76 cores. In at least one embodiment, the CPU chip 404 is a server chip.

[0067] In at least one embodiment, CPU chip 404 operates in an Advanced RISC Microprocessor (ARM) environment.

[0068] In at least one embodiment, an application running on CPU chip 404 can use a combination of multiple cores. In at least one embodiment, a combination of 28 cores is used. In at least one embodiment, if no thermal policy is applied, the application running on CPU chip 404 will run at an unconstrained performance level. In at least one embodiment, applications using less than a threshold number of cores run at an unconstrained performance level without being thermally limited. In at least one embodiment, the threshold is 36 cores.

[0069] In at least one embodiment, deep learning and artificial intelligence applications are applications that run on the CPU chip 404.

[0070] In at least one embodiment, software and / or firmware provides hot core mask information to the ARM kernel / scheduler to obtain these inputs. In at least one embodiment, the OS scheduler operates independently of the hot core mask. In at least one embodiment, Nvidia software and / or firmware cooperates with the kernel to implement extremely low power states in heat-shielded cores. In at least one embodiment, the extremely low power states are limited to processing interrupts or other strictly related work.

[0071] Figure 5 An example 500 of a relationship between a controller and multiple processor cores using application-specific thermal information is shown in accordance with at least one embodiment.

[0072] In step 502, in at least one embodiment, based on information (profile 504) of the expected core usage of the application provided by the given application, pathological use cases of thermal conditions are identified. In at least one embodiment, the firmware and software tracks which processors a given application chooses to use and compares the group of processors to at least one profile to see if it is one of those combinations identified as masked combinations. In at least one embodiment, the worst-case thermal core combination is characterized by firmware and / or software. In an embodiment, the worst-case characterization is based on performance testing of a given application relative to a predefined workload. In at least one embodiment, these specific combinations are masked so that the scheduler schedules threads. In at least one embodiment, the firmware prevents the OS scheduler from scheduling threads using these combinations. In at least one embodiment, the firmware and / or software determines whether each processor core capacity is running at peak capacity. (Fmax) In at least one embodiment, the core mask is indicated to the kernel to prevent the corresponding thread from being made available to the scheduler. The firmware updates the capacity of the processor to the peak capacity by setting Fmax via the ACPI table, which is available to the scheduler.

[0073] In step 506, in at least one embodiment, the ACPI table is updated by the firmware based on the capacity of each core. In one embodiment, the firmware updates the capacity of each processor core to the scheduler via the ACPI table. In one embodiment, the scheduler is an ARM core / scheduler.

[0074] In step 508, in at least one embodiment, the firmware monitors the status of the core thermal sensors relative to temperature. In at least one embodiment, the firmware monitors the thermals associated with the core of the thermal of interest according to the software implemented thermal policy specification and proceeds to thermal shutdown 512 when appropriate.

[0075] In step 510, in at least one embodiment, processor core utilization is monitored while one or more application threads are executing on the processor core. In at least one embodiment, this monitoring includes identifying patterns of processor core utilization. For example, in at least one embodiment, the monitoring of the core utilization pattern is performed in accordance with Figures 1 to 4 The relevant description is carried out.

[0076] At step 512, in at least one embodiment, application execution is suspended if it is determined that temperature conditions appear to exceed or are at risk of exceeding recommended levels based on the thermal sensor information and core utilization patterns monitored in steps 508 and 510. In at least one embodiment, suspending execution includes causing the core to stop executing instructions, referred to as a thermal shutdown in at least one embodiment.

[0077] In step 514, in at least one embodiment, a core mask is applied based on the thermal constraints. Once all of these conditions are met, the controller indicates the core mask to the kernel so that the kernel does not make these threads available to the scheduler. In at least one embodiment, the firmware and / or software provides the thermal core mask to the ARM kernel / scheduler to accept these inputs without exposing these cores to the OS scheduler.

[0078] At step 516, in at least one embodiment, those cores to which the mask was applied in step 514 are placed in low power states. In at least one embodiment, firmware and / or software cooperates with the cores to arrange these low power states to allow only minimal basic activities, such as the handling of interrupts.

[0079] At step 518, in at least one embodiment, thread scheduling on the unshielded cores continues, and at step 520, in at least one embodiment, one or more applications are executed.

[0080] Figure 6A process 600 of managing application scheduling to avoid worst-case processor utilization patterns according to at least one embodiment is shown. In at least one embodiment, an OS scheduler 602 communicates with a kernel 604 to apply 606 a core mask based on a thermal constraint. In at least one embodiment, the thermal constraint is indicated as a pattern of processor core utilization and provided in a configuration file 614. In at least one embodiment, the process 600 checks at 608 whether conditions 610a-610c are true. In at least one embodiment, at 610a, the process 600 compares the configuration file 614 information to the core usage expected for a given application. In at least one embodiment, at 610b, the process 600 updates the capacity of each core to the OS scheduler 602 via an ACPI table. In at least one embodiment, at 610c, the process 600 monitors thermal sensors and checks against limits. In at least one embodiment, a thermally shielded core is placed in a low power state at 612. In at least one embodiment, this can potentially improve energy efficiency by saving energy from processor utilization that might otherwise be shielded to prevent pathological patterns of processor utilization.

[0081] In at least one embodiment, namely the example embodiment of process 600, the processor includes one or more circuits for controlling utilization of a combination of processing cores based at least in part on historical thermal characteristics of the combination of processing cores.

[0082] In at least one embodiment, the processor comprises a combination of the processing cores. In at least one embodiment, the processor is a central processing unit ("CPU"). In at least one embodiment, the one or more circuits are used to measure thermal characteristics based at least in part on an average temperature measured by thermal sensors at multiple locations on a chip (e.g., a chip implementing the processor, including the processing cores).

[0083] In at least one embodiment, the historical thermal characteristics indicate a processor core utilization pattern. In at least one embodiment, the historical thermal characteristics are determined by measuring thermal characteristics generated by the operation of various types or categories of application workloads. In at least one embodiment, the application workload is a machine learning workload, such as a workload related to deep learning. In at least one embodiment, the historical thermal characteristics are stored in a configuration file. In at least one embodiment, the configuration file is accessible to one or more of the OS scheduler 602 and the kernel 604. In at least one embodiment, the one or more circuits are used to load the historical thermal characteristics from the configuration file. In at least one embodiment, the historical thermal characteristics are used in connection with steps 610a-610c to determine whether one or more processor cores should be shielded.

[0084] In at least one embodiment, the combination of processor cores is shielded based at least in part on historical thermal characteristics of the combination of processing cores. In at least one embodiment, the shielding includes causing an application thread to be avoided from being scheduled on the processing cores.

[0085] In at least one embodiment, the processor uses Figures 1 to 6 Process 600 may be performed using techniques consistent with one or more described embodiments.

[0086] In at least one embodiment, a computing system including one or more processors performs process 600. In at least one embodiment, the computing system includes one or more processors to use Figures 1 to 6 Process 600 may be performed using techniques consistent with one or more described embodiments.

[0087] In at least one embodiment, the non-transitory computer readable medium includes instructions that, when executed by one or more processors of a computing system, cause the computing system to perform process 600. In at least one embodiment, the instructions cause the computing system to use information related to Figures 1 to 6 Process 600 is performed using techniques consistent with one or more embodiments described herein.

[0088] Data Center

[0089] Figure 7 An example data center 700 is shown in accordance with at least one embodiment. In at least one embodiment, the data center 700 includes, but is not limited to, a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0090] In at least one embodiment, Figure 7As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources ("node CRs") 716 (1)-716 (N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 716 (1)-716 (N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), data processing units (DPUs) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 716 (1)-716 (N) may be a server having one or more of the above computing resources.

[0091] In at least one embodiment, the grouped computing resources 714 may include a separate grouping of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. The separate grouping of node CRs within the grouped computing resources 714 may include computing, network, memory or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules and network switches in any combination.

[0092] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may include a software design infrastructure ("SDI") management entity for data center 700. In at least one embodiment, resource coordinator 712 may include hardware, software, or some combination thereof.

[0093] In at least one embodiment, Figure 7As shown, the framework layer 720 includes, but is not limited to, a job scheduler 732, a configuration manager 734, a resource manager 736, and a distributed file system 738. In at least one embodiment, the framework layer 720 may include a framework that supports software 752 of the software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 752 or the application 742 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 738 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 732 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 700. In at least one embodiment, the configuration manager 734 may be able to configure different layers, such as the software layer 730 and the framework layer 720 including Spark and a distributed file system 738 for supporting large-scale data processing. In at least one embodiment, the resource manager 736 can manage cluster or group computing resources mapped to or allocated to support the distributed file system 738 and the job scheduler 732. In at least one embodiment, the cluster or group computing resources may include grouped computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 736 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0094] In at least one embodiment, the software 752 included in the software layer 730 may include software used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0095] In at least one embodiment, the one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. The one or more types of applications may include, but are not limited to, CUDA applications.

[0096] In at least one embodiment, any of the configuration manager 734, resource manager 736, and resource coordinator 712 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of the data center 700 from making potentially bad configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0097] Computer-based systems

[0098] The following figures set forth, but are not limiting of, exemplary computer-based systems that may be used to implement at least one embodiment.

[0099] Figure 8 A processing system 800 is shown according to at least one embodiment. In at least one embodiment, the system 800 includes one or more processors 802 and one or more graphics processors 808, and can be a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 802 or processor cores 807. In at least one embodiment, the processing system 800 is a processing platform incorporated into a system on a chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device. In at least one embodiment, the processor core 807 is referred to as a computing unit or an operation unit.

[0100] In at least one embodiment, the processing system 800 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console for gaming and media consoles. In at least one embodiment, the processing system 800 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 800 may also include a wearable device coupled to or integrated in a wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 800 is a television or set-top box device having one or more processors 802 and a graphical interface generated by one or more graphics processors 808.

[0101] In at least one embodiment, one or more processors 802 each include one or more processor cores 807 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 807 is configured to process a specific instruction set 809. In at least one embodiment, the instruction set 809 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing by very long instruction words (VLIW). In at least one embodiment, multiple processor cores 807 can each process different instruction sets 809, which can include instructions that help emulate other instruction sets. In at least one embodiment, the processor core 807 can also include other processing devices, such as a digital signal processor ("DSP").

[0102] In at least one embodiment, the processor 802 includes a cache memory (cache) 804. In at least one embodiment, the processor 802 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared between the various components of the processor 802. In at least one embodiment, the processor 802 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can share the logic between the processor cores 807 using known cache coherence techniques. In at least one embodiment, the processor 802 additionally includes a register file 806, and the processor 802 may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 806 may include general registers or other registers.

[0103] In at least one embodiment, one or more processors 802 are coupled to one or more interface buses 810 to transmit communication signals, such as address, data, or control signals, between the processor 802 and other components in the system 800. In at least one embodiment, the interface bus 810 can be a processor bus in one embodiment, such as a version of a direct media interface (DMI) bus. In at least one embodiment, the interface bus 810 is not limited to a DMI bus, and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 802 includes an integrated memory controller 816 and a platform controller hub 830. In at least one embodiment, the memory controller 816 facilitates communication between storage devices and other components of the processing system 800, while the platform controller hub (PCH) 830 provides connections to input / output (I / O) devices through a local I / O bus.

[0104] In at least one embodiment, the storage device 820 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, a phase change memory device, or have appropriate performance for use as a processor memory. In at least one embodiment, the storage device 820 may be used as a system memory of the processing system 800 to store data 822 and instructions 821 for use when one or more processors 802 execute an application or process. In at least one embodiment, the memory controller 816 is also coupled to an optional external graphics processor 812, which may communicate with one or more graphics processors 808 in the processor 802 to perform graphics and media operations. In at least one embodiment, the display device 811 may be connected to the processor 802. In at least one embodiment, the display device 811 may include one or more of the internal display devices, such as in a mobile electronic device or portable computer device or an external display device connected via a display interface (e.g., a display port (DisplayPort) or the like). In at least one embodiment, the display device 811 may include a head mounted display (HMD), such as a stereoscopic display device for use in a virtual reality (VR) application or an augmented reality (AR) application.

[0105] In at least one embodiment, the platform controller hub 830 enables peripheral devices to be connected to the storage device 820 and the processor 802 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 846, a network controller 834, a firmware interface 828, a wireless transceiver 826, a touch sensor 825, a data storage device 824 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 824 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 825 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 826 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or long-term evolution (LTE) transceiver. In at least one embodiment, the firmware interface 828 enables communication with the system firmware, and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, the network controller 834 can enable network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 810. In at least one embodiment, the audio controller 846 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 800 includes an optional legacy I / O controller 840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 800. In at least one embodiment, the platform controller hub 830 may also be connected to one or more universal serial bus (USB) controllers 842 that connect input devices such as a keyboard and mouse 843 combination, a camera 844, or other USB input devices.

[0106] In at least one embodiment, instances of the memory controller 816 and the platform controller hub 830 may be integrated into a discrete external graphics processor, such as the external graphics processor 812. In at least one embodiment, the platform controller hub 830 and / or the memory controller 816 may be external to one or more processors 802. For example, in at least one embodiment, the processing system 800 may include the external memory controller 816 and the platform controller hub 830, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 802.

[0107] Fig. 9A computer system 900 is shown according to at least one embodiment. In at least one embodiment, the computer system 900 can be a system with interconnected devices and components, a SOC, or some combination. In at least one embodiment, the computer system 900 is formed by a processor 902, which can include an execution unit for executing instructions. In at least one embodiment, the computer system 900 can include, but is not limited to, components, such as the processor 902, which employs an execution unit including logic to execute algorithms for process data. In at least one embodiment, the computer system 900 can include a processor, such as the Intel Corporation of Santa Clara, California, available from Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 900 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0108] In at least one embodiment, the computer system 900 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors ("DSPs"), SoCs, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0109] In at least one embodiment, computer system 900 may include, but is not limited to, a processor 902, which may include, but is not limited to, one or more execution units 908, which may be configured to execute Compute Unified Device Architecture ("CUDA"). Developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, the computer system 900 is a single processor desktop or server system. In at least one embodiment, the computer system 900 may be a multi-processor system. In at least one embodiment, the processor 902 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 902 may be coupled to a processor bus 910, which may transmit data signals between the processor 902 and other components in the computer system 900.

[0110] In at least one embodiment, the processor 902 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 904. In at least one embodiment, the processor 902 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to the processor 902. In at least one embodiment, the processor 902 may include a combination of internal and external caches. In at least one embodiment, the register file 906 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and an instruction pointer register.

[0111] In at least one embodiment, an execution unit 908, including but not limited to logic to perform integer and floating point operations, is also located in the processor 902. The processor 902 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 908 may include logic for processing a packed instruction set 909. In at least one embodiment, by including the packed instruction set 909 in the instruction set of the general purpose processor 902, and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general purpose processor 902. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may not require the transfer of smaller units of data on the processor's data bus to perform one or more operations on one data element at a time.

[0112] In at least one embodiment, execution unit 908 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 900 may include, but is not limited to, memory 920. In at least one embodiment, memory 920 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 920 may store instructions 919 and / or data 921 represented by data signals that may be executed by processor 902.

[0113] In at least one embodiment, the system logic chip can be coupled to the processor bus 910 and the memory 920. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 916, and the processor 902 can communicate with the MCH 916 via the processor bus 910. In at least one embodiment, the MCH 916 can provide a high-bandwidth memory path 918 to the memory 920 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 916 can initiate data signals between the processor 902, the memory 920, and other components in the computer system 900, and bridge data signals between the processor bus 910, the memory 920, and the system I / O 922. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 916 can be coupled to the memory 920 via a high-bandwidth memory path 918, and the graphics / video card 912 can be coupled to the MCH 916 via an Accelerated Graphics Port ("AGP") interconnect 914.

[0114] In at least one embodiment, the computer system 900 can use the system I / O 922 as a proprietary hub interface bus to couple the MCH 916 to an I / O controller hub ("ICH") 930. In at least one embodiment, the ICH 930 can provide direct connections to certain I / O devices through a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 920, the chipset, and the processor 902. Examples can include, but are not limited to, an audio controller 929, a firmware hub ("Flash BIOS") 928, a wireless transceiver 926, a data store 924, a traditional I / O controller 923 including a user input 925 and a keyboard interface, a serial expansion port 927 (e.g., USB), and a network controller 934. The data store 924 can include a hard drive, a floppy drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0115] In at least one embodiment, Fig. 9 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Fig. 9 An exemplary SoC may be shown. In at least one embodiment, Fig. 9 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of system 900 are interconnected using a compute express link ("CXL") interconnect.

[0116] Fig.10 A system 1000 is shown in accordance with at least one embodiment. In at least one embodiment, the system 1000 is an electronic device utilizing a processor 1010. In at least one embodiment, the system 1000 can be, for example but not limited to, a notebook computer, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more local or cloud service providers, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0117] In at least one embodiment, system 1000 may include, but is not limited to, a processor 1010 communicatively coupled to any suitable number or variety of components, peripherals, modules, or devices. In at least one embodiment, processor 1010 is coupled using a bus or interface, such as an I 2 C bus, system management bus ("SMBus"), low pin count (LPC) bus, serial peripheral interface ("SPI"), high definition audio ("HDA") bus, serial advanced technology attachment ("SATA") bus, USB (version 1, 2, 3), or universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig.10 A system is shown, which includes interconnected hardware devices or "chips". In at least one embodiment, Fig.10 An exemplary SoC may be shown. In at least one embodiment, Fig.10 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig.10 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0118] In at least one embodiment, Fig.10The display 1024, touch screen 1025, touch pad 1030, near field communication unit ("NFC") 1045, sensor hub 1040, thermal sensor 1046, fast chipset ("EC") 1035, trusted platform module ("TPM") 1038, BIOS / firmware / flash memory ("BIOS, FW Flash") 1022, DSP 1060, solid state disk ("SSD") or hard disk drive ("HDD") 1020, wireless local area network unit ("WLAN") 1050, Bluetooth unit 1052, wireless wide area network unit ("WWAN") 1056, global positioning system (GPS) 1055, camera ("USB 3.0 camera") 1054 (e.g., USB 3.0 camera) or low power double data rate ("LPDDR") memory unit ("LPDDR3") 1015 implemented in, for example, the LPDDR3 standard may be included. Each of these components may be implemented in any suitable manner.

[0119] In at least one embodiment, other components may be communicatively coupled to the processor 1010 through the components discussed above. In at least one embodiment, the accelerometer 1041, ambient light sensor (“ALS”) 1042, compass 1043, and gyroscope 1044 may be communicatively coupled to the sensor hub 1040. In at least one embodiment, the thermal sensor 1039, fan 1037, keyboard 1036, and touchpad 1030 may be communicatively coupled to the EC 1035. In at least one embodiment, the speaker 1063, earphone 1064, and microphone (“mic”) 1065 may be communicatively coupled to the audio unit (“audio codec and class D amplifier”) 1062, which in turn may be communicatively coupled to the DSP 1060. In at least one embodiment, the audio unit 1062 may include, for example, but not limited to, an audio encoder / decoder (“codec”) and a class D amplifier. In at least one embodiment, the SIM card (“SIM”) 1057 may be communicatively coupled to the WWAN unit 1056. In at least one embodiment, components such as the WLAN unit 1050 and the Bluetooth unit 1052 and the WWAN unit 1056 may be implemented as a next generation form factor (NGFF).

[0120] Fig.11An exemplary integrated circuit 1100 is shown in accordance with at least one embodiment. In at least one embodiment, the exemplary integrated circuit 1100 is a SoC, which may be manufactured using one or more IP cores. In at least one embodiment, the integrated circuit 1100 includes one or more application processors 1105 (e.g., CPU, DPU), at least one graphics processor 1110, and may additionally include an image processor 1115 and / or a video processor 1120, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1100 includes peripheral or bus logic, including a USB controller 1125, a UART controller 1130, an SPI / SDIO controller 1135, and an I 2 S / I 2 C controller 1140. In at least one embodiment, the integrated circuit 1100 may include a display device 1145 coupled to one or more of a High Definition Multimedia Interface ("HDMI") controller 1150 and a Mobile Industry Processor Interface ("MIPI") display interface 1155. In at least one embodiment, storage may be provided by a flash memory subsystem 1160, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1165 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1170.

[0121] Fig.12 A computing system 1200 is shown in accordance with at least one embodiment. In at least one embodiment, the computing system 1200 includes a processing subsystem 1201 having one or more processors 1202 and a system memory 1204 communicating via an interconnect path that may include a memory hub 1205. In at least one embodiment, the memory hub 1205 may be a separate component within a chipset component or may be integrated within the one or more processors 1202. In at least one embodiment, the memory hub 1205 is coupled to an I / O subsystem 1211 via a communication link 1206. In at least one embodiment, the I / O subsystem 1211 includes an I / O hub 1207 that may enable the computing system 1200 to receive input from one or more input devices 1208. In at least one embodiment, the I / O hub 1207 may enable a display controller, included in the one or more processors 1202, to provide output to one or more display devices 1210A. In at least one embodiment, the one or more display devices 1210A coupled to the I / O hub 1207 may include local, internal, or embedded display devices.

[0122] In at least one embodiment, the processing subsystem 1201 includes one or more parallel processors 1212 coupled to the memory hub 1205 via a bus or other communication link 1213. In at least one embodiment, the communication link 1213 can be one of many standard-based communication link technologies or protocols, such as but not limited to PCIe, or can be a communication interface or communication structure for a vendor. In at least one embodiment, the one or more parallel processors 1212 form a parallel or vector processing system in a computing concentration, which can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor or computing unit. In at least one embodiment, the one or more parallel processors 1212 form a graphics processing subsystem that can output pixels to one of the one or more display devices 1210A coupled via the I / O hub 1207. In at least one embodiment, the one or more parallel processors 1212 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 1210B.

[0123] In at least one embodiment, system storage unit 1214 can be connected to I / O hub 1207 to provide a storage mechanism for computing system 1200. In at least one embodiment, I / O switch 1216 can be used to provide an interface mechanism to enable connection between I / O hub 1207 and other components, such as network adapter 1218 and / or wireless network adapter 1219 that can be integrated into the platform, as well as various other devices that can be added through one or more additional devices 1220. In at least one embodiment, network adapter 1218 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1219 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more radios.

[0124] In at least one embodiment, computing system 1200 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1207. Fig.12 The communication paths that interconnect the various components in the system can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0125] In at least one embodiment, one or more parallel processors 1212 include circuits optimized for graphics and video processing (including, for example, video output circuits) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1212 include circuits optimized for general processing. In at least one embodiment, the components of the computing system 1200 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1212, memory hub 1205, processor 1202, and I / O hub 1207 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computing system 1200 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1200 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, the I / O subsystem 1211 and the display device 1210B are omitted from the computing system 1200.

[0126] Processing system

[0127] The following figures illustrate, but are not limited to, exemplary processing systems that may be used to implement at least one embodiment.

[0128] Fig.13 An accelerated processing unit ("APU") 1300 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 1300 was developed by AMD, Inc. of Santa Clara, California. In at least one embodiment, the APU 1300 may be configured to execute application programs, such as CUDA programs. In at least one embodiment, the APU 1300 includes, but is not limited to, a core complex 1310, a graphics complex 1340, a fabric 1360, an I / O interface 1370, a memory controller 1380, a display controller 1392, and a multimedia engine 1394. In at least one embodiment, the APU 1300 may include, but is not limited to, any combination of any number of core complexes 1310, any number of graphics complexes 1350, any number of display controllers 1392, and any number of multimedia engines 1394. For purposes of illustration, multiple instances of similar objects are represented herein by reference numerals, where the reference numeral identifies the object and the number in parentheses identifies the desired instance.

[0129] In at least one embodiment, core complex 1310 is a CPU, graphics complex 1340 is a GPU, and APU 1300 is a processing unit that is not limited to core complex 1310 and graphics complex 1340 integrated onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 1310, while other tasks may be assigned to graphics complex 1340. In at least one embodiment, core complex 1310 is configured to execute main control software associated with APU 1300, such as an operating system. In at least one embodiment, core complex 1310 is the main processor of APU 1300, which controls and coordinates the operations of other processors. In at least one embodiment, core complex 1310 issues commands that control the operations of graphics complex 1340. In at least one embodiment, core complex 1310 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1340 may be configured to execute device executable code derived from CUDA source code.

[0130] In at least one embodiment, core complex 1310 includes, but is not limited to, cores 1320(1)-1320(4) and L3 cache 1330. In at least one embodiment, core complex 1310 may include, but is not limited to, any number of cores 1320 in any combination and any number and type of caches. In at least one embodiment, cores 1320 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1320 is a CPU core. In at least one embodiment, cores 1320 are referred to as computational units or operational units.

[0131] In at least one embodiment, each core 1320 includes, but is not limited to, a fetch / decode unit 1322, an integer execution engine 1324, a floating point execution engine 1326, and an L2 cache 1328. In at least one embodiment, the fetch / decode unit 1322 fetches instructions, decodes these instructions, generates micro-operations, and dispatches separate micro-instructions to the integer execution engine 1324 and the floating point execution engine 1326. In at least one embodiment, the fetch / decode unit 1322 can dispatch one micro-instruction to the integer execution engine 1324 and another micro-instruction to the floating point execution engine 1326 at the same time. In at least one embodiment, the integer execution engine 1324 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating point engine 1326 performs, but is not limited to, floating point and vector operations. In at least one embodiment, the fetch-decode unit 1322 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 1324 and the floating point execution engine 1326.

[0132] In at least one embodiment, each core 1320(i) may access an L2 cache 1328(i) included in the core 1320(i), where i is an integer representing a specific instance of the core 1320. In at least one embodiment, each core 1320 included in the core complex 1310(j) is connected to other cores 1320 included in the core complex 1310(j) via an L3 cache 1330(j) included in the core complex 1310(j), where j is an integer representing a specific instance of the core complex 1310. In at least one embodiment, a core 1320 included in a core complex 1310(j) may access all L3 caches 1330(j) included in the core complex 1310(j), where j is an integer representing a specific instance of the core complex 1310. In at least one embodiment, the L3 cache 1330 may include, but is not limited to, any number of slices.

[0133] In at least one embodiment, graphics complex 1340 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1340 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex 1340 is configured to perform operations that are not related to graphics. In at least one embodiment, graphics complex 1340 is configured to perform both graphics-related operations and graphics-independent operations.

[0134] In at least one embodiment, graphics complex 1340 includes, but is not limited to, any number of compute units 1350 and L2 cache 1342. In at least one embodiment, compute units 1350 share L2 cache 1342. In at least one embodiment, L2 cache 1342 is partitioned. In at least one embodiment, graphics complex 1340 includes, but is not limited to, any number of compute units 1350 and any number (including zero) and type of caches. In at least one embodiment, graphics complex 1340 includes, but is not limited to, any number of specialized graphics hardware.

[0135] In at least one embodiment, each computing unit 1350 includes, but is not limited to, any number of SIMD units 1352 and shared memory 1354. In at least one embodiment, each SIMD unit 1352 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each computing unit 1350 can execute any number of thread blocks, but each thread block is executed on a single computing unit 1350. In at least one embodiment, thread blocks include, but are not limited to, any number of execution threads. In at least one embodiment, a work group is a thread block. In at least one embodiment, each SIMD unit 1352 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, a prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicated via a shared memory 1354.

[0136] In at least one embodiment, fabric 1360 is a system interconnect that facilitates data and control transfers across core complex 1310, graphics complex 1340, I / O interface 1370, memory controller 1380, display controller 1392, and multimedia engine 1394. In at least one embodiment, APU 1300 may include, in addition to or in lieu of fabric 1360, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 1300. In at least one embodiment, I / O interface 1370 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripherals are coupled to I / O interface 1370. In at least one embodiment, peripheral devices coupled to I / O interface 1370 may include, but are not limited to, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0137] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as a liquid crystal display (LCD) device. In at least one embodiment, multimedia engine 1394 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, etc. In at least one embodiment, memory controller 1380 facilitates data transfer between APU 1300 and unified system memory 1390. In at least one embodiment, core complex 1310 and graphics complex 1340 share unified system memory 1390.

[0138] In at least one embodiment, the APU 1300 implements a memory subsystem including, but not limited to, any number and type of memory controllers 1380 and memory devices that may be dedicated to one component or shared among multiple components (e.g., shared memory 1354). In at least one embodiment, the APU 1300 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1428, L3 cache 1330, and L2 cache 1342), each of which may be private or shared among any number of components (e.g., core 1320, core complex 1310, SIMD unit 1352, compute unit 1350, and graphics complex 1340).

[0139] Fig.14 A CPU 1400 according to at least one embodiment is shown. In at least one embodiment, the CPU 1400 is developed by AMD, Inc. of Santa Clara, California. In at least one embodiment, the CPU 1400 may be configured to execute an application program. In at least one embodiment, the CPU 1400 is configured to execute a main control software, such as an operating system. In at least one embodiment, the CPU 1400 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1400 may be configured to execute a host executable code derived from a CUDA source code, and the external GPU may be configured to execute a device executable code derived from such a CUDA source code. In at least one embodiment, the CPU 1400 includes, but is not limited to, any number of core complexes 1410, structures 1460, I / O interfaces 1470, and memory controllers 1480.

[0140] In at least one embodiment, core complex 1410 includes, but is not limited to, cores 1420(1)-1420(4) and L3 cache 1430. In at least one embodiment, core complex 1410 may include, but is not limited to, any number of cores 1420 and any combination of any number and type of caches. In at least one embodiment, core 1420 is configured to execute instructions of a specific ISA. In at least one embodiment, each core 1420 is a CPU core.

[0141] In at least one embodiment, each core 1420 includes, but is not limited to, a fetch / decode unit 1422, an integer execution engine 1424, a floating point execution engine 1426, and an L2 cache 1428. In at least one embodiment, the fetch / decode unit 1422 fetches instructions, decodes these instructions, generates micro-operations, and dispatches separate micro-instructions to the integer execution engine 1424 and the floating point execution engine 1426. In at least one embodiment, the fetch / decode unit 1422 can dispatch one micro-instruction to the integer execution engine 1424 and another micro-instruction to the floating point execution engine 1426 at the same time. In at least one embodiment, the integer execution engine 1424 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating point engine 1426 performs, but is not limited to, floating point and vector operations. In at least one embodiment, the fetch-decode unit 1422 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 1424 and the floating point execution engine 1426.

[0142] In at least one embodiment, each core 1420(i) may access an L2 cache 1428(i) included in the core 1420(i), where i is an integer representing a specific instance of the core 1420. In at least one embodiment, each core 1420 included in the core complex 1410(j) is connected to other cores 1420 included in the core complex 1410(j) via an L3 cache 1430(j) included in the core complex 1410(j), where j is an integer representing a specific instance of the core complex 1410. In at least one embodiment, a core 1420 included in a core complex 1410(j) may access all L3 caches 1430(j) included in the core complex 1410(j), where j is an integer representing a specific instance of the core complex 1410. In at least one embodiment, the L3 cache 1430 may include, but is not limited to, any number of slices.

[0143] In at least one embodiment, fabric 1460 is a system interconnect that facilitates data and control transfers across core complexes 1410(1)-1410(N) (where N is an integer greater than zero), I / O interface 1470, and memory controller 1480. In at least one embodiment, CPU 1400 may include, in addition to or in lieu of fabric 1460, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to CPU 1400. In at least one embodiment, I / O interface 1470 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripherals are coupled to I / O interface 1470. In at least one embodiment, peripherals coupled to I / O interface 1470 may include, but are not limited to, a display, keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, etc.

[0144] In at least one embodiment, memory controller 1480 facilitates data transfers between CPU 1400 and system memory 1490. In at least one embodiment, core complex 1410 and graphics complex 1440 share system memory 1490. In at least one embodiment, CPU 1400 implements a memory subsystem, which includes, but is not limited to, any number and type of memory controllers 1480 and memory devices that may be dedicated to one component or shared between multiple components. In at least one embodiment, CPU 1400 implements a cache subsystem, which includes, but is not limited to, one or more cache memories (e.g., L2 cache 1428 and L3 cache 1430), each of which may be private to a component or shared between any number of components (e.g., core 1420 and core complex 1410).

[0145] Fig.15An exemplary accelerator integrated slice 1590 according to at least one embodiment is shown. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines in multiple graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engine may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a general package, line card, or chip.

[0146] The application effective address space 1582 within the system memory 1514 stores process elements 1583. In one embodiment, the process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on the processor 1507. The process element 1583 contains the processing state of the corresponding application 1580. The work descriptor ("WD") 1584 contained in the process element 1583 can be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, the WD 1584 is a pointer to a job request queue in the application effective address space 1582.

[0147] Graphics acceleration module 1546 and / or each graphics processing engine can be shared by all or part of the processes in the system. In at least one embodiment, an infrastructure for establishing a processing state and sending WD 1584 to graphics acceleration module 1546 to start a job in a virtualized environment can be included.

[0148] In at least one embodiment, a dedicated process programming model is implemented for. In this model, a single process owns a graphics acceleration module 1546 or an individual graphics processing engine. Since the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 1546 is allocated.

[0149] In operation, the WD acquisition unit 1591 in the accelerator integrated slice 1590 acquires the next WD 1584, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1546. Data from the WD 1584 can be stored in registers 1545 for use by a memory management unit ("MMU") 1539, an interrupt management circuit 1547, and / or an environment management circuit 1548, as shown. For example, one embodiment of the MMU 1539 includes a segment / page roaming circuit for accessing a segment / page table 1586 within an OS virtual address space 1585. The interrupt management circuit 1547 can process an interrupt event (INT) 1592 received from the graphics acceleration module 1546. When performing a graph operation, an effective address 1593 generated by the graphics processing engine is converted to an actual address by the MMU 1539.

[0150] In one embodiment, the same register set 1545 is replicated for each graphics processing engine and / or graphics acceleration module 1546 and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integrated slice 1590. An exemplary register that can be initialized by a hypervisor is shown in Table 1.

[0151] Table 1 – Registers initialized by the hypervisor

[0152] 1 Slice Control Register 2 Real address (RA) plan processing area pointer 3 Authorization Mask Override Register 4 Interrupt vector table input offset 5 Interrupt vector table entry restriction 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0153] Example registers that may be initialized by the operating system are shown in Table 2.

[0154] Table 2 – Operating System Initialization Registers

[0155] 1 Process and thread identification 2 Effective Address (EA) environment save / restore pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) stores the segment table pointer 5 Mask of Authority 6 Job Descriptor

[0156] In one embodiment, each WD 1584 is specific to a specific graphics acceleration module 1546 and / or a specific graphics processing engine. It contains all the information needed by the graphics processing engine to do its work or work, or it can be a pointer to a memory location where the application has established a command queue for the work to be done.

[0157] Figures 16A-16B An exemplary graphics processor according to at least one embodiment of the present invention is shown. In at least one embodiment, any exemplary graphics processor can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits can be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used in a SoC.

[0158] Fig.16A An exemplary graphics processor 1610 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Fig. 16B An additional exemplary graphics processor 1640 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, according to at least one embodiment. In at least one embodiment, Fig.16A The graphics processor 1610 is a low power graphics processor core. In at least one embodiment, Fig. 16B The graphics processor 1640 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1610, 1640 can be Fig.11 A variant of graphics processor 1110.

[0159] In at least one embodiment, the graphics processor 1610 includes a vertex processor 1605 and one or more fragment processors 1615A-1615N (e.g., 1615A, 1615B, 1615C, 1615D to 1615N-1 and 1615N). In at least one embodiment, the graphics processor 1610 can execute different shader programs via separate logic, so that the vertex processor 1605 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1615A-1615N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1605 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 1615A-1615N use the primitives and vertex data generated by the vertex processor 1605 to generate a frame buffer displayed on a display device. In at least one embodiment, fragment processors 1615A-1615N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0160] In at least one embodiment, graphics processor 1610 additionally includes one or more MMUs 1620A-1620B, caches 1625A-1625B, and circuit interconnects 1630A-1630B. In at least one embodiment, one or more MMUs 1620A-1620B provide a mapping of virtual to physical addresses for graphics processor 1610, including for vertex processor 1605 and / or fragment processors 1615A-1615N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1625A-1625B. In at least one embodiment, one or more MMUs 1620A-1620B may synchronize with other MMUs within the system, including with Fig.11 One or more MMUs associated with one or more application processors 1105, image processor 1115, and / or video processor 1120 enable each processor 1105-1120 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1630A-1630B enable graphics processor 1610 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0161] In at least one embodiment, graphics processor 1640 includes Fig.16A One or more MMUs 1620A-1620B, caches 1625A-1625B, and circuit interconnects 1630A-1630B of a graphics processor 1610. In at least one embodiment, graphics processor 1640 includes one or more shader cores 1655A-1655N (e.g., 1655A, 1655B, 1655C, 1655D, 1655E, 1655F, to 1655N-1 and 1655N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the plurality of shader cores may vary. In at least one embodiment, the graphics processor 1640 includes an inter-core task manager 1645 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1655A-1655N and a tiling unit 1658 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0162] Fig.17A1700 according to at least one embodiment. In at least one embodiment, the graphics core 1700 may include Fig.11 In at least one embodiment, the graphics core 1700 may be Fig. 16B 1655A-1655N. In at least one embodiment, the graphics core 1700 includes a shared instruction cache 1702, a texture unit 1718, and a cache / shared memory 1720, which are common to the execution resources within the graphics core 1700. In at least one embodiment, the graphics core 1700 may include multiple slices 1701A-1701N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1700. The slices 1701A-1701N may include support logic including a local instruction cache 1704A-1704N, a thread scheduler 1706A-1706N, a thread dispatcher 1708A-1708N, and a set of registers 1710A-1710N. In at least one embodiment, slices 1701A-1701N may include a set of additional function units ("AFU's") 1712A-1712N, floating point units ("FPUs") 1714A-1714N, integer arithmetic logic units ("ALUs") 1716A-1716N, address calculation units ("ACUs") 1713A-1713N, double precision floating point units ("DPFPUs") 1715A-1715N, and matrix processing units ("MPUs") 1717A-1717N. In at least one embodiment, graphics core 1700 is referred to as a compute unit or operation unit.

[0163] In one embodiment, the FPU 1714A-1714N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1715A-1715N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1716A-1716N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1717A-1717N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1717A-1717N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1712A-1712N can perform additional logical operations that are not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0164] Fig. 17B A general purpose graphics processing unit (GPGPU) 1730 in at least one embodiment is shown. In at least one embodiment, GPGPU 1730 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 1730 can be configured to enable highly parallel computing operations to be performed by a GPU array. In at least one embodiment, GPGPU 1730 can be directly linked to other instances of GPGPU 1730 to create a multi-GPU cluster to improve the execution time for CUDA programs. In at least one embodiment, GPGPU 1730 includes a host interface 1732 to enable connection with a host processor. In at least one embodiment, host interface 1732 is a PCIe interface. In at least one embodiment, host interface 1732 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1730 receives commands from a host processor and dispatches execution threads associated with those commands to a set of computing clusters 1736A-1736H using a global scheduler 1734. In at least one embodiment, the computing clusters 1736A-1736H share a cache memory 1738. In at least one embodiment, the cache memory 1738 can be used as a high-level cache for the cache memories within the computing clusters 1736A-1736H.

[0165] In at least one embodiment, GPGPU 1730 includes memory 1744A-1744B coupled to compute clusters 1736A-1736H via a set of memory controllers 1742A-1742B. In at least one embodiment, memory 1744A-1744B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory ("SGRAM"), including graphics double data rate ("GDDR") memory.

[0166] In at least one embodiment, computing clusters 1736A-1736H each include a set of graphics cores, such as Fig.17A The graphics core 1700, which may include multiple types of integer and floating point logic units, may perform computational operations at various precisions, including computations suitable for use with CUDA programs. For example, in at least one embodiment, at least a subset of the floating point units in each of the compute clusters 1736A-1736H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

[0167] In at least one embodiment, multiple instances of GPGPU 1730 may be configured to operate as a computing cluster. Computing clusters 1736A-1736H may implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 1730 communicate through host interface 1732. In at least one embodiment, GPGPU 1730 includes an I / O hub 1739 that couples GPGPU 1730 with GPU link 1740, enabling direct connection to other instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a dedicated GPU to GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1730 are located in separate data processing systems and communicate via network devices accessible via host interface 1732. In at least one embodiment, GPU link 1740 may be configured to be connected to a host processor, in addition to or in lieu of host interface 1732. In at least one embodiment, GPGPU 1730 may be configured to execute CUDA programs.

[0168] Fig.18A A parallel processor 1800 is shown in accordance with at least one embodiment. In at least one embodiment, various components of parallel processor 1800 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit ("ASIC"), or an FPGA.

[0169] In at least one embodiment, parallel processor 1800 includes parallel processing unit 1802. In at least one embodiment, parallel processing unit 1802 includes I / O unit 1804, which enables communication with other devices, including other instances of parallel processing unit 1802. In at least one embodiment, I / O unit 1804 can be directly connected to other devices. In at least one embodiment, I / O unit 1804 is connected to other devices by using a hub or switch interface (e.g., memory hub 1805). In at least one embodiment, the connection between memory hub 1805 and I / O unit 1804 forms a communication link. In at least one embodiment, I / O unit 1804 is connected to host interface 1806 and memory crossbar switch 1816, wherein host interface 1806 receives commands for performing processing operations and memory crossbar switch 1816 receives commands for performing memory operations.

[0170] In at least one embodiment, when the host interface 1806 receives the command buffer via the I / O unit 1804, the host interface 1806 can direct work operations to execute those commands to the front end 1808. In at least one embodiment, the front end 1808 is coupled with a scheduler 1810, which is configured to distribute commands or other work items to the processing array 1812. In at least one embodiment, the scheduler 1810 ensures that the processing array 1812 is properly configured and in a valid state before assigning tasks to the processing array 1812 in the processing array 1812. In at least one embodiment, the scheduler 1810 is implemented by firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1810 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executing on the processing array 1812. In at least one embodiment, the host software can prove the workload for scheduling on the processing array 1812 through one of a plurality of graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 1812 by scheduler 1810 logic within a microcontroller that includes scheduler 1810 .

[0171] In at least one embodiment, the processing array 1812 may include up to "N" processing clusters (e.g., cluster 1814A, cluster 1814B, through cluster 1814N). In at least one embodiment, each cluster 1814A-1814N of the processing array 1812 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1810 may allocate work to the clusters 1814A-1814N of the processing array 1812 using various scheduling and / or work allocation algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 1810, or may be assisted in part by compiler logic during the compilation of program logic configured to be executed by the processing array 1812. In at least one embodiment, different clusters 1814A-1814N of the processing array 1812 may be allocated to process different types of programs or to perform different types of computations.

[0172] In at least one embodiment, the processing array 1812 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 1812 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 1812 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0173] In at least one embodiment, the processing array 1812 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 1812 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 1812 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1802 may transfer data from the system memory via the I / O unit 1804 for processing. In at least one embodiment, during processing, the transferred data may be stored to an on-chip memory (e.g., parallel processor memory 1822) during processing and then written back to the system memory.

[0174] In at least one embodiment, when parallel processing unit 1802 is used to perform graph processing, scheduler 1810 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1814A-1814N of processing array 1812. In at least one embodiment, portions of processing array 1812 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 1814A-1814N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1814A-1814N for further processing.

[0175] In at least one embodiment, the processing array 1812 can receive processing tasks to be performed via the scheduler 1810, which receives commands defining the processing tasks from the front end 1808. In at least one embodiment, the processing tasks can include an index of the data to be processed, which can include surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 1810 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 1808. In at least one embodiment, the front end 1808 can be configured to ensure that the processing array 1812 is configured to a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0176] In at least one embodiment, each of the one or more instances of parallel processing unit 1802 can be coupled to parallel processor memory 1822. In at least one embodiment, parallel processor memory 1822 can be accessed via memory crossbar switch 1816, which can receive memory requests from processing array 1812 and I / O unit 1804. In at least one embodiment, memory crossbar switch 1816 can access parallel processor memory 1822 via memory interface 1818. In at least one embodiment, memory interface 1818 can include multiple partition units (e.g., partition unit 1820A, partition unit 1820B to partition unit 1820N), which can each be coupled to a portion of parallel processor memory 1822 (e.g., memory units). In at least one embodiment, the plurality of partition units 1820A-1820N are configured to be equal to the number of memory cells, such that the first partition unit 1820A has a corresponding first memory cell 1824A, the second partition unit 1820B has a corresponding memory cell 1824B, and the Nth partition unit 1820N has a corresponding Nth memory cell 1824N. In at least one embodiment, the number of partition units 1820A-1820N may not be equal to the number of memory devices.

[0177] In at least one embodiment, memory units 1824A-1824N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1824A-1824N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory units 1824A-1824N, allowing partition units 1820A-1820N to write portions of each rendering target in parallel to efficiently use the available bandwidth of parallel processor memory 1822. In at least one embodiment, local instances of parallel processor memory 1822 may be excluded in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0178] In at least one embodiment, any of the clusters 1814A-1814N of the processing array 1812 can process data to be written to any memory unit 1824A-1824N within the parallel processor memory 1822. In at least one embodiment, the memory crossbar 1816 can be configured to transmit the output of each cluster 1814A-1814N to any partition unit 1820A-1820N or another cluster 1814A-1814N, and the cluster 1814A-1814N can perform other processing operations on the output. In at least one embodiment, each cluster 1814A-1814N can communicate with the memory interface 1818 through the memory crossbar 1816 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 1816 has connections to memory interface 1818 to communicate with I / O unit 1804, and connections to local instances of parallel processor memory 1822 to enable processing units within different processing clusters 1814A-1814N to communicate with system memory or other memory that is not local to parallel processing unit 1802. In at least one embodiment, memory crossbar switch 1816 may use virtual channels to separate traffic flows between clusters 1814A-1814N and partition units 1820A-1820N.

[0179] In at least one embodiment, multiple instances of parallel processing unit 1802 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1802 may be configured to interoperate, even if different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1802 may include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 1802 or parallel processor 1800 may be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0180] Fig.18BA processing cluster 1894 according to at least one embodiment is shown. In at least one embodiment, the processing cluster 1894 is included in a parallel processing unit. In at least one embodiment, the processing cluster 1894 is an instance of one of the processing clusters 1814A-1814N of Figure 18. In at least one embodiment, the processing cluster 1894 can be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, a single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit, which is configured to issue instructions to a group of processing engines in each processing cluster 1894.

[0181] In at least one embodiment, the operation of the processing cluster 1894 can be controlled by assigning processing tasks to the pipeline manager 1832 of the SIMT parallel processor. In at least one embodiment, the pipeline manager 1832 receives instructions from the scheduler 1810 of Figure 18 and manages the execution of these instructions through the graphics multiprocessor 1834 and / or the texture unit 1836. In at least one embodiment, the graphics multiprocessor 1834 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures can be included in the processing cluster 1894. In at least one embodiment, one or more instances of the graphics multiprocessor 1834 can be included in the processing cluster 1894. In at least one embodiment, the graphics multiprocessor 1834 can process data, and the data crossbar switch 1840 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 1832 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar switch 1840.

[0182] In at least one embodiment, each graphics multiprocessor 1834 within a processing cluster 1894 may include the same set of function execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where a new instruction may be issued before a previous instruction is completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0183] In at least one embodiment, the instructions transmitted to the processing cluster 1894 constitute threads. In at least one embodiment, a group of threads executed across a group of parallel processing engines is a thread group. In at least one embodiment, the thread group executes the program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 1834. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 1834. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during the cycle that is processing the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 1834. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 1834, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1834.

[0184] In at least one embodiment, graphics multiprocessor 1834 includes internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 1834 can abandon the internal cache and use cache memory (e.g., L1 cache 1848) within processing cluster 1894. In at least one embodiment, each graphics multiprocessor 1834 can also access partition units (e.g., Fig.18A 1820A-1820N) that are shared between all processing clusters 1894 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1834 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1802 can be used as global memory. In at least one embodiment, processing cluster 1894 includes multiple instances of graphics multiprocessor 1834, which can share common instructions and data that can be stored in L1 cache 1848.

[0185] In at least one embodiment, each processing cluster 1894 may include an MMU 1845 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1845 may reside within the memory interface 1818 of FIG. 18. In at least one embodiment, the MMU 1845 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (talk more about tiles) and optionally to cache line indexes. In at least one embodiment, the MMU 1845 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 1834 or L1 cache 1848 or processing cluster 1894. In at least one embodiment, the physical address is processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0186] In at least one embodiment, the processing clusters 1894 can be configured such that each graphics multiprocessor 1834 is coupled to a texture unit 1836 to perform texture mapping operations, which may involve determining texture sample locations, reading texture data, and filtering texture data, for example. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1834, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1834 outputs processed tasks to a data crossbar 1840 to provide the processed tasks to another processing cluster 1894 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 1816. In at least one embodiment, a pre-raster operations unit ("preROP") 1842 is configured to receive data from graphics multiprocessor 1834, direct the data to a ROP unit, which may be located with a partition unit as described herein (e.g., partition units 1820A-1820N of FIG. 18). In at least one embodiment, the PreROP 1842 unit may perform optimizations for color blending, organize pixel color data, and perform address translations.

[0187] Fig.18C A graphics multiprocessor 1896 is shown according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 1896 is Fig.18B1834. In at least one embodiment, the graphics multiprocessor 1896 is coupled to the pipeline manager 1832 of the processing cluster 1894. In at least one embodiment, the graphics multiprocessor 1896 has an execution pipeline that includes, but is not limited to, an instruction cache 1852, an instruction unit 1854, an address mapping unit 1856, a register file 1858, one or more GPGPU cores 1862, and one or more LSUs 1866. The GPGPU cores 1862 and the LSUs 1866 are coupled to the cache memory 1872 and the shared memory 1870 via a memory and cache interconnect 1868.

[0188] In at least one embodiment, the instruction cache 1852 receives the instruction stream to be executed from the pipeline manager 1832. In at least one embodiment, the instructions are cached in the instruction cache 1852 and dispatched for execution by the instruction unit 1854. In one embodiment, the instruction unit 1854 can dispatch the instructions as a thread group (e.g., a warp), assigning each thread of the thread group to a different execution unit within the GPGPU core 1862. In at least one embodiment, the instruction can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1856 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the LSU 1866.

[0189] In at least one embodiment, register file 1858 provides a set of registers for the functional units of graphics multiprocessor 1896. In at least one embodiment, register file 1858 provides temporary storage for operands for data paths of functional units (e.g., GPGPU core 1862, LSU 1866) connected to graphics multiprocessor 1896. In at least one embodiment, register file 1858 is divided between each functional unit such that a dedicated portion of register file 1858 is allocated to each functional unit. In at least one embodiment, register file 1858 is divided between different thread groups being executed by graphics multiprocessor 1896.

[0190] In at least one embodiment, the GPGPU cores 1862 may each include an FPU and / or ALU for executing instructions of the graphics multiprocessor 1896. The GPGPU cores 1862 may be similar in architecture or the architecture may be different. In at least one embodiment, the first portion of the GPGPU core 1862 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core 1862 includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1896 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1862 may also include fixed or special-function logic.

[0191] In at least one embodiment, the GPGPU core 1862 includes SIMD logic capable of executing a single instruction to multiple sets of data. In at least one embodiment, the GPGPU core 1862 can physically execute SIMD4, SIMD8 and SIMD9 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0192] In at least one embodiment, the memory and cache interconnect 1868 is an interconnect network that connects each functional unit of the graphics multiprocessor 1896 to the register file 1858 and the shared memory 1870. In at least one embodiment, the memory and cache interconnect 1868 is a crossbar interconnect that allows the LSU 1866 to implement load and store operations between the shared memory 1870 and the register file 1858. In at least one embodiment, the register file 1858 can operate at the same frequency as the GPGPU core 1862, so that the latency of data transfer between the GPGPU core 1862 and the register file 1858 is very low. In at least one embodiment, the shared memory 1870 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 1896. In at least one embodiment, the cache memory 1872 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 1836. In at least one embodiment, the shared memory 1870 can also be used as a program managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 1872, threads executing on GPGPU core 1862 may programmatically store data in shared memory.

[0193] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0194] Fig.19Graphics processor 1900 is shown in accordance with at least one embodiment. In at least one embodiment, graphics processor 1900 includes ring interconnect 1902, pipeline front end 1904, media engine 1937, and graphics cores 1980A-1980N. In at least one embodiment, ring interconnect 1902 couples graphics processor 1900 to other processing units, including other graphics processors or one or more general purpose processor cores. In at least one embodiment, graphics processor 1900 is one of many processors integrated within a multi-core processing system.

[0195] In at least one embodiment, the graphics processor 1900 receives batches of commands via a ring interconnect 1902. In at least one embodiment, the input commands are interpreted by a command streamer 1903 in a pipeline front end 1904. In at least one embodiment, the graphics processor 1900 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 1980A-1980N. In at least one embodiment, for 3D geometry processing commands, the command streamer 1903 provides the commands to a geometry pipeline 1936. In at least one embodiment, for at least some media processing commands, the command streamer 1903 provides the commands to a video front end 1934, which is coupled to a media engine 1937. In at least one embodiment, the media engine 1937 includes a video quality engine (VQE) 1930 for video and image post-processing, and a multi-format encoding / decoding (MFX) 1933 engine for providing hardware accelerated media data encoding and decoding. In at least one embodiment, geometry pipeline 1936 and media engine 1937 each generate execution threads for thread execution resources provided by at least one graphics core 1980A.

[0196] In at least one embodiment, the graphics processor 1900 includes scalable thread execution resources featuring modular graphics cores 1980A-1980N (sometimes referred to as core slices), each of which has multiple sub-cores 1950A-550N, 1960A-1960N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 1900 can have any number of graphics cores 1980A to 1980N. In at least one embodiment, the graphics processor 1900 includes a graphics core 1980A having at least a first sub-core 1950A and a second sub-core 1960A. In at least one embodiment, the graphics processor 1900 is a low-power processor having a single sub-core (e.g., 1950A). In at least one embodiment, the graphics processor 1900 includes multiple graphics cores 1980A-1980N, each of which includes a group of first sub-cores 1950A-1950N and a group of second sub-cores 1960A-1960N. In at least one embodiment, each of the first sub-cores 1950A-1950N includes at least a first set of execution units (EUs) 1952A-1952N and media / texture samplers 1954A-1954N. In at least one embodiment, each of the second sub-cores 1960A-1960N includes at least a second set of execution units 1962A-1962N and samplers 1964A-1964N. In at least one embodiment, each of the sub-cores 1950A-1950N, 1960A-1960N shares a set of shared resources 1970A-1970N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.

[0197] Fig. 20 A processor 2000 according to at least one embodiment is shown. In at least one embodiment, the processor 2000 may include, but is not limited to, logic circuits for executing instructions. In at least one embodiment, the processor 2000 may execute instructions, including x86 instructions, ARM instructions, special instructions for ASICs, and the like. In at least one embodiment, the processor 2010 may include registers for storing packed data, such as 64-bit wide MMXTM registers in microprocessors enabled by Intel Corporation, Santa Clara, California, using MMX technology. In at least one embodiment, MMX registers available in integer and floating point form may operate with packed data elements, which are accompanied by SIMD and streaming SIMD extension ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX or higher versions (generally referred to as "SSEx") technology may hold such packed data operands. In at least one embodiment, the processor 2010 may execute instructions to accelerate CUAD programs.

[0198] In at least one embodiment, the processor 2000 includes an in-order front end ("front end") 2001 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, the front end 2001 may include several units. In at least one embodiment, an instruction prefetcher 2026 fetches instructions from memory and provides the instructions to an instruction decoder 2028, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2028 decodes the received instructions into one or more operations of so-called "microinstructions" or "micro-operations" (also referred to as "micro-operations" or "microinstructions") for execution. In at least one embodiment, the instruction decoder 2028 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, the trace cache 2030 can assemble the decoded microinstructions into a program-ordered sequence or trace in a microinstruction queue 2034 for execution. In at least one embodiment, when the trace cache 2030 encounters a complex instruction, the microcode ROM 2032 provides the microinstructions required to complete the operation.

[0199] In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions may require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 2028 may access the microcode ROM 2032 to execute the instruction. In at least one embodiment, the instruction may be decoded into a small number of micro-operations for processing at the instruction decoder 2028. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction may be stored in the microcode ROM 2032. In at least one embodiment, the trace cache 2030 references the entry point programmable logic array ("PLA") to determine the correct micro-instruction pointer for reading the microcode sequence from the microcode ROM 2032 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2032 completes the micro-operation sequencing of the instruction, the front end 2001 of the machine may resume fetching micro-operations from the trace cache 2030.

[0200] In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 2003 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance when the instructions go down the pipeline and are scheduled for execution. The out-of-order execution engine 2003 includes, but is not limited to, a distributor / register renamer 2040, a memory microinstruction queue 2042, an integer / floating point microinstruction queue 2044, a memory scheduler 2046, a fast scheduler 2002, a slow / general floating point scheduler ("slow / general FP scheduler") 2004, and a simple floating point scheduler ("simple FP scheduler") 2006. In at least one embodiment, the fast scheduler 2002, the slow / general floating point scheduler 2004, and the simple floating point scheduler 2006 are also collectively referred to as "microinstruction schedulers 2002, 2004, 2006". The distributor / register renamer 2040 allocates the machine buffers and resources required for each microinstruction to be executed in sequence. In at least one embodiment, the allocator / register renamer 2040 renames the logical registers to entries in the register file. In at least one embodiment, the allocator / register renamer 2040 also allocates entries for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 2042 for memory operations and an integer / floating point microinstruction queue 2044 for non-memory operations, in front of the memory scheduler 2046 and the microinstruction schedulers 2002, 2004, 2006. In at least one embodiment, the microinstruction schedulers 2002, 2004, 2006 determine when the microinstructions are ready to execute based on the readiness of their slave input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2002 of at least one embodiment can schedule on every half of the main clock cycle, while the slow / general floating point scheduler 2004 and the simple floating point scheduler 2006 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2002, 2004, 2006 arbitrate dispatch ports to schedule microinstructions for execution.

[0201] In at least one embodiment, execution block 2011 includes, but is not limited to, integer register file / branch network 2008, floating point register file / branch network ("FP register file / branch network") 2010, address generation units ("AGU") 2012 and 2014, fast arithmetic logic units ("fast ALU") 2016 and 2018, slow ALU 2020, floating point ALU ("FP") 2022, and floating point move unit ("FP move") 2024. In at least one embodiment, integer register file / branch network 2008 and floating point register file / bypass network 2010 are also referred to herein as "register files 2008, 2010". In at least one embodiment, ALUs 2012 and 2014, fast ALUs 2016 and 2018, slow ALU 2020, floating point ALU 2022, and floating point move unit 2024 are also referred to herein as "execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024". In at least one embodiment, the execution blocks may include, but are not limited to, any number (including zero) and types of register files, branch networks, address generation units, and execution units (in any combination).

[0202] In at least one embodiment, register files 2008, 2010 may be arranged between microinstruction schedulers 2002, 2004, 2006 and execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024. In at least one embodiment, integer register file / branch network 2008 performs integer operations. In at least one embodiment, floating point register file / branch network 2010 performs floating point operations. In at least one embodiment, each of register files 2008, 2010 may include but is not limited to a branch network that can bypass or forward the just completed result that has not yet been written to the register file to a new slave object. In at least one embodiment, register files 2008, 2010 can communicate data with each other. In at least one embodiment, integer register file / branch network 2008 may include but is not limited to two separate register files, one register file for low-order 32-bit data, and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2010 may include, but is not limited to, 128-bit wide entries, since floating point instructions typically have operands that are 64 to 128 bits wide.

[0203] In at least one embodiment, the execution units 2012, 2014, 2016, 2018, 2020, 2022, 2024 can execute instructions. In at least one embodiment, the register files 2008, 2010 store integer and floating point data operand values ​​that the microinstructions need to execute. In at least one embodiment, the processor 2000 may include, but is not limited to, any number of execution units 2012, 2014, 2016, 2018, 2020, 2022, 2024 and combinations thereof. In at least one embodiment, the floating point ALU 2022 and the floating point move unit 2024 can perform floating point, MMX, SIMD, AVX and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating point ALU 2022 may include, but is not limited to, a 64-bit by 64-bit floating point divider to perform division, square root and remainder micro-operations. In at least one embodiment, floating point hardware may be used to process instructions involving floating point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2016, 2018. In at least one embodiment, fast ALUs 2016, 2018 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations enter slow ALUs 2020 because slow ALUs 2020 can include, but are not limited to, integer execution hardware for long-delay type operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by AGUS 2012, 2014. In at least one embodiment, fast ALUs 2016, fast ALUs 2018, and slow ALUs 2020 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALUs 2016, fast ALUs 2018, and slow ALUs 2020 can be implemented to support various data bit sizes including 16, 32, 128, 256, etc. In at least one embodiment, the floating point ALU 2022 and floating point move unit 2024 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2022 and floating point move unit 2024 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0204] In at least one embodiment, microinstruction schedulers 2002, 2004, 2006 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed in processor 2000, processor 2000 can also include logic for handling memory misses. In at least one embodiment, if the data load in the data cache misses, there may be dependent operations running in the pipeline, which temporarily prevents the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and independent operations can be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0205] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. On the contrary, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques by circuits within the processor, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packaging data.

[0206] Fig.21 A processor 2100 is shown according to at least one embodiment. In at least one embodiment, the processor 2100 includes, but is not limited to, one or more processor cores (cores) 2102A-2102N, an integrated memory controller 2114, and an integrated graphics processor 2108. In at least one embodiment, the processor 2100 may include additional cores up to and including the additional processor core 2102N represented by the dashed box. In at least one embodiment, each processor core 2102A-2102N includes one or more internal cache units 2104A-2104N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2106. In at least one embodiment, the one or more processor cores 2102A-2102N are referred to as one or more computational units or operation units.

[0207] In at least one embodiment, the internal cache units 2104A-2104N and the shared cache unit 2106 represent a cache memory hierarchy within the processor 2100. In at least one embodiment, the cache memory units 2104A-2104N may include at least one level of instruction and data within each processor core and one or more levels of cache in a shared mid-level cache, such as L2, L3, Level 4 (L4), or other levels of cache, where the highest level of cache is classified as LLC before external memory. In at least one embodiment, cache coherency logic maintains coherency between the various cache units 2106 and 2104A-2104N.

[0208] In at least one embodiment, the processor 2100 may also include a set of one or more bus controller units 2116 and a system agent core 2110. In at least one embodiment, the one or more bus controller units 2116 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2110 provides management functions for various processor components. In at least one embodiment, the system agent core 2110 includes one or more integrated memory controllers 2114 to manage access to various external memory devices (not shown).

[0209] In at least one embodiment, one or more processor cores 2102A-2102N include support for multiple threads simultaneously. In at least one embodiment, system agent core 2110 includes components for coordinating and operating processor cores 2102A-2102N during multithreaded processing. In at least one embodiment, system agent core 2110 may additionally include a power control unit (PCU) that includes logic and components to adjust one or more power states of processor cores 2102A-2102N and graphics processor 2108.

[0210] In at least one embodiment, the processor 2100 additionally includes a graphics processor 2108 to perform graphics processing operations. In at least one embodiment, the graphics processor 2108 is coupled to a shared cache unit 2106 and a system agent core 2110 including one or more integrated memory controllers 2114. In at least one embodiment, the system agent core 2110 also includes a display controller 2111 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2111 may also be a separate module coupled to the graphics processor 2108 via at least one interconnect, or may be integrated within the graphics processor 2108.

[0211] In at least one embodiment, a ring-based interconnect unit 2112 is used to couple the internal components of the processor 2100. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2108 is coupled to the ring interconnect 2112 via an I / O link 2113.

[0212] In at least one embodiment, I / O link 2113 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 2118 (e.g., eDRAM modules). In at least one embodiment, each of processor cores 2102A-2102N and graphics processor 2108 uses embedded memory module 2118 as a shared LLC.

[0213] In at least one embodiment, the processor cores 2102A-2102N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2102A-2102N are heterogeneous in terms of ISA, wherein one or more processor cores 2102A-2102N execute a common instruction set, while one or more other processor cores 2102A-2102N execute a subset of a common instruction set or a different instruction set. In at least one embodiment, the processor cores 2102A-2102N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2100 can be implemented on one or more chips or as a SoC integrated circuit.

[0214] Fig. 22 A graphics processor core 2200 is shown in accordance with at least one described embodiment. In at least one embodiment, the graphics processor core 2200 is included within a graphics core array. In at least one embodiment, the graphics processor core 2200 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2200 is an example of a graphics core slice, and the graphics processors described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2200 may include a fixed function block 2230 coupled to a plurality of sub-cores 2201A-2201F, also referred to as sub-slices, which include modular blocks of general purpose and fixed function logic.

[0215] In at least one embodiment, fixed function block 2230 includes a geometry / fixed function pipeline 2236, which may be shared by all sub-cores in graphics processor 2200, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2236 includes a 3D fixed function pipeline, a video front end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0216] In at least one embodiment, the fixed function block 2230 also includes a graphics SoC interface 2237, a graphics microcontroller 2238, and a media pipeline 2239. The graphics SoC interface 2237 provides an interface between the graphics core 2200 and other processor cores in the SoC integrated circuit system. In at least one embodiment, the graphics microcontroller 2238 is a programmable subprocessor that can be configured to manage various functions of the graphics processor 2200, including thread dispatching, scheduling, and preemption. In at least one embodiment, the media pipeline 2239 includes logic that helps decode, encode, pre-process, and / or post-process multimedia data including image and video data. In at least one embodiment, the media pipeline 2239 implements media operations via requests to calculation or sampling logic within the sub-cores 2201-2201F.

[0217] In at least one embodiment, the SoC interface 2237 enables the graphics core 2200 to communicate with a general application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2237 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline), and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 2200 and the CPU within the SoC. In at least one embodiment, the SoC interface 2237 may also implement power management controls for the graphics core 2200 and enable interfaces between the clock domain of the graphics core 2200 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2237 enables command buffers to be received from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2239 when media operations are to be performed, or may be assigned to the geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2236, geometry and fixed function pipeline 2214) when graph processing operations are to be performed.

[0218] In at least one embodiment, the graphics microcontroller 2238 can be configured to perform various scheduling and management tasks for the graphics core 2200. In at least one embodiment, the graphics microcontroller 2238 can perform graph and / or compute workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2202A-2202F, 2204A-2204F in the sub-cores 2201A-2201F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2200 can submit a workload to one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 2238 may also facilitate low power or idle states for the graphics core 2200, thereby providing the graphics core 2200 with the ability to save and restore registers across low power state transitions within the graphics core 2200 independent of the operating system and / or graphics driver software on the system.

[0219] In at least one embodiment, the graphics core 2200 may have more or fewer sub-cores than the sub-cores 2201A-2201F shown, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, the graphics core 2200 may also include shared function logic 2210, shared and / or cache memory 2212, geometry / fixed function pipelines 2214, and additional fixed function logic 2216 to accelerate various graphics and compute processing operations. In at least one embodiment, the shared function logic 2210 may include logic units (e.g., samplers, math and / or inter-thread communication logic) that may be shared by each of the N sub-cores within the graphics core 2200. The shared and / or cache memory 2212 may be the LLC of the N sub-cores 2201A-2201F within the graphics core 2200, and may also be used as a shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2214 may be included in place of geometry / fixed function pipeline 2236 within fixed function block 2230 and may include the same or similar logic units.

[0220] In at least one embodiment, the graphics core 2200 includes additional fixed function logic 2216, which may include various fixed function acceleration logic for use by the graphics core 2200. In at least one embodiment, the additional fixed function logic 2216 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and the culling pipeline within the geometry / fixed function pipeline 2216, 2236, it is an additional geometry pipeline that may be included in the additional fixed function logic 2216. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, so that shading can be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2216 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether they are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0221] In at least one embodiment, the additional fixed function logic 2216 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for implementing a slowed down CUAD program.

[0222] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2201A-2201F that can be used to perform graphics, media, and compute operations in response to requests from a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-core 2201A-2201F includes multiple EU arrays 2202A-2202F, 2204A-2204F, thread dispatch and inter-thread communication (TD / IC) logic 2203A-2203F, 3D (e.g., texture) samplers 2205A-2205F, media samplers 2206A-2206F, shader processors 2207A-2207F, and shared local memory (SLM) 2208A-2208F. Each of the EU arrays 2202A-2202F, 2204A-2204F includes multiple execution units, which are GUGPUs capable of servicing graphics, media, or computing operations, performing floating-point and integer / fixed-point logic operations, including graphics, media, or computing shader programs. In at least one embodiment, the TD / IC logic 2203A-2203F performs local thread dispatching and thread control operations for the execution units within the sub-core, and facilitates communication between threads executed on the execution units of the sub-core. In at least one embodiment, the 3D samplers 2205A-2205F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, the media samplers 2206A-2206F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2201A-2201F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2201A-2201F may utilize shared local memory 2208A-2208F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[0223] Fig.23A parallel processing unit ("PPU") 2300 is shown according to at least one embodiment. In at least one embodiment, the PPU 2300 is configured with machine-readable code that, if executed by the PPU 2300, causes the PPU 2300 to perform some or all of the processes and techniques described throughout this document. In at least one embodiment, the PPU 2300 is a multithreaded processor implemented on one or more integrated circuit devices, and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by the PPU 2300. In at least one embodiment, the PPU 2300 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device (such as an LCD device). In at least one embodiment, the PPU 2300 is used to perform calculations, such as linear algebra operations and machine learning operations. Fig.23 The example parallel processor is shown for illustrative purposes only, and should be construed as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0224] In at least one embodiment, one or more PPUs 2300 are configured to accelerate high performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2300 are configured to accelerate CUDA programs. In at least one embodiment, PPU 2300 includes, but is not limited to, I / O unit 2306, front end unit 2310, scheduler unit 2312, work distribution unit 2314, hub 2316, crossbar switch (“Xbar”) 2320, one or more general processing clusters (“GPC”) 2318, and one or more partition units (“memory partition units”) 2322. In at least one embodiment, PPU 2300 is connected to a host processor or other PPU 2300 via one or more high-speed GPU interconnects (“GPU interconnects”) 2308. In at least one embodiment, PPU 2300 is connected to a host processor or other peripheral devices via a system bus or interconnect 2302. In one embodiment, PPU 2300 is connected to a local memory including one or more memory devices ("memory") 2304. In at least one embodiment, memory device 2304 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high bandwidth memory ("HBM") subsystem, and multiple DRAM dies are stacked within each device.

[0225] In at least one embodiment, the high-speed GPU interconnect 2308 may refer to a wire-based multi-lane communication link that the system uses to scale and includes one or more PPUs 2300 ("CPUs") in conjunction with one or more CPUs, supporting cache coherency between the PPU 2300 and the CPUs and CPU mastering. In at least one embodiment, the high-speed GPU interconnect 2308 transmits data and / or commands to other units of the PPU 2300, such as one or more copy engines, video encoders, video decoders, power management units, and / or other units in the PPU 2300 through the hub 2316. Fig.23 Other components that may not be explicitly shown.

[0226] In at least one embodiment, the I / O unit 2306 is configured to receive data from the host processor ( Fig.23In at least one embodiment, the I / O unit 2306 communicates with the host processor directly through the system bus 2302 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 2306 can communicate with one or more other processors (e.g., one or more PPUs 2300) via the system bus 2302. In at least one embodiment, the I / O unit 2306 implements a PCIe interface for communicating over a PCIe bus. In at least one embodiment, the I / O unit 2306 implements an interface for communicating with external devices.

[0227] In at least one embodiment, the I / O unit 2306 decodes packets received via the system bus 2302. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2300 to perform various operations. In at least one embodiment, the I / O unit 2306 sends the decoded commands to various other units of the PPU 2300 as specified by the commands. In at least one embodiment, the commands are sent to the front end unit 2310 and / or to the hub 2316 or other units of the PPU 2300, such as one or more replication engines, video encoders, video decoders, power management units, etc. ( Fig.23 In at least one embodiment, I / O unit 2306 is configured to route communications between various logical units of PPU 2300.

[0228] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2300 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2300—the host interface unit can be configured to access the buffer in the system memory connected to the system bus 2302 via the memory request transmitted via the I / O unit 2306 through the system bus 2302. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPU 2300, so that the front end unit 2310 receives one or more command stream pointers and manages one or more command streams, reads commands from the command stream and forwards the commands to the various units of the PPU 2300.

[0229] In at least one embodiment, the front end unit 2310 is coupled to a scheduler unit 2312 that configures the various GPCs 2318 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2312 is configured to track state information related to the various tasks managed by the scheduler unit 2312, where the state information may indicate which GPC 2318 the task is assigned to, whether the task is active or inactive, a priority associated with the task, etc. In at least one embodiment, the scheduler unit 2312 manages multiple tasks that are executed on one or more GPCs 2318.

[0230] In at least one embodiment, the scheduler unit 2312 is coupled to a work distribution unit 2314, which is configured to dispatch tasks for execution on the GPCs 2318. In at least one embodiment, the work distribution unit 2314 tracks a plurality of scheduled tasks received from the scheduler unit 2312 and the work distribution unit 2314 manages a pending task pool and an active task pool for each GPC 2318. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2318; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively processed by the GPC 2318, such that as one of the tasks in the GPC 2318 completes execution, the task is evicted from the active task pool of the GPC 2318 and one of the other tasks is selected from the pending task pool and scheduled for execution on the GPC 2318. In at least one embodiment, if an active task is idle on GPC 2318, such as while waiting for data dependencies to be resolved, the active task is evicted from GPC 2318 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on GPC 2318.

[0231] In at least one embodiment, work distribution unit 2314 communicates with one or more GPCs 2318 via XBar 2320. In at least one embodiment, XBar 2320 is an interconnect network that couples many units of PPU 2300 to other units of PPU 2300 and can be configured to couple work distribution unit 2314 to a specific GPC 2318. In at least one embodiment, other units of one or more PPU 2300 can also be connected to XBar 2320 through hub 2316.

[0232] In at least one embodiment, the tasks are managed by the scheduler unit 2312 and assigned to one of the GPCs 2318 by the work distribution unit 2314. The GPC 2318 is configured to process the tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 2318, routed to different GPCs 2318 via the XBar 2320, or stored in the memory 2304. In at least one embodiment, the results can be written to the memory 2304 via the partition unit 2322, which implements a memory interface for writing data to or reading data from the memory 2304. In at least one embodiment, the results can be transmitted to another PPU 2300 or CPU via the high-speed GPU interconnect 2308. In at least one embodiment, the PPU 2300 includes, but is not limited to, U partition units 2322, which is equal to the number of separate and different memory devices 2304 coupled to the PPU 2300.

[0233] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2300. In one embodiment, multiple computing applications are executed simultaneously by the PPU 2300, and the PPU 2300 provides isolation, quality of service (“QoS”), and independent address spaces for multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2300, and the driver core outputs the tasks to one or more streams processed by the PPU 2300. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads, including instructions for executing tasks and exchanging data through a shared memory.

[0234] Fig.24 FIG. 24 shows a GPC 2400 according to at least one embodiment. In at least one embodiment, the GPC 2400 is Fig.232318. In at least one embodiment, each GPC 2400 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2400 includes, but is not limited to, a pipeline manager 2402, a pre-raster operations unit ("PROP") 2404, a raster engine 2408, a work distribution crossbar ("WDX") 2416, a memory management unit ("MMU") 2418, one or more data processing clusters ("DPCs") 2406, and any suitable combination of components.

[0235] In at least one embodiment, the operation of the GPC 2400 is controlled by a pipeline manager 2402. In at least one embodiment, the pipeline manager 2402 manages the configuration of one or more DPCs 2406 to process tasks assigned to the GPC 2400. In at least one embodiment, the pipeline manager 2402 configures at least one of the one or more DPCs 2406 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 2406 is configured to execute vertex shader programs on a programmable streaming multiprocessor (“SM”) 2414. In at least one embodiment, the pipeline manager 2402 is configured to route packets received from the work distribution unit to appropriate logic units within the GPC 2400, and in at least one embodiment, some packets may be routed to fixed function hardware units in the PROP 2404 and / or the raster engine 2408, while other packets may be routed to the DPC 2406 for processing by the primitive engine 2412 or the SM 2414. In at least one embodiment, pipeline manager 2402 configures at least one of DPCs 2406 to implement a neural network model and / or a computational pipeline. In at least one embodiment, pipeline manager 2402 configures at least one of DPCs 2406 to execute at least a portion of a CUDA program.

[0236] In at least one embodiment, PROP unit 2404 is configured to route data generated by raster engine 2408 and DPC 2406 to a raster operations ("ROP") unit in a partition unit, such as described above in conjunction with Fig.232322, etc., described in more detail. In at least one embodiment, the PROP unit 2404 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, the raster engine 2408 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 2408 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are transmitted to the coarse raster engine to generate coverage information for the basic primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is transmitted to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where fragments outside the frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to a fine raster engine to generate properties for the pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 2408 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within the DPC 2406).

[0237] In at least one embodiment, each DPC 2406 included in GPC 2400 includes, but is not limited to, an M-pipeline controller ("MPC") 2410; a primitive engine 2412; one or more SMs 2414; and any suitable combination thereof. In at least one embodiment, MPC 2410 controls the operation of DPC 2406, routing packets received from pipeline manager 2402 to appropriate units in DPC 2406. In at least one embodiment, packets associated with vertices are routed to primitive engine 2412, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to SM 2414.

[0238] In at least one embodiment, SM 2414 includes, but is not limited to, a programmable stream processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 2414 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a specific thread group simultaneously, and implements a single instruction, multiple data ("SIMD") architecture, wherein each thread in a group of threads (e.g., a warp) is configured to process different data sets based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instruction. In at least one embodiment, SM 2414 implements a single instruction, multiple thread ("SIMT") architecture, wherein each thread in a group of threads is configured to process different data sets based on the same instruction set, but wherein individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby achieving concurrency between warps and serial execution within the warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. Fig.25 At least one embodiment of SM 2414 is described in further detail.

[0239] In at least one embodiment, the MMU 2418 is used between the GPC 2400 and the memory partition unit (e.g., Fig.23 The MMU 2418 provides an interface between the partition unit 2322 of the memory, and provides virtual address to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2418 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0240] Fig.25 Streaming multiprocessor ("SM") 2500 is shown in accordance with at least one embodiment. In at least one embodiment, SM 2500 is Fig.24SM 2500. In at least one embodiment, SM 2500 includes, but is not limited to, instruction cache 2502; one or more scheduler units 2504; register file 2508; one or more processing cores ("cores") 2510; one or more special function units ("SFUs") 2512; one or more load / store units ("LSUs") 2514; interconnect network 2516; shared memory / level 1 ("L1") cache 2518; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), and each task is assigned to a specific data processing cluster ("DPC") within a GPC, and if the task is associated with a shader program, the task is assigned to one of SM 2500. In at least one embodiment, scheduler unit 2504 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 2500. In at least one embodiment, the scheduler unit 2504 schedules thread blocks to execute as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 2504 manages a plurality of different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from a plurality of different cooperative groups to various functional units (e.g., processing core 2510, SFU 2512, and LSU 2514) in each clock cycle.

[0241] In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, thereby enabling the expression of richer and more efficient parallel decompositions. In at least one embodiment, the cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the API of the conventional programming model provides a single, simple construct for synchronizing cooperative threads: a barrier across all threads of a thread block (e.g., a syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide functional interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads in a cooperative group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, so that libraries and utility functions can be safely synchronized in their local environment without having to make assumptions about convergence. In at least one embodiment, the cooperation group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization over an entire grid of thread blocks.

[0242] In at least one embodiment, the dispatch unit 2506 is configured to send instructions to one or more of the functional units, and the scheduler unit 2504 includes but is not limited to two dispatch units 2506 that enable two different instructions from the same thread warp to be dispatched per clock cycle. In at least one embodiment, each scheduler unit 2504 includes a single dispatch unit 2506 or additional dispatch units 2506.

[0243] In at least one embodiment, each SM 2500 includes, in at least one embodiment, but is not limited to, a register file 2508 that provides a set of registers for the functional units of the SM 2500. In at least one embodiment, the register file 2508 is divided between each functional unit, so that a dedicated portion of the register file 2508 is allocated to each functional unit. In at least one embodiment, the register file 2508 is divided between different thread warps executed by the SM 2500, and the register file 2508 provides temporary storage for operands of the data paths connected to the functional units. In at least one embodiment, each SM 2500 includes, but is not limited to, a plurality of L processing cores 2510. In at least one embodiment, the SM 2500 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 2510. In at least one embodiment, each processing core 2510 includes, in at least one embodiment, but is not limited to, a full pipeline, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 2510 includes, but is not limited to, 64 single precision (32-bit) floating point cores, 64 integer cores, 32 double precision (64-bit) floating point cores, and 8 tensor cores.

[0244] In at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 2510. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0245] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating point matrices, and the accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, the tensor core performs a 32-bit floating point accumulation operation on the 16-bit floating point input data. In at least one embodiment, the 16-bit floating point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as a CUDA-C++ API) exposes specialized matrix loads, matrix multiplications and accumulations, and matrix storage operations to efficiently use tensor cores from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the warp level interface assumes a 16×16 size matrix across all 32 warp threads.

[0246] In at least one embodiment, each SM 2500 includes, but is not limited to, M SFUs 2512 that perform special functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 2512 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 2512 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texture pixels) from memory and sample the texture maps to produce sampled texture values ​​for use by shader programs executed by the SM 2500. In at least one embodiment, the texture maps are stored in a shared memory / L1 cache 2518. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM 2500 includes, but is not limited to, two texture units.

[0247] In at least one embodiment, each SM 2500 includes, but is not limited to, N LSUs 2514 that implement load and store operations between the shared memory / L1 cache 2518 and the register file 2508. In at least one embodiment, each SM 2500 includes, but is not limited to, an interconnect network 2516 that connects each functional unit to the register file 2508, and the LSUs 2514 connect to the register file 2508 and the shared memory / L1 cache 2518. In at least one embodiment, the interconnect network 2516 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 2508, and to connect the LSUs 2514 to memory locations in the register file 2508 and the shared memory / L1 cache 2518.

[0248] In at least one embodiment, the shared memory / L1 cache 2518 is an array of on-chip memory that allows data storage and communication between the SM 2500 and the primitive engines and between threads in the SM 2500 in at least one embodiment. In at least one embodiment, the shared memory / L1 cache 2518 includes, but is not limited to, a storage capacity of 128KB and is located in the path from the SM 2500 to the partition unit. In at least one embodiment, the shared memory / L1 cache 2518 is used in at least one embodiment for caching reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 2518, the L2 cache, and the memory is a backing store.

[0249] In at least one embodiment, data cache and shared memory functions are combined into a single memory block, providing improved performance for both types of memory access. In at least one embodiment, the capacity is used by programs that do not use the shared memory or as a cache, for example, if the shared memory is configured to use half of the capacity, the texture and load / store operations can use the remaining capacity. According to at least one embodiment, the integration within the shared memory / L1 cache 2518 enables the shared memory / L1 cache 2518 to be used as a high-throughput pipeline for streaming data while providing high bandwidth and low latency access to frequently reused data. In at least one embodiment, when configured for general parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, a fixed-function GPU is bypassed, thereby creating a simpler programming model. In at least one embodiment, in a general parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure that each thread generates unique results, use SM 2500 to execute the program and perform computations, use shared memory / L1 cache 2518 to communicate between threads, and use LSU 2514 to read and write global memory through shared memory / L1 cache 2518 and memory partitioning units. In at least one embodiment, when configured for general parallel computing, SM 2500 writes commands to scheduler unit 2504 that can be used to start new work on a DPC.

[0250] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., wireless, handheld device), a PDA, a digital camera, a vehicle, a head mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system on a chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.).

[0251] In at least one embodiment, the PPU may be included on a graphics card that includes one or more storage devices. The graphics card may be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated GPU ("iGPU") included in a chipset of the motherboard.

[0252] Software Construction for General Computing

[0253] The following figures illustrate, but are not limited to, exemplary software configurations for implementing at least one embodiment.

[0254] Fig.26 A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler instructions, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronosgroup), TM ), SYCL, or Intel One API.

[0255] In at least one embodiment, the software stack 2600 of the programming platform provides an execution environment for the application 2601. In at least one embodiment, the application 2601 may include any computer software that can be launched on the software stack 2600. In at least one embodiment, the application 2601 may include, but is not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

[0256] In at least one embodiment, the application 2601 and the software stack 2600 run on the hardware 2607. In at least one embodiment, the hardware 2607 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support programming platforms. In at least one embodiment, for example, using CUDA, the software stack 2600 may be vendor-specific and only compatible with devices from a specific vendor. In at least one embodiment, for example, in using OpenCL, the software stack 2600 can be used with devices from different vendors. In at least one embodiment, the hardware 2607 includes a host connected to one or more devices, which can be accessed via an application programming interface (API) call to perform computing tasks. In at least one embodiment, compared to the host in the hardware 2607, it may include but is not limited to a CPU (but may also include a computing device) and its memory, and the devices in the hardware 2607 may include but are not limited to a GPU, FPGA, AI engine or other computing device (but may also include a CPU) and its memory.

[0257] In at least one embodiment, the software stack 2600 of the programming platform includes, but is not limited to, multiple libraries 2603, runtime 2605, and device kernel drivers 2606. In at least one embodiment, each of the libraries 2603 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the library 2603 may include, but is not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the library 2603 includes functions optimized for execution on one or more types of devices. In at least one embodiment, the library 2603 may include, but is not limited to, functions for performing math, deep learning, and / or other types of operations on the device. In at least one embodiment, the library 2603 is associated with a corresponding API 2602, which may include one or more APIs that expose functions implemented in the library 2603. In at least one embodiment, a processor (e.g., a CPU, a GPU) executes, calls, or otherwise uses one or more APIs to prioritize kernels. For example, a first kernel (e.g., a parent kernel) can launch a second kernel (e.g., a child kernel), and the processor can use the second kernel to launch an additional kernel (e.g., a grandchild kernel) that is independent of the first kernel. In at least one embodiment, the processor executes an API to support dynamic stream priorities (e.g., updating priorities when performing operations using streams). For example, when the processor executes the API, it allows a programmer to copy stream priorities from one stream to one or more other streams.

[0258] In at least one embodiment, the software stack 2600 includes an API to support dynamic stream priorities (e.g., updating the priority when performing an operation with the stream), which allows the programmer to set the priority of the stream at any time after the stream is created. In at least one embodiment, the software stack 2600 includes an API to support dynamic stream priorities (e.g., updating the priority when performing an operation with the stream), which allows the programmer to obtain the current priority of the stream, where the priority is one of multiple attributes of the stream. In at least one embodiment, the software stack 2600 includes an API to support dynamic stream priorities (e.g., updating the priority when performing an operation with the stream), which allows the programmer to obtain the current priority of the stream as a single attribute. In at least one embodiment, the software stack 2600 includes an API to support dynamic stream priorities (e.g., updating the priority when performing an operation with the stream), which allows the programmer to launch the kernel to perform an operation on the stream at a set priority, which may be different from the stream priority.

[0259] In at least one embodiment, the application 2601 is written as source code that is compiled into executable code as follows: Figure 31-332601. In at least one embodiment, the executable code of the application 2601 can be run at least in part on an execution environment provided by the software stack 2600. In at least one embodiment, during the execution of the application 2601, code that needs to be run on the device (as opposed to the host) can be obtained. In this case, in at least one embodiment, the runtime 2605 can be called to load and start the necessary code on the device. In at least one embodiment, the runtime 2605 can include any technically feasible runtime system that can support the execution of the application 2601.

[0260] In at least one embodiment, runtime 2605 is implemented as one or more runtime libraries associated with a corresponding API (which is shown as API 2604). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, etc. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory and transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching functions on a device (sometimes referred to as "kernels" when the function is a global function callable from the host), and functions for setting attribute values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0261] In at least one embodiment, the runtime library and corresponding API 2604 may be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs may expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API may be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs may be language-specific APIs layered on top of a language-independent runtime API.

[0262] In at least one embodiment, the device kernel driver 2606 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 2606 can provide APIs such as API 2604 and / or low-level functions that other software depends on. In at least one embodiment, the device kernel driver 2606 can be configured to compile the intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 2606 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code (cache compiled binary code) for a specific target device at runtime, which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on the target device, which may not exist when the source code is initially compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without the need for the device kernel driver 2606 to compile the IR code at runtime.

[0263] Fig. 27 According to at least one embodiment, Fig.26 2701. In at least one embodiment, the CUDA software stack 2700 on which the application 2701 can be launched includes a CUDA library 2703, a CUDA runtime 2705, a CUDA driver 2707, and a device kernel driver 2708. In at least one embodiment, the CUDA software stack 2700 is executed on hardware 2709, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0264] In at least one embodiment, the application 2701, the CUDA runtime 2705, and the device kernel driver 2708 can respectively perform functions similar to the application 2601, the runtime 2605, and the device kernel driver 2606, and the above combination Fig.26It is described. In at least one embodiment, the CUDA driver 2707 includes a library (libcuda.so) that implements the CUDA driver API 2706. In at least one embodiment, similar to the CUDA runtime API 2704 implemented by the CUDA runtime library (cudart), the CUDA driver API 2706 can disclose but is not limited to functions for memory management, execution control, device management, error handling, synchronization and / or graphics interoperability, etc. In at least one embodiment, the CUDA driver API 2706 is different from the CUDA runtime API 2704 in that the CUDA runtime API 2704 simplifies device code management by providing implicit initialization, context (similar to process) management, and module (similar to dynamically loaded library) management. In contrast to the high-level CUDA runtime API 2704, in at least one embodiment, the CUDA driver API 2706 is a low-level API that provides finer-grained control over the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 2706 can disclose functions for context management that are not disclosed by the CUDA runtime API 2704. In at least one embodiment, the CUDA driver API 2706 is also language-independent and supports, for example, OpenCL in addition to the CUDA runtime API 2704. Furthermore, in at least one embodiment, the development libraries including the CUDA runtime 2705 can be considered separate from the driver components, including the user-mode CUDA driver 2707 and the kernel-mode device driver 2708 (sometimes also referred to as a "display" driver).

[0265] In at least one embodiment, the CUDA library 2703 may include, but is not limited to, a math library, a deep learning library, a parallel algorithm library, and / or a signal / image / video processing library, which may be utilized by parallel computing applications (e.g., application 2701). In at least one embodiment, the CUDA library 2703 may include a math library, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subroutines ("BLAS") for performing linear algebra operations; the cuFFT library for computing fast Fourier transforms ("FFTs"), and the cuRAND library for generating random numbers, etc. In at least one embodiment, the CUDA library 2703 may include a deep learning library, such as the cuDNN library for primitives of deep neural networks and the TensorRT platform for high-performance deep learning inference, etc.

[0266] Fig.28 According to at least one embodiment, Fig.26In at least one embodiment, the ROCm software stack 2800 on which the application 2801 can be launched includes a language runtime 2803, a system runtime 2805, a thunk 2807, and a ROCm kernel driver 2808. In at least one embodiment, the ROCm software stack 2800 is executed on hardware 2809, which may include a ROCm-enabled GPU developed by AMD, Inc. of Santa Clara, California.

[0267] In at least one embodiment, application 2801 may execute in conjunction with the above Fig.26 In addition, in at least one embodiment, the language runtime 2803 and the system runtime 2805 can perform functions similar to those of the application 2601 discussed above. Fig.26 The language runtime 2803 and the system runtime 2805 have similar functions. In at least one embodiment, the difference between the language runtime 2803 and the system runtime 2805 is that the system runtime 2805 is a language-independent runtime that implements the ROCr system runtime API 2804 and utilizes the heterogeneous system architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user mode API that exposes interfaces for accessing and interacting with AMDGPU, including functions for memory management, execution control of kernels dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared to the system runtime 2805, the language runtime 2803 is an implementation of a language-specific runtime API 2802 layered on top of the ROCr system runtime API 2804. In at least one embodiment, the language runtime API may include, but is not limited to, a portable heterogeneous computing interface ("HIP") language runtime API, a heterogeneous computing compiler ("HCC") language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes a combination of the above Fig. 27 Functions similar to the CUDA runtime API 2704 discussed above, such as those used for memory management, execution control, device management, error handling, synchronization, etc.

[0268] In at least one embodiment, thunk (ROCt) 2807 is an interface 2806 that can be used to interact with the underlying ROCm driver 2808. In at least one embodiment, the ROCm driver 2808 is a ROCk driver, which is a combination of the AMDGPU driver and the HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Fig.26 The HSA kernel driver 2606 is a device kernel driver that allows different types of processors to more efficiently share system resources via hardware features.

[0269] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 2800 above the language runtime 2803 and provide for integration with the above. Fig. 27 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFT, and the like.

[0270] Fig.29 According to at least one embodiment, Fig.26 In at least one embodiment, the OpenCL software stack 2900 on which the application 2901 can be launched includes an OpenCL framework 2910, an OpenCL runtime 2906, and a driver 2907. In at least one embodiment, the OpenCL software stack 2900 is executed on hardware 2709 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0271] In at least one embodiment, the application 2901, the OpenCL runtime 2906, the device kernel driver 2907 and the hardware 2908 can each execute in conjunction with the above Fig.26 The discussed application 2601, runtime 2605, device kernel driver 2606, and hardware 2607 have similar functionality. In at least one embodiment, the application 2901 also includes an OpenCL kernel 2902 having code to be executed on the device.

[0272] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 2903 and runtime API 2905. In at least one embodiment, the runtime API 2905 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context, and the runtime API 2905 can use the context to manage the command queue, program objects and kernel objects, shared memory objects, etc. of the device. In at least one embodiment, the platform API 2903 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer from and to devices, etc. In addition, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, etc.

[0273] In at least one embodiment, compiler 2904 is also included in OpenCL framework 2910. In at least one embodiment, source code can be compiled offline before executing the application or compiled online during execution of the application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 2904, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0274] Fig.30 Software supported by a programming platform according to at least one embodiment is shown. In at least one embodiment, the programming platform 3004 is configured to support various programming models 3003, middleware and / or libraries 3002, and frameworks 3001 that the application 3000 can rely on. In at least one embodiment, the application 3000 can be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL"), and / or NVIDIA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computing on the underlying hardware.

[0275] In at least one embodiment, programming platform 3004 can be a combination of the above Fig. 27 , Fig.28 and Fig.29 One of the CUDA, ROCm or OpenCL platforms described. In at least one embodiment, the programming platform 3004 supports multiple programming models 3003, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, the programming model 3003 can expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3003 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multiprocessing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0276] In at least one embodiment, the library and / or middleware 3002 provides an abstract implementation of the programming model 3004. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those that can be obtained from the programming platform 3004, such middleware also includes software that provides services to the application. In at least one embodiment, the library and / or middleware 3002 may include, but is not limited to, cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. In addition, in at least one embodiment, the library and / or middleware 3002 may include NCCL and ROCm communication collection libraries ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0277] In at least one embodiment, application framework 3001 relies on library and / or middleware 3002. In at least one embodiment, each application framework 3001 is a software framework for implementing a standard structure of application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework.

[0278] Fig.31 Compiled code according to at least one embodiment is shown to Figure 26-29In at least one embodiment, compiler 3101 receives source code 3100, which includes both host code and device code. In at least one embodiment, compiler 3101 is configured to convert source code 3100 into host executable code 3102 for execution on the host and device executable code 3103 for execution on the device. In at least one embodiment, source code 3100 can be compiled offline before executing the application, or compiled online during execution of the application.

[0279] In at least one embodiment, source code 3100 may include code in any programming language supported by compiler 3101, such as C++, C, Fortran, etc. In at least one embodiment, source code 3100 may be included in a single-source file having a mixture of host code and device code, and indicating the location of the device code therein. In at least one embodiment, the single-source file may be a .cu file including CUDA code or a .hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3100 may include multiple source code files, rather than a single source file, in which host code and device code are separated.

[0280] In at least one embodiment, the compiler 3101 is configured to compile the source code 3100 into a host executable code 3102 for execution on a host and a device executable code 3103 for execution on a device. In at least one embodiment, the compiler 3101 performs operations including parsing the source code 3100 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where the source code 3100 includes a single source file, the compiler 3101 can separate the device code from the host code in such a single source file, compile the device code and the host code into the device executable code 3103 and the host executable code 3102, respectively, and link the device executable code 3103 and the host executable code 3102 together in a single file, as described below with respect to Fig.32 discussed in more detail.

[0281] In at least one embodiment, the host executable code 3102 and the device executable code 3103 can be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, the host executable code 3102 can include native object code, and the device executable code 3103 can include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both the host executable code 3102 and the device executable code 3103 can include target binary code.

[0282] Fig.32 is a compiled code according to at least one embodiment to Figure 26-29 3201 is a more detailed illustration of the execution on one of the programming platforms of . In at least one embodiment, the compiler 3201 is configured to receive the source code 3200, compile the source code 3200, and output an executable file 3210. In at least one embodiment, the source code 3200 is a single source file, such as a .cu file, a .hip.cpp file, or a file in other formats, which includes both host code and device code. In at least one embodiment, the compiler 3201 can be, but is not limited to, the NVIDIA CUDA compiler ("NVCC") for compiling CUDA code in .cu files, or the HCC compiler for compiling HIP code in .hip.cpp files.

[0283] In at least one embodiment, compiler 3201 includes compiler front end 3202, host compiler 3205, device compiler 3206, and linker 3209. In at least one embodiment, compiler front end 3202 is configured to separate device code 3204 from host code 3203 in source code 3200. In at least one embodiment, device code 3204 is compiled by device compiler 3206 into device executable code 3208, which may include binary code or IR code as described. In at least one embodiment, host code 3203 is separately compiled by host compiler 3205 into host executable code 3207. In at least one embodiment, for NVCC, host compiler 3205 may be, but is not limited to, a general C / C++ compiler that outputs native object code, and device compiler 3206 may be, but is not limited to, a low-level virtual machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both the host compiler 3205 and the device compiler 3206 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0284] In at least one embodiment, after source code 3200 is compiled into host executable code 3207 and device executable code 3208, linker 3209 links host and device executable code 3207 and 3208 together in executable file 3210. In at least one embodiment, native object code for the host and PTX or binary code for the device may be linked together in an Executable and Linkable Format ("ELF") file, which is a container format for storing object code.

[0285] Fig.333302. In at least one embodiment, source code 3300 is passed through conversion tool 3301, which converts source code 3300 into converted source code 3302. In at least one embodiment, compiler 3303 is used to compile converted source code 3302 into host executable code 3304 and device executable code 3305, which is similar to the process of compiler 3101 compiling source code 3100 into host executable code 3102 and device executable code 3103, as described above in conjunction with Fig.31 discussed.

[0286] In at least one embodiment, the conversion performed by conversion tool 3301 is used to port source code 3300 to execute in an environment different from that on which it was originally intended to run. In at least one embodiment, conversion tool 3301 may include, but is not limited to, a HIP converter for "hipifying" CUDA code for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, conversion of source code 3300 may include parsing source code 3300 and converting calls to APIs provided by one programming model (e.g., CUDA) to corresponding calls to APIs provided by another programming model (e.g., HIP), as described below in conjunction with Fig.34A and Fig.35 Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, CUDA driver API, and / or CUDA library may be converted to corresponding HIP API calls. In at least one embodiment, the automatic conversion performed by the conversion tool 3301 may sometimes be incomplete, requiring additional manual work to fully port the source code 3300.

[0287] Configuring GPUs for general computing

[0288] The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computing source code according to at least one embodiment.

[0289] Fig.34AA system 3400 is shown configured to compile and execute CUDA source code 3410 using different types of processing units in accordance with at least one embodiment. In at least one embodiment, the system 3400 includes, but is not limited to, CUDA source code 3410, a CUDA compiler 3450, a host executable 3470(1), a host executable 3470(2), a CUDA device executable 3484, a CPU 3490, a CUDA-enabled GPU 3494, a GPU 3492, a CUDA to HIP conversion tool 3420, a HIP source code 3430, a HIP compiler driver 3440, an HCC 3460, and an HCC device executable 3482.

[0290] In at least one embodiment, the CUDA source code 3410 is a collection of human-readable codes of the CUDA programming language. In at least one embodiment, the CUDA code is a human-readable code of the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language, which includes but is not limited to defining device code and distinguishing mechanisms between device code and host code. In at least one embodiment, the device code is a source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3490, GPU 3492, or another GPGPU. In at least one embodiment, the host code is a source code that can be executed on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3490.

[0291] In at least one embodiment, the CUDA source code 3410 includes, but is not limited to, any number (including zero) of global functions 3412, any number (including zero) of device functions 3414, any number (including zero) of host functions 3416, and any number (including zero) of host / device functions 3418. In at least one embodiment, global functions 3412, device functions 3414, host functions 3416, and host / device functions 3418 can be mixed in the CUDA source code 3410. In at least one embodiment, each global function 3412 is executable on a device and can be called from a host. Therefore, in at least one embodiment, one or more of the global functions 3412 can serve as an entry point for a device. In at least one embodiment, each global function 3412 is a kernel. In at least one embodiment and in a technique called dynamic parallelism, one or more global functions 3412 define a kernel that can be executed on a device and can be called from such a device. In at least one embodiment, the kernel is executed N times (where N is any positive integer) in parallel by N different threads on a device during execution.

[0292] In at least one embodiment, each device function 3414 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3416 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 3416 defines both a host version of a function that is executable on a host and can only be called from such a host, and a device version of a function that is executable on a device and can only be called from such a device.

[0293] In at least one embodiment, the CUDA source code 3410 may also include, but is not limited to, any number of calls to any number of functions defined by the CUDA runtime API 3402. In at least one embodiment, the CUDA runtime API 3402 may include, but is not limited to, any number of functions executed on the host for allocating and deallocating device memory, transferring data between host memory and device memory, managing systems with multiple devices, and the like. In at least one embodiment, the CUDA source code 3410 may also include any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, the CUDA API may be any API designed to be used by CUDA code. In at least one embodiment, the CUDA API includes, but is not limited to, the CUDA runtime API 3402, the CUDA driver API, an API for any number of CUDA libraries, and the like. In at least one embodiment and relative to the CUDA runtime API 3402, the CUDA driver API is a lower-level API, but may provide finer-grained control over the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, and the like.

[0294] In at least one embodiment, the CUDA compiler 3450 compiles input CUDA code (e.g., CUDA source code 3410) to generate host executable code 3470 (1) and CUDA device executable code 3484. In at least one embodiment, the CUDA compiler 3450 is NVCC. In at least one embodiment, the host executable code 3470 (1) is a compiled version of the host code included in the input source code executable on the CPU 3490. In at least one embodiment, the CPU 3490 can be any processor optimized for sequential instruction processing.

[0295] In at least one embodiment, the CUDA device executable code 3484 is a compiled version of the device code included in the input source code executable on the CUDA-enabled GPU 3494. In at least one embodiment, the CUDA device executable code 3484 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3484 includes, but is not limited to, IR code, such as PTX code, which is further compiled by the device driver at runtime into binary code for a specific target device (e.g., a CUDA-enabled GPU 3494). In at least one embodiment, the CUDA-enabled GPU 3494 can be any processor optimized for parallel instruction processing and supporting CUDA. In at least one embodiment, the CUDA-enabled GPU 3494 is developed by NVIDIA Corporation of Santa Clara, California.

[0296] In at least one embodiment, the CUDA to HIP conversion tool 3420 is configured to convert the CUDA source code 3410 into a functionally similar HIP source code 3430. In at least one embodiment, the HIP source code 3430 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is a human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language, which includes but is not limited to a functionally similar version of the CUDA mechanism for defining device code and distinguishing device code from host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes but is not limited to a mechanism for defining global functions 3412, but such a HIP programming language may lack support for dynamic parallelism, and therefore, the global functions 3412 defined in the HIP code can only be called from the host.

[0297] In at least one embodiment, the HIP source code 3430 includes, but is not limited to, any number (including zero) of global functions 3412, any number (including zero) of device functions 3414, any number (including zero) of host functions 3416, and any number (including zero) of host / device functions 3418. In at least one embodiment, the HIP source code 3430 may also include any number of calls to any number of functions specified in the HIP runtime API 3432. In one embodiment, the HIP runtime API 3432 includes, but is not limited to, functionally similar versions of a subset of functions included in the CUDA runtime API 3402. In at least one embodiment, the HIP source code 3430 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, the HIP API includes, but is not limited to, the HIP runtime API 3432, the HIP driver API, an API for any number of HIP libraries, an API for any number of ROCm libraries, and the like.

[0298] In at least one embodiment, the CUDA to HIP conversion tool 3420 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA to HIP conversion tool 3420 converts any number of calls to functions specified in the CUDA runtime API 3402 to any number of calls to functions specified in the HIP runtime API 3432.

[0299] In at least one embodiment, the CUDA to HIP conversion tool 3420 is a tool called hipify-perl, which performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 3420 is a tool called hipify-clang, which performs a more complex and robust conversion process relative to hipify-perl, which involves parsing the CUDA code using clang (compiler front end) and then converting the resulting symbols. In at least one embodiment, in addition to those modifications performed by the CUDA to HIP conversion tool 3420, correctly converting the CUDA code to HIP code may also require modifications (e.g., manual editing).

[0300] In at least one embodiment, the HIP compiler driver 3440 is a front end that determines the target device 3446 and then configures a compiler compatible with the target device 3446 to compile the HIP source code 3430. In at least one embodiment, the target device 3446 is a processor optimized for parallel instruction processing. In at least one embodiment, the HIP compiler driver 3440 can determine the target device 3446 in any technically feasible manner.

[0301] In at least one embodiment, if the target device 3446 is CUDA compatible (e.g., a CUDA-enabled GPU 3494), the HIP compiler driver 3440 generates HIP / NVCC compile commands 3442. In at least one embodiment and in conjunction with Fig.34B As described in more detail, HIP / NVCC compile command 3442 configures CUDA compiler 3450 to compile HIP source code 3430 using, but not limited to, HIP to CUDA translation headers and CUDA runtime libraries. In at least one embodiment and in response to HIP / NVCC compile command 3442, CUDA compiler 3450 generates host executable code 3470(1) and CUDA device executable code 3484.

[0302] In at least one embodiment, if the target device 3446 is not compatible with CUDA, the HIP compiler driver 3440 generates HIP / HCC compilation commands 3444. In at least one embodiment and in conjunction with Fig.34C Described in more detail, the HIP / HCC compile command 3444 configures the HCC 3460 to compile the HIP source code 3430 using the HCC header and the HIP / HCC runtime library. In at least one embodiment and in response to the HIP / HCC compile command 3444, the HCC 3460 generates a host executable code 3470 (2) and an HCC device executable code 3482. In at least one embodiment, the HCC device executable code 3482 is a compiled version of the device code included in the HIP source code 3430 that can be executed on the GPU 3492. In at least one embodiment, the GPU 3492 can be any processor optimized for parallel instruction processing, incompatible with CUDA and compatible with HCC. In at least one embodiment, the GPU 3492 is developed by AMD, Inc. of Santa Clara, California. In at least one embodiment, the GPU 3492 is a GPU 3492 that is not CUDA-enabled.

[0303] For illustrative purposes only, Fig.34A3490 and different devices. In at least one embodiment, the direct CUDA process compiles the CUDA source code 3410 for execution on the CPU 3490 and the CUDA-enabled GPU 3494 without converting the CUDA source code 3410 to the HIP source code 3430. In at least one embodiment, the indirect CUDA process converts the CUDA source code 3410 to the HIP source code 3430 and then compiles the HIP source code 3430 for execution on the CPU 3490 and the CUDA-enabled GPU 3494. In at least one embodiment, the CUDA / HCC process converts the CUDA source code 3410 to the HIP source code 3430 and then compiles the HIP source code 3430 for execution on the CPU 3490 and the GPU 3492.

[0304] A direct CUDA flow that can be implemented in at least one embodiment can be depicted by a dashed line and a series of bubble annotations A1-A3. In at least one embodiment, and as indicated by bubble annotation A1, a CUDA compiler 3450 receives a CUDA source code 3410 and a CUDA compile command 3448 that configures the CUDA compiler 3450 to compile the CUDA source code 3410. In at least one embodiment, the CUDA source code 3410 used in the direct CUDA flow is written in the CUDA programming language, which is based on other programming languages ​​other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3448, the CUDA compiler 3450 generates a host executable code 3470 (1) and a CUDA device executable code 3484 (indicated by bubble annotation A2). In at least one embodiment and as indicated by bubble annotation A3, the host executable code 3470 (1) and the CUDA device executable code 3484 can be executed on a CPU 3490 and a CUDA-enabled GPU 3494, respectively. In at least one embodiment, the CUDA device executable code 3484 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3484 includes, but is not limited to, PTX code, and is further compiled into binary code for a specific target device at runtime.

[0305] The indirect CUDA flow that can be implemented in at least one embodiment can be described by a dashed line and a series of bubble notes B1-B6. In at least one embodiment and as shown in bubble note B1, the CUDA to HIP conversion tool 3420 receives the CUDA source code 3410. In at least one embodiment and as shown in bubble note B2, the CUDA to HIP conversion tool 3420 converts the CUDA source code 3410 to HIP source code 3430. In at least one embodiment and as shown in bubble note B3, the HIP compiler driver 3440 receives the HIP source code 3430 and determines whether the target device 3446 is CUDA enabled.

[0306] In at least one embodiment and as indicated by bubble note B4, HIP compiler driver 3440 generates HIP / NVCC compile commands 3442 and sends both HIP / NVCC compile commands 3442 and HIP source code 3430 to CUDA compiler 3450. Fig.34B As described in more detail, the HIP / NVCC compile command 3442 configures the CUDA compiler 3450 to compile the HIP source code 3430 using, but not limited to, the HIP to CUDA translation header and the CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compile command 3442, the CUDA compiler 3450 generates a host executable code 3470 (1) and a CUDA device executable code 3484 (indicated by bubble note B5). In at least one embodiment and as indicated by bubble note B6, the host executable code 3470 (1) and the CUDA device executable code 3484 can be executed on a CPU 3490 and a CUDA-enabled GPU 3494, respectively. In at least one embodiment, the CUDA device executable code 3484 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3484 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0307] The CUDA / HCC flow that can be implemented in at least one embodiment can be described by a solid line and a series of bubble comments C1-C6. In at least one embodiment and as shown in bubble comment C1, the CUDA to HIP conversion tool 3420 receives the CUDA source code 3410. In at least one embodiment and as shown in bubble comment C2, the CUDA to HIP conversion tool 3420 converts the CUDA source code 3410 to the HIP source code 3430. In at least one embodiment and as shown in bubble comment C3, the HIP compiler driver 3440 receives the HIP source code 3430 and determines that the target device 3446 is not CUDA-enabled.

[0308] In at least one embodiment, the HIP compiler driver 3440 generates a HIP / HCC compile command 3444 and sends both the HIP / HCC compile command 3444 and the HIP source code 3430 to the HCC 3460 (indicated by bubble comment C4). Fig.34C As described in more detail, the HIP / HCC compile command 3444 configures the HCC 3460 to compile the HIP source code 3430 using, but not limited to, the HCC header and the HIP / HCC runtime library. In at least one embodiment and in response to the HIP / HCC compile command 3444, the HCC 3460 generates a host executable code 3470(2) and an HCC device executable code 3482 (indicated by bubble comment C5). In at least one embodiment and as indicated by bubble comment C6, the host executable code 3470(2) and the HCC device executable code 3482 can be executed on the CPU 3490 and the GPU 3492, respectively.

[0309] In at least one embodiment, after converting the CUDA source code 3410 to the HIP source code 3430, the HIP compiler driver 3440 can then be used to generate executable code for the CUDA-enabled GPU 3494 or GPU 3492 without re-implementing the CUDA to HIP conversion tool 3420. In at least one embodiment, the CUDA to HIP conversion tool 3420 converts the CUDA source code 3410 to the HIP source code 3430, which is then stored in memory. In at least one embodiment, the HIP compiler driver 3440 then configures the HCC 3460 to generate a host executable code 3470 (2) and an HCC device executable code 3482 based on the HIP source code 3430. In at least one embodiment, the HIP compiler driver 3440 then configures the CUDA compiler 3450 to generate a host executable code 3470 (1) and a CUDA device executable code 3484 based on the stored HIP source code 3430.

[0310] Fig.34B 3490 and a CUDA-enabled GPU 3494 are configured to compile and execute Fig.34A In at least one embodiment, the system 3404 includes, but is not limited to, the CUDA source code 3410, a CUDA to HIP conversion tool 3420, a HIP source code 3430, a HIP compiler driver 3440, a CUDA compiler 3450, a host executable code 3470(1), a CUDA device executable code 3484, a CPU 3490, and a CUDA-enabled GPU 3494.

[0311] In at least one embodiment and as previously incorporated herein Fig.34A As described, CUDA source code 3410 includes, but is not limited to, any number (including zero) of global functions 3412, any number (including zero) of device functions 3414, any number (including zero) of host functions 3416, and any number (including zero) of host / device functions 3418. In at least one embodiment, CUDA source code 3410 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0312] In at least one embodiment, the CUDA to HIP conversion tool 3420 converts the CUDA source code 3410 into HIP source code 3430. In at least one embodiment, the CUDA to HIP conversion tool 3420 converts each kernel call in the CUDA source code 3410 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3410 into any number of other functionally similar HIP calls.

[0313] In at least one embodiment, the HIP compiler driver 3440 determines that the target device 3446 is CUDA-enabled and generates HIP / NVCC compile commands 3442. In at least one embodiment, the HIP compiler driver 3440 then configures the CUDA compiler 3450 via the HIP / NVCC compile commands 3442 to compile the HIP source code 3430. In at least one embodiment, as part of configuring the CUDA compiler 3450, the HIP compiler driver 3440 provides access to a HIP to CUDA translation header 3452. In at least one embodiment, the HIP to CUDA translation header 3452 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs to any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, the CUDA compiler 3450 uses the HIP to CUDA translation header 3452 in conjunction with a CUDA runtime library 3454 corresponding to the CUDA runtime API 3402 to generate host executable code 3470 (1) and CUDA device executable code 3484. In at least one embodiment, the host executable code 3470(1) and the CUDA device executable code 3484 can then be executed on the CPU 3490 and the CUDA-enabled GPU 3494, respectively. In at least one embodiment, the CUDA device executable code 3484 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3484 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0314] Fig.34C A system 3406 is shown that is configured to compile and execute using a CPU 3490 and a non-CUDA enabled GPU 3492 according to at least one embodiment. Fig.34A CUDA source code 3410. In at least one embodiment, system 3406 includes, but is not limited to, CUDA source code 3410, CUDA to HIP conversion tool 3420, HIP source code 3430, HIP compiler driver 3440, HCC 3460, host executable code 3470(2), HCC device executable code 3482, CPU 3490, and GPU 3492.

[0315] In at least one embodiment, and as previously described herein in conjunction with Fig.34AAs described, CUDA source code 3410 includes, but is not limited to, any number (including zero) of global functions 3412, any number (including zero) of device functions 3414, any number (including zero) of host functions 3416, and any number (including zero) of host / device functions 3418. In at least one embodiment, CUDA source code 3410 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0316] In at least one embodiment, the CUDA to HIP conversion tool 3420 converts the CUDA source code 3410 into HIP source code 3430. In at least one embodiment, the CUDA to HIP conversion tool 3420 converts each kernel call in the CUDA source code 3410 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the source code 3410 into any number of other functionally similar HIP calls.

[0317] In at least one embodiment, the HIP compiler driver 3440 then determines that the target device 3446 is not CUDA-enabled and generates HIP / HCC compile commands 3444. In at least one embodiment, the HIP compiler driver 3440 then configures the HCC 3460 to execute the HIP / HCC compile commands 3444 to compile the HIP source code 3430. In at least one embodiment, the HIP / HCC compile commands 3444 configure the HCC 3460 to generate host executable code 3470 (2) and HCC device executable code 3482 using, but not limited to, a HIP / HCC runtime library 3458 and an HCC header 3456. In at least one embodiment, the HIP / HCC runtime library 3458 corresponds to the HIP runtime API 3432. In at least one embodiment, the HCC header 3456 includes, but is not limited to, any number and type of interoperability mechanisms for the HIP and HCC. In at least one embodiment, the host executable code 3470 ( 2 ) and the HCC device executable code 3482 may be executed on the CPU 3490 and the GPU 3492 , respectively.

[0318] Fig.35 According to at least one embodiment, Fig.34C34. An exemplary kernel converted by the CUDA to HIP conversion tool 3420 of FIG. 34. In at least one embodiment, the CUDA source code 3410 divides the overall problem that a given kernel is designed to solve into relatively coarse sub-problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, an arbitrary number of threads. In at least one embodiment, each sub-problem is divided into relatively small pieces that can be solved in parallel by the threads in the thread block in a cooperative manner. In at least one embodiment, threads within a thread block can collaborate by sharing data through shared memory and by synchronizing execution to coordinate memory access.

[0319] In at least one embodiment, the CUDA source code 3410 organizes the thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads, and the grid includes, but is not limited to, any number of thread blocks.

[0320] In at least one embodiment, a kernel is a function in device code defined using the "__global__" declaration specifier. In at least one embodiment, the CUDA kernel launch syntax 3510 is used to specify the size of the grid on which the kernel is executed for a given kernel call and the associated streams. In at least one embodiment, the CUDA kernel launch syntax 3510 is specified as "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<< ... >>>" construct that is inserted between the kernel name ("KernelName") and the parenthesized list of kernel parameters ("KernelArguments"). In at least one embodiment, the CUDA kernel launch syntax 3510 includes, but is not limited to, a CUDA launch function syntax rather than an execution configuration syntax.

[0321] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, but is not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing a kernel is given a unique thread ID that can be accessed within the kernel through a built-in variable (e.g., "threadIdx").

[0322] In at least one embodiment, with respect to CUDA kernel launch syntax 3510, "SharedMemorySize" is an optional parameter that specifies the number of bytes in shared memory that are dynamically allocated for each thread block for a given kernel call in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax 3510, SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax 3510, "stream" is an optional parameter that specifies the associated stream and defaults to zero to specify the default stream. In at least one embodiment, a stream is a sequence of commands that are executed in order (which may be issued by different host threads). In at least one embodiment, different streams can execute commands out of order or simultaneously with respect to each other.

[0323] In at least one embodiment, CUDA source code 3410 includes, but is not limited to, a kernel definition and a main function for an exemplary kernel "MatAdd". In at least one embodiment, the main function is host code executed on a host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to execute on a device. In at least one embodiment, as shown, the kernel MatAdd adds two matrices A and B of size NxN, where N is a positive integer, and stores the result in a matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16x 16 and the numBlocks variable as N / 16xN / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);". In at least one embodiment, and in accordance with CUDA kernel launch syntax 3510, kernel MatAdd is executed using a grid of thread blocks of size N / 16×N / 16, where each thread block has a size of 16×16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in the grid executes kernel MatAdd to perform a pairwise addition.

[0324] In at least one embodiment, while converting CUDA source code 3410 to HIP source code 3430, CUDA to HIP conversion tool 3420 converts each kernel call in CUDA source code 3410 from CUDA kernel launch syntax 3510 to HIP kernel launch syntax 3520, and converts any number of other CUDA calls in source code 3410 to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3520 is specified as "hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, SharedMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax 3520 as in CUDA kernel launch syntax 3510 (described previously herein). In at least one embodiment, the parameters SharedMemorySize and Stream are required in the HIP kernel launch syntax 3520 and are optional in the CUDA kernel launch syntax 3510.

[0325] In at least one embodiment, in addition to causing the kernel MatAdd to execute on the device, Fig.35 A portion of the HIP source code 3430 depicted in Fig.35 3410 is the same as a portion of the CUDA source code 3410 depicted in FIG. In at least one embodiment, kernel MatAdd is defined in HIP source code 3430 with the same “__global__” declaration specifier as kernel MatAdd is defined in CUDA source code 3410. In at least one embodiment, the kernel call in HIP source code 3430 is “hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);”, while the corresponding kernel call in CUDA source code 3410 is “MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);".

[0326] Fig.36 In more detail, the Fig.34C 3492. In at least one embodiment, the GPU 3492 is developed by AMD of Santa Clara. In at least one embodiment, the GPU 3492 can be configured to perform computing operations in a highly parallel manner. In at least one embodiment, the GPU 3492 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the GPU 3492 is configured to perform operations unrelated to graphics. In at least one embodiment, the GPU 3492 is configured to perform both operations related to graphics and operations unrelated to graphics. In at least one embodiment, the GPU 3492 can be configured to execute device code included in the HIP source code 3430.

[0327] In at least one embodiment, GPU 3492 includes, but is not limited to, any number of programmable processing units 3620, command processor 3610, L2 cache 3622, memory controller 3670, DMA engine 3680(1), system memory controller 3682, DMA engine 3680(2), and GPU controller 3684. In at least one embodiment, each programmable processing unit 3620 includes, but is not limited to, workload manager 3630 and any number of compute units 3640. In at least one embodiment, command processor 3610 reads commands from one or more command queues (not shown) and distributes the commands to workload manager 3630. In at least one embodiment, for each programmable processing unit 3620, the associated workload manager 3630 distributes work to the compute units 3640 included in the programmable processing unit 3620. In at least one embodiment, each compute unit 3640 can execute any number of thread blocks, but each thread block executes on a single compute unit 3640. In at least one embodiment, a work group is a thread block.

[0328] In at least one embodiment, each computing unit 3640 includes, but is not limited to, any number of SIMD units 3650 and shared memory 3660. In at least one embodiment, each SIMD unit 3650 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3650 includes, but is not limited to, a vector ALU 3652 and a vector register file 3654. In at least one embodiment, each SIMD unit 3650 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), wherein each thread in the warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predictions can be used to disable one or more threads in the warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicated via a shared memory 3660.

[0329] In at least one embodiment, programmable processing unit 3620 is referred to as a "shader engine". In at least one embodiment, each programmable processing unit 3620 includes, but is not limited to, any number of dedicated graphics hardware in addition to compute unit 3640. In at least one embodiment, each programmable processing unit 3620 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of rendering backends, a workload manager 3630, and any number of compute units 3640.

[0330] In at least one embodiment, the compute units 3640 share an L2 cache 3622. In at least one embodiment, the L2 cache 3622 is partitioned. In at least one embodiment, all compute units 3640 in a GPU 3492 can access GPU memory 3690. In at least one embodiment, the memory controller 3670 and the system memory controller 3682 facilitate data transfers between the GPU 3492 and a host, and the DMA engine 3680 (1) enables asynchronous memory transfers between the GPU 3492 and the host. In at least one embodiment, the memory controller 3670 and the GPU controller 3684 facilitate data transfers between the GPU 3492 and other GPUs 3492, and the DMA engine 3680 (2) enables asynchronous memory transfers between the GPU 3492 and other GPUs 3492.

[0331] In at least one embodiment, GPU 3492 includes, but is not limited to, any number and type of system interconnects that facilitate data and control transfers between any number and type of directly or indirectly linked components within or outside GPU 3492. In at least one embodiment, GPU 3492 includes, but is not limited to, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, GPU 3492 may include, but is not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3492 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 3670 and system memory controller 3682) and memory devices (e.g., shared memory 3660) dedicated to one component or shared between multiple components. In at least one embodiment, GPU3492 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3622), each of which can be private or shared among any number of components (e.g., SIMD units 3650, compute units 3640, and programmable processing units 3620).

[0332] Fig.37 37 shows how threads of an exemplary CUDA grid 3720 are mapped to Fig.363720. In at least one embodiment, and for illustration purposes only, the grid 3720 has a GridSize of BX times BY times 1 and a BlockSize of TX times TY times 1. Thus, in at least one embodiment, the grid 3720 includes, but is not limited to, (BX*BY) thread blocks 3730, each of which includes, but is not limited to, (TX*TY) threads 3740. The threads 3740 are Fig.37 Depicted as a curved arrow.

[0333] In at least one embodiment, grid 3720 is mapped to programmable processing units 3620(1), which include, but are not limited to, compute units 3640(1)-3640(C). In at least one embodiment and as shown, (BJ*BY) thread blocks 3730 are mapped to compute unit 3640(1), and the remaining thread blocks 3730 are mapped to compute unit 3640(2). In at least one embodiment, each thread block 3730 may include, but are not limited to, any number of thread warps, and each thread warp is mapped to Fig.36 The different SIMD units 3650.

[0334] In at least one embodiment, the warps in a given thread block 3730 may be synchronized together and communicate through a shared memory 3660 included in the associated compute unit 3640. For example and in at least one embodiment, the warps in thread block 3730 (BJ, 1) may be synchronized together and communicate through a shared memory 3660 (1). For example and in at least one embodiment, the warps in thread block 3730 (BJ+1, 1) may be synchronized together and communicate through a shared memory 3660 (2).

[0335] Fig.38How to migrate existing CUDA code to data parallel C++ code according to at least one embodiment is shown. Data Parallel C++ (DPC++) may refer to an open, standards-based alternative to a single-architecture proprietary language that allows developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and also perform custom adjustments for specific accelerators. DPC++ uses similar and / or identical C and C++ constructs based on ISOC++ that developers may be familiar with. DPC++ incorporates the standard SYCL of the Khronos Group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer that builds on the underlying concepts, portability, and efficiency of OpenCL, which enables code for heterogeneous processors to be written in a "single-source" style using standard C++. SYCL can enable single-source development, where C++ template functions can contain both host code and device code to build complex algorithms accelerated using OpenCL, and then reuse them throughout the source code for different types of data.

[0336] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be deployed across various hardware targets. In at least one embodiment, the DPC++ compiler is used to generate DPC++ applications that can be deployed across various hardware targets, and the DPC++ compatibility tool can be used to migrate CUDA applications to multi-platform programs in DPC++. In at least one embodiment, the DPC++ base toolkit includes: a DPC++ compiler for deploying applications across various hardware targets; a DPC++ library for improving productivity and performance of CPUs, GPUs, and FPGAs; a DPC++ compatibility tool for migrating CUDA applications to multi-platform applications; and any suitable combination thereof.

[0337] In at least one embodiment, the DPC++ programming model is used to simplify one or more aspects related to programming CPUs and accelerators by using modern C++ features to express parallelism with a programming language called Data Parallel C++. The DPC++ programming language can be used for code reuse for hosts (e.g., CPUs) and accelerators (e.g., GPUs or FPGAs) using a single source language, and clearly communicates execution and memory dependencies. Mappings within the DPC++ code can be used to convert an application to run on the hardware or set of hardware devices that best accelerates the workload. The host can be used to simplify the development and debugging of device code even on platforms where no accelerator is available.

[0338] In at least one embodiment, CUDA source code 3800 is provided as input to DPC++ compatibility tool 3802 to generate human-readable DPC++ 3804. In at least one embodiment, human-readable DPC++ 3804 includes inline comments generated by DPC++ compatibility tool 3802 that guide developers on how and / or where to modify DPC++ code to complete the coding and tuning to desired performance 3806, thereby generating DPC++ source code 3808.

[0339] In at least one embodiment, the CUDA source code 3800 is or includes a collection of human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA source code 3800 is a human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language, which includes, but is not limited to, mechanisms for defining device code and distinguishing device code from host code. In at least one embodiment, the device code is source code that can be executed on a device (e.g., a GPU or FPGA) after compilation, and may include one or more parallelizable workflows that can be executed on one or more processor cores of the device. In at least one embodiment, the device may be a processor that is optimized for parallel instruction processing, such as a CUDA-enabled GPU, a GPU, or another GPGPU, etc. In at least one embodiment, the host code is source code that can be executed on a host after compilation. In at least one embodiment, some or all of the host code and device code can be executed in parallel across the CPU and GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. In combination Fig.38 The CUDA source code 3800 described may be consistent with that discussed elsewhere in this document.

[0340] In at least one embodiment, DPC++ compatibility tool 3802 refers to an executable tool, program, application, or any other suitable type of tool for facilitating migration of CUDA source code 3800 to DPC++ source code 3808. In at least one embodiment, DPC++ compatibility tool 3802 is a command-line based code migration tool that can be used as part of a DPC++ toolkit for porting existing CUDA sources to DPC++. In at least one embodiment, DPC++ compatibility tool 3802 converts some or all of the source code of a CUDA application from CUDA to DPC++ and generates a result file written at least in part in DPC++, referred to as human-readable DPC++ 3804. In at least one embodiment, human-readable DPC++ 3804 includes comments generated by DPC++ compatibility tool 3802 to indicate where user intervention may be required. In at least one embodiment, user intervention is necessary when CUDA source code 3800 calls a CUDA API that has no similar DPC++ API; other examples of requiring user intervention will be discussed in more detail later.

[0341] In at least one embodiment, the workflow for migrating CUDA source code 3800 (e.g., an application or portion thereof) includes creating one or more compilation database files; migrating CUDA to DPC++ using DPC++ compatibility tool 3802; completing the migration and verifying correctness, thereby generating DPC++ source code 3808; and compiling DPC++ source code 3808 using the DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts commands used when a Makefile is executed and stores them in a compilation database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, the interception of build commands converts Makefile commands into DPC compatibility commands.

[0342] In at least one embodiment, intercept-build is a utility script that intercepts the build process to capture compile options, macro definitions, and include paths, and writes the data to a compile database file. In at least one embodiment, the compile database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 3802 parses the compile database and applies options when migrating input sources. In at least one embodiment, the use of intercept-build is optional, but highly recommended for Make or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files: commands may include necessary compile flags; directories may include paths to header files; files may include paths to CUDA files.

[0343] In at least one embodiment, the DPC++ compatibility tool 3802 migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ as much as possible. In at least one embodiment, the DPC++ compatibility tool 3802 is available as part of a toolkit. In at least one embodiment, the DPC++ toolkit includes an intercept-build tool. In at least one embodiment, the intercept-build tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, the DPC++ compatibility tool 3802 uses the compilation database generated by the intercept-build tool to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, the DPC++ compatibility tool 3802 generates human-readable DPC++3804, which can be DPC++ code, such as generated by the DPC++ compatibility tool 3802, which cannot be compiled by the DPC++ compiler and requires additional pipelines to verify the code portion that is not correctly migrated, and may involve manual intervention, such as intervention by developers. In at least one embodiment, DPC++ compatibility tool 3802 provides hints or tools embedded in the code to help developers manually migrate additional code that cannot be automatically migrated. In at least one embodiment, migration is a one-time activity for source files, projects, or applications.

[0344] In at least one embodiment, the DPC++ compatibility tool 3802 is able to successfully migrate all portions of the CUDA code to DPC++, and there may simply be an optional step for manually verifying and tuning the performance of the generated DPC++ source code. In at least one embodiment, the DPC++ compatibility tool 3802 directly generates DPC++ source code 3808 that is compiled by the DPC++ compiler, without requiring or utilizing manual intervention to modify the DPC++ code generated by the DPC++ compatibility tool 3802. In at least one embodiment, the DPC++ compatibility tool generates compilable DPC++ code that developers can selectively tune based on performance, readability, maintainability, and other various considerations, or any combination thereof.

[0345] In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files at least in part using DPC++ compatibility tool 3802. In at least one embodiment, the CUDA source code includes one or more header files, which may include CUDA header files. In at least one embodiment, the CUDA source file includes a header file that can be used to print text.<cuda.h> Header files and<stdio.h> Header file. In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as or related to:

[0346]

[0347]

[0348] In at least one embodiment, and in conjunction with the CUDA source files presented above, the DPC++ compatibility tool 3802 parses the CUDA source code and replaces the header files with the appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is the concept of a thread ID, and accordingly, in DPC++ or SYCL, there is a local identifier for each element.

[0349] In at least one embodiment, and in relation to the CUDA source file presented above, there are two vectors A and B that are initialized and the vector addition result is placed into vector C as part of VectorAddKernel(). In at least one embodiment, as part of migrating CUDA code to DPC++ code, DPC++ compatibility tool 3802 converts the CUDA thread ID used to index work elements to SYCL standard addressing of work elements via local IDs. In at least one embodiment, the DPC++ code generated by DPC++ compatibility tool 3802 can be optimized - for example, by reducing the dimensionality of nd_item, thereby increasing memory and / or processor utilization.

[0350] In at least one embodiment and in conjunction with the CUDA source files presented above, memory allocations are migrated. In at least one embodiment, cudaMalloc() is migrated to a unified shared memory SYCL call malloc_device() to which the device and context are passed, relying on SYCL concepts such as platforms, devices, contexts, and queues. In at least one embodiment, a SYCL platform can have multiple devices (e.g., host and GPU devices); a device can have multiple queues to which jobs can be submitted; each device can have a context; and a context can have multiple devices and manage shared memory objects.

[0351] In at least one embodiment and in conjunction with the CUDA source file presented above, the main() function invokes or calls VectorAddKernel() to add two vectors A and B and store the result in vector C. In at least one embodiment, the CUDA code that calls VectorAddKernel() is replaced by DPC++ code to submit the kernel to the command queue for execution. In at least one embodiment, the command group handler cgh passes data, synchronization, and computation submitted to the queue, and parallel_for is called for multiple global elements and multiple work items in the work group that calls VectorAddKernel().

[0352] In at least one embodiment and in conjunction with the CUDA source files presented above, CUDA calls to copy device memory and then free memory of vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating point variables) is migrated as is without modification by the DPC++ compatibility tool 3802. In at least one embodiment, the DPC++ compatibility tool 3802 modifies the CUDA API for memory setup and / or host calls to execute a kernel on an accelerated device. In at least one embodiment and in conjunction with the CUDA source files presented above, a corresponding human-readable DPC++ 3804 (e.g., compilable) is written as or in relation to:

[0353]

[0354]

[0355] In at least one embodiment, human-readable DPC++ 3804 refers to the output generated by the DPC++ compatibility tool 3802 and can be optimized in one way or another. In at least one embodiment, the human-readable DPC++ 3804 generated by the DPC++ compatibility tool 3802 can be manually edited by the developer after migration to make it easier to maintain, performance, or other considerations. In at least one embodiment, the DPC++ code generated by the DPC++ compatibility tool 3802 (e.g., the disclosed DPC++) can be optimized by removing repeated calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a 3-dimensional nd_range, which can be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, the developer can manually edit the DPC++ code generated by the DPC++ compatibility tool 3802 to replace the use of unified shared memory with accessors. In at least one embodiment, the DPC++ compatibility tool 3802 has an option to change how it migrates CUDA code to DPC++ code. In at least one embodiment, DPC++ compatibility tool 3802 is verbose because it uses generic templates to migrate CUDA code to DPC++ code, which is applicable to a large number of cases.

[0356] In at least one embodiment, the migration workflow from CUDA to DPC++ includes the following steps: preparing for migration using an intercept-build script; performing migration of a CUDA project to DPC++ using the DPC++ compatibility tool 3802; manually reviewing and editing the migrated source files to ensure their completeness and correctness; and compiling the final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of the DPC++ source code may be required in one or more scenarios, including but not limited to: the migrated API does not return an error code (CUDA code can return an error code, which can then be used by the application, but SYCL uses exceptions to report errors, so the error code is not used to reveal the error); DPC++ does not support CUDA computing capability related logic; statements cannot be deleted. In at least one embodiment, scenarios where DPC++ code requires manual intervention may include but are not limited to: error code logic is replaced with (*,0) code or commented out; equivalent DPC++ API is not available; CUDA computing capability related logic; hardware related API (clock()); missing feature unsupported API; execution time measurement logic; handling built-in vector type conflicts; migration of cuBLAS API; and more.

[0357] In at least one embodiment, one or more of the techniques described herein utilize an API programming model. In at least one embodiment, the oneAPI programming model refers to a programming model for interacting with different computing accelerator architectures. In at least one embodiment, oneAPI refers to an application programming interface (API) designed to interact with various computing accelerator architectures. In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language refers to a high-level language for data parallel programming productivity. In at least one embodiment, the DPC++ programming language is based at least in part on the C and / or C++ programming languages. In at least one embodiment, the oneAPI programming model is a programming model such as those developed by Intel Corporation of Santa Clara, California.

[0358] In at least one embodiment, oneAPI and / or oneAPI programming model are used to interact with various accelerators, GPUs, processors, and / or variants thereof, architectures. In at least one embodiment, oneAPI includes a set of libraries that implement various functions. In at least one embodiment, oneAPI includes at least oneAPIDPC++ library, oneAPI math kernel library, oneAPI data analysis library, oneAPI deep neural network library, oneAPI collective communication library, oneAPI thread building block library, oneAPI video processing library and / or variants thereof.

[0359] In at least one embodiment, the oneAPIDPC++ library (also known as oneDPL) is a library that implements algorithms and functions to accelerate DPC++ kernel programming. In at least one embodiment, oneDPL implements one or more Standard Template Library (STL) functions. In at least one embodiment, oneDPL implements one or more parallel STL functions. In at least one embodiment, oneDPL provides a set of library classes and functions, such as parallel algorithms, iterators, function object classes, range-based APIs, and / or variants thereof. In at least one embodiment, oneDPL implements one or more classes and / or functions of the C++ standard library. In at least one embodiment, oneDPL implements one or more random number generator functions.

[0360] In at least one embodiment, the oneAPI Math Kernel Library (also known as oneMKL) is a library that implements various optimization and parallelization routines for various mathematical functions and / or operations. In at least one embodiment, oneMKL implements one or more Basic Linear Algebra Subprograms (BLAS) and / or Linear Algebra Packaging (LAPACK) dense linear algebra routines. In at least one embodiment, oneMKL implements one or more sparse BLAS linear algebra routines. In at least one embodiment, oneMKL implements one or more random number generators (RNGs). In at least one embodiment, oneMKL implements one or more vector math (VM) routines for performing mathematical operations on vectors. In at least one embodiment, oneMKL implements one or more Fast Fourier Transform (FFT) functions.

[0361] In at least one embodiment, the oneAPI Data Analysis Library (also known as oneDAL) is a library that implements various data analysis applications and distributed computing. In at least one embodiment, oneDAL implements various algorithms for preprocessing, transformation, analysis, modeling, verification, and decision-making for data analysis in batch, online, and distributed processing modes. In at least one embodiment, oneDAL implements various C++ and / or Java APIs and various connectors to one or more data sources. In at least one embodiment, oneDAL implements DPC++API extensions to traditional C++ interfaces and enables GPUs to be used for various algorithms.

[0362] In at least one embodiment, the oneAPI deep neural network library (also referred to as oneDNN) is a library that implements various deep learning functions. In at least one embodiment, oneDNN implements various neural network, machine learning and deep learning functions, algorithms and / or variations thereof.

[0363] In at least one embodiment, the oneAPI Collective Communications Library (also referred to as oneCCL) is a library that implements various applications of deep learning and machine learning workloads. In at least one embodiment, oneCCL is built on lower-level communication middleware such as the Message Passing Interface (MPI) and libfabrics. In at least one embodiment, oneCCL enables a set of deep learning specific optimizations such as prioritization, persistent operations, out-of-order execution, and / or variations thereof. In at least one embodiment, oneCCL implements various CPU and GPU functions.

[0364] In at least one embodiment, the oneAPI thread building block library (also referred to as oneTBB) is a library that implements various parallelization processes for various applications. In at least one embodiment, oneTBB is used for task-based shared parallel programming on the host. In at least one embodiment, oneTBB implements general parallel algorithms. In at least one embodiment, oneTBB implements concurrent containers. In at least one embodiment, oneTBB implements a scalable memory allocator. In at least one embodiment, oneTBB implements a work-stealing task scheduler. In at least one embodiment, oneTBB implements low-level synchronization primitives. In at least one embodiment, oneTBB is compiler-independent and can be used on various processors, such as GPUs, PPUs, CPUs and / or variants thereof.

[0365] In at least one embodiment, the oneAPI Video Processing Library (also known as oneVPL) is a library for accelerating video processing in one or more applications. In at least one embodiment, oneVPL implements various video decoding, encoding, and processing functions. In at least one embodiment, oneVPL implements various functions for media pipelines on CPUs, GPUs, and other accelerators. In at least one embodiment, oneVPL implements device discovery and selection for media-centric and video analytics workloads. In at least one embodiment, oneVPL implements API primitives for zero-copy buffer sharing.

[0366] In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language is a programming language that includes, but is not limited to, a functionally similar version of the CUDA mechanisms that define device code and distinguish between device code and host code. In at least one embodiment, the DPC++ programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, one or more CUDA programming model operations are performed using the oneAPI programming model using the DPC++ programming language.

[0367] It should be noted that although the example embodiments described herein may involve the CUDA programming model, the techniques described herein may be used with any suitable programming model, such as HIP, oneAPI (e.g., using oneAPI-based programming to perform or implement the methods disclosed herein), and / or variations thereof.

[0368] In at least one embodiment, one or more components of the system and / or processor disclosed above may communicate with one or more CPUs, ASICs, GPUs, FPGAs, or other hardware, circuits, or integrated circuit components, including, for example, an amplifier or upsampler for upscaling an image, an image mixer or image mixer component for fusing, mixing, or adding images together, a sampler for sampling an image (e.g., as part of a DSP), a neural network circuit configured to perform an upscaling of an image (e.g., from a low-resolution image to a high-resolution image), or other hardware for modifying or generating an image, frame, or video to adjust its resolution, size, or pixels; one or more components of the system and / or processor disclosed above may use the components described in the present disclosure to perform methods, operations, or instructions for generating or modifying an image.

[0369] At least one embodiment of the present disclosure may be described in terms of the following:

[0370] 1. A processor comprising: one or more circuits for controlling utilization of a combination of processing cores based at least in part on historical thermal characteristics of the combination of processing cores.

[0371] 2. The processor of clause 1, wherein the historical thermal characteristics are indicative of processor core utilization patterns.

[0372] 3. A processor as described in clause 1 or 2, wherein the one or more circuits are used to load the historical thermal characteristics from a configuration file.

[0373] 4. The processor of any of clauses 1-3, wherein a central processing unit ("CPU") comprises a combination of said processing cores.

[0374] 5. The processor of any of clauses 1-4, wherein the combination of processor cores is shielded based at least in part on the historical thermal characteristics of the combination of processing cores.

[0375] 6. A processor as described in any of clauses 1-5, wherein the one or more circuits are used to measure the thermal characteristic based at least in part on an average temperature measured by thermal sensors located at multiple locations on a chip including the processing core.

[0376] 7. A processor as described in any of clauses 1-6, wherein the processor core utilization pattern is related to a machine learning workload.

[0377] 8. A system comprising: one or more circuits for controlling utilization of a combination of processing cores based at least in part on historical thermal characteristics of the combination of processing cores.

[0378] 9. The system of clause 8, wherein the historical thermal characteristics indicate a processor core utilization pattern.

[0379] 10. The system of clause 8 or 9, wherein the one or more circuits are configured to load the historical thermal characteristics from a configuration file.

[0380] 11. The system of any of clauses 8-10, wherein a processor chip comprises a combination of the processing cores.

[0381] 12. The system of any of clauses 8-11, wherein the combination of processor cores is shielded based at least in part on the historical thermal characteristics of the combination of processing cores.

[0382] 13. The system of any of clauses 8-12, wherein the one or more circuits are configured to measure the thermal characteristic based at least in part on an average temperature obtained by thermal sensors located at a plurality of locations on a chip including the processing core.

[0383] 14. A system as described in any of clauses 8-13, wherein the processor core utilization pattern is related to a machine learning workload.

[0384] 15. A machine-readable medium having stored thereon a set of instructions that, when executed by one or more processors, cause the one or more processors to at least control utilization of a combination of processing cores based at least in part on historical thermal characteristics of the combination of processing cores.

[0385] 16. The machine-readable medium of clause 15, wherein the historical thermal characteristics are indicative of a processor core utilization pattern.

[0386] 17. The machine-readable medium of clause 15 or 16, comprising further instructions that, when executed by one or more processors, cause the one or more processors to load the historical thermal characteristics from a configuration file.

[0387] 18. The machine-readable medium of any of clauses 15-17, wherein a multi-core central processing unit ("CPU") comprises a combination of the processing cores.

[0388] 19. The machine-readable medium of any of clauses 15-18, wherein the combination of processor cores is shielded based at least in part on the historical thermal characteristics of the combination of processing cores.

[0389] 20. The machine-readable medium of any of clauses 15-19, comprising further instructions that, when executed by one or more processors, cause the one or more circuits to cause one or more shielded processor cores to enter a low power state.

[0390] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described in detail above. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, it is intended to cover all modifications, alternative constructions, and equivalents that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0391] Unless otherwise noted or clearly contradictory to the context, in the context of describing the disclosed embodiments (particularly in the context of the appended claims), the use of the terms "one" and "an" and "the" and similar references should be interpreted as covering the singular and plural, rather than as definitions of terms. Unless otherwise noted, the terms "include", "have", "include" and "contain" should be interpreted as open terms (meaning "including but not limited to") unless otherwise noted. The term "connected" (which refers to a physical connection when unmodified) should be interpreted as partially or completely included, attached to or connected together, even if there are some interventions. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, respectively, and each individual value is incorporated into the specification as if it were individually described herein. Unless otherwise noted or contradictory to the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set including one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0392] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B and C" are understood in context to be generally used to refer to an item, clause, or the like that may be A or B or C, or any non-empty subset of the set A and B and C. For example, in the illustrative example of a set having three members, the conjunction phrases "at least one of A, B, and C" and "at least one of A, B and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunction language is not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. In addition, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to a plural state (e.g., "plurality of items" means a plurality of items). The number of items in a plurality of items is at least two, but may be more if expressly indicated or indicated by context. Further, the phrase "based on" means "based at least in part on" rather than "based solely on" unless otherwise specified or clear from context.

[0393] Unless otherwise indicated herein or clearly contradictory to the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are jointly executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions), but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) on which executable instructions are stored, which, when executed by one or more processors of a computer system (e.g., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes multiple non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the multiple non-transitory computer-readable storage media lack all the code, but multiple non-transitory computer-readable storage media store all the code together. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors, for example, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0394] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the implementation of the operations. In addition, a computer system that implements at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system that includes multiple devices that operate in different ways, so that the distributed computer system performs the operations described herein, and so that a single device does not perform all operations.

[0395] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating that any non-claimed element is essential to practicing the disclosure.

[0396] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0397] In the specification and claims, the terms "coupled" and "connected," as well as their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. On the contrary, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0398] Unless explicitly stated otherwise, it is to be understood that throughout the specification, terms such as “processing”, “computing”, “calculating”, “determining” and the like refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electronic) in registers and / or memories of the computing system into other data similarly represented as physical quantities in the memories, registers or other such information storage, transmission or display devices of the computing system.

[0399] In a similar manner, the term "processor" may refer to any device or part of a memory that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Similarly, each process may refer to multiple processes to execute instructions sequentially or in parallel, continuously or intermittently. The terms "system" and "method" may be used interchangeably herein, as long as a system may embody one or more methods, and a method may be considered a system.

[0400] In at least one embodiment, the arithmetic logic unit is a group of combinational logic circuits that use one or more inputs to produce a result. In at least one embodiment, the processor uses the arithmetic logic unit to implement mathematical operations, such as addition, subtraction, or multiplication. In at least one embodiment, the arithmetic logic unit is used to implement logical operations, such as logical AND / OR or XOR. In at least one embodiment, the arithmetic logic unit is stateless and is made of physical switch components (such as semiconductor transistors) arranged to form logic gates. In at least one embodiment, the arithmetic logic unit can be operated internally as a stateful logic circuit with an associated clock. In at least one embodiment, the arithmetic logic unit can be constructed as an asynchronous logic circuit with an internal state that is not maintained in an associated register group. In at least one embodiment, the arithmetic logic unit is used by the processor to combine operands stored in one or more registers of the processor and generate outputs that can be stored in another register or memory location by the processor.

[0401] In at least one embodiment, as a result of processing instructions retrieved by the processor, the processor presents one or more inputs or operands to the arithmetic logic unit, causing the arithmetic logic unit to produce a result based at least in part on the instruction code provided to the input of the arithmetic logic unit. In at least one embodiment, the instruction code provided by the processor to the ALU is based at least in part on the instructions executed by the processor. In at least one embodiment, the combinational logic in the ALU processes the inputs and produces an output, which is placed on a bus within the processor. In at least one embodiment, the processor selects a destination register, memory location, output device, or output storage location on an output bus so that the processor is clocked so that the result produced by the ALU is sent to the desired location.

[0402] In this document, reference may be made to obtaining, acquiring, receiving or inputting analog or digital data into a subsystem, a computer system or a computer-implemented machine. The process of obtaining, acquiring, receiving or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving data as a parameter of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending or presenting analog or digital data can be accomplished by transmitting data as an input or output parameter of a function call, an application programming interface or an interprocess communication mechanism.

[0403] Although the above discussion sets forth example implementations of the described techniques, other architectures may be used to implement the described functionality and are intended to fall within the scope of the present disclosure. In addition, although specific responsibilities are defined above for discussion purposes, various functions and responsibilities may be allocated and divided in different ways, depending on the circumstances.

[0404] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

1. A processor, comprising: One or more circuits for controlling utilization of a combination of processing cores based at least in part on historical thermal characteristics of the combination of processing cores.

2. The processor according to claim 1, wherein: The historical thermal characteristics are indicative of processor core utilization patterns.

3. The processor according to claim 1, wherein: The one or more circuits are configured to load the historical thermal characteristics from a configuration file.

4. The processor according to claim 1, wherein: The central processing unit CPU comprises a combination of said processing cores.

5. The processor according to claim 1, wherein: The combination of processor cores is shielded based at least in part on the historical thermal characteristics of the combination of processing cores.

6. The processor of claim 1, wherein: The one or more circuits are configured to measure the thermal characteristic based at least in part on an average temperature measured by thermal sensors at a plurality of locations on a chip including the processing core.

7. The processor according to claim 1, wherein: The processor core utilization patterns are associated with machine learning workloads.

8. A system comprising: One or more circuits for controlling utilization of a combination of processing cores based at least in part on historical thermal characteristics of the combination of processing cores.

9. The system according to claim 8, wherein: The historical thermal characteristics are indicative of processor core utilization patterns.

10. The system according to claim 8, wherein: The one or more circuits are configured to load the historical thermal characteristics from a configuration file.

11. The system according to claim 8, wherein: A processor chip includes a combination of the processing cores.

12. The system according to claim 8, wherein: The combination of processor cores is shielded based at least in part on the historical thermal characteristics of the combination of processing cores.

13. The system according to claim 8, wherein: The one or more circuits are configured to measure the thermal characteristic based at least in part on an average temperature obtained by thermal sensors located at a plurality of locations on a chip including the processing core.

14. The system according to claim 8, wherein: The processor core utilization patterns are associated with machine learning workloads.

15. A machine-readable medium having stored thereon a set of instructions that, when executed by one or more processors, cause the one or more processors to at least control utilization of a combination of processing cores based at least in part on historical thermal characteristics of the combination of processing cores.

16. The machine-readable medium of claim 15, wherein: The historical thermal characteristics are indicative of processor core utilization patterns.

17. The machine-readable medium of claim 15, comprising further instructions that, when executed by one or more processors, cause the one or more processors to load the historical thermal characteristics from a configuration file.

18. The machine-readable medium of claim 15, wherein: A multi-core central processing unit CPU comprises a combination of said processing cores.

19. The machine-readable medium of claim 15, wherein: The combination of processor cores is shielded based at least in part on the historical thermal characteristics of the combination of processing cores.

20. The machine-readable medium of claim 15, comprising further instructions that, when executed by one or more processors, cause the one or more circuits to cause one or more shielded processor cores to enter a low power state.

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