Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps: forming dummy gates on an NMOS (N-channel Metal Oxide Semiconductor) device region and a PMOS (P-channel Metal Oxide Semiconductor) device region included in a substrate; a functional layer is formed on the side wall of the pseudo gate and the substrate, and the area, outside the pseudo gate and the functional layer on the side wall of the pseudo gate, of the PMOS device area is a reserved area; forming a photoresist layer which covers the NMOS device region and is provided with an opening in the PMOS device region after the functional layer is formed; etching the functional layer by using the photoresist layer as a mask until the surface of the reserved area is exposed, and then removing the photoresist layer; forming a preparation groove in the reserved area; wherein the functional layer is formed by cyclically executing the first step and the second step, the first step comprises forming a sub-functional layer covering the pseudo gate and the substrate, and the second step comprises introducing etching gas downwards from the upper part of the substrate to etch the sub-functional layer until the part, at the top of the pseudo gate, of the sub-functional layer is etched. According to the invention, the pseudo gates of the NMOS device and the PMOS device are equal in height with low cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the process of manufacturing semiconductor structures, in order to improve the driving current of PMOS (i.e. P-type metal-oxide-semiconductor) devices, germanium silicon epitaxial technology is widely used. In the germanium silicon epitaxial technology, after the NMOS (i.e. N-type metal-oxide-semiconductor) device is covered by a photoresist layer, only a germanium silicon trench is formed in the substrate of the PMOS device. In the existing technology for forming germanium silicon trenches, the pseudo gate of the PMOS device will be greatly damaged, resulting in the pseudo gates of the NMOS device and the PMOS device being different in height, so that the chemical mechanical polishing (CMP) of the interlayer dielectric (ILD) formed subsequently is affected, and the higher pseudo gate of the NMOS device is also prone to cause gaps in the interlayer dielectric layer formed subsequently. Summary of the invention

[0003] In view of the above problems, the present application provides a semiconductor structure and a method for manufacturing the same, aiming to achieve equal heights of pseudo gates of NMOS devices and PMOS devices at a relatively low cost.

[0004] According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor structure, comprising:

[0005] Providing a substrate, the substrate comprising an NMOS device region and a PMOS device region;

[0006] forming dummy gates on the NMOS device region and the PMOS device region;

[0007] Forming a functional layer on the sidewall of the dummy gate and on the substrate, wherein the area of ​​the PMOS device region other than under the dummy gate and the functional layer on the sidewall of the dummy gate is a reserved area;

[0008] After the functional layer is formed, a photoresist layer is formed covering the NMOS device region and having an opening in the PMOS device region;

[0009] Using the photoresist layer as a mask to etch the functional layer until the surface of the reserved area is exposed, and then removing the photoresist layer;

[0010] forming a preliminary groove in the reserved area;

[0011] Wherein, a functional layer is formed on the side wall of the dummy gate and the substrate by cyclically executing the first step and the second step, wherein the first step includes: forming a sub-functional layer covering the dummy gate and the substrate, and the second step includes: passing an etching gas from above the substrate downward to etch the sub-functional layer until the sub-functional layer on the top of the dummy gate is etched away.

[0012] Optionally, the first step forms the sub-functional layer by using any one of an atomic layer deposition process, a chemical vapor deposition process and a physical vapor deposition process.

[0013] Optionally, the sub-functional layer has a thickness of 20 angstroms to 50 angstroms.

[0014] Optionally, in the second step, the flow rate of the etching gas is controlled so that the time taken to etch away the portion of the sub-functional layer on the top of the dummy gate is 4s-8s.

[0015] Optionally, the sub-functional layer is made of silicon nitride, the dummy gate includes a top protective layer located on the top and the top protective layer is made of silicon oxide, and the etching gas used in the second step is a plasma gas mixed with carbon tetrafluoride and fluoromethane.

[0016] Optionally, the material used for the functional layer is silicon nitride, the pseudo gate includes a top protective layer located on the top and the material used for the top protective layer is silicon oxide, and the functional layer is etched using the photoresist layer as a mask, including: dry etching the functional layer using a plasma gas mixed with carbon tetrafluoride and fluoromethane as an etching gas.

[0017] Optionally, the manufacturing method further comprises:

[0018] Before forming the functional layer, a surface protection layer is formed on the dummy gate and the substrate, and the functional layer formed thereafter covers the surface protection layer on the sidewall of the dummy gate and the substrate;

[0019] After etching the functional layer using the photoresist layer as a mask, etching the surface protection layer using the photoresist layer as a mask, wherein the functional layer is etched until a portion of the surface protection layer on the reserved area is exposed, and the surface protection layer is etched until a surface of the reserved area is exposed.

[0020] Optionally, the thickness of the surface protection layer is smaller than the thickness of the functional layer.

[0021] Optionally, the manufacturing method further comprises: widening the preliminary trench by etching to form a sigma trench for growing silicon germanium.

[0022] According to a second aspect of the present invention, a semiconductor structure is provided. The semiconductor structure is manufactured by any one of the manufacturing methods described in the first aspect.

[0023] The unexpected technical effects of this application are:

[0024] According to the manufacturing method of the semiconductor structure provided by the embodiment of the present application, after forming a functional layer on the side wall of the dummy gate and on the substrate, a photoresist layer covering the NMOS device area and opening on the PMOS device area is formed, and then the functional layer is etched using the photoresist layer as a mask until the surface of the reserved area in the PMOS device area is exposed. In this process, there is no functional layer that can be etched on the top of the dummy gate in the PMOS device area, so that there is basically no etching phenomenon on the top of the dummy gate in the PMOS device area. After that, the photoresist layer is removed to form a preliminary groove in the reserved area of ​​the PMOS device area. The dummy gate on the NMOS device area and the dummy gate on the PMOS device area will be etched in the same way during the formation of the preliminary groove because there is no functional layer on the top of each of them, so that the dummy gate on the NMOS device area and the dummy gate on the PMOS device area can basically achieve the same height. Among them, a functional layer is formed on the side wall of the dummy gate and on the substrate by cyclically executing the first step and the second step, the first step includes: forming a sub-functional layer covering the dummy gate and the substrate, and the second step includes: introducing an etching gas from above the substrate downward to etch the sub-functional layer until the sub-functional layer on the top of the dummy gate is etched away, and the sub-functional layer on the side wall of the dummy gate and the substrate has a lower etching rate than the sub-functional layer on the top of the dummy gate because the contact angle with the etching gas is smaller than that of the sub-functional layer on the top of the dummy gate. Therefore, when the sub-functional layer on the top of the dummy gate is etched away, the sub-functional layer on the side wall of the dummy gate and the substrate is partially retained. The process forms a patterned functional layer without using a high-cost mask, thereby basically achieving the same height of the pseudo gates of NMOS devices and PMOS devices at a relatively low cost.

[0025] Furthermore, in the first step, any one of the atomic layer deposition process, chemical vapor deposition process and physical vapor deposition process is used to form a sub-functional layer, thereby ensuring that the portion of the formed sub-functional layer on the pseudo-gate side wall and the substrate has the same thickness as the portion on the pseudo-gate top. In this way, after the second step is executed, the difference in contact angles between different portions of the sub-functional layer and the etching gas can be utilized to better achieve that the portion of the sub-functional layer on the pseudo-gate top is etched away while the portion of the sub-functional layer on the pseudo-gate side wall and the substrate is partially retained.

[0026] Furthermore, the thickness of the sub-functional layer is 20 angstroms to 50 angstroms. The reason for this setting is that if the thickness of the sub-functional layer is too small, in order to form a functional layer with a preset thickness that defines the reserved area in the PMOS device area, it is necessary to cyclically execute the first step and the second step more times, thereby increasing the time consumption for forming the functional layer during the multiple alternations between the first step and the second step; conversely, if the thickness of the sub-functional layer is too large, the second step needs to be executed for a longer time and / or use a larger etching gas flow rate to etch away the portion of the sub-functional layer on the top of the dummy gate. Executing the second step for a longer time and using a larger etching gas flow rate will cause the etching gas to gather in the middle of the dummy gate, thereby affecting the etching uniformity of the portion of the sub-functional layer on the dummy gate sidewall and the substrate, and further affecting the quality of the formed functional layer.

[0027] Furthermore, in the second step, the flow rate of the etching gas is controlled so that the time taken to etch away the sub-functional layer with a thickness of 20 angstroms to 50 angstroms at the top of the pseudo gate is 4s-8s. The reason for this setting is that if the time taken to execute the second step once is too long, the time taken to form the functional layer will be increased; conversely, if the time taken to execute the second step once is too short, the flow rate of the etching gas needs to be increased for the sub-functional layer with a certain thickness. However, if the flow rate of the etching gas is too large, the etching gas will quickly pass over the top of the pseudo gate and gather in the middle of the pseudo gate, thereby reducing the etching rate of the sub-functional layer at the top of the pseudo gate. In addition, the etching gas gathered in the middle of the pseudo gate will also cause uneven etching of the sub-functional layer on the side walls of the pseudo gate and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0029] Figure 1a A cross-sectional schematic diagram showing a substrate and a dummy gate completely covered by a photoresist layer in the prior art;

[0030] Figure 1b A cross-sectional schematic diagram showing a substrate and a dummy gate after an NMOS device region is covered by a photoresist layer in the prior art;

[0031] Figure 1c A schematic cross-sectional view of a substrate and a dummy gate after the surface of a reserved area of ​​a PMOS device region is exposed in the prior art is shown;

[0032] Figure 1d A schematic cross-sectional view of a substrate and a dummy gate after a preliminary trench is etched in a PMOS device region in the prior art is shown;

[0033] Figure 1e A schematic cross-sectional view of a substrate and a dummy gate after a sigma trench is etched in a PMOS device region in the prior art is shown;

[0034] Figure 1f A cross-sectional schematic diagram of a substrate and a dummy gate after removing a photoresist layer in the prior art is shown;

[0035] Figure 1g A schematic cross-sectional view of a substrate and a dummy gate after a silicon germanium trench is formed in a PMOS device region in the prior art is shown;

[0036] Figure 1h A cross-sectional schematic diagram showing a substrate and a dummy gate after removing a functional layer in the prior art;

[0037] Figure 2a A schematic diagram showing a dummy gate on a PMOS device region in a semiconductor structure manufactured by prior art;

[0038] Figure 2b A schematic diagram showing a dummy gate on an NMOS device region in a semiconductor structure manufactured by prior art;

[0039] Figure 3a A schematic diagram showing a pseudo gate on a PMOS device region after an etching process is performed to expose the surface of a reserved region in a process of manufacturing a semiconductor structure in the prior art;

[0040] Figure 3b A schematic diagram showing a pseudo gate on a PMOS device region after an etching process is performed to form a preliminary trench in a process of manufacturing a semiconductor structure in the prior art;

[0041] Figure 4 A schematic diagram showing an intermediate dielectric layer formed by a semiconductor structure manufactured based on prior art;

[0042] Figure 5 A flow chart showing a method for manufacturing a semiconductor structure according to an embodiment of the present application;

[0043] Figure 6a A cross-sectional schematic diagram showing an exemplary substrate and a dummy gate according to an embodiment of the present application;

[0044] Figure 6b A cross-sectional schematic diagram showing an exemplary structure formed after the first step is performed for the first time according to an embodiment of the present application;

[0045] Figure 6c A cross-sectional schematic diagram showing an exemplary structure formed after the second step is performed for the first time according to an embodiment of the present application;

[0046] Figure 6d A cross-sectional schematic diagram showing an exemplary functional layer after formation according to an embodiment of the present application;

[0047] Figure 6eA cross-sectional schematic diagram showing an exemplary substrate and a dummy gate after an NMOS device region is covered by a photoresist layer according to an embodiment of the present application;

[0048] Figure 6f A schematic cross-sectional view showing a substrate and a dummy gate after the surface of a reserved area of ​​an exemplary PMOS device region is exposed according to an embodiment of the present application;

[0049] Figure 6g A cross-sectional schematic diagram of an exemplary substrate and a dummy gate after removing a photoresist layer according to an embodiment of the present application is shown;

[0050] Figure 6h A schematic cross-sectional view of a substrate and a dummy gate after etching a preliminary trench in an exemplary PMOS device region according to an embodiment of the present application is shown;

[0051] Figure 6i A schematic cross-sectional view of a substrate and a dummy gate after etching a sigma trench in an exemplary PMOS device region according to an embodiment of the present application is shown;

[0052] Figure 6j A schematic cross-sectional view of a substrate and a dummy gate after a silicon germanium trench is formed in an exemplary PMOS device region according to an embodiment of the present application is shown.

[0053] Explanation of the reference numerals: 11-substrate; 12-pseudo gate; 12a-gate conductive layer; 12b-gate insulating layer; 12c-top protective layer; 12d-side wall; 13-functional layer; 13'-sub-functional layer; 14-surface protective layer; 15-photoresist layer; 16-bottom anti-reflective coating; 17-preparatory groove; 18-sigma groove; 19-SiGe groove. DETAILED DESCRIPTION

[0054] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0055] This application may be presented in a variety of forms, some examples of which are described below.

[0056] In the germanium-silicon epitaxial technology, after the NMOS device is covered by a photoresist layer, only a germanium-silicon trench is formed in the substrate of the PMOS device, thereby increasing the compressive stress of the PMOS device and improving the driving current of the PMOS device. Figure 1a to Figure 1h The process of forming a germanium silicon trench in the prior art is shown. Figure 1a to Figure 1h The prior art for forming a silicon germanium trench is introduced in detail.

[0057] like Figure 1aAs shown, the substrate 11 includes an NMOS device region and a PMOS device region, dummy gates 12 are formed on the NMOS device region and the PMOS device region, respectively, a functional layer 13 is formed on the substrate 11 and the dummy gate 12, and the area of ​​the PMOS device region outside the dummy gate 12 and the functional layer 13 on the sidewall of the dummy gate 12 is a reserved area. Figure 1a The reserved area is framed by a dotted frame. In some examples, a surface protection layer 14 is first formed on the substrate 11 and the dummy gate 12, and then a functional layer 13 is formed, and the later formed functional layer 13 covers the first formed surface protection layer 14. The material used for the functional layer 13 can be silicon nitride, and its function is to control the position of the reserved area in the PMOS device area by adjusting its own thickness. The material used for the surface protection layer 14 can be silicon oxide (SiO2), and its function is to strengthen the protection of the dummy gate 12.

[0058] The pseudo gate 12 includes a stacked structure formed by stacking a gate conductor layer 12a, a gate insulating layer 12b and a top protective layer 12c, and a sidewall 12d arranged on the sidewall of the stacked structure. The top protective layer 12c and the sidewall 12d are combined to protect the gate conductor layer 12a and the gate insulating layer 12b. In this way, combined with the protective effect of the surface protective layer 14, it is ensured that the gate conductor layer 12a and the gate insulating layer 12b will not be damaged during the formation of the germanium silicon trench. The material used for the gate conductor layer 12a can be polysilicon, the material used for the gate insulating layer 12b can be silicon nitride, the material used for the top protective layer 12c can be silicon oxide, and the material used for the sidewall 12d can be silicon nitride.

[0059] In the process of forming the SiGe trench, firstly form Figure 1b The photoresist layer 15 shown only covers the functional layer 13 on the NMOS device region. Figure 1a As shown in the figure, a photoresist layer 15 covering all the functional layers 13 is first formed, and then the photoresist layer 15 on the PMOS device area is etched away by exposure and development, thereby forming a photoresist layer 15 covering the functional layer 13 on the NMOS device area and opening on the PMOS device area. Figure 1a As shown, a bottom anti-reflection coating 16 covering the entire functional layer 13 is first formed, and the photoresist layer 15 formed later covers the bottom anti-reflection coating 16 formed earlier. Therefore, in order to achieve that only the functional layer 13 on the NMOS device area is covered, it is necessary to expose and develop the photoresist layer 15 in combination with etching the bottom anti-reflection coating 16.

[0060] Next, use Figure 1bThe photoresist layer 15 shown and the bottom anti-reflective coating 16 present in some examples are used to etch the functional layer 13 and the surface protection layer 14. During the etching process, since only the functional layer 13 on the NMOS device area is covered, the functional layer 13 and the surface protection layer 14 on the NMOS device area are not etched, while the functional layer 13 and the surface protection layer 14 on the PMOS device area will be etched. Specifically, the functional layer 13 is first etched until the portion of the surface protection layer 14 on the reserved area in the PMOS device area is exposed, and then the surface protection layer 14 is etched until the surface of the reserved area in the PMOS device area is exposed. It should be understood that in the first etching process of the functional layer 13, the functional layer 13 on the top of the pseudo gate 12 in the PMOS device area will be etched away at the same time, and in the subsequent etching process of the surface protection layer 14, the surface protection layer 14 on the top of the pseudo gate 12 in the PMOS device area will be etched away at the same time, so as to Figure 1c The dummy gate 12 on the PMOS device region is shown to be exposed after this process.

[0061] Next, dry etching is performed by plasma gas to form a Figure 1d The prepared groove 17 shown. It should be noted that, Figure 1d Only one preliminary groove 17 is shown, and in practice, preliminary grooves 17 can be formed in the reserved areas on both sides of each dummy gate 12 in the PMOS device area. Specifically, the etching rate of the plasma gas for dry etching to silicon is greater than the etching rate to silicon nitride and silicon oxide, and because the functional layer 13 in the NMOS device area is covered by the photoresist layer 15, only the functional layer 13 made of silicon nitride material, the surface protection layer 14 and the top protection layer 12c made of silicon oxide material, and the reserved area made of silicon material in the PMOS device area are etched during the dry etching process, and the etched portions of the functional layer 13, the surface protection layer 14 and the top protection layer 12c are less than those of the reserved area.

[0062] Afterwards, wet etching is used to widen the Figure 1d The prepared groove 17 is formed as shown in FIG. Figure 1e Sigma groove 18 shown, and as Figure 1f As shown Figure 1e The photoresist layer 15 shown is removed by an ashing process and the bottom anti-reflection coating 16 present in some examples is removed, and in the Figure 1f The sigma trench 18 shown in FIG. 1 is formed by growing silicon germanium. Figure 1g The germanium silicon trench 19 is formed, thereby completing the formation process of the germanium silicon trench 19. Figure 1h As shown Figure 1g The functional layer 13 for defining the reserved area on each dummy gate 12 is removed.

[0063] Based on the above introduction to the formation process of the SiGe trench 19, it can be seen that: Figure 1c The etching process shown in FIG. 1 is performed to expose the surface of the reserved area. Figure 1d In the etching process for forming the preliminary groove 17 shown in FIG. 1 , since there is no photoresist layer 15 on the PMOS device region, the functional layer 13 on the top of the dummy gate 12 on the PMOS device region and the surface protection layer 14 in some examples will be etched away, and then the top protection layer 12c and the sidewall 12d included in the dummy gate 12 will be partially etched away, so that the dummy gate 12 on the PMOS device region is damaged. For the example where the surface protection layer 14 is present, the final formed Figure 1h In the semiconductor structure shown, there are a top protective layer 12c and a surface protective layer 14 on the top of the dummy gate 12 in the NMOS device region, so that the dummy gate 12 on the PMOS device region is damaged, resulting in the tops of the dummy gates 12 in the PMOS device region and the NMOS device region having different heights of silicon oxide; for the example in which there is no surface protective layer 14, in the finally formed semiconductor structure, there is a complete top protective layer 12c on the top of the dummy gate 12 in the NMOS device region, so that the dummy gate 12 on the PMOS device region is damaged, resulting in a height difference between the dummy gates 12 in the PMOS device region and the NMOS device region.

[0064] Figure 2a and Figure 2b Schematic diagrams of a dummy gate on a PMOS device region and a schematic diagram of a dummy gate on an NMOS device region in a semiconductor structure in an example where a surface protection layer 14 is present and manufactured using the above technology are respectively shown, wherein: Figure 2a The silicon oxide on the top of the pseudo gate in the PMOS device area is 10.2nm high. Figure 2b The figure shows that the silicon oxide on the top of the dummy gate in the NMOS device region is 32.1 nm high. It can be seen that the silicon oxide on the top of the dummy gate in the PMOS device region and the NMOS device region has different heights.

[0065] Figure 3a and Figure 3b Schematic diagrams of a dummy gate on a PMOS device region at different stages in another example of a surface protection layer 14 manufactured using the above technology are shown respectively, wherein: Figure 3a FIG. 1 is a schematic diagram of a dummy gate on a PMOS device region after an etching process is performed to expose the surface of a reserved region. Figure 3a The silicon oxide on top of the pseudo gate in the middle PMOS device area is 32.6nm high; Figure 3b FIG. 1 is a schematic diagram of a dummy gate on a PMOS device region after an etching process is performed to form a preliminary trench. Figure 3bThe silicon oxide on the top of the dummy gate in the PMOS device region is 13.4 nm high. It can be seen that the silicon oxide on the top of the dummy gate in the PMOS device region will be significantly reduced in height during the etching process for forming the preliminary trench.

[0066] It should be noted that Figure 1h In the subsequent steps of the semiconductor structure shown, doping ions are implanted into the substrate 11 to form source and drain regions on both sides of the dummy gate 12. After that, an interlayer dielectric layer is formed on the source and drain regions and the top of the dummy gate 12, and the dummy gate 12 is removed from the interlayer dielectric layer and replaced with a high dielectric metal gate structure. Therefore, after the interlayer dielectric layer is formed, it is ground until the surface is flush and the gate insulation layer 12b of the dummy gate 12 is exposed. In the example where the surface protection layer 14 exists, the top of the dummy gate 12 in the PMOS device area and the NMOS device area has different heights of silicon oxide, and in the example where the surface protection layer 14 does not exist, the dummy gate 12 in the PMOS device area and the NMOS device area has a height difference, which will cause the subsequent chemical mechanical polishing load (loading) of the interlayer dielectric layer. In addition, in the example where the surface protection layer 14 exists, the silicon oxide on the top of the dummy gate 12 in the NMOS device area is higher, and in the example where the surface protection layer 14 does not exist, the dummy gate 12 in the NMOS device area is higher, which is easy to cause gaps in the interlayer dielectric layer. Figure 4 As shown in the example where the surface protection layer 14 exists, the silicon oxide on the top of the dummy gate 12 in the NMOS device region is higher, resulting in a gap in the formed interlayer dielectric layer as framed by a white dotted line.

[0067] In view of the above reasons, an embodiment of the present application provides a method for manufacturing a semiconductor structure. Figure 5 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present application. Figure 5 As shown, the manufacturing method includes:

[0068] Step S110, providing a substrate, the substrate including an NMOS device region and a PMOS device region;

[0069] Step S120, forming dummy gates on the NMOS device region and the PMOS device region;

[0070] Step S130, forming a functional layer on the sidewall of the dummy gate and on the substrate by cyclically executing the first step and the second step, the area of ​​the PMOS device region outside the dummy gate and the functional layer on the sidewall of the dummy gate is a reserved area, wherein the first step includes: forming a sub-functional layer covering the dummy gate and the substrate, and the second step includes: introducing an etching gas from above the substrate downward to etch the sub-functional layer until a portion of the sub-functional layer on the top of the dummy gate is etched away;

[0071] Step S140, after the functional layer is formed, a photoresist layer is formed covering the NMOS device region and having an opening in the PMOS device region;

[0072] Step S150, using the photoresist layer as a mask to etch the functional layer until the surface of the reserved area is exposed, and then removing the photoresist layer;

[0073] Step S160 , forming a preliminary trench in the reserved area.

[0074] It should be noted that after forming the functional layer in step S130, a reserved area is defined in the PMOS device area, and the etching of the functional layer in step S150 until the surface of the reserved area is exposed is for directly etching the reserved area in step S160 to form a groove for growing silicon germanium in the reserved area. The etching of the reserved area in step S160 adopts high-selectivity etching, that is, the etching rate of the reserved area is greater than that of the functional layer and the dummy gate, so that the functional layer and the dummy gate will be etched in the process of forming the preliminary groove, but the etched portion is less than that of the substrate.

[0075] It should be understood that the dummy gate is less damaged when the dummy gate is etched away during the preparation of the trench, thereby not affecting the performance of the high dielectric metal gate structure that replaces the dummy gate. Figure 3a and Figure 3b The one shown still exists.

[0076] In the embodiment of the present application, since the functional layer formed by cyclically executing the first step and the second step is only located on the sidewall of the dummy gate and on the substrate, the etching of the functional layer using the photoresist layer as a mask will basically not cause etching on the top of the dummy gate in the PMOS device area, so that when the photoresist layer is removed, there is basically no difference between the dummy gates in the NMOS device area and the PMOS device area, and then in the process of forming the preliminary groove after the photoresist layer is removed, since the dummy gate in the NMOS device area and the dummy gate in the PMOS device area do not have a functional layer on the top, the dummy gate in the NMOS device area and the dummy gate in the PMOS device area will be etched in the same way, so that the dummy gate in the NMOS device area and the dummy gate in the PMOS device area can basically achieve the same height. Among them, in the process of cyclically executing the first step and the second step to form the functional layer, it is not necessary to use a high-cost mask, so the dummy gates of the NMOS device and the PMOS device are basically equal in height at a relatively low cost.

[0077] Figures 6a to 6j is a schematic diagram of each step of a method for manufacturing a semiconductor structure provided in an embodiment of the present application. Figure 5 as well as Figures 6a to 6j The manufacturing method of the semiconductor structure provided in the embodiment of the present application is described in detail.

[0078] The substrate provided in step S110 and the dummy gate formed in step S120 may be as follows: Figure 6a See Figure 6aThe substrate 11 includes an NMOS device region and a PMOS device region, and the dummy gate 12 includes a stacked structure formed by stacking a gate conductor layer 12a, a gate insulating layer 12b and a top protective layer 12c, and a sidewall 12d arranged on the sidewall of the stacked structure.

[0079] The sub-functional layer formed by performing the first step for the first time in step S130 can be as follows: Figure 6b See Figure 6b In the first step, any one of the atomic layer deposition process, chemical vapor deposition process and physical vapor deposition process can be used to form the sub-functional layer 13', so as to ensure that the sub-functional layer 13' formed on the side wall of the dummy gate 12 and the substrate 11 has the same thickness as the part on the top of the dummy gate 12. In this way, after the second step in step S130 is executed, the difference in contact angles between different parts of the sub-functional layer 13' and the etching gas can be utilized to better achieve that the part of the sub-functional layer 13' on the top of the dummy gate 12 is etched away while the part of the sub-functional layer 13' on the side wall of the dummy gate 12 and the substrate 11 is partially retained.

[0080] The thickness of the sub-functional layer 13' formed by executing the first step once should not be too small or too large. If the thickness of the sub-functional layer 13' is too small, in order to form a functional layer 13 with a preset thickness defining a reserved area in the PMOS device area, the first step and the second step need to be executed repeatedly for a relatively long time, thereby increasing the time consumption of forming the functional layer 13 during the relatively long alternation between the first step and the second step; on the contrary, if the thickness of the sub-functional layer 13' is too large, the second step needs to be executed for a relatively long time and / or a relatively large etching gas flow rate to etch away the part of the sub-functional layer 13' on the top of the pseudo gate 12. The execution of the second step for a relatively long time and the use of a relatively large etching gas flow rate will cause the etching gas to gather in the middle of the pseudo gate 12, thereby affecting the etching uniformity of the part of the sub-functional layer 13' on the sidewall of the pseudo gate 12 and the substrate 11, thereby affecting the quality of the formed functional layer 13. For this reason, in the embodiment of the present application, the first step is executed once to form a sub-functional layer 13' with a thickness of 20 angstroms to 50 angstroms.

[0081] After the second step is performed for the first time in step S130, the remaining part of the sub-functional layer 13' can be as follows: Figure 6c See Figure 6c The portions of the sub-functional layer 13' on the sidewalls of the dummy gate 12 and the substrate 11 are thinned due to the etching process in the second step, and the portion of the sub-functional layer 13' on the top of the dummy gate 12 is removed due to the etching process in the second step.

[0082] The duration of the second step being executed once should not be too short or too long. If the duration of the second step being executed once is too long, the time consumed in forming the functional layer 13 will be increased; conversely, if the duration of the second step being executed once is too short, the flow rate of the etching gas needs to be increased for the sub-functional layer 13' of a certain thickness. Since the flow rate of the etching gas is too large, the etching gas will quickly pass over the top of the pseudo gate 12 and gather in the middle of the pseudo gate 12, thereby reducing the etching rate of the sub-functional layer 13' at the top of the pseudo gate 12, and the etching gas gathered in the middle of the pseudo gate 12 will also cause uneven etching of the sub-functional layer 13' on the sidewall of the pseudo gate 12 and the substrate 11. For this reason, in the embodiment of the present application, when the first step is executed once to form a sub-functional layer 13' with a thickness of 20 angstroms to 50 angstroms, the time consumed in etching the sub-functional layer 13' at the top of the pseudo gate 12 by controlling the flow rate of the etching gas is 4s-8s.

[0083] The material of the above-mentioned sub-functional layer 13' may be silicon nitride, and the dummy gate 12 may include a top protective layer 12c located on the top as described above, and the material of the top protective layer 12c is silicon oxide, so that the sub-functional layer 13' formed in the first step and covering the dummy gate 12 and the substrate 11 can be etched in the second step using a mixed gas of carbon tetrafluoride (CF4) and fluoromethane (CH3F) as an etching gas. Since the etching rate of the mixed gas of carbon tetrafluoride and fluoromethane for silicon nitride is much greater than the etching rate for silicon oxide, when the sub-functional layer 13' on the top of the dummy gate 12 is etched away, the top protective layer 12c included in the dummy gate 12 can be substantially undamaged.

[0084] In some examples, in the first step, a sub-functional layer 13' with a thickness of 30 angstroms is formed by performing a deposition process for 4-8s; in the second step, a mixed gas of carbon tetrafluoride and fluoromethane is used as an etching gas to etch the sub-functional layer 13'. Specifically, since the contact angle between the portion of the sub-functional layer 13' at the top of the dummy gate 12 and the etching gas is larger, the portion of the sub-functional layer 13' at the top of the dummy gate 12 is more easily exposed to the etching gas, so that the portion of the sub-functional layer 13' at the top of the dummy gate 12 is etched faster; and the etching gas accounts for a smaller proportion of the space between the dummy gates 12, so that the portion of the sub-functional layer 13' on the side wall of the dummy gate 12 and the substrate 11 is etched slower, and the portion of the sub-functional layer 13' on the substrate 11 is exposed to a smaller amount of etching gas due to the short etching gas introduction time, so that the etching speed is slower. In some experiments of this example, when the sub-functional layer 13' on the top of the dummy gate 12 is partially etched away, the sub-functional layer 13' on the substrate 11 has a thickness of about 15 angstroms, and the sub-functional layer 13' on the sidewall of the dummy gate 12 has a thickness of more than 10 angstroms. When the thickness of the formed functional layer 13 on the sidewall of the dummy gate 12 needs to be 60 angstroms, the first step and the second step need to be executed 6 times in a cycle, that is, after the first step and the second step are executed once in succession, the process of executing the first step and the second step in succession is repeated until the first step and the second step are executed in succession 6 times. Figure 6d Shows multiple loop executions Figure 6b The first step shown and Figure 6c The functional layer 13 formed after the second step is shown Figure 1a The functional layer 13 shown in FIG. Figure 6d The main difference of the functional layer 13 shown is that it does not cover the top of the dummy gate 12 .

[0085] The material used for the functional layer 13 may be silicon nitride, and the dummy gate 12 may include a top protective layer 12c located at the top as described above, and the material used for the top protective layer 12c is silicon oxide. In step S150, the etching of the functional layer 13 is performed by dry etching using a plasma gas mixed with carbon tetrafluoride and fluoromethane as an etching gas. Since the etching rate of the mixed gas of carbon tetrafluoride and fluoromethane for silicon nitride is much greater than the etching rate for silicon oxide, the top protective layer 12c included in the dummy gate 12 on the PMOS device region is basically not damaged during the execution of step S150, so that the execution of step S150 basically does not cause a height difference between the dummy gate 12 on the NMOS device region and the dummy gate 12 on the PMOS device region.

[0086] Furthermore, the method for manufacturing a semiconductor structure provided in the embodiment of the present application may further include: before forming the functional layer 13 by executing step S130, Figure 6aAs shown, a surface protection layer 14 is formed on the dummy gate 12 and the substrate 11, so that the dummy gate 12 is protected by the surface protection layer 14, and the functional layer 13 formed thereafter directly covers the portion of the surface protection layer 14 on the side wall of the dummy gate 12 and the substrate 11, thereby indirectly covering the side wall of the dummy gate 12 and the substrate 11; and the surface protection layer 14 is subsequently etched using the photoresist layer as a mask after etching the functional layer 13 in step S150. It should be understood that the thickness of the surface protection layer 14 formed above should be appropriate so that there is a gap between the surface protection layers 14 on the side walls of adjacent dummy gates 12, and similarly, the thickness of the functional layer 13 formed above should be appropriate so that there is a gap between the functional layers 13 on the side walls of adjacent dummy gates 12, so that the function of the functional layer 13 in defining the reserved area is not affected. Figure 6d The reserved area defined by the functional layer 13 is framed by a dotted line.

[0087] In the example of forming the surface protection layer 14, step S140 is performed to form a Figure 6e The photoresist layer 15 shown in FIG. 1 covers the functional layer 13 on the NMOS device region and the surface protection layer 14 on the top of the dummy gate 12. In step S150, the functional layer 13 is etched using the photoresist layer 15 as a mask until the surface protection layer 14 on the reserved area is exposed. Then, the surface protection layer 14 is etched using the photoresist layer 15 as a mask. Figure 6f As shown, the reserved area is etched until the surface is exposed. In this way, the reserved area can be directly etched in step S160 to form a trench for growing silicon germanium in the reserved area. Figure 6g FIG. 1 is a schematic diagram showing the removal of the photoresist layer 15 before step S160 is performed.

[0088] It should be noted that the thickness of the surface protection layer 14 formed before the execution of step S130 is substantially uniform, so in the process of etching the surface protection layer 14 using the photoresist layer 15 as a mask, the portion of the surface protection layer 14 on the top of the pseudo gate 12 in the PMOS device area will be etched away at the same time, which will affect the filling and grinding of the subsequent interlayer dielectric layer. In this regard, since the role of the surface protection layer 14 is to protect the pseudo gate 12, the thickness of the surface protection layer 14 can be adjusted, so that the thickness of the surface protection layer 14 can be made smaller than the thickness of the functional layer 13, so that the thickness of the surface protection layer 14 is small, and the absence of the surface protection layer 14 on the top of the pseudo gate 12 in the PMOS device area and the presence of the surface protection layer 14 on the top of the pseudo gate 12 in the NMOS device area will not have a significant impact on the filling and grinding of the subsequent interlayer dielectric layer. In practice, due to reasons such as process accuracy, the removal of the photoresist layer 15 may damage the nearby functional layer 13 and even the exposed surface protection layer 14 after the functional layer 13 is damaged. The portions of the functional layer 13 and the surface protection layer 14 on the side walls of the dummy gate 12 may be damaged to a greater extent, especially because the portion of the photoresist layer 15 between the dummy gates 12 is more difficult to remove. Therefore, the thickness of the functional layer 13 is greater than that of the surface protection layer 14, which can also make up for the lack of protection due to the thin surface protection layer 14, and ultimately ensure that the dummy gate 12 will not be damaged and the subsequent interlayer dielectric layer will not be adversely affected due to the thick surface protection layer 14.

[0089] The material of the surface protection layer 14 may be silicon oxide, and the etching of the surface protection layer 14 may be performed by dry etching using carbon tetrafluoride plasma gas as etching gas.

[0090] In some examples, the material of the substrate 11 is silicon, the material of the functional layer 13 is silicon nitride, the material of the surface protection layer 14 is silicon oxide, and the material of the top protection layer 12c in the pseudo gate 12 is silicon oxide. Step S160, forming a preliminary groove in the reserved area, can include: performing dry etching with hydrogen bromide (HBr) plasma gas as an etching gas to form a Figure 6h The prepared groove 17 is shown.

[0091] It should be noted that when dry etching is performed using hydrogen bromide plasma gas as an etching gas, silicon will be etched at a higher etching rate and silicon oxide and silicon nitride will be etched at a lower etching rate. Figure 6gThe reserved area in the PMOS device area shown in the figure is etched, and the top protection layer 12c in the pseudo gate 12 on the PMOS device area is etched at the same time, and the portion of the surface protection layer 14 on the NMOS device area at the top of the pseudo gate 12 is etched at the same time, and even after the portion of the surface protection layer 14 on the top of the pseudo gate 12 is etched away, the top protection layer 12c in the pseudo gate 12 is etched. However, in this etching process, since the tops of the pseudo gates 12 on the PMOS device area and the NMOS device area are all silicon oxide, the etching height difference of the silicon oxide on the tops of the pseudo gates 12 on the PMOS device area and the NMOS device area is not generated. The height difference between the silicon oxide on the tops of the pseudo gates 12 on the PMOS device area and the NMOS device area is only caused by the previous process of etching the surface protection layer 14 using the photoresist layer 15 as a mask, thereby Figure 6h The height difference between the silicon oxide on the top of the dummy gate 12 in the PMOS device region and the NMOS device region is only the thickness of the surface protection layer 14, so it will not have a significant impact on the subsequent filling and grinding of the interlayer dielectric layer.

[0092] The method for manufacturing a semiconductor structure provided in the embodiment of the present application may further include: after step S160, widening the preliminary trench 17 by etching to form Figure 6i The sigma trench 18 for growing silicon germanium is shown. Then, silicon germanium is grown in the sigma trench 18 to form a Figure 6j The SiGe trench 19 shown in FIG. 1 is formed, thereby completing the formation process of the SiGe trench 19. It should be noted that Figure 6j Only one SiGe trench 19 is shown. In practice, one SiGe trench 19 may be formed in the reserved area on both sides of each dummy gate 12 in the PMOS device region.

[0093] The manufacturing method of the semiconductor structure provided in the above embodiment mainly provides a detailed introduction to the improvements compared with the prior art, aiming to illustrate that the improvements compared with the prior art can reduce the chemical mechanical polishing load of the interlayer dielectric layer in the manufacturing process of the semiconductor structure and can reduce the probability of the existence of gaps in the interlayer dielectric layer included in the semiconductor structure. For contents other than the improvements, please refer to the relevant description of the prior art.

[0094] Corresponding to the manufacturing method of the semiconductor structure provided in the above embodiments, another embodiment of the present application also provides a semiconductor structure, which is manufactured by any of the manufacturing methods provided in the above embodiments. Since the chemical mechanical polishing load of the interlayer dielectric layer during the manufacturing process is small and the probability of the existence of gaps in the interlayer dielectric layer is low, the semiconductor structure has excellent electrical properties and low manufacturing cost. Figure 6j The structure shown can be regarded as an exemplary structure of a part of the semiconductor structure provided in the embodiment of the present application. It should be understood that Figures 6a to 6jThe formation process of the SiGe trench 19 is mainly illustrated. Therefore, in order to have a complete structure of a PMOS device and an NMOS device, the semiconductor structure provided in the embodiment of the present application must also be formed in Figure 6j A source region, a drain region and connecting lines are further formed on the structure shown, and an isolation structure between different MOS devices is also formed. Figure 6j The structure shown is only an exemplary illustration of the formed SiGe trench 19 and does not limit the number of PMOS devices and NMOS devices in the semiconductor structure provided in the embodiment of the present application.

[0095] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Providing a substrate, the substrate comprising an NMOS device region and a PMOS device region; forming dummy gates on the NMOS device region and the PMOS device region; Forming a functional layer on the sidewall of the dummy gate and on the substrate, wherein the area of ​​the PMOS device region other than under the dummy gate and the functional layer on the sidewall of the dummy gate is a reserved area; After the functional layer is formed, a photoresist layer is formed covering the NMOS device region and having an opening in the PMOS device region; Using the photoresist layer as a mask to etch the functional layer until the surface of the reserved area is exposed, and then removing the photoresist layer; forming a preliminary groove in the reserved area; Wherein, a functional layer is formed on the side wall of the dummy gate and the substrate by cyclically executing the first step and the second step, wherein the first step includes: forming a sub-functional layer covering the dummy gate and the substrate, and the second step includes: passing an etching gas from above the substrate downward to etch the sub-functional layer until the sub-functional layer on the top of the dummy gate is etched away.

2. The manufacturing method according to claim 1, wherein: The first step forms the sub-functional layer by using any one of an atomic layer deposition process, a chemical vapor deposition process and a physical vapor deposition process.

3. The manufacturing method according to claim 2, wherein: The thickness of the sub-functional layer is 20 angstroms to 50 angstroms.

4. The manufacturing method according to claim 3, wherein: In the second step, the flow rate of the etching gas is controlled so that the portion of the sub-functional layer on the top of the dummy gate is etched away, and the time taken is 4s-8s.

5. The manufacturing method according to claim 1, wherein: The material used for the sub-functional layer is silicon nitride, the pseudo gate includes a top protective layer located on the top and the material used for the top protective layer is silicon oxide, and the etching gas used in the second step is a plasma gas mixed with carbon tetrafluoride and fluoromethane.

6. The manufacturing method according to claim 1, wherein: The material used for the functional layer is silicon nitride, the pseudo gate includes a top protective layer located on the top and the material used for the top protective layer is silicon oxide, and the functional layer is etched using the photoresist layer as a mask, including: dry etching the functional layer using a plasma gas mixed with carbon tetrafluoride and fluoromethane as an etching gas.

7. The manufacturing method according to claim 1, further comprising: Before forming the functional layer, a surface protection layer is formed on the dummy gate and the substrate, and the functional layer formed thereafter covers the surface protection layer on the sidewall of the dummy gate and the substrate; After etching the functional layer using the photoresist layer as a mask, etching the surface protection layer using the photoresist layer as a mask, wherein the functional layer is etched until a portion of the surface protection layer on the reserved area is exposed, and the surface protection layer is etched until a surface of the reserved area is exposed.

8. The manufacturing method according to claim 7, wherein: The thickness of the surface protection layer is smaller than the thickness of the functional layer.

9. The manufacturing method according to claim 1, further comprising: The preliminary trench is widened by etching to form a sigma trench for growing silicon germanium.

10. A semiconductor structure, wherein the semiconductor structure is manufactured by the manufacturing method according to any one of claims 1 to 9.

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