General verification system, device and method suitable for functional performance of FPGA (Field Programmable Gate Array) device

Abstract

The invention discloses a universal verification system, device and method suitable for the functional performance of an FPGA device, and relates to the technical field of FPGA device testing, the universal verification system comprises verification hardware, verification software, a verification auxiliary instrument and environment equipment, and the specific verification steps are as follows: step 1, on-chip logic function verification; step 2, common interface function verification; 3, software and hardware adaptability function verification; 4, comprehensive performance function verification; 5, dynamic power consumption testing; step 6, common IP function verification; 7, testing associated parameters; step 8, system adaptability; and step 9, environment adaptability. The universal verification system is suitable for verification of a serial interface function, a multi-path IO compatibility test function, development software platform adaptability, simulator adaptability, a configuration mode, configuration starting time, a signal processing function, official IP supportability and the like, and has functions of a high-speed interface protocol, an Aurora protocol, a DDR protocol, an IIC protocol, an SPI protocol and the like.

Description

Technical Field

[0001] The present invention relates to the field of FPGA device testing technology, and in particular to a universal verification system, device and method suitable for functional performance of FPGA devices. Background Art

[0002] FPGAs are composed of many programmable logic elements (such as logic gates, registers, and memory cells) that can be combined into complex digital circuits. FPGA design can be completed using hardware description languages ​​(such as Verilog and VHDL), which can then be synthesized and downloaded to the FPGA chip to program the implementation of the function.

[0003] FPGAs are widely used in many application areas, including digital signal processing, image processing, communications, and control systems, etc. Due to their flexibility and programmability, FPGAs are widely used in areas that require rapid prototyping and reconfigurable electronic systems.

[0004] As the scale of FPGAs continues to expand, the requirements for their fault detection and reliability verification are also getting higher and higher. The programmability of FPGAs brings many challenges to the complete and comprehensive testing of the FPGA itself. FPGA testing must consider various fault models to fully detect the fault tolerance of these devices and device defects. Logic resources must be tested in different operating modes, which in turn requires multiple reconfigurations of the logic resources under test in the FPGA.

[0005] FPGA is the core device of signal processing circuits (systems). It has powerful performance, high working speed, rich interface types and large number, and complex working circuits. Through user programming, FPGA can realize various complex and high-performance functions. The peripheral circuits required for the working circuit of FPGA include memory, configuration PROM or FLASH, clock, power supply, etc. Depending on the user's use, it also includes network port, DDR, high-speed data interface, AD / DA chip data interface, I2C or SPI memory, asynchronous serial interface, etc. FPGA includes various hardware units such as BRAM, CRM and various software IP core functions. Its own functions are very powerful and its internal structure is very complex.

[0006] At the same time, as the number of FPGA interfaces increases and the transmission rate increases, the difficulty of these tests will become more and more prominent in ATE testing, the requirements for ATE hardware and software control will gradually increase, and the testing cost will increase. Currently, the performance test of the same type of FPGA requires multiple layout test board hardware to split the performance into several parts for testing, which leads to increased testing time and cost.

[0007] At present, due to the limitation of vector storage depth of the automatic test system itself, FPGA detection of different resources and fault coverage needs to be repeatedly configured. The corresponding configuration bit stream is long and there are many configuration files. It is difficult for the automatic test system to load all configuration files into the test system memory at one time, so it has to be loaded multiple times, resulting in an exponential increase in test time. At the same time, the automatic test equipment (ATE) is mainly for the DC parameters, AC parameters and some functional tests of the device. In order to repeatedly verify the FPGA function, it is necessary to design different layout test boards according to different test function items to mobilize the automatic test equipment (ATE) resources and frequently change the test board for testing.

[0008] The use of automatic test equipment (ATE) specifically includes the following deficiencies:

[0009] 1. Repeated configuration and replacement of Layout test boards result in a long test time;

[0010] 2. Design different Layout test boards for different functions, resulting in increased costs;

[0011] 3. Due to the heavy size of automatic test equipment (ATE), high and low temperature tests can be carried out by using a heat flow meter close to the test board, but it is difficult to use external equipment to carry out tests in special environments such as vibration environment and low pressure environment;

[0012] 4. The test items do not meet the requirements of actual environment applications, including verification of serial interface functions, multi-channel IO compatibility test functions, development software platform adaptability, simulator adaptability, configuration methods, configuration startup time, signal processing functions, and official IP support. They are not applicable to high-speed interface protocols, Aurora protocols, DDR protocols, IIC protocols, SPI protocols, etc. Summary of the invention

[0013] In view of the deficiencies in the prior art, the present invention provides a universal verification system, device and method suitable for the functional performance of FPGA-type devices, which solves the problems raised in the above-mentioned background technology.

[0014] To achieve the above objectives, the present invention is implemented by the following technical solution: a general verification method applicable to the functional performance of FPGA-type devices, comprising the following verification steps:

[0015] Step 1: Verify the on-chip logic function. The specific contents are as follows:

[0016] (1) I2C communication: In-board closed-loop test method, the FPGA program is used to write and read the E2PROM of the I2C interface, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0017] (2) SPI communication: In-board closed-loop test method, the FPGA program is used to write and read the E2PROM of the I2C interface, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0018] (3) On-chip memory read and write: In-board closed-loop test method, the FPGA program is used to write and read the internal memory of the FPGA, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal;

[0019] (4) Multiplier: In the closed-loop test mode on the board, the multiplier IP is called, the bit width of the multiplicand A and the multiplier B is set to 4 bits, and the output product P width is 8 bits; the values ​​of A and B increase from 1 to 15, with a total of 225 groups, and the multiplied number and product value are sent to the host computer, which verifies the calculation result;

[0020] (5) Serial communication: The host computer sends a self-test command, and after the FPGA successfully parses it, it returns the self-test success information to the host computer;

[0021] (6) Ethernet communication: The host computer sends a self-test command, and after the FPGA successfully parses it, it returns the self-test success information to the host computer;

[0022] Step 2: Verify common interface functions. The specific contents are as follows:

[0023] (1) Debug interface function: Scan FPGA devices and burn software to FPGA through JTAG burner, and debug and run online after burning;

[0024] (2) High-speed serial interface function: In-board closed-loop test method, optical fiber communication is realized through the Aurora protocol, and the optical port loopback method is used for testing. The send data and the receive data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0025] Step 3: Verify the adaptability of software and hardware functions. The specific contents are as follows:

[0026] Development software platform adaptability function: compile, burn, enter debugging mode through FPGA development software platform, debug FPGA online, and view FPGA operation status in real time;

[0027] Step 4: Comprehensive performance function verification, the specific contents are as follows:

[0028] (1) Configuration mode: Change the configuration mode of the FPGA by turning on the DIP switch. If the FPGA startup indicator DONE turns from off to on, it is normal. Otherwise, it is abnormal.

[0029] (2) Configuration start time: The time difference from when the FPGA's VCCO rises to 90% to when the DONE signal jumps to a "high level" is measured, which is the configuration start time;

[0030] (3) Signal processing function: FPGA calls FFTIP, configures 50M clock, inputs a set of pre-stored single-tone data into FFTIP, and then sends the real and imaginary data output by IP to the host computer, which processes the data into a phase-frequency curve to determine whether it is normal;

[0031] Step 5: Dynamic power consumption test, the details are as follows:

[0032] VCCINT working current and voltage: The verification board designs a high-power precision resistor with a small resistance value on the core voltage input path of the FPGA, and cooperates with the current monitoring chip to perform real-time testing on the current and voltage of the resistor. See the design circuit for details. Figure 2 , the test results are displayed through the host computer software;

[0033] Step 6: Verify common IP functions. The details are as follows:

[0034] (1) DDR: In-board closed-loop test method, the FPGA program is used to write and read the DDR memory, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0035] (2) Clock generator: FPGA calls the internal PLL. The clock after monitoring the PLL with an oscilloscope should be 50 MHz.

[0036] (3) FIFO: In-board closed-loop test method, the internal FIFO memory is written and read through the FPGA program, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0037] Step 7: Associated parameter test, the specific contents are as follows:

[0038] Parameter test of correlation between VCCINT working current and FPGA resource utilization: Design FPGA applications with resource utilization of 10%, 20%, 30%, 40%, 50%, 60%, and 70% respectively, run them after burning them, record the corresponding VCCINT working current, and form a correlation curve between dynamic current and resource utilization;

[0039] Step 8: System adaptability, the specific contents are as follows:

[0040] Core voltage deviation: Verify that the board uses different configuration resistors of the DC / DC chip designed for the core voltage. Select different resistors through the DIP switch to control the output core voltage to be in three different ranges: normal, upward deviation, and downward deviation. During the test, adjust the core voltage to normal, upward deviation, and downward deviation through the DIP switch to achieve core voltage deviation. Under the deviation condition, test the above-mentioned various functions of the FPGA.

[0041] Step 9: Environmental adaptability, the specific contents are as follows:

[0042] Environmental stress is applied according to environmental test conditions, during which on-chip logic, high-speed serial interface, signal processing, and common IP function tests are carried out. After the test, the system is restored to normal temperature conditions for final testing; including high and low temperature working tests, high and low temperature impact tests, high and low temperature storage tests, mechanical vibration tests, mechanical impact tests, and low pressure working tests.

[0043] A universal verification system for the functional performance of FPGA devices as described in the above claims, comprising verification hardware, verification software, verification auxiliary instruments, and environmental equipment, specifically divided into FPGA verification boards, host computers, auxiliary instruments, and environmental test equipment;

[0044] in,

[0045] The host computer consists of automatic test software and FPGA software platform;

[0046] Automatic test software used to control the test process and record test results and data.

[0047] Optionally, the auxiliary instruments include a DC power supply, a digital oscilloscope, and a multimeter.

[0048] Optionally, the environmental testing equipment includes temperature, mechanics, and low-pressure environmental testing equipment.

[0049] A universal verification device for the functional performance of FPGA-type devices as described in any one of the above claims, comprising a verification board, wherein the verification board includes an FPGA chip, power supply, clock, configuration startup, debugging interface, serial port circuit, network port circuit, high-speed interface, and memory.

[0050] Optionally, the verification board is designed in a whole-board manner, that is, all circuits of the entire verification board include the verified FPGA device, serial port chip, FLASH chip, EEPROM chip, DDR chip, optical module, and power supply.

[0051] Optionally, the power supply includes normal power supply, bias pulling, and current monitoring.

[0052] Optionally, the high-speed interface uses fiber optic communication.

[0053] The present invention provides a general verification system, device and method applicable to the functional performance of FPGA devices, which has the following beneficial effects:

[0054] This universal verification system for the functional performance of FPGA-type devices implements data transmission in a self-loop manner within the board, and verifies the sending and receiving functions of the transmitted data at the same time, shortening the test time; the whole board method can verify multiple groups of projects at the same time, reduce the types of verification boards, and reduce costs; the whole board environmental test can be placed in a test box, and the signal is monitored by cable lead-out to make up for the lack of test items; it is closest to the actual use of the device, and the signal between the verified device and the processor is completed in one PCB, the signal path is short, no cable or connector transfer is required, the signal integrity is good, and it is not easily affected by external interference. The interface device performance test is more stable and reliable, and it is more suitable for high-speed interface protocol verification.

[0055] This universal verification device for the functional performance of FPGA-type devices will give full play to the advantages of the whole-board method, adopt the on-board self-loop data transmission method, stably and reliably implement the functional performance test of the high-speed interface protocol, and can flexibly implement the power bias, timing bias, resource occupancy rate and power consumption and other extreme performance tests of FPGA-type devices. It cites the highlights of the power bias circuit, current acquisition circuit, and on-board self-loop data transmission method.

[0056] Power supply bias: Due to the FPGA core power supply V CCINT The voltage is small and the current is large, and there is a strong binding timing relationship with other multiple power supply groups, clocks, reset and other signals of the FPGA. If an external DC power supply is used to power and bias the FPGA, the allowable bias range is narrow due to the small absolute value of the voltage. At the same time, the working current is large and the transmission loss is large. The bias adjustment of the external DC power supply is easy to fluctuate out of the allowable range, which damages the FPGA, is unsafe, and cannot meet the timing requirements. This method verifies the method of designing a bias circuit inside the board. Configuration resistors with different bias values ​​are designed around the DC / DC chip powered on the board. Different bias voltages are selected by using the on-board DIP switch. It has the characteristics of high bias accuracy, no effect on the FPGA startup timing, easy operation, safety and stability.

[0057] Circuit acquisition circuit: Real-time, safe and accurate measurement of FPGA working current. Using precision resistors and current monitoring circuits, the working current can be measured in real time and accurately without affecting the operation of FPGA. Compared with conventional multimeters and other instruments, this method is safer and will not cause damage due to improper operation. This method is more suitable for current testing in test environments such as temperature, mechanics, and low pressure.

[0058] In-board self-loop data transmission method: Most of the various verification functions of FPGA adopt the in-board closed-loop verification method, which reduces the demand for test devices and instruments. At the same time, it ensures the integrity and high-speed transmission of high-speed signals and avoids errors in test results.

[0059] This general verification method for the functional performance of FPGA devices has the following beneficial effects:

[0060] Verify the process assembly adaptability of the device under test (DUT): Verify the board card according to the manual of the device under test and the assembly process standards of the application industry, carry out device PCB packaging design and layout design, make verification board thickness, carry out welding work according to the assembly process standards, and verify the assembly adaptability of the device;

[0061] Verify the functions and performance indicators of the device under test (DUT): The verification board is placed in the verification system. Under typical or dedicated working circuits, verify the DUT's on-chip logic, communication function, on-chip memory read and write function, online debugging function, memory interface function, high-speed serial interface function, IO compatibility test function, development software platform adaptability, simulator adaptability, configuration mode, configuration startup time, signal processing function, and official IP support, etc.;

[0062] Board-level environmental adaptability and working stability: The verification board is placed in a temperature environment, a mechanical environment, a low-pressure environment, etc., to conduct online testing on the functional performance of the device under test (DUT);

[0063] When verifying the performance of signal processing functions, a self-loop test was used. The main idea is that the FPGA device sends data through the transceiver chip and then the FPGA receives the signal, and the bit error rate analysis is performed to reduce the use of auxiliary devices, cables and external instrument monitoring, greatly reducing hardware costs;

[0064] The verification board PCB adopts a partition layout design for the verified devices and auxiliary function devices. The middle area is concentrated with FPGA verified devices, and the surrounding area is auxiliary function devices, which improves the maintainability of the verification board. Figure 2 shown.

[0065] Currently, the test system is suitable for functional performance verification of 5-series and 7-series FPGA devices, and has successfully verified the functional performance of on-chip logic, communication function, on-chip memory read and write function, online debugging function, memory interface function, high-speed serial interface function, IO compatibility test function, development software platform adaptability, simulator adaptability, configuration mode, configuration startup time, signal processing function, and official IP support.

[0066] The whole-board verification method of this solution is closer to the actual application environment of the device, and the verification results are closer to the actual application environment; at the same time, it makes up for the lack of test items of automatic test equipment (ATE), and can carry out targeted environmental stress tests according to industry requirements;

[0067] Through PCB partition layout design, under the same environmental stress test, external methods can be used to protect auxiliary components to work normally under thermal stress and mechanical stress, thereby reducing the use level of auxiliary components and reducing the cost of verification boards;

[0068] The hardware adopts a universal design solution, which improves the versatility of PCB and reduces the design and use costs;

[0069] The self-loop test method is used to reduce the use of cables and connectors, avoid signal transmission interference, attenuation, poor contact and other problems, and ensure high-speed, high-quality signal transmission; at the same time, it reduces the number of auxiliary instruments used and reduces the design and use costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 It is a block diagram of the overall test system architecture in the invention;

[0071] Figure 2 This is a schematic diagram of the general PCB structure in the invention. DETAILED DESCRIPTION

[0072] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0073] In the description of the present invention, unless otherwise specified, "plurality" means two or more than two; the orientations or positional relationships indicated by the terms "upper", "lower", "left", "right", "inner", "outer", "front end", "rear end", "head", "tail", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0074] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0075] Embodiment 1: A general verification method applicable to the functional performance of FPGA devices, comprising the following verification steps:

[0076] Step 1: Verify the on-chip logic function. The specific contents are as follows:

[0077] (1) I2C communication: In-board closed-loop test method, the FPGA program is used to write and read the E2PROM of the I2C interface, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0078] (2) SPI communication: In-board closed-loop test method, the FPGA program is used to write and read the E2PROM of the I2C interface, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0079] (3) On-chip memory read and write: In-board closed-loop test method, the FPGA program is used to write and read the internal memory of the FPGA, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal;

[0080] (4) Multiplier: In the closed-loop test mode on the board, the multiplier IP is called, the bit width of the multiplicand A and the multiplier B is set to 4 bits, and the output product P width is 8 bits; the values ​​of A and B increase from 1 to 15, with a total of 225 groups, and the multiplied number and product value are sent to the host computer, which verifies the calculation result;

[0081] (5) Serial communication: The host computer sends a self-test command, and after the FPGA successfully parses it, it returns the self-test success information to the host computer;

[0082] (6) Ethernet communication: The host computer sends a self-test command, and after the FPGA successfully parses it, it returns the self-test success information to the host computer;

[0083] Step 2: Verify common interface functions. The specific contents are as follows:

[0084] (1) Debug interface function: Scan FPGA devices and burn software to FPGA through JTAG burner, and debug and run online after burning;

[0085] (2) High-speed serial interface function: In-board closed-loop test method, optical fiber communication is realized through the Aurora protocol, and the optical port loopback method is used for testing. The send data and the receive data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0086] Step 3: Verify the adaptability of software and hardware functions. The specific contents are as follows:

[0087] Development software platform adaptability function: compile, burn, enter debugging mode through FPGA development software platform, debug FPGA online, and view FPGA operation status in real time;

[0088] Step 4: Comprehensive performance function verification, the specific contents are as follows:

[0089] (1) Configuration mode: Change the configuration mode of the FPGA by turning on the DIP switch. If the FPGA startup indicator DONE turns from off to on, it is normal. Otherwise, it is abnormal.

[0090] (2) Configuration start time: The time difference from when the FPGA's VCCO rises to 90% to when the DONE signal jumps to a "high level" is measured, which is the configuration start time;

[0091] (3) Signal processing function: FPGA calls FFTIP, configures 50M clock, inputs a set of pre-stored single-tone data into FFTIP, and then sends the real and imaginary data output by IP to the host computer, which processes the data into a phase-frequency curve to determine whether it is normal;

[0092] Step 5: Dynamic power consumption test, the details are as follows:

[0093] VCCINT working current and voltage: The verification board designs a high-power precision resistor with a small resistance value on the core voltage input path of the FPGA, and cooperates with the current monitoring chip to perform real-time testing on the current and voltage of the resistor. See the design circuit for details. Figure 2 , the test results are displayed through the host computer software;

[0094] Step 6: Verify common IP functions. The details are as follows:

[0095] (1) DDR: In-board closed-loop test method, the FPGA program is used to write and read the DDR memory, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0096] (2) Clock generator: FPGA calls the internal PLL. The clock after monitoring the PLL with an oscilloscope should be 50 MHz.

[0097] (3) FIFO: In-board closed-loop test method, the internal FIFO memory is written and read through the FPGA program, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal.

[0098] Step 7: Associated parameter test, the specific contents are as follows:

[0099] Parameter test of correlation between VCCINT working current and FPGA resource utilization: Design FPGA applications with resource utilization of 10%, 20%, 30%, 40%, 50%, 60%, and 70% respectively, run them after burning them, record the corresponding VCCINT working current, and form a correlation curve between dynamic current and resource utilization;

[0100] Step 8: System adaptability, the specific contents are as follows:

[0101] Core voltage deviation: Verify that the board uses different configuration resistors of the DC / DC chip designed for the core voltage. Select different resistors through the DIP switch to control the output core voltage to be in three different ranges: normal, upward deviation, and downward deviation. During the test, adjust the core voltage to normal, upward deviation, and downward deviation through the DIP switch to achieve core voltage deviation. Under the deviation condition, test the above-mentioned various functions of the FPGA.

[0102] Step 9: Environmental adaptability, the specific contents are as follows:

[0103] Environmental stress is applied according to environmental test conditions, during which on-chip logic, high-speed serial interface, signal processing, and common IP function tests are carried out. After the test, the system is restored to normal temperature conditions for final testing; including high and low temperature working tests, high and low temperature impact tests, high and low temperature storage tests, mechanical vibration tests, mechanical impact tests, and low pressure working tests.

[0104] Embodiment 2: A general verification system for the functional performance of FPGA devices, including verification hardware, verification software, verification auxiliary instruments, and environmental equipment, specifically divided into FPGA verification boards, host computers, auxiliary instruments, and environmental test equipment;

[0105] in,

[0106] The host computer consists of automatic test software and FPGA software platform;

[0107] Automatic testing software to control the test process and record test results and data;

[0108] Auxiliary instruments include DC power supply, digital oscilloscope, and multimeter;

[0109] Environmental testing equipment includes temperature, mechanics, and low pressure environmental testing equipment.

[0110] Embodiment 3: A general verification device for the functional performance of FPGA devices, including a verification board, wherein the verification board includes an FPGA chip, a power supply, a clock, a configuration startup, a debugging interface, a serial port circuit, a network port circuit, a high-speed interface, and a memory;

[0111] The verification board is designed in a whole-board manner, that is, all circuits of the entire verification board include the verified FPGA device, serial port chip, FLASH chip, EEPROM chip, DDR chip, optical module, and power supply;

[0112] in,

[0113] Power supply includes normal power supply, bias pulling and current monitoring;

[0114] High-speed interface uses optical fiber communication.

[0115] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A general verification method for the functional performance of FPGA devices, characterized in that: The verification steps include: Step 1: Verify the on-chip logic function. The specific contents are as follows: (1) I2C communication: In-board closed-loop test method, the FPGA program is used to write and read the E2PROM of the I2C interface, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal. (2) SPI communication: In-board closed-loop test method, the FPGA program is used to write and read the E2PROM of the I2C interface, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal. (3) On-chip memory read and write: In-board closed-loop test method, the FPGA program is used to write and read the internal memory of the FPGA, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal; (4) Multiplier: In the closed-loop test mode on the board, the multiplier IP is called, the bit width of the multiplicand A and the multiplier B is set to 4 bits, and the output product P width is 8 bits; the values ​​of A and B increase from 1 to 15, with a total of 225 groups, and the multiplied number and product value are sent to the host computer, which verifies the calculation result; (5) Serial communication: The host computer sends a self-test command, and after the FPGA successfully parses it, it returns the self-test success information to the host computer; (6) Ethernet communication: The host computer sends a self-test command, and after the FPGA successfully parses it, it returns the self-test success information to the host computer; Step 2: Verify common interface functions. The specific contents are as follows: (1) Debug interface function: Scan FPGA devices and burn software to FPGA through JTAG burner, and debug and run online after burning; (2) High-speed serial interface function: In-board closed-loop test method, optical fiber communication is realized through the Aurora protocol, and the optical port loopback method is used for testing. The send data and the receive data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal. Step 3: Verify the adaptability of software and hardware functions. The specific contents are as follows: Development software platform adaptability function: compile, burn, enter debugging mode through FPGA development software platform, debug FPGA online, and view FPGA operation status in real time; Step 4: Comprehensive performance function verification, the specific contents are as follows: (1) Configuration mode: Change the configuration mode of the FPGA by turning on the DIP switch. If the FPGA startup indicator DONE turns from off to on, it is normal. Otherwise, it is abnormal. (2) Configuration start time: The time difference from when the FPGA's VCCO rises to 90% to when the DONE signal jumps to a "high level" is the configuration start time. (3) Signal processing function: FPGA calls FFTIP, configures 50M clock, inputs a set of pre-stored single-tone data into FFTIP, and then sends the real and imaginary data output by IP to the host computer, which processes the data into a phase-frequency curve to determine whether it is normal; Step 5: Dynamic power consumption test, the details are as follows: VCCINT working current and voltage: The verification board designs a high-power precision resistor with a small resistance value on the core voltage input path of the FPGA, and cooperates with the current monitoring chip to perform real-time testing on the current and voltage of the resistor. The designed circuit is shown in Figure 2, and the test results are displayed by the host computer software; Step 6: Verify common IP functions. The details are as follows: (1) DDR: In-board closed-loop test method, the FPGA program is used to write and read the DDR memory, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal. (2) Clock generator: FPGA calls the internal PLL. The clock after monitoring the PLL with an oscilloscope should be 50 MHz. (3) FIFO: In-board closed-loop test method, the internal FIFO memory is written and read through the FPGA program, and the written data and read data are sent to the host computer. The host computer compares the data to see if they are consistent and determines whether the function is normal. Step 7: Associated parameter test, the specific contents are as follows: Parameter test of correlation between VCCINT working current and FPGA resource utilization: Design FPGA applications with resource utilization of 10%, 20%, 30%, 40%, 50%, 60%, and 70% respectively, run them after burning them, record the corresponding VCCINT working current, and form a correlation curve between dynamic current and resource utilization; Step 8: System adaptability, the specific contents are as follows: Core voltage deviation: The verification board uses different configuration resistors of the DC / DC chip designed for the core voltage. Different resistors are selected through the DIP switch to control the output core voltage to be in three different amplitudes: normal, upward deviation, and downward deviation. The designed circuit is shown in Figure 3. During the test, the core voltage is adjusted to normal, upward deviation, and downward deviation through the DIP switch to achieve core voltage deviation. Under the deviation condition, the above-mentioned various functions of the FPGA are tested; Step 9: Environmental adaptability, the specific contents are as follows: Environmental stress is applied according to environmental test conditions, during which on-chip logic, high-speed serial interface, signal processing, and common IP function tests are carried out. After the test, the system is restored to normal temperature conditions for final testing; including high and low temperature working tests, high and low temperature impact tests, high and low temperature storage tests, mechanical vibration tests, mechanical impact tests, and low pressure working tests.

2. A universal verification system for functional performance of FPGA devices as claimed in claim 1, characterized in that: Including verification hardware, verification software, verification auxiliary instruments, and environmental equipment, which are specifically divided into FPGA verification boards, host computers, auxiliary instruments, and environmental test equipment; in, The host computer consists of automatic test software and FPGA software platform; Automatic test software used to control the test process and record test results and data.

3. The universal verification device for functional performance of FPGA devices according to claim 2, characterized in that: The auxiliary instruments include a direct current power supply, a digital oscilloscope and a multimeter.

4. The universal verification device for functional performance of FPGA devices according to claim 2, characterized in that: The environmental testing equipment includes temperature, mechanics and low pressure environmental testing equipment.

5. A general verification device for functional performance of FPGA-type devices as described in any one of claims 1 to 4, characterized in that: It includes a verification board, which includes an FPGA chip, power supply, clock, configuration startup, debugging interface, serial port circuit, network port circuit, high-speed interface, and memory.

6. The universal verification device for functional performance of FPGA devices according to claim 5, characterized in that: The verification board is designed in a whole-board manner, that is, all circuits of the entire verification board include the verified FPGA device, serial port chip, FLASH chip, EEPROM chip, DDR chip, optical module, and power supply.

7. The universal verification device for functional performance of FPGA devices according to claim 5, characterized in that: The power supply includes normal power supply, bias pulling and current monitoring.

8. The universal verification device for functional performance of FPGA devices according to claim 5, characterized in that: The high-speed interface uses optical fiber communication.

Images