Display substrate and display device

Abstract

The embodiment of the invention provides a display substrate and a display device. The display substrate comprises a grid signal line layer and a source and drain electrode layer. The gate signal line layer comprises a second signal line part of a gate signal line, and the source and drain electrode layer comprises a first signal line part of the gate signal line; in the same grid signal line, the second signal line part is connected with the first signal line part through the first via hole; the material resistivity of the first signal line part is smaller than that of the second signal line part; the grid signal line layer further comprises a fourth signal line part of the data signal line, and the source and drain electrode layer further comprises a third signal line part of the data signal line; in the same data signal line, the adjacent third signal line part and fourth signal line part are connected through a second via hole; the orthographic projection of the third signal line part and the orthographic projection of the first signal line part on an array substrate of the display substrate are not overlapped, and the orthographic projection of the fourth signal line part and the orthographic projection of the first signal line part on the array substrate are overlapped.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of the liquid crystal display industry, the forms of display products are becoming increasingly diverse. In order to improve the user experience, display products of all forms have a trend of increasing in size, among which the car screen is the most prominent. Most car screens are horizontally designed, and with the development of car screens, car screens are gradually turning to integration, which makes the length of car screens longer and longer. Correspondingly, the resistance of the gate signal line is getting larger and larger, and the gate signal transmitted through the gate signal line will be attenuated and delayed, resulting in abnormal display problems on the screen. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a display substrate and a display device to improve the abnormal display problem of the display screen. The specific technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a display substrate, the display substrate comprising:

[0005] Gate signal line layer, source and drain electrode layer;

[0006] The gate signal line layer includes a second signal line portion of the gate signal line, and the source-drain electrode layer includes a first signal line portion of the gate signal line;

[0007] In the same gate signal line, the second signal line portion in the gate signal line layer is connected to the first signal line portion in the source-drain electrode layer through a first via hole;

[0008] The material resistivity of the first signal line portion is less than the material resistivity of the second signal line portion;

[0009] The gate signal line layer further includes a fourth signal line portion of the data signal line, and the source-drain electrode layer further includes a third signal line portion of the data signal line;

[0010] In the same data signal line, the adjacent third signal line portion and the fourth signal line portion are connected through the second via hole;

[0011] The orthographic projections of the third signal line portion and the first signal line portion on the array substrate of the display substrate have no overlapping portion, and the orthographic projections of the fourth signal line portion and the first signal line portion on the array substrate have an overlapping portion.

[0012] In a possible implementation, the same gate signal line includes a plurality of second signal line portions and a first signal line portion, and each second signal line portion of the same gate signal line is connected to the first signal line portion through a first via hole.

[0013] In one possible implementation,

[0014] In the column direction of the display substrate, the first width of the first signal line portion is smaller than the second width of the first signal line portion; wherein the first width is the width of the first signal line portion at a position where the projection overlaps with the fourth signal line portion, and the second width is the width of the first signal line portion where there is no projection overlap with the fourth signal line portion.

[0015] In one possible implementation,

[0016] The i-th second signal line portion of the N-th gate signal line corresponds to the i-th sub-pixel in the N-th row of pixel units;

[0017] or,

[0018] The i-th second signal line portion of the N-th gate signal line corresponds to the 2i-1-th and 2i-th sub-pixels in the N-th row of pixel units;

[0019] or,

[0020] The i-th second signal line portion of the N-th gate signal line corresponds to the 3i-2-th, 3i-1-th and 3i-th sub-pixels in the N-th row of pixel units;

[0021] Wherein, N is an integer not less than 1, and i is an integer not less than 1.

[0022] In one possible implementation,

[0023] In the column direction of the display substrate, a preset distance is arranged between the drain of the data writing transistor of each sub-pixel in the Nth row of pixel units and the Nth gate signal line.

[0024] In one possible implementation,

[0025] In the row direction of the display substrate, for the data writing transistor of each sub-pixel, the drain and source of the data writing transistor are arranged on both sides of its own gate.

[0026] In one possible implementation,

[0027] In the column direction of the display substrate, for the data writing transistor of each sub-pixel, the drain and source of the data writing transistor are arranged on one side of its own gate.

[0028] In one possible implementation,

[0029] In the column direction of the display substrate, for the data writing transistor of each sub-pixel, the drain and source of the data writing transistor are arranged on both sides of its own gate.

[0030] In a possible implementation manner, the display substrate further includes: an array substrate, a first insulating layer, an active layer, a second insulating layer, and a third insulating layer;

[0031] The first insulating layer is arranged on the array substrate, the active layer is arranged on a side of the first insulating layer away from the array substrate, the second insulating layer is arranged on a side of the active layer away from the array substrate, the gate signal line layer is arranged on a side of the second insulating layer away from the array substrate, the third insulating layer is arranged on a side of the gate signal line layer away from the array substrate, and the source-drain electrode layer is arranged on a side of the third insulating layer away from the array substrate.

[0032] In a second aspect, an embodiment of the present application provides a display device, comprising a display substrate as described in any one of the first aspects.

[0033] Beneficial effects of the embodiments of the present application:

[0034] A display substrate and a display device provided in an embodiment of the present application, the display substrate comprises: a gate signal line layer and a source-drain electrode layer; the gate signal line layer comprises a second signal line portion of the gate signal line, and the source-drain electrode layer comprises a first signal line portion of the gate signal line; in the same gate signal line, the second signal line portion in the gate signal line layer is connected to the first signal line portion in the source-drain electrode layer through a first via hole; the material resistivity of the first signal line portion is less than the material resistivity of the second signal line portion; the gate signal line layer further comprises a fourth signal line portion of the data signal line, and the source-drain electrode layer further comprises a third signal line portion of the data signal line; in the same data signal line, the adjacent third signal line portion is connected to the fourth signal line portion through a second via hole; the orthographic projections of the third signal line portion and the first signal line portion on the array substrate of the display substrate have no overlapping portion, and the orthographic projections of the fourth signal line portion and the first signal line portion on the array substrate have overlapping portions. By designing the first signal line portion in the gate signal line, compared with the related art in which the gate signal line is only formed by the material of the second signal line portion, the resistance of the gate signal line can be reduced, the attenuation and delay of the gate signal can be improved, and the abnormal display problem of the display screen can be improved.

[0035] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0037] Figure 1a It is a schematic diagram of the first structure of a display panel in the related art;

[0038] Figure 1b It is a second structural schematic diagram of a display panel in the related art;

[0039] Figure 2 A waveform diagram of gate signal attenuation in the related art;

[0040] Figure 3a A schematic diagram of a top view structure of a display substrate in the related art;

[0041] Figure 3b A schematic diagram of a stacking structure of a display substrate in the related art;

[0042] Figure 4a A first schematic top view of a display substrate provided in an embodiment of the present application;

[0043] Figure 4b for Figure 4a Schematic diagram of the stacking structure of the structure shown in the AA' direction;

[0044] Figure 4c for Figure 4a Schematic diagram of the stacking structure of the structure shown in the BB' direction;

[0045] Figure 5 A second schematic top view of a display substrate provided in an embodiment of the present application;

[0046] Figure 6 A third schematic top view of the display substrate provided in an embodiment of the present application;

[0047] Figure 7 A schematic diagram of a stacking structure of a display substrate provided in an embodiment of the present application;

[0048] Figure 8 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0050] With the continuous development of the liquid crystal display industry, the forms of display products are becoming increasingly diverse. In order to improve the user experience, display products of all forms have a trend of increasing in size, among which the car screen is the most prominent. Most car screens are horizontally designed, and with the development of car screens, car screens are gradually turning to integration, which makes the length of car screens longer and longer. Correspondingly, the resistance of the gate signal line is getting larger and larger, and the gate signal transmitted through the gate signal line will be attenuated and delayed, resulting in abnormal display problems on the screen.

[0051] Specifically, Figure 1a and Figure 1b As shown, the gate signal line of the LCD panel is designed in the row direction and is controlled by GOA (Gate Driver on Array) and is turned on row by row for scanning. The data signal line of the LCD panel is designed in the column direction. Usually, when the corresponding row gate signal line is turned on, the data write transistor of each sub-pixel in the row is turned on, and the data signal of the data signal line is written into the pixel electrode through the data write transistor. There is a voltage difference between the storage capacitor formed by the pixel electrode and the common electrode, and the storage capacitor is charged. The pixel corresponds to the liquid crystal deflection, and the backplane is transparent to the display screen. Therefore, when the length of the screen becomes longer and longer, the resistance of the gate signal line becomes larger and larger, and the gate signal transmitted through the gate signal line will be attenuated and delayed, such as Figure 2 As shown, the data writing transistor of the sub-pixel is insufficiently driven, that is, the transistor is not turned on well, which leads to abnormal display problems such as uneven display on the screen.

[0052] In order to ensure good image quality of the long horizontal display screen, it is crucial to reduce the resistance of the gate signal line. According to the formula R=ρ×L / S (ρ is the material resistivity, L is the material length, S is the material cross-sectional area, and R is the material resistance), the resistance of the gate signal line is usually reduced by reducing the material resistivity, reducing the wiring length, and increasing the wiring cross-sectional area. However, the above-mentioned means of reducing resistance all have corresponding restrictions. Replacing the material of the gate signal line may lead to the complication of the process and increase the cost. Reducing the length of the gate signal line is limited by the size of the display product, and increasing the cross-sectional area of ​​the gate signal line is limited by the characteristics of the display product and the pixel aperture ratio.

[0053] Taking the NMOS (Metal-Oxide-Semiconductor Field-Effect Transistor) pixel structure where the source and drain of the transistor are located on the left and right sides of its own gate as an example, the sub-pixels in the display area of ​​the display panel are arranged in an array, and the gate signal line and the data signal line intersect vertically. Figure 3a The gate of the sub-pixel and the gate signal line are made of the same material, and the gate of the sub-pixel and the gate signal line are connected in an "integrated" manner. The resistivity of the sub-pixel gate material cannot be too small, while the data signal line is made of another material. In order to match the best effect of pixel charging, the resistivity of the material selected for the data signal line is much smaller than that of the gate signal line material. The sub-pixel adopts a top-gate structure, which can be seen in Figure 3b The gate and gate signal line (set in the gate signal line layer) are located above the active layer, and the data signal line (set in the source-drain electrode layer) is located above the gate signal line. The gate signal line and the data signal line are separated by an insulating layer. In addition to the insulating function, the insulating layer also determines the color of the display panel. It is generally made of SiN X The stacked structure formed by SiO2 (silicon nitride) and SiO2 (silicon dioxide) has a thickness of about 5000 angstroms (angstroms are the units of thickness, 1 nanometer = 10 angstroms), so the flattening effect is limited. In order to reduce the risk of breakage of the data signal line at the intersection with the gate signal line, the thickness of the gate signal line cannot be made very thick.

[0054] At the same time, the gate signal line is formed by wet etching, and the bias of wet etching is used to form the LDD (Lightly Doped Drain) channel of NMOS. For device tolerance, the channel length of the LDD channel is required to be at least not less than 0.75 microns. The channel length of the LDD channel limits the thickness of the gate signal line (the greater the thickness, the greater the bias, and the smaller the channel length). In order to form the correct transistor size, the thickness of the gate signal line cannot be made very thick, and is generally around 3000 angstroms.

[0055] In summary, when the material resistivity is high, the thickness cannot be thickened, and the display product size is limited, the resistance of the gate signal line is relatively fixed. For example, for a 16-inch horizontal screen, the resistance of the gate signal line will be tens of kilo-ohms, which is very unfavorable for pixel charging. The corresponding resistance of the data signal line of the same size is much smaller, about 0.133% of the gate signal line. However, if the gate signal line and the data signal line are interchanged in material, the pixel charging will be worse, close to a passive state.

[0056] On the other hand, the entire gate signal line of the display area of ​​the display panel is a "large resistance and long trace" structure. During the manufacturing process and subsequent product use, static electricity accumulation and slow static electricity release may occur. When the static electricity cannot be fully released, it may cause damage to the transistor, thereby causing various problems.

[0057] In order to reduce the resistance of the gate signal line and improve the abnormal display problem of the display screen, the embodiment of the present application provides a display substrate and a display device.

[0058] Next, the display substrate provided in the embodiment of the present application is described in detail. Figure 4a , Figure 4b and Figure 4c , Figure 4a A first schematic top view of the display substrate 1 provided in an embodiment of the present application (a schematic top view based on a stacking structure), Figure 4b for Figure 4a Schematic diagram of the stacking structure of the structure shown in the AA' direction, Figure 4c for Figure 4a The schematic diagram of the stacking structure of the structure shown in the BB' direction shows that the substrate 1 includes:

[0059] Gate signal line layer 11, source-drain electrode layer 12;

[0060] The gate signal line layer 11 includes a second signal line portion 111 of the gate signal line, and the source-drain electrode layer 12 includes a first signal line portion 121 of the gate signal line;

[0061] In the same gate signal line, the second signal line portion 111 in the gate signal line layer 11 is connected to the first signal line portion 121 in the source-drain electrode layer 12 through the first via 171;

[0062] The material resistivity of the first signal line portion 121 is less than the material resistivity of the second signal line portion 111;

[0063] The gate signal line layer 11 further includes a fourth signal line portion 112 of the data signal line, and the source-drain electrode layer 12 further includes a third signal line portion 122 of the data signal line;

[0064] In the same data signal line, the adjacent third signal line portion 122 and the fourth signal line portion 112 are connected through the second via 172;

[0065] The orthographic projections of the third signal line portion 122 and the first signal line portion 121 on the array substrate 13 of the display substrate 1 have no overlapping portion, and the orthographic projections of the fourth signal line portion 112 and the first signal line portion 121 on the array substrate 13 have overlapping portions.

[0066] In the embodiment of the present application, by designing the first signal line portion 121 in the gate signal line, compared with the gate signal line in the related art that is formed only by the material of the second signal line portion 111, the resistance of the gate signal line can be reduced, the attenuation and delay of the gate signal can be improved, and the abnormal display problem of the display screen can be improved. In addition, for the position where the first signal line portion 121 intersects with the data signal line, the fourth signal line portion 112 of the data signal line is used to perform jumper insulation treatment at this position, thereby improving the problem of metal short circuit on the same layer.

[0067] In a possible implementation, see Figure 4a , Figure 4b and Figure 4c The same gate signal line includes a plurality of second signal line portions 111 and a first signal line portion 121 , and each second signal line portion 111 of the same gate signal line is connected to the first signal line portion 121 through a first via 171 .

[0068] It should be noted that the projections described below are all orthographic projections on the array substrate 13 .

[0069] Each gate signal line in the embodiment of the present application is composed of a first signal line portion 121 and a plurality of second signal line portions 111. The second signal line portion 111 is a wiring for transmitting gate signals in the related art, and the first signal line portion 121 is a wiring for transmitting gate signals newly added in the source-drain electrode layer 12 (when performing the mask process, the gate signal line portions between sub-pixels in the related art are disconnected to form a plurality of second signal line portions 111, each second signal line portion 111 is connected to the first signal line portion 121 through a first via 171, and the first signal line portion 121 is connected in parallel to the disconnected plurality of second signal line portions 111 as a gate signal compensation line).

[0070] The data signal line in the present application is composed of a third signal line portion 122 and a fourth signal line portion 112. The third signal line portion 122 is a routing line for transmitting data signals in the related art, and the fourth signal line portion 112 is a routing line for transmitting data signals newly added in the gate signal line layer 11 (since the first signal line portion 121 is in the source-drain electrode layer 12, if the data signal line is not jumpered, there will be a problem of metal short circuit in the same layer. For the position where the first signal line portion 121 intersects with the data signal line, the fourth signal line portion 112 of the data signal line is jumpered and insulated at this position, which can improve the problem of metal short circuit in the same layer. The fourth signal line portion 112 is connected to the adjacent third signal line portion 122 through the second via 172).

[0071] The material of the first signal line portion 121 can be the same as the material of the third signal line portion 122 , or other materials can be selected. The material selection principle is based on the premise of not increasing the mask cost.

[0072] The material of the fourth signal line portion 112 may be the same as that of the second signal line portion 111 .

[0073] In one possible implementation, the material of the first signal line portion 121 is the same as the material of the third signal line portion 122, and the material of the fourth signal line portion 112 is the same as the material of the second signal line portion 111, so that the capacitance at the overlapping position of the gate signal line and the data signal line does not change (in the related art, the gate signal line in the gate signal line layer overlaps with the data signal line in the source-drain electrode layer, and in the present application, the first signal line portion 121 in the source-drain electrode layer 12 overlaps with the fourth signal line portion 112 in the gate signal line layer 11).

[0074] Understandably, Figure 4a , Figure 4b and Figure 4c The structure is illustrated in that the drain and source of the data writing transistor are arranged on both sides of its own gate in the row direction of the display substrate 1 .

[0075] Understandably, Figure 4a , Figure 4b and Figure 4c It is only a partial illustration.

[0076] In the embodiment of the present application, the gate signal line portion between the sub-pixels in the related art is disconnected (the fourth signal line portion 112 is in the gate signal line layer 11, and the disconnection can improve the problem of metal short circuit in the same layer), and a plurality of second signal line portions 111 are formed, each of which is connected to the first signal line portion 121 through the first via 171, and the first signal line portion 121 is connected in parallel to the disconnected plurality of second signal line portions 111 as a gate signal compensation line (the material resistivity of the first signal line portion 121 is less than the material resistivity of the second signal line portion 111, and the gate signal is transmitted through the first signal line portion 121), which can reduce the resistance of the gate signal line without increasing the mask cost, improve the attenuation and delay of the gate signal, and improve the abnormal display problem of the display screen. Moreover, the second signal line portion 111 is a short wiring structure, which is not easy to accumulate electrostatic charge. Although the first signal line portion 121 is a long wiring structure, it has a low resistivity, a small resistance of the long wiring structure, and a strong ability to conduct away electrostatic charge, which can improve the electrostatic accumulation problem in the related art and reduce the damage of the transistor. Furthermore, for the intersection of the first signal line portion 121 and the data signal line, the fourth signal line portion 112 of the data signal line is used to perform jumper insulation processing at the intersection, thereby improving the problem of metal short circuit on the same layer.

[0077] In one possible implementation, see Figure 4a ,

[0078] In the column direction of the display substrate 1, the first width d1 of the first signal line portion 121 is smaller than the second width d2 of the first signal line portion 121; wherein the first width d1 is the width of the first signal line portion 121 at a position where the projection overlaps with the fourth signal line portion 112, and the second width d2 is the width of the first signal line portion 121 at a portion where the projection does not overlap with the fourth signal line portion 112.

[0079] In the column direction of the display substrate 1 , the width of the first signal line portion 121 becomes thinner at a position where it overlaps with the projection of the fourth signal line portion 112 , and the first signal line portion 121 presents a step shape.

[0080] In the embodiment of the present application, by reducing the width of the projected overlapping position of the first signal line portion 121 and the fourth signal line portion 112, the short circuit problem between the first signal line portion 121 and the third signal line portion 122 can be further improved, and the usage ratio of the fourth signal line portion 112 can be reduced, thereby ensuring the low resistivity of the data signal line and ensuring the display quality of the display screen.

[0081] In one possible implementation,

[0082] The i-th second signal line portion 111 of the N-th gate signal line corresponds to the i-th sub-pixel in the N-th row of pixel units;

[0083] or,

[0084] The i-th second signal line portion 111 of the N-th gate signal line corresponds to the 2i-1-th and 2i-th sub-pixels in the N-th row of pixel units;

[0085] or,

[0086] The i-th second signal line portion 111 of the N-th gate signal line corresponds to the 3i-2-th, 3i-1-th and 3i-th sub-pixels in the N-th row of pixel units;

[0087] Wherein, N is an integer not less than 1, and i is an integer not less than 1.

[0088] There are many ways to disconnect the gate signal line portion between sub-pixels. The disconnection method can be set according to the pixel size. The gate signal line portion between each sub-pixel can be disconnected once, the gate signal line portion between every two sub-pixels can be disconnected once, the gate signal line portion between every three sub-pixels can be disconnected once, and so on. If there is relatively sufficient space, the gate signal line portion between each sub-pixel can be disconnected once. In the same gate signal line, each second signal line portion 111 is connected to the first signal line portion 121 through the first via 171, and the gate 113 of the data writing transistor of each sub-pixel is "integrated" with the corresponding second signal line portion 111, that is, each sub-pixel obtains a gate signal from the first signal line portion 121, and transmits the gate signal using the first signal line portion 121 with a very small resistivity, so that each sub-pixel has a sufficient gate voltage, the switching of the sub-pixel is fully controlled, and the control effect of the gate signal is in an optimal state.

[0089] For the mode where the gate signal line portion between every two sub-pixels is disconnected once, each second signal line portion 111 is connected to the first signal line portion 121 through the first via hole 171, but each second signal line portion 111 is "integrated" with the gate 113 of the data writing transistor of the two sub-pixels. At this time, the data signal line cannot be jumped with the help of the gate signal line layer 11, but can be jumped with the help of other film layers.

[0090] For the mode where the gate signal line portion between every three sub-pixels is disconnected once, each second signal line portion 111 is connected to the first signal line portion 121 through the first via hole 171, but each second signal line portion 111 is "integrated" connected to the gate 113 of the data writing transistor of the three sub-pixels. At this time, the data signal line cannot be jumped with the help of the gate signal line layer 11, but can be jumped with the help of other film layers.

[0091] In a possible implementation, see Figure 4a ,

[0092] In the column direction of the display substrate 1 , a preset distance is arranged between the drain of the data writing transistor of each sub-pixel in the Nth row of pixel units and the Nth gate signal line.

[0093] The first signal line portion 121 is used as a gate signal compensation line and is designed on the same layer as the third signal line portion 122 of the data signal line and the drain 123 of the data writing transistor (the drain 123 is arranged in the source-drain electrode layer 12). A preset distance must be set between the drain 123 and the first signal line portion 121 to avoid overlap between the first signal line portion 121 and the drain 123, so as to prevent the formation of coupling capacitance.

[0094] In the embodiment of the present application, by setting a preset distance between the drain 123 and the first signal line portion 121 , it is possible to avoid overlap between the first signal line portion 121 and the drain 123 , thereby preventing the formation of coupling capacitance.

[0095] In a possible implementation, see Figure 4a In the row direction of the display substrate 1 , for each sub-pixel data writing transistor, the drain 123 and the source 124 of the data writing transistor are arranged on both sides of its own gate 113 .

[0096] exist Figure 4a In the structure shown, the gate 113 of the data write transistor and the second signal line portion 111 are "integrated" into an inverted "F" shape, the drain 123 and the source 124 of the data write transistor are connected through a via and an active layer 15 (the orthographic projection of the active layer 15 on the array substrate 13 intersects with the orthographic projection of the gate 113 on the array substrate 13), the source 124 (the source 124 is arranged in the source-drain electrode layer 12) is connected to the data signal line, and the drain 123 is connected to the relevant transistor.

[0097] Understandably, Figure 4a The figure shows a data writing transistor of a target sub-pixel.

[0098] In one possible implementation, see Figure 5 In the column direction of the display substrate 1 , for the data writing transistor of each sub-pixel, the drain 123 and the source 124 of the data writing transistor are arranged on one side of its own gate 113 .

[0099] exist Figure 5 In the structure shown, the gate 113 of the data write transistor and the second signal line portion 111 are "integrated" in the shape of a letter "I", the orthographic projection of the gate 113 on the array substrate 13 is included in the orthographic projection of the first signal line portion 121 on the array substrate 13, the drain 123 and the source 124 of the data write transistor are connected through a via and an active layer 15 (the orthographic projection of the active layer 15 on the array substrate 13 intersects with the orthographic projection of the gate 113 on the array substrate 13), the source 124 (the source 124 is arranged in the source-drain electrode layer 12) is connected to the data signal line, and the drain 123 is connected to the relevant transistor.

[0100] Understandably, Figure 5 The figure shows a data writing transistor of a target sub-pixel.

[0101] In one possible implementation, see Figure 6In the column direction of the display substrate 1 , for the data writing transistor of each sub-pixel, the drain 123 and the source 124 of the data writing transistor are arranged on both sides of its own gate 113 .

[0102] exist Figure 6 In the structure shown, the gate 113 of the data write transistor and the second signal line portion 111 are "integrated" in a "T" shape, a part of the orthographic projection of the gate 113 on the array substrate 13 is included in the orthographic projection of the first signal line portion 121 on the array substrate 13, the drain 123 and the source 124 of the data write transistor are connected through a via and an active layer 15 (the orthographic projection of the active layer 15 on the array substrate 13 intersects with the orthographic projection of the gate 113 on the array substrate 13), the source 124 (the source 124 is arranged in the source-drain electrode layer 12) is connected to the data signal line, and the drain 123 is connected to the relevant transistor.

[0103] Understandably, Figure 6 The figure shows a data writing transistor of a target sub-pixel.

[0104] In one possible implementation, see Figure 7 The display substrate 1 further includes: an array substrate 13, a first insulating layer 14, an active layer 15, a second insulating layer 16, and a third insulating layer 17;

[0105] The first insulating layer 14 is arranged on the array substrate 13, the active layer 15 is arranged on a side of the first insulating layer 14 away from the array substrate 13, the second insulating layer 16 is arranged on a side of the active layer 15 away from the array substrate 13, the gate signal line layer 11 is arranged on a side of the second insulating layer 16 away from the array substrate 13, the third insulating layer 17 is arranged on a side of the gate signal line layer 11 away from the array substrate 13, and the source-drain electrode layer 12 is arranged on a side of the third insulating layer 17 away from the array substrate 13.

[0106] In a possible implementation, based on the gate signal line provided in the present application, the film thickness of the gate signal line can be appropriately thinned according to actual conditions to reduce the strength of the LDD channel edge electric field and increase the life of the pixel electrode.

[0107] The present application also provides a display device 2, see Figure 8 , the display device 2 includes a display substrate 1 as described in any of the above embodiments.

[0108] The display device 2 may be a vehicle-mounted display screen, a computer display screen, or other types of display screens, etc., and this application does not make any specific limitation on this.

[0109] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0110] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0111] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A display substrate, characterized in that: The display substrate comprises: Gate signal line layer, source and drain electrode layer; The gate signal line layer includes a second signal line portion of the gate signal line, and the source-drain electrode layer includes a first signal line portion of the gate signal line; In the same gate signal line, the second signal line portion in the gate signal line layer is connected to the first signal line portion in the source-drain electrode layer through a first via hole; The material resistivity of the first signal line portion is less than the material resistivity of the second signal line portion; The gate signal line layer further includes a fourth signal line portion of the data signal line, and the source-drain electrode layer further includes a third signal line portion of the data signal line; In the same data signal line, the adjacent third signal line portion and the fourth signal line portion are connected through the second via hole; The orthographic projections of the third signal line portion and the first signal line portion on the array substrate of the display substrate have no overlapping portion, and the orthographic projections of the fourth signal line portion and the first signal line portion on the array substrate have an overlapping portion.

2. The display substrate according to claim 1, characterized in that: The same gate signal line includes a plurality of second signal line portions and a first signal line portion, and each second signal line portion of the same gate signal line is connected to the first signal line portion through a first via hole.

3. The display substrate according to claim 2, characterized in that: In the column direction of the display substrate, the first width of the first signal line portion is smaller than the second width of the first signal line portion; wherein the first width is the width of the first signal line portion at a position where the projection overlaps with the fourth signal line portion, and the second width is the width of the first signal line portion where there is no projection overlap with the fourth signal line portion.

4. The display substrate according to claim 2, characterized in that: The i-th second signal line portion of the N-th gate signal line corresponds to the i-th sub-pixel in the N-th row of pixel units; or, The i-th second signal line portion of the N-th gate signal line corresponds to the 2i-1-th and 2i-th sub-pixels in the N-th row of pixel units; or, The i-th second signal line portion of the N-th gate signal line corresponds to the 3i-2-th, 3i-1-th and 3i-th sub-pixels in the N-th row of pixel units; Wherein, N is an integer not less than 1, and i is an integer not less than 1.

5. The display substrate according to claim 4, characterized in that: In the column direction of the display substrate, a preset distance is arranged between the drain of the data writing transistor of each sub-pixel in the Nth row of pixel units and the Nth gate signal line.

6. The display substrate according to claim 5, characterized in that: In the row direction of the display substrate, for the data writing transistor of each sub-pixel, the drain and source of the data writing transistor are arranged on both sides of its own gate.

7. The display substrate according to claim 5, characterized in that: In the column direction of the display substrate, for the data writing transistor of each sub-pixel, the drain and source of the data writing transistor are arranged on one side of its own gate.

8. The display substrate according to claim 5, characterized in that: In the column direction of the display substrate, for the data writing transistor of each sub-pixel, the drain and source of the data writing transistor are arranged on both sides of its own gate.

9. The display substrate according to claim 2, characterized in that: The display substrate further comprises: an array substrate, a first insulating layer, an active layer, a second insulating layer, and a third insulating layer; The first insulating layer is arranged on the array substrate, the active layer is arranged on a side of the first insulating layer away from the array substrate, the second insulating layer is arranged on a side of the active layer away from the array substrate, the gate signal line layer is arranged on a side of the second insulating layer away from the array substrate, the third insulating layer is arranged on a side of the gate signal line layer away from the array substrate, and the source-drain electrode layer is arranged on a side of the third insulating layer away from the array substrate.

10. A display device, characterized in that: The display device comprises the display substrate as claimed in any one of claims 1 to 9.

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