A power device layout structure and manufacturing method thereof

Abstract

The present application relates to the field of semiconductor technology, and provides a power device layout structure and a manufacturing method thereof, wherein the power device layout structure includes a plurality of cells repeatedly arranged along a first direction and a second direction, wherein the cells include: a P-type well region doping region, an N-type heavily doped region, a P-type heavily doped region, a JFET region doping region, a gate and a source through hole, wherein the first main island portion of each cell is connected to the first auxiliary arm of the cell adjacent in the first direction, and the first auxiliary arm of each cell and the first auxiliary arm of an adjacent cell in the second direction are the same auxiliary arm that overlap with each other; the gate is a split gate structure, covering the edge or all of the JFET region doping region, the P-type well region doping region and the N-type heavily doped region. The present application effectively solves the technical problem of low channel density of planar power devices; while increasing the channel density, it does not increase too much gate-drain capacitance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power device layout structure and a manufacturing method thereof. Background Art

[0002] At present, mainstream power devices usually use multiple cells in parallel to reduce on-resistance, but the increase in the number of parallel cells will lead to an increase in chip area and cost. In order to reduce costs and obtain lower on-resistance in the same area, increasing the channel density of the device becomes the key. Under the same manufacturing process, the total channel width of the device is an important factor in determining the on-resistance.

[0003] The difference in cells and their layout directly affects the channel density in the device. Through calculation, it is found that the channel density of the traditional stripe layout is low, while the square, field, triangle, H-shaped and hexagonal dense packing layout can effectively increase the channel density, thereby reducing the on-resistance, but these layouts still have room for improvement. In addition, this type of layout increases the number of gates, resulting in a sharp increase in gate-drain capacitance, which in turn reduces the high-frequency characteristics of the device.

[0004] Chinese invention patent CN108899319B discloses a layout structure and layout method for increasing the channel density of VDMOS, the layout structure includes a plurality of cells repeatedly arranged along the first direction and the second direction: each cell may include: a first trench gate, a second trench gate, a third trench gate and a contact hole; wherein in the repeatedly arranged structure, the second trench gate of each cell and the first trench gate of an adjacent cell in the first direction are the same trench gates that overlap with each other; that is, the repeated structure can be considered to include: a first trench gate, a third trench gate and a contact hole. The invention can adjust the space to be small, the channel density to be small, and the capacitance value to be large.

[0005] Chinese invention patent CN109698229B discloses a semiconductor power element, including an n-type drift layer; a plurality of first p-type doped regions arranged in the n-type drift layer, the first p-type doped region including a first p-type doped portion and a plurality of first p-type doped arms extending outward from the first p-type doped portion; a plurality of n-type doped regions arranged in the first p-type doped region, the n-type doped region including an n-type doped portion corresponding to the first p-type doped portion and a plurality of n-type doped arms extending outward from the n-type doped portion corresponding to the first p-type doped arms. Although the invention increases the channel density, the capacitance value is relatively large.

[0006] US Patent No. 11018228 discloses a silicon carbide semiconductor device, including a drift layer, a first doping region, a second doping region, a plurality of third doping regions, a gate insulating layer, a gate electrode and a source electrode. Through a specific structural design, such as a plurality of legs and arms of the first doping region, and a plurality of source portions and arms of the second doping region, the channel width density of the device can be significantly improved, thereby reducing the channel resistance and improving the device performance. The invention has aligned support arms, a small adjustable space, and a large capacitance value. Summary of the invention

[0007] In order to help solve the above technical problems, the present application provides a power device layout structure and a manufacturing method thereof.

[0008] In a first aspect, the present application provides a power device layout structure, which adopts the following technical solution:

[0009] A power device layout structure, wherein the power device layout structure comprises a plurality of cells repeatedly arranged along a first direction and a second direction, the cells comprising:

[0010] A P-type well region doping region includes a first auxiliary arm, a second auxiliary arm, a first main island portion, a second main island portion, a first auxiliary branch arm group, and a second auxiliary branch arm group. The first main island portion of each cell is connected to the first auxiliary arm of the cell adjacent in the first direction. The first auxiliary arm of each cell and the first auxiliary arm of a cell adjacent in the second direction are the same auxiliary arm that overlaps with each other. The first auxiliary branch arm group and the second auxiliary branch arm group adjacent in the second direction are the same auxiliary branch arm group. The first direction is a direction perpendicular to the first auxiliary arm, and the second direction is a direction parallel to the first auxiliary arm.

[0011] An N-type heavily doped region, wherein the N-type heavily doped region is disposed in the P-type well region doping region;

[0012] A P-type heavily doped region, wherein the P-type heavily doped region is disposed in the first main island portion and the second main island portion;

[0013] A JFET region doping region, wherein the JFET region doping region is between the first auxiliary arm and the second auxiliary arm;

[0014] The gate and source through holes are split gate structures, covering the edges or all of the JFET region doping region, the P-type well region doping region and the N-type heavily doped region, and the splitting spacing h of the split gate structure is greater than or equal to 0.

[0015] Preferably, the splitting spacing h is greater than or equal to 1 um and less than or equal to 5 um.

[0016] Preferably, one end of the first main island part is connected to the first auxiliary arm, and the other end is connected to the first auxiliary support arm group, the second main island part is arranged between the first auxiliary arm and the first auxiliary support arm group, one end of the second main island part is connected to the second auxiliary arm, and the first auxiliary support arm group and the second auxiliary support arm group are symmetrically arranged on both sides of the second main island part.

[0017] Preferably, the first auxiliary arm and the second auxiliary arm are both in the shape of long strips, the P-type well region doping area extends a channel relative to the N-type heavily doped area, the P-type heavily doped area is arranged in the middle area between the first main island part and the second main island part, the source through hole is arranged above the P-type well region doping area and overlaps with the N-type heavily doped part, and there is a source-gate distance d with the gate, and the source-gate distance d is greater than or equal to 0.2um and less than or equal to 1um.

[0018] Preferably, the widths of the first main island portion and the second main island portion are both c and are calculated in the following manner:

[0019] c=e+2d+2f, where e is the width of the source through hole, d is the source-gate distance, and f is the width of the gate covering the doped region of the P-type well region;

[0020] The lengths of the first main island portion and the second main island portion are both g and are calculated as follows:

[0021] g=n×b+(n+1)×a, where n is an integer greater than or equal to 1, b is the width of the doped region of the P-type well region, the distance between the first auxiliary arm and the second auxiliary arm, the distance between the first main island part and the second auxiliary arm, the distance between the first auxiliary branch arm group and the second main island part, and the distance between the second auxiliary branch arm group and the second main island part are all a.

[0022] Preferably, the first auxiliary support arm group includes a first auxiliary support arm, and the second auxiliary support arm group includes a second auxiliary support arm.

[0023] Preferably, the first auxiliary support arm group includes two parallel first auxiliary support arms, and the second auxiliary support arm group includes two parallel second auxiliary support arms.

[0024] Preferably, the first auxiliary arm group includes a first auxiliary arm, the second auxiliary arm group includes two parallel second auxiliary arms, and a third auxiliary arm is connected to a side of the second main island portion close to the first main island portion.

[0025] In a second aspect, the present application provides a method for manufacturing a power device layout structure as described in any one of the first aspects, using the following technical solution:

[0026] A method for manufacturing a power device layout structure as described in any one of the first aspects above, wherein the manufacturing method comprises:

[0027] Providing a wafer including a substrate and an N-type drift layer;

[0028] Doping the wafer, performing P-type well region doping, N-type heavy doping and P-type heavy doping respectively;

[0029] High temperature annealing of the doped wafer;

[0030] forming an oxide layer, a polysilicon gate layer and an interlayer dielectric layer on the wafer;

[0031] forming a source via layer and a metal silicide layer;

[0032] Deposition of top metal and interlayers completes the device fabrication.

[0033] Preferably, the wafer is doped, and P-type well region doping, N-type heavy doping and P-type heavy doping are performed respectively, including: JFET region doping is performed.

[0034] In summary, the present application provides a power device layout structure and a manufacturing method thereof, which effectively solve the technical problem of low channel density of planar power devices; by providing a new cellular layout structure, a larger total channel width can be achieved within the same area, that is, the channel density is increased without increasing too much gate-drain capacitance; the width of the auxiliary arm can be flexibly adjusted according to the application requirements of the device, so as to choose whether to adopt a split gate form to reduce the gate-drain capacitance, and increase the length or number of the auxiliary arms to increase the channel density; the technical effect of increasing more channel density while increasing less gate-drain capacitance can be better achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic structural diagram of a first embodiment of a power device layout structure of the present application;

[0036] Figure 2 for Figure 1 A schematic diagram of the structure of a cell in the embodiment shown;

[0037] Figure 3 A schematic structural diagram of a second embodiment of a power device layout structure of the present application;

[0038] Figure 4 for Figure 3 A schematic diagram of the structure of a cell in the embodiment shown;

[0039] Figure 5 A schematic structural diagram of a third embodiment of a power device layout structure of the present application;

[0040] Figure 6 for Figure 5 A schematic diagram of the structure of a cell in the embodiment shown;

[0041] Figure 7 The present invention is a flow chart of an embodiment of a method for manufacturing a power device layout structure of the present invention.

[0042] Figure markings: 10-P-type well region doping region; 11-first auxiliary arm; 12-second auxiliary arm; 13-first main island portion; 14-first auxiliary branch arm; 15-second auxiliary branch arm; 16-second main island portion; 17-third auxiliary branch arm; 20-N-type heavily doped region; 30-P-type heavily doped region; 40-JFET region doping region. DETAILED DESCRIPTION

[0043] The present application is further described below in conjunction with the accompanying drawings, and the structure and principle of the present application are very clear to people in the field. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0044] Figure 1 is a schematic structural diagram of a first embodiment of a power device layout structure of the present application, Figure 2 for Figure 1 Schematic diagram of the structure of the cell in the embodiment shown. In this embodiment, the power device layout structure of the present application includes a plurality of cells repeatedly arranged along the first direction and the second direction, and the cell includes a P-type well region doping region 10, an N-type heavily doped region 20, a P-type heavily doped region 30, a JFET region doping region 40, a gate (not shown in the figure) and a source through hole (not shown in the figure).

[0045] Specifically, the P-type well doping region 10 includes a first auxiliary arm 11, a second auxiliary arm 12, a first main island portion 13, a second main island portion 16, a first auxiliary arm group and a second auxiliary arm group. One end of the first main island portion 13 is connected to the first auxiliary arm 11, and the other end is connected to the first auxiliary arm group. The second main island portion 16 is arranged between the first auxiliary arm 11 and the first auxiliary arm group. One end of the second main island portion 16 is connected to the second auxiliary arm 12. The first auxiliary arm group and the second auxiliary arm group are symmetrically arranged on both sides of the second main island portion 16. The first auxiliary arm 11 and the second auxiliary arm 12 are both long strips. In this embodiment, the first auxiliary arm group includes a first auxiliary arm 14, and the second auxiliary arm group includes a second auxiliary arm 15.

[0046] The first main island portion 13 of each cell is connected to the first auxiliary arm 11 of the cell adjacent in the first direction, the first auxiliary arm 11 of each cell and the first auxiliary arm 11 of an adjacent cell in the second direction are the same auxiliary arm that overlaps with each other, the first auxiliary branch arm 14 group and the second auxiliary branch arm 15 group adjacent in the second direction are the same auxiliary branch arm group, the first direction is a direction perpendicular to the first auxiliary arm 11, and the second direction is a direction parallel to the first auxiliary arm 11.

[0047] The N-type heavily doped region 20 is arranged in the P-type well doping region 10, and the P-type well doping region 10 extends a channel relative to the N-type heavily doped region 20, and its channel length Lch ranges from 0.2um to 1um; the P-type heavily doped region 30 is arranged in the first main island part 13 and the second main island part 16, and the P-type heavily doped region 30 is arranged in the middle area between the first main island part 13 and the second main island part 16; the JFET region doping region 40, the JFET region doping region 40 is between the first auxiliary arm 11 and the second auxiliary arm 12; the source through hole is arranged above the P-type well doping region 10 and overlaps with the N-type heavily doped part, and there is a source-gate distance d with the gate, the source-gate distance d is greater than or equal to 0.2um and less than or equal to 1um, and there is a certain distance between the source through hole and the gate to prevent gate-source short circuit, and the source-gate distance d is generally defined by the foundry as the minimum size.

[0048] Channel density refers to the total length of channels distributed per unit area. In semiconductor devices, channel density refers to the number or total length of channels per unit area. In a split-gate structure, the gate bar is split into two or more parts, leaving an open area in the middle that is not covered by the gate bar. This structure causes the channel to bend or narrow at the opening area, thereby changing the effective length of the channel and affecting the channel density.

[0049] The gate-drain capacitance is the capacitance between the gate and the drain. It is one of the important parameters that affect the performance of semiconductor devices, such as switching speed, power consumption and stability. The split-gate structure reduces the gate-drain capacitance by reducing the overlap size between the gate electrode and the drain. Since the gate bar is split into two or more parts, there is an open area in the middle that is not covered by the gate bar, which weakens the capacitive coupling between the gate and the drain, thereby reducing the gate-drain capacitance. Smaller gate-drain capacitance can speed up the switching speed of the device, reduce power consumption and improve stability.

[0050] The gate of the present application is a split gate structure, covering the edge or all of the JFET region doping region 40, the P-type well region doping region 10 and the N-type heavily doped region 20. The split gate structure has a split spacing h, where h is greater than or equal to 0. When h is equal to 0, it means that the gate completely covers the JFET region doping region 40, the P-type well region doping region 10 and the N-type heavily doped region 20.

[0051] When the P-type well doping region 10 and the JFET doping region 40 are narrower, the so-called narrower means that the spacing between the gates split above the middle of the P-type well doping region 10 or the JFET doping region 40 is smaller than the minimum spacing set by the foundry, then a higher channel density can be obtained.

[0052] When the P-type well doping region 10 and the JFET doping region 40 are relatively wide, the gate split in the middle can be greater than or equal to the minimum spacing specified by the foundry, and the split gate combination method can be selected. At this time, the gate is only located at the edge of the P-type well doping region 10 and the N-type heavily doped region 20 to match it. In this case, the gate-drain capacitance can be reduced. Therefore, a more suitable range is given in this embodiment, so that the power device layout structure of the present application can reduce more gate-drain capacitance while meeting the high channel density. The split spacing h of the present application is greater than or equal to 1um and less than or equal to 5um.

[0053] The widths of the first main island portion 13 and the second main island portion 16 are both c and are calculated as follows:

[0054] c=e+2d+2f, where e is the width of the source through hole, d is the source-gate distance, and f is the width of the gate covering the P-type well doping region 10;

[0055] The lengths of the first main island portion 13 and the second main island portion 16 are both g and are calculated as follows:

[0056] g=n×b+(n+1)×a, where n is an integer greater than or equal to 1, b is the width of the P-type well doping region 10, the distance between the first auxiliary arm 11 and the second auxiliary arm 12, the distance between the first main island portion 13 and the second auxiliary arm 12, the distance between the first auxiliary arm 14 group and the second main island portion 16, and the distance between the second auxiliary arm 15 group and the second main island portion 16 are all a. The width b of the P-type well doping region 10 is based on the minimum size defined by the foundry and the designer's setting. If it is too wide, the channel density will be reduced, and if it is too narrow, it will not meet the foundry's regulations. Therefore, this embodiment provides a more appropriate range, so that the channel density is improved while meeting the factory's regulations. The width b of the P-type well doping region 10 is greater than or equal to 1um and less than or equal to 5um. The main island portion is cross-located in the middle and on both sides of the auxiliary arm. This cross layout can increase the length of the auxiliary arm as much as possible, thereby effectively increasing the channel density.

[0057] Figure 3 is a schematic structural diagram of a second embodiment of a power device layout structure of the present application, Figure 4 for Figure 3 A schematic diagram of the structure of a cell in the embodiment shown. In this embodiment, the first auxiliary support arm 14 group includes two parallel first auxiliary support arms 14 , and the second auxiliary support arm 15 group includes two parallel second auxiliary support arms 15 .

[0058] Figure 5 is a schematic structural diagram of a third embodiment of a power device layout structure of the present application, Figure 6 for Figure 5 Schematic diagram of the structure of the cell in the embodiment shown. The first auxiliary arm 14 group includes a first auxiliary arm 14, the second auxiliary arm 15 group includes two parallel second auxiliary arms 15, and the second main island portion 16 is connected to a third auxiliary arm 17 on one side close to the first main island portion 13. The second embodiment and the third embodiment further improve the channel density by increasing the number of auxiliary arms.

[0059] Figure 7 This is a flow chart of an embodiment of a method for manufacturing a power device layout structure of the present application, the manufacturing method comprising:

[0060] Step S1: providing a wafer including a substrate and an N-type drift layer.

[0061] Step S2: doping the wafer, performing P-type well region doping, N-type heavy doping and P-type heavy doping respectively.

[0062] Step S3: performing high temperature annealing on the doped wafer.

[0063] Step S4: forming an oxide layer, a polysilicon gate layer and an interlayer dielectric layer on the wafer.

[0064] Step S5: forming a source via layer and a metal silicide layer.

[0065] Step S6: depositing the top metal layer and the interlayer to complete the device manufacturing.

[0066] The above step S2 may further include: performing doping on the JFET region; if not doped, the region is an N-type drift layer.

Claims

1. A power device layout structure, characterized in that: The power device layout structure includes a plurality of cells repeatedly arranged along a first direction and a second direction, and the cells include: A P-type well region doping region includes a first auxiliary arm, a second auxiliary arm, a first main island portion, a second main island portion, a first auxiliary branch arm group, and a second auxiliary branch arm group. The first main island portion of each cell is connected to the first auxiliary arm of the cell adjacent in the first direction. The first auxiliary arm of each cell and the first auxiliary arm of a cell adjacent in the second direction are the same auxiliary arm that overlaps with each other. The first auxiliary branch arm group and the second auxiliary branch arm group adjacent in the second direction are the same auxiliary branch arm group. The first direction is a direction perpendicular to the first auxiliary arm, and the second direction is a direction parallel to the first auxiliary arm. An N-type heavily doped region, wherein the N-type heavily doped region is disposed in the P-type well region doping region; A P-type heavily doped region, wherein the P-type heavily doped region is disposed in the first main island portion and the second main island portion; A JFET region doping region, wherein the JFET region doping region is between the first auxiliary arm and the second auxiliary arm; The gate and source through holes are split gate structures, covering the edges or all of the JFET region doping region, the P-type well region doping region and the N-type heavily doped region, and the splitting spacing h of the split gate structure is greater than or equal to 0.

2. The power device layout structure according to claim 1, characterized in that: The splitting distance h is greater than or equal to 1 um and less than or equal to 5 um.

3. The power device layout structure according to claim 1, characterized in that: One end of the first main island part is connected to the first auxiliary arm, and the other end is connected to the first auxiliary support arm group. The second main island part is arranged between the first auxiliary arm and the first auxiliary support arm group. One end of the second main island part is connected to the second auxiliary arm. The first auxiliary support arm group and the second auxiliary support arm group are symmetrically arranged on both sides of the second main island part.

4. The power device layout structure according to claim 3, characterized in that: The first auxiliary arm and the second auxiliary arm are both in the shape of long strips, the P-type well region doping area extends a channel relative to the N-type heavily doped area, the P-type heavily doped area is arranged in the middle area between the first main island part and the second main island part, the source through hole is arranged above the P-type well region doping area and overlaps with the N-type heavily doped part, and there is a source-gate distance d with the gate, and the source-gate distance d is greater than or equal to 0.2um and less than or equal to 1um.

5. The power device layout structure according to claim 4, characterized in that: The widths of the first main island portion and the second main island portion are both c and are calculated as follows: c=e+2d+2f, where e is the width of the source through hole, d is the source-gate distance, and f is the width of the gate covering the doped region of the P-type well region; The lengths of the first main island portion and the second main island portion are both g and are calculated as follows: g=n×b+(n+1)×a, where n is an integer greater than or equal to 1, b is the width of the doped region of the P-type well region, the distance between the first auxiliary arm and the second auxiliary arm, the distance between the first main island part and the second auxiliary arm, the distance between the first auxiliary branch arm group and the second main island part, and the distance between the second auxiliary branch arm group and the second main island part are all a.

6. The power device layout structure according to claim 5, characterized in that: The first auxiliary support arm group includes a first auxiliary support arm, and the second auxiliary support arm group includes a second auxiliary support arm.

7. The power device layout structure according to claim 5, characterized in that: The first auxiliary support arm group includes two parallel first auxiliary support arms, and the second auxiliary support arm group includes two parallel second auxiliary support arms.

8. The power device layout structure according to claim 5, characterized in that: The first auxiliary arm group includes a first auxiliary arm, the second auxiliary arm group includes two parallel second auxiliary arms, and a third auxiliary arm is connected to a side of the second main island portion close to the first main island portion.

9. A method for manufacturing a power device layout structure according to any one of claims 1 to 8, characterized in that: The manufacturing method comprises: Providing a wafer including a substrate and an N-type drift layer; Doping the wafer, performing P-type well region doping, N-type heavy doping and P-type heavy doping respectively; Performing high temperature annealing on the doped wafer; forming an oxide layer, a polysilicon gate layer and an interlayer dielectric layer on the wafer; forming a source via layer and a metal silicide layer; Deposition of top metal and interlayers completes the device fabrication.

10. The manufacturing method according to claim 9, characterized in that: The wafer is doped, and P-type well region doping, N-type heavy doping and P-type heavy doping are performed respectively, including: JFET region doping.

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