Double-phase lightweight asynchronous circuit based on time sequence borrowing and control method thereof

Abstract

The invention discloses a double-phase lightweight asynchronous circuit based on time sequence borrowing and a control method thereof. The circuit comprises a control path and a data path. The control access comprises a double-phase lightweight asynchronous controller and a lightweight asynchronous controller; the data path comprises a storage unit and a combinational logic unit. The method comprises the following steps: carrying out asynchronization processing based on a register circuit to obtain an asynchronized register circuit; carrying out distinguishing processing on the asynchronized register circuit based on time sequence constraint to obtain a distinguished register circuit; a double-phase lightweight asynchronous controller and a lightweight asynchronous controller are introduced, margin sensing asynchronous control processing is carried out on the distinguished register circuits, and time sequence pulse control signals are generated. According to the embodiment of the invention, the control signals with different pulse widths can be matched with the requirements of the latch, so that the execution efficiency of the instruction is improved, and the optimization of the power consumption and the area of the asynchronous circuit is realized. The method can be widely applied to the technical field of integrated circuit design.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a dual-phase lightweight asynchronous circuit based on timing borrowing and a control method thereof. Background Art

[0002] As the scale of integrated circuits continues to expand, the power consumption brought by the complex global clock network limits the development of synchronous circuits. Asynchronous circuits use handshake logic to replace global clocks, which has been proven to have the advantage of low power consumption. Among different types of asynchronous circuits, 2-phase data bundling has a wider application due to its lower area overhead. Compared with registers, latches have also been proven to have the advantage of low power consumption. In addition, latches also have the characteristics of timing borrowing, so they have the potential to increase the operating frequency of the circuit. Latches have more stringent requirements for their control signals. If the pulse width is too high, the latch faces a greater risk of holding time violation. If the pulse width is too low, the latch cannot fully exert the advantage of timing borrowing. However, the asynchronous circuit design methods in the related art are mostly register-oriented, and the control signals generated by the controllers at all levels cannot be properly controlled, that is, the pulse width of each latch cannot be controlled in a targeted manner, which makes it difficult to ensure the normal operation of the latch, and it is even more difficult to give full play to the low power consumption advantage and timing borrowing characteristics of the latch. In addition, its asynchronous control method cannot completely eliminate the adverse effects of the phase skew generated by the asynchronous handshake logic. The phase skew will aggravate the impact of the critical path on the circuit performance.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to propose a dual-phase lightweight asynchronous circuit based on timing borrowing and a control method thereof, which can match the requirements of the latch through two control signals with different pulse widths, thereby optimizing the power consumption and area of ​​the asynchronous circuit.

[0005] To achieve the above-mentioned purpose, an embodiment of the present application provides a dual-phase lightweight asynchronous circuit based on timing borrowing, wherein the circuit includes a control path and a data path, wherein the output end of the control path is connected to the input end of the data path, wherein:

[0006] The control path includes a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller, the dual-phase lightweight asynchronous controller and the lightweight asynchronous controller are connected via an asynchronous control chain, and the control path is used to generate a first asynchronous control signal and a second asynchronous control signal;

[0007] The data path includes a storage unit and a combinational logic unit, the storage units are connected through the combinational logic unit, the storage unit includes a common latch, a key latch and a memory, the data path is used for calculation and storage, and timing borrowing occurs under the control of the first asynchronous control signal and the second asynchronous control signal.

[0008] In some embodiments, the dual-phase lightweight asynchronous controller includes a multiplexer, an XOR gate, a first XOR gate, a second XOR gate, a first pulse control module and a second pulse control module, the first input end of the multiplexer obtains an input request signal, the second input end of the multiplexer is connected to the output end of the XOR gate, the first output end of the multiplexer, the first input end of the XOR gate, the first end of the first pulse control module, the second input end of the first XOR gate, the second output end of the multiplexer, the second end of the second pulse control module are connected to the first input end of the second XOR gate, the second end of the first pulse control module is connected to the first input end of the first XOR gate, the first end of the second pulse control module is connected to the second input end of the second XOR gate, the first output end of the multiplexer outputs an output request signal, the second output end of the multiplexer outputs an output response signal, and the second input end of the XOR gate obtains an input response signal, wherein:

[0009] The multiplexer is used to initialize the handshake signal and transmit the output request signal;

[0010] The XNOR gate is used to determine the phase of the output request signal and the phase of the input response signal;

[0011] The first XOR gate is used to generate the first asynchronous control signal;

[0012] The second XOR gate is used to generate the second asynchronous control signal;

[0013] The first pulse control module is used to adjust the clock pulse width of the first asynchronous control signal;

[0014] The second pulse control module is used to adjust the clock pulse width of the second asynchronous control signal.

[0015] In some embodiments, the control path further includes a delay unit, and the delay unit is used to control the phase difference between the first asynchronous control signal and the second asynchronous control signal.

[0016] In some embodiments, a clock pulse width of the first asynchronous control signal is greater than a clock pulse width of the second asynchronous control signal.

[0017] In some embodiments, the timing margin of the common latch is greater than the timing margin of the critical latch.

[0018] In some embodiments, the first asynchronous control signal is used to control the operation of the key latch, and the second asynchronous control signal is used to control the operation of the common latch and the memory.

[0019] To achieve the above object, another aspect of the embodiment of the present application provides a control method for a dual-phase lightweight asynchronous circuit based on timing borrowing, the method comprising the following steps:

[0020] Performing asynchronous processing based on the register circuit to obtain an asynchronous register circuit;

[0021] Performing differentiation processing on the asynchronous register circuit based on the timing constraint to obtain a differentiated register circuit, wherein the differentiated register circuit includes a common latch, a key latch and a memory;

[0022] A dual-phase lightweight asynchronous controller and a lightweight asynchronous controller are introduced to perform margin-aware asynchronous control processing on the differentiated register circuit to generate a timing pulse control signal.

[0023] In some embodiments, the performing differentiation processing on the asynchronous register circuit based on the timing constraint to obtain the differentiated register circuit includes:

[0024] Set time thresholds;

[0025] Obtain the timing lengths of the timing paths corresponding to several data paths through a timing constraint analysis tool;

[0026] If the timing length of the timing path corresponding to the data path is less than the time threshold, the storage unit is divided into a common latch and a memory;

[0027] If the timing length of the timing path corresponding to the data path is greater than the time threshold, the storage unit is distinguished as a critical latch;

[0028] The common latch, the memory and the key latch are integrated to obtain the differentiated register circuit.

[0029] In some embodiments, the introducing of the dual-phase lightweight asynchronous controller and the lightweight asynchronous controller, performing margin-aware asynchronous control processing on the differentiated register circuit, and generating a timing pulse control signal includes:

[0030] Introducing the dual-phase lightweight asynchronous controller and the lightweight asynchronous controller;

[0031] Generate a first asynchronous control signal and a second asynchronous control signal by the dual-phase lightweight asynchronous controller, wherein the lightweight asynchronous controller generates the second asynchronous control signal;

[0032] The operation of the key latch is controlled by the first asynchronous control signal, and the operation of the common latch and the memory is controlled by the second asynchronous control signal to generate the timing pulse control signal.

[0033] In some embodiments, the dual-phase lightweight asynchronous controller controls the phase difference between the first asynchronous control signal and the second asynchronous control signal by introducing a delay unit.

[0034] The embodiments of the present application include at least the following beneficial effects: The present application provides a dual-phase lightweight asynchronous circuit based on timing borrowing and a control method thereof. The scheme generates a first asynchronous control signal and a second asynchronous control signal by introducing a dual-phase lightweight asynchronous controller, and further divides the storage unit into a common latch, a key latch and a memory according to the timing margin. The first asynchronous control signal is used to control the key latch, and the second asynchronous control signal is used to control the common latch and the memory. There is no need to introduce a complex clock network, thereby optimizing the power consumption and area of ​​the asynchronous circuit. The control signals with two different pulse widths are matched with the requirements of the latch, thereby avoiding the phase skew caused by the asynchronous handshake logic and improving the execution efficiency of the instruction, thereby giving full play to the low power consumption advantage and timing borrowing characteristics of the latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a structural schematic diagram of a dual-phase lightweight asynchronous circuit based on timing borrowing provided in an embodiment of the present application;

[0036] Figure 2 It is a schematic diagram of the steps of a control method of a dual-phase lightweight asynchronous circuit based on timing borrowing provided by an embodiment of the present application;

[0037] Figure 3 is a schematic diagram of the pulse width requirement of the latch provided in an embodiment of the present application;

[0038] Figure 4 It is a structural schematic diagram of a dual-phase lightweight asynchronous controller provided in an embodiment of the present application;

[0039] Figure 5 is a pulse control logic diagram of a pulse control unit provided in an embodiment of the present application;

[0040] Figure 6 It is a logic diagram of an asynchronous control method based on timing borrowing provided in an embodiment of the present application;

[0041] Figure 7 is a schematic diagram of a register-based synchronization circuit structure provided in an embodiment of the present application;

[0042] Figure 8 It is a schematic diagram of a register-based asynchronous circuit structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0044] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0045] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0047] In the related art, latches have more stringent requirements on their control signals. If the pulse width is too high, the latch faces a greater risk of holding time violation. If the pulse width is too low, the latch cannot fully take advantage of the timing borrowing. Figure 3As shown in the figure. The latches at different positions in the circuit have different requirements for control signals. Therefore, for latch design, asynchronous circuits that can provide flexible control signals are more suitable than synchronous circuits that use global clock networks. However, most of the existing asynchronous circuit design methods are register-oriented. The control signals generated by controllers at all levels cannot be properly controlled, making it difficult to ensure the normal operation of the latch, and it is even more difficult to give full play to the low power consumption advantages and timing borrowing characteristics of the latch.

[0048] In the related art, the conversion from synchronous circuit to 2-phase data bundled asynchronous circuit is realized by using automated scripts, but some of them are not suitable for latch design, and for those suitable for latch design, their design process is not flexible and cannot give full play to the timing borrowing characteristics of the latch. Existing asynchronous controllers such as click controllers and lightweight asynchronous controllers cannot specifically control the pulse width of each latch, so they cannot give full play to the timing borrowing and low power consumption characteristics of the latch, and their asynchronous control methods cannot completely eliminate the adverse effects of phase skew caused by asynchronous handshake logic, and the performance of asynchronous circuits will still be limited by the critical path.

[0049] In view of this, an embodiment of the present application provides a dual-phase lightweight asynchronous circuit based on timing borrowing. By utilizing the timing borrowing characteristics of the latch, the limitation of the critical path on the circuit performance is reduced, so that the performance of the circuit is close to the average performance. The proposed asynchronous control method will resolve the adverse effects of phase skew, so that each latch in the circuit works at a suitable pulse width, thereby fully utilizing the characteristics of timing borrowing and low power consumption.

[0050] Reference Figure 1 , Figure 1 A structural diagram of a dual-phase lightweight asynchronous circuit based on timing borrowing provided by an embodiment of the present invention, referring to Figure 1 , the circuit includes a control path and a data path, the output end of the control path is connected to the input end of the data path, wherein:

[0051] The control path includes a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller, the dual-phase lightweight asynchronous controller and the lightweight asynchronous controller are connected through an asynchronous control chain, and the control path is used to generate a first asynchronous control signal and a second asynchronous control signal;

[0052] Further, it should be noted that the dual-phase lightweight asynchronous controller includes a multiplexer M1, an XOR gate U1, a first XOR gate U2, a second XOR gate U3, a first pulse control module PCM1 and a second pulse control module PCM2, the first input end of the multiplexer obtains an input request signal, the second input end of the multiplexer is connected to the output end of the XOR gate, the first output end of the multiplexer, the first input end of the XOR gate, the first end of the first pulse control module, the second input end of the first XOR gate, the second output end of the multiplexer, and the second end of the second pulse control module are connected to the first input end of the second XOR gate, and the second end of the first pulse control module is connected to the first input end of the first XOR gate. The first end of the second pulse control module is connected to the second input end of the second XOR gate, the first output end of the multiplexer outputs an output request signal, the second output end of the multiplexer outputs an output response signal, and the second input end of the XOR gate obtains an input response signal, wherein the multiplexer is used to initialize the handshake signal and transmit the output request signal; the XOR gate is used to determine the phase of the output request signal and the phase of the input response signal; the first XOR gate is used to generate a first asynchronous control signal; the second XOR gate is used to generate a second asynchronous control signal; the first pulse control module is used to adjust the clock pulse width of the first asynchronous control signal; and the second pulse control module is used to adjust the clock pulse width of the second asynchronous control signal.

[0053] In this embodiment, in order to give full play to the low power consumption and timing borrowing characteristics of the latch, in the embodiment of the present invention, the latch is divided into two categories, one is the latch on the longer timing path, which is called the key latch in this embodiment; the other is the latch on the shorter timing path, that is, it has more timing margin, which is called the ordinary latch in this embodiment. In order to distinguish these two types of latches from the design, the embodiment of the present invention sets a time threshold in the timing constraint through the "set_max_delay" instruction, and the tool automatically analyzes the timing path that exceeds this threshold, and then screens out the key latches on the longer path.

[0054] Further explanation of the timing paths of critical latches and ordinary latches shows that the critical latch is located on a longer timing path, so the risk of causing a hold time violation is lower, and it is necessary to strive for as much timing margin as possible. Therefore, the critical latch is suitable for a wider pulse width, that is, the timing borrowing feature can be used to a large extent to alleviate the timing pressure. The ordinary latch is located on a shorter timing path, has a larger timing margin, and has a greater risk of causing a hold time violation. Therefore, the ordinary latch is more suitable for a narrower pulse width, that is, it does not require too much timing borrowing to alleviate the setup time pressure, and a narrower pulse width can minimize the risk of a hold time violation.

[0055] In order to achieve flexible control of the dual-phase latch, the embodiment of the present invention designs a dual-phase lightweight asynchronous controller (DPLAC), such as Figure 4 As shown in the figure, the asynchronous handshake logic consists of an XNOR gate and a 3-1 multiplexer. Compared with other traditional asynchronous controllers, DPLAC has a simpler structure and can minimize the power consumption and area overhead of the asynchronous control chain while ensuring the correctness of the handshake logic.

[0056] Further, the dual-phase lightweight asynchronous controller is described in detail. Figure 4 As shown in the figure, the two control signals of different phases generated by the dual-phase asynchronous controller are the first asynchronous pulse and the second asynchronous pulse, and the two control signals will control the key latch and the common latch respectively. The final effect that can be achieved is: the pulse width of the control signal of the key latch is larger, that is, there is more timing margin for other timing paths to borrow, and the pulse width of the control signal of the common latch is smaller, that is, the cost of holding time violation is very small.

[0057] In addition, Figure 4 The meaning of other signals in are explained as follows:

[0058] The reset signal is used to initialize the system when the circuit starts, that is, to reset all signals to 0;

[0059] The input request signal and the output response signal are used to handshake with the previous asynchronous controller, receive the request from the previous circuit, and return the response signal to the previous circuit;

[0060] The output request signal and the input response signal are used to handshake with the next-level asynchronous controller, send a request signal to the next-level circuit, and receive a response signal sent by the next-level circuit.

[0061] right Figure 4 The components in the figure are explained as follows:

[0062] The multiplexer M1 is used to initialize the handshake signal, transmit the output request signal or keep the handshake signal state unchanged;

[0063] The XOR gate U1 is used to determine whether the phase of the output request signal is consistent with the phase of the response signal;

[0064] XOR gate U2 is used to generate a first asynchronous pulse;

[0065] XOR gate U2 is used to generate a second asynchronous pulse;

[0066] The first pulse control module PCM1 and the second pulse control module PCM2 are used to adjust the clock pulse width.

[0067] Finally, the regulation working principle of the first pulse control module PCM1 and the second pulse control module PCM2 is explained. In addition to the handshake logic, each dual-phase lightweight asynchronous controller has a pulse control unit (pulse control module, PCM) and an XOR gate to flexibly control the two different pulse widths required by the dual-phase latch. The implementation method of the pulse control unit is as follows Figure 5 As shown, in the synthesis and implementation stage of digital integrated circuit design, the pulse width of the control signal can be flexibly and accurately controlled through the three steps of constraint, inspection and correction.

[0068] 1) Pulse width constraint: After the latch-based asynchronous circuit is imported into the synthesis tool (such as Design Compiler) in the form of a gate-level netlist, "Set_min_pulse_width" is used to set the minimum pulse width of the control signal of a certain latch or a group of latches;

[0069] 2) Pulse width detection: Next, in the clock tree synthesis stage (a step in layout and routing, which needs to be completed in the layout and routing tool, such as IC Compiler), "Report_min_pulse_width" is used to check the pulse width of the latch constrained in the pulse width constraint. If the actual pulse width does not meet the constraints in the pulse width constraint, the tool will report a violation and how much it differs from the constraint;

[0070] 3) Pulse width correction: If the pulse width does not meet the requirements of the pulse width constraint during pulse width detection, if the pulse width is too small, "Insert_buffer" will be used to insert a delay unit to widen the pulse width; if the pulse width is too large, "remove_buffer" will be used to shorten the pulse width. Finally, the timing report given by the analysis tool is used to check whether the timing borrowing occurs as expected, and whether there are still timing violations in the circuit. If all goes well, a waveform check is performed to complete the design.

[0071] Furthermore, it should be noted that the control path also includes a delay unit, and the delay unit is used to control the phase difference between the first asynchronous control signal and the second asynchronous control signal.

[0072] The clock pulse width of the first asynchronous control signal is greater than the clock pulse width of the second asynchronous control signal.

[0073] The data path includes a storage unit and a combinational logic unit. The storage units are connected through the combinational logic unit. The storage unit includes a common latch, a key latch and a memory. The data path is used for calculation and storage, and timing borrowing occurs under the control of a first asynchronous control signal and a second asynchronous control signal.

[0074] Specifically, the timing margin of the common latch is greater than the timing margin of the critical latch. More specifically, the first asynchronous control signal is used to control the operation of the critical latch, and the second asynchronous control signal is used to control the operation of the common latch and the memory.

[0075] In summary, in the timing analysis of the synthesis tool, instructions such as "report_timing" will be used to perceive the timing margin of each timing path. Assuming that the Nth stage of the circuit has a longer timing path, a dual-phase lightweight asynchronous controller needs to be applied to control the latch of the Nth stage. In addition, the memory is usually regarded as a register in the timing analysis, and the control signal of the memory usually requires a wider pulse width to ensure its normal operation. Therefore, for the stage including storage in the circuit, a dual-phase lightweight asynchronous controller is also needed to generate two different pulse control signals. For the stages in the pipeline with looser timing, in order to minimize the hardware overhead of the asynchronous control chain, only an ordinary LAC controller needs to be selected.

[0076] Further embodiments of the present invention Figure 1 To elaborate on the explanation, Figure 4 The figure shows a part of an asynchronous pipeline, which includes three stages, assuming that they are the N-1 stage, the N stage and the N+1 stage. The asynchronous circuit mainly includes two parts, one is the control path and the other is the data path.

[0077] The control path is mainly an asynchronous control chain composed of DPLAC and LAC, that is, a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller. First, the input request signal and the output response signal are used to handshake with the upper circuit; the output request signal and the input response signal are used to handshake with the lower circuit. The delay unit in the control path is used to control the phase difference between different asynchronous control signals. DPLAC or LAC will provide asynchronous control signals for controlling one or a batch of storage units.

[0078] The data path is mainly composed of storage units and combinational logic. In the embodiment of the present invention, the latch is the main storage unit in the data path. In addition, there is also a memory in the circuit, and the memory is also a storage unit in the data path. And the latch will be divided into a key latch and a common latch.

[0079] In addition, the longer timing paths in the circuit often pass through some specific circuit modules. Therefore, in order to reduce the adverse effects of phase skew caused by asynchronous handshake, the asynchronous start signal (Async_Start) is set at the stage where complex circuit modules are gathered, such as Figure 1 In this startup mode, the adverse effect of phase skew on the circuit will be alleviated.

[0080] See also Figure 2 The embodiment of the present application also provides a control method for a dual-phase lightweight asynchronous circuit based on timing borrowing, which can realize the above-mentioned dual-phase lightweight asynchronous circuit based on timing borrowing, and the method includes the following steps:

[0081] S100, performing asynchronous processing based on the register circuit to obtain an asynchronous register circuit;

[0082] S200, performing differentiation processing on the asynchronous register circuit based on the timing constraint to obtain a differentiated register circuit, wherein the differentiated register circuit includes a common latch, a key latch and a memory;

[0083] It should be noted that, in some embodiments, step S200 may include: S210, setting a time threshold; S220, obtaining the timing length of the timing path corresponding to the data path through a timing constraint analysis tool; S230, if the timing length of the timing path corresponding to the data path is less than the time threshold, the storage unit is divided into a common latch and a memory; S240, if the timing length of the timing path corresponding to the data path is greater than the time threshold, the storage unit is divided into a critical latch; S250, integrating the common latch, the memory and the critical latch to obtain a differentiated register circuit.

[0084] S300, introducing a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller, performing margin-aware asynchronous control processing on the differentiated register circuit, and generating a timing pulse control signal;

[0085] It should be noted that, in some embodiments, step S300 may include: S310, introducing a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller; S320, generating a first asynchronous control signal and a second asynchronous control signal through the dual-phase lightweight asynchronous controller, and the lightweight asynchronous controller generates a second asynchronous control signal; S330, controlling the operation of the key latch through the first asynchronous control signal, and controlling the operation of the ordinary latch and the memory through the second asynchronous control signal, and generating a timing pulse control signal.

[0086] In some specific embodiments, the dual-phase lightweight asynchronous controller controls the phase difference between the first asynchronous control signal and the second asynchronous control signal by introducing a delay unit.

[0087] In summary, the control method of the dual-phase lightweight asynchronous circuit of the embodiment of the present invention can be automatically implemented by a commercial EDA tool. Figure 6 ,First, for a mainstream ,register-based circuit design (the control path is composed of ,global clocks, and the data path is composed of ,combinatorial logic and registers), such as Figure 7 As shown, it needs to be asynchronous first. The circuit after asynchronousization is as follows Figure 8 As shown (the data path is still composed of combinational logic and registers, while the control path becomes a two-phase single-rail Click control chain).

[0088] Then, under appropriate timing constraints, the synthesis tool (such as Design Compiler) generates a gate-level netlist. The tool will then generate a timing report based on the timing constraints to distinguish between longer and shorter paths in the circuit, which is also the basis for distinguishing between critical latches and ordinary latches.

[0089] Further apply the DPLAC and margin-aware asynchronous control methods mentioned in this method; the TCL script will automatically implement the conversion from registers to latches, and the control end of DPLAC will accurately control each latch in the circuit. The timing constraints suitable for the latch will be used to complete the second synthesis, mainly "set_multicycle_path" and other instructions will ensure the correct timing check of the latch. Finally, after pulse width control and placement and routing, the tool will output the final circuit netlist.

[0090] Therefore, compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0091] 1) Lower power consumption and area overhead: Compared with registers, latches have lower power consumption and area overhead. However, latches have a higher risk of hold time violations, and repairing hold timing violations requires hardware overhead. In the asynchronous control method involved in the present invention, due to the classification of latches and dual-phase control of the present invention, the risk of hold time violations is minimized. Therefore, compared with register design, the embodiments of the present invention can bring lower power consumption and area overhead. In addition, compared with the complex clock network of traditional synchronous circuits, or the Click control chain of traditional asynchronous circuits, the asynchronous circuit involved in the embodiments of the present invention adopts a lighter-weight asynchronous control, which further optimizes the power consumption and area of ​​the circuit.

[0092] 2) Higher speed, that is, the circuit has a higher operating frequency: the highest operating frequency of existing register-based synchronous circuits or asynchronous circuits is limited by the critical path. By using the timing borrowing method involved in the embodiment of the present invention, the timing requirements for the critical path will be reduced, which also means that the main frequency of the circuit will be significantly improved.

[0093] In summary, compared with a synchronous processor, the asynchronous processor constructed in the embodiment of the present invention has a speed increase of 1.58 times and a power consumption reduction of 28.71%.

[0094] It can be understood that the contents of the above method embodiments are all applicable to the present circuit embodiment, the functions specifically implemented by the present circuit embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0095] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A dual-phase lightweight asynchronous circuit based on timing borrowing, characterized in that: The circuit comprises a control path and a data path, wherein an output end of the control path is connected to an input end of the data path, wherein: The control path includes a dual-phase lightweight asynchronous controller and a lightweight asynchronous controller, the dual-phase lightweight asynchronous controller and the lightweight asynchronous controller are connected via an asynchronous control chain, and the control path is used to generate a first asynchronous control signal and a second asynchronous control signal; The data path includes a storage unit and a combinational logic unit, the storage units are connected through the combinational logic unit, the storage unit includes a common latch, a key latch and a memory, the data path is used for calculation and storage, and timing borrowing occurs under the control of the first asynchronous control signal and the second asynchronous control signal.

2. The circuit according to claim 1, characterized in that The dual-phase lightweight asynchronous controller includes a multiplexer, an XOR gate, a first XOR gate, a second XOR gate, a first pulse control module and a second pulse control module. The first input end of the multiplexer obtains an input request signal, the second input end of the multiplexer is connected to the output end of the XOR gate, the first output end of the multiplexer, the first input end of the XOR gate, the first end of the first pulse control module, the second input end of the first XOR gate, the second output end of the multiplexer, and the second end of the second pulse control module are connected to the first input end of the second XOR gate, the second end of the first pulse control module is connected to the first input end of the first XOR gate, the first end of the second pulse control module is connected to the second input end of the second XOR gate, the first output end of the multiplexer outputs an output request signal, the second output end of the multiplexer outputs an output response signal, and the second input end of the XOR gate obtains an input response signal, wherein: The multiplexer is used to initialize the handshake signal and transmit the output request signal; The XNOR gate is used to determine the phase of the output request signal and the phase of the input response signal; The first XOR gate is used to generate the first asynchronous control signal; The second XOR gate is used to generate the second asynchronous control signal; The first pulse control module is used to adjust the clock pulse width of the first asynchronous control signal; The second pulse control module is used to adjust the clock pulse width of the second asynchronous control signal.

3. The circuit according to claim 1, characterized in that The control path further includes a delay unit, and the delay unit is used to control the phase difference between the first asynchronous control signal and the second asynchronous control signal.

4. The circuit according to claim 1, characterized in that A clock pulse width of the first asynchronous control signal is greater than a clock pulse width of the second asynchronous control signal.

5. The circuit according to claim 1, characterized in that The timing margin of the common latch is greater than the timing margin of the key latch.

6. The circuit according to claim 1, characterized in that The first asynchronous control signal is used to control the operation of the key latch, and the second asynchronous control signal is used to control the operation of the common latch and the memory.

7. A control method for a dual-phase lightweight asynchronous circuit based on timing borrowing, characterized in that: The method comprises the following steps: Performing asynchronous processing based on the register circuit to obtain an asynchronous register circuit; Performing differentiation processing on the asynchronous register circuit based on the timing constraint to obtain a differentiated register circuit, wherein the differentiated register circuit includes a common latch, a key latch and a memory; A dual-phase lightweight asynchronous controller and a lightweight asynchronous controller are introduced to perform margin-aware asynchronous control processing on the differentiated register circuit to generate a timing pulse control signal.

8. The method according to claim 7, characterized in that The step of performing differentiation processing on the asynchronous register circuit based on the timing constraint to obtain the differentiated register circuit includes: Set time thresholds; Obtain the timing lengths of the timing paths corresponding to several data paths through a timing constraint analysis tool; If the timing length of the timing path corresponding to the data path is less than the time threshold, the storage unit is divided into a common latch and a memory; If the timing length of the timing path corresponding to the data path is greater than the time threshold, the storage unit is distinguished as a critical latch; The common latch, the memory and the key latch are integrated to obtain the differentiated register circuit.

9. The method according to claim 7, characterized in that: The dual-phase lightweight asynchronous controller and the lightweight asynchronous controller are introduced to perform margin-aware asynchronous control processing on the differentiated register circuit to generate a timing pulse control signal, including: Introducing the dual-phase lightweight asynchronous controller and the lightweight asynchronous controller; Generate a first asynchronous control signal and a second asynchronous control signal by the dual-phase lightweight asynchronous controller, wherein the lightweight asynchronous controller generates the second asynchronous control signal; The operation of the key latch is controlled by the first asynchronous control signal, and the operation of the common latch and the memory is controlled by the second asynchronous control signal to generate the timing pulse control signal.

10. The method according to claim 7, characterized in that The dual-phase lightweight asynchronous controller controls the phase difference between the first asynchronous control signal and the second asynchronous control signal by introducing a delay unit.

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