Gate drive circuit and display device

Abstract

The invention provides a gate drive circuit and a display device. The gate driving circuit comprises a first node control circuit, a first holding circuit, a first output circuit and a first node voltage stabilizing circuit. The first node control circuit is configured to control a voltage level of the first node. The first holding circuit is configured to hold a voltage level of the first node according to a voltage level of the second node. The first output circuit is configured to output a gate signal from a gate signal output terminal according to a voltage level of the first node. The first node voltage stabilizing circuit is configured to be turned on according to a touch signal of a first level in a touch period to control the voltage level of the second node, so that the first maintaining circuit is turned off, and the voltage level of the first node is stabilized. Thus, the first node voltage stabilizing circuit solves the problem that the first node leaks electricity through the first maintaining circuit in the touch control time period, stabilizes the voltage level of the first node in the touch control time period, and further solves the problem of abnormal display of the voltage level of the first node caused by electricity leakage.

Description

Technical Field

[0001] The present application relates to the technical field of gate drive circuits, and in particular to a gate drive circuit and a display device. Background Art

[0002] Generally speaking, the gate driving circuit in the display device is composed of multiple stages of gate driving units connected in series. Each stage of the gate driving unit is used to output a gate driving signal and open the corresponding pixel row through the gate driving signal so that each pixel in the pixel row can write the required display data.

[0003] However, in the touch state, the touch signal will affect the gate driving signal output by the gate driving circuit, thereby causing display abnormality. Summary of the invention

[0004] The embodiments of the present application provide a gate driving circuit and a display device to improve the display abnormality problem caused by leakage of the voltage level of the first node of the gate driving circuit, so as to at least solve part of the above problems.

[0005] In a first aspect, an embodiment of the present application provides a gate drive circuit. The gate drive circuit includes a first node control circuit, a first maintenance circuit, a first output circuit, and a first node voltage stabilization circuit. The first node control circuit is configured to control the voltage level of the first node. The first maintenance circuit is configured to maintain the voltage level of the first node according to the voltage level of the second node. The first output circuit is configured to output a gate signal from a gate signal output terminal according to the voltage level of the first node. The first node voltage stabilization circuit is configured to be turned on during a touch period according to a touch signal of a first level input from a touch signal input terminal to control the voltage level of the second node, so that the first maintenance circuit is turned off, thereby stabilizing the voltage level of the first node.

[0006] In a second aspect, an embodiment of the present application further provides a display device, which includes the above-mentioned gate driving circuit.

[0007] In the gate driving circuit and display device of the embodiment of the present application, the first node voltage stabilizing circuit improves the problem of leakage of the first node through the first maintaining circuit during the touch period, stabilizes the voltage level of the first node during the touch period, and further improves the display abnormality problem caused by leakage of the voltage level of the first node. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application;

[0009] Figure 2 A circuit diagram of an N-th gate driving unit provided in an embodiment of the present application;

[0010] Figure 3 A working timing diagram of the gate drive circuit provided in an embodiment of the present application;

[0011] Figure 4 A schematic diagram of the cross-sectional structure of a display device provided in an embodiment of the present application.

[0012] The reference numerals are as follows:

[0013] 100. Gate driving circuit;

[0014] 200, gate driving unit; 210, (Ni)th gate driving unit; 220, Nth gate driving unit; 230, (N+j)th gate driving unit;

[0015] 301, first node control circuit; T11, first node control transistor;

[0016] 302, a first maintaining circuit; T42, T43, a first maintaining transistor;

[0017] 303, a first output circuit; T21, a first output transistor; T31, a second output transistor;

[0018] 304, first node voltage stabilizing circuit; T91, T92, first node voltage stabilizing transistor;

[0019] 305, reset circuit; TrQ, reset transistor;

[0020] 306, a second maintaining circuit; T41, a second maintaining transistor;

[0021] 307, second node control circuit; 3071, first inverter; 3072, second inverter; T51, T61, first transistor; T52, T62, second transistor; T54, T64, third transistor; T53, T63, fourth transistor;

[0022] 308, a third maintaining circuit; T32, T33, a third maintaining transistor;

[0023] 309, a second output circuit; T22, a third output transistor;

[0024] 310, fourth maintaining circuit; T72, T73, fourth maintaining transistor;

[0025] 311, touch control voltage stabilizing circuit; T81, touch control voltage stabilizing transistor;

[0026] Cb, capacitor;

[0027] VGL, a first voltage input terminal;

[0028] TP, touch signal input terminal;

[0029] ST(N+j), first stage transmission signal; ST(n+j), first stage transmission signal input terminal;

[0030] ST(Ni), second stage transmission signal; ST(ni), second stage transmission signal input terminal;

[0031] ST(N), third-level transmission signal; ST(n), third-level transmission signal output terminal;

[0032] CK(n), clock signal input terminal;

[0033] G(n), gate signal output terminal; Reset, reset signal input terminal;

[0034] LC1, LC2, second voltage input terminal;

[0035] Q(n), first node; K(n), P(n), second node;

[0036] 400, display device; 500, display panel; 501, substrate; 502, counter substrate; 503, pixel electrode layer; 504, drive circuit layer; 600, touch layer. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0038] See also Figure 1 As shown, an embodiment of the present application provides a gate driving circuit 100. The gate driving circuit 100 is applied to a display panel including a touch layer. In other words, the gate driving circuit 100 is applied to a display panel with a touch function.

[0039] The display panel may be at least one of a liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel, a sub-millimeter light emitting diode display panel, and a quantum dot display panel. The touch layer may be integrated inside the display panel, or the touch layer may be externally mounted on the outside of the display panel.

[0040] The gate driving circuit 100 includes a plurality of gate driving units 200. The plurality of gate driving units 200 are used to output multi-level scanning signals. Figure 1As shown, the plurality of gate driving units 200 include a (Ni)th gate driving unit 210, an Nth gate driving unit 220, and an (N+j)th gate driving unit 230, i and j are integers greater than or equal to 1, and N is an integer greater than or equal to 2. The (N+j)th gate driving unit 230 outputs a scan signal G(N+j) and a first-level transmission signal ST(N+j). The (Ni)th gate driving unit 210 outputs a scan signal G(Ni) and a second-level transmission signal ST(Ni). The Nth-level gate driving unit 220 outputs a scan signal G(N) and a third-level transmission signal ST(N). The first-level transmission signal ST(N+j) is a subsequent-level transmission signal of the third-level transmission signal ST(N). The second-level transmission signal ST(Ni) is a previous-level transmission signal of the third-level transmission signal ST(N).

[0041] In order to describe the technical solution of the embodiment of the present application, the Nth level gate driving unit is taken as an example for illustration, where N is an integer greater than or equal to 2.

[0042] See also Figure 2 As shown, the gate driving circuit 100 includes a first node control circuit 301 , a first maintaining circuit 302 , a first output circuit 303 and a first node voltage stabilizing circuit 304 .

[0043] The first node control circuit 301 is configured to control the voltage level of the first node Q(n). The first maintenance circuit 302 is configured to maintain the voltage level of the first node Q(n) according to the voltage level of the second node ((K(n), P(n))). The first output circuit 303 is configured to output a gate signal from the gate signal output terminal G(n) according to the voltage level of the first node Q(n). The first node voltage stabilization circuit 304 is configured to turn on according to the touch signal of the first level input from the touch signal input terminal TP during the touch period to control the voltage level of the second node (K(n), P(n)), so that the first maintenance circuit 302 is turned off, thereby stabilizing the voltage level of the first node Q(n).

[0044] The first node voltage stabilizing circuit 304 of the gate driving unit 200 pulls down the second node (K(n), P(n)) to a low level according to the touch signal of the first level, and the first maintaining circuit 302 is turned off according to the low level of the second node (K(n), P(n)), thereby improving the leakage problem of the first node Q(n) through the first maintaining circuit 302 during the touch period, stabilizing the voltage level of the first node Q(n) during the touch period, and further improving the display abnormality problem caused by the leakage of the voltage level of the first node Q(n).

[0045] It should be noted that, during the touch period, in order to reduce the impact of touch on the display process, the selection process of the scan line is usually paused during the touch stage. For example, the paused gate drive circuit continues to output the on-scan signal to the selected scan line. However, during the pre-charge period of the first node of the current-level gate drive circuit, the first node is at a high potential, and the pause operation will cause the risk of leakage at the first node. Leakage of the first node will cause the output level of the current-level transmission signal to be low, resulting in a decrease in the charging rate of the lower-level gate drive circuit that is charged according to the current-level transmission signal, or causing the lower-level gate drive circuit that is turned on according to the current-level transmission signal to be unable to turn on, thereby causing display abnormalities such as horizontal stripes or lines that are often black.

[0046] Furthermore, for the unselected scan line, when the voltage level of the first node of the gate driving unit connected to the unselected scan line is low, the voltage level of the second node is high. If the first node voltage stabilizing circuit 304 is not added, the first maintaining circuit 302 will be turned on according to the high level of the second node, so that the voltage level of the first node Q(n) is pulled down to a low level.

[0047] In the embodiment of the present application, no matter the gate driving unit connected to the selected scan line or the unselected scan line, in the touch stage, the additional first node voltage stabilizing circuit 304 pulls down the voltage level of the second node (K(n), P(n)) according to the touch signal of the first level, and the first maintenance circuit 302 is in a closed state according to the level pulled down by the second node (K(n), P(n)), and the first node Q(n) hardly leaks from the first maintenance circuit 302. Therefore, after the first node Q(n) switches from the pre-charge period of the display stage to the touch stage, the voltage level of the first node Q(n) is almost stable in the touch stage, which improves the display abnormality problems such as horizontal stripes or black lines caused by leakage when the first node Q(n) switches from the pre-charge period of the display stage to the touch stage.

[0048] In some embodiments, the first node voltage regulator circuit 304 is further configured to be turned off in the display stage according to a touch signal of a second level input from the touch signal input terminal TP. The second level is lower than the first level. In other words, the first node voltage regulator circuit 304 is turned on in the touch stage according to a high-level touch signal, and is turned off in the display stage according to a low-level touch signal, thereby improving the display abnormality problem caused by leakage of the voltage level of the first node Q(n) in the touch stage, and reducing the influence of the first node voltage regulator circuit 304 on the display process.

[0049] In some embodiments, the first node voltage regulator circuit 304 includes a first node voltage regulator transistor (T91, T92). The source and drain of the first node voltage regulator transistor (T91, T92) are connected between the second node (K(n), P(n)) and the first voltage input terminal VGL. The gate of the first node voltage regulator transistor (T91, T92) is connected to the touch signal input terminal TP.

[0050] In some embodiments, the first voltage input terminal VGL is configured to input a first level signal. The first level signal has a low level.

[0051] In some embodiments, the first node voltage regulation circuit 304 may include one or more first node voltage regulation transistors ( T91 , T92 ).

[0052] In an example embodiment, Figure 2 As shown, the first node voltage stabilizing circuit 304 may include a first node voltage stabilizing transistor T91 and a first node voltage stabilizing transistor T92. The first node voltage stabilizing transistor T91 and the first node voltage stabilizing transistor T92 work alternately and periodically. The source and drain of the first node voltage stabilizing transistor T91 are connected between the second node K(n) and the first voltage input terminal VGL. The source and drain of the first node voltage stabilizing transistor T92 are connected between the second node P(n) and the first voltage input terminal VGL. The gates of the first node voltage stabilizing transistor T91 and the first node voltage stabilizing transistor T92 are both connected to the touch signal input terminal TP.

[0053] In some embodiments, the first node voltage regulator transistor (T91, T92) is an N-type transistor or a P-type transistor. The first node voltage regulator transistor (T91, T92) is selected from any one of a low temperature polysilicon transistor, a metal oxide transistor, and a single crystal silicon transistor. Exemplarily, the first node voltage regulator transistor (T91, T92) is an N-type low temperature polysilicon transistor.

[0054] In some embodiments, see Figure 2As shown, the first node control circuit 301 includes a first node control transistor T11. The source and drain of the first node control transistor T11 are connected between the first node Q(n) and the second-level signal input terminal ST(ni) or the start signal input terminal STV. The gate of the first node control transistor T11 is connected to the second-level signal input terminal ST(ni) or the start signal input terminal STV. In this way, the first node control transistor T11 controls the voltage level of the first node Q(n) according to the second-level signal ST(Ni) input by the second-level signal input terminal ST(ni) or the start signal input by the start signal input terminal STV. For example, the high-level second-level signal ST(Ni) or the start signal is output to the first node Q(n) to pull up the voltage level of the first node Q(n), thereby precharging the first node Q(n).

[0055] It should be noted that, for the first few levels of gate driving units of the gate driving circuit 100, for example, the first level gate driving unit, the source and drain of the first node control transistor T11 can be connected between the start signal input terminal STV and the first node Q(n), and the gate of the first node control transistor T11 can be connected between the start signal input terminal STV and the first node Q(n).

[0056] For other gate driving units except the first few stages of gate driving units, for example, the Nth stage gate driving unit, the source and drain of the first node control transistor T11 can be connected between the second stage signal input terminal ST(ni) and the first node Q(n), and the gate of the first node control transistor T11 is connected to the second stage signal input terminal ST(ni).

[0057] In some embodiments, the second-stage transmission signal input terminal ST(ni) inputs the second-stage transmission signal, and the second-stage transmission signal is the previous-stage transmission signal output by the previous-stage gate driving unit (the (Ni)th gate driving unit) of the Nth-stage gate driving unit. In the case where the second-stage transmission signal is the previous-stage transmission signal, the first node control circuit 301 can realize the pre-charging of the first node Q(n) according to the previous-stage transmission signal, thereby improving the charging rate of the first node Q(n).

[0058] In an exemplary embodiment, i is equal to 4, but is not limited thereto. It is understood that i may also be 1, 2, 3 or 8, etc.

[0059] In some embodiments, the first node control transistor T11 is an N-type transistor or a P-type transistor. The first node control transistor T11 is selected from any one of a low temperature polysilicon transistor, a metal oxide transistor, and a single crystal silicon transistor. Exemplarily, the first node control transistor T11 is an N-type low temperature polysilicon transistor.

[0060] In some embodiments, see Figure 2 As shown, the first output circuit 303 includes a first output transistor T21. The source and drain of the first output transistor T21 are connected between the clock signal input terminal CK(n) and the gate signal output terminal G(n). The gate of the first output transistor T21 is connected to the first node Q(n). In this way, the first output transistor T21 can disconnect or connect the clock signal input terminal CK(n) and the gate signal output terminal G(n) according to the voltage level of the first node Q(n).

[0061] The clock signal input terminal CK(n) is configured to output a clock signal. The clock signal includes a high-level clock signal and a low-level clock signal. In some embodiments, the plurality of clock signal input terminals CK(n) include a first clock signal input terminal CK(1) to an eighth clock signal input terminal CK(8), but is not limited thereto.

[0062] In an exemplary embodiment, the first output transistor T21 is turned on according to the high level of the first node Q(n), and outputs a high-level clock signal to the gate signal output terminal G(n) as a high-level scanning signal. The high-level scanning signal is a turn-on scanning signal, which can select the pixel connected to the scanning line, so that the pixel can receive the data signal. In addition, the first output transistor T21 is also turned on according to the high level of the first node Q(n), and outputs a low-level clock signal to the gate signal output terminal G(n) as a low-level scanning signal. The low-level scanning signal is a cut-off scanning signal, and the pixel connected to the scanning line cannot be selected, so that the pixel cannot receive the data signal. Therefore, the scanning signal is output through the first output transistor T21.

[0063] In some embodiments, see Figure 2 As shown, the first output circuit 303 may further include a second output transistor T31. The source and drain of the second output transistor T31 are connected between the first voltage input terminal VGL and the gate signal output terminal G(n). The gate of the second output transistor T31 is connected to the first-stage transmission signal input terminal ST(n+j). In this way, the second output transistor T31 can pull the voltage level of the gate signal output terminal G(n) to the low level corresponding to the first level signal according to the first-stage transmission signal.

[0064] The first-stage transmission signal input terminal ST(n+j) inputs the first-stage transmission signal ST(N+j). The first-stage transmission signal ST(N+j) is a subsequent-stage transmission signal output by the subsequent-stage gate driving unit (the (N+j)th gate driving unit) of the Nth-stage gate driving unit. When the first-stage transmission signal ST(N+j) is a subsequent-stage transmission signal, the first output circuit 303 can pull down the first node Q(n) to a low level according to the subsequent-stage transmission signal.

[0065] In an exemplary embodiment, j is equal to i, and is equal to 4, but is not limited thereto. It is understandable that j may also be 1, 2, 3 or 8, etc.

[0066] In another exemplary embodiment, when the first output transistor T21 outputs a high-level clock signal as a high-level scanning signal to the gate signal output terminal G(n), that is, when the first output transistor T21 plays the role of pulling up the level of the gate signal output terminal G(n), the second output transistor T31 can output a low-level first-level signal as a low-level scanning signal to the gate signal output terminal G(n), that is, the second output transistor T31 plays the role of pulling down the level of the gate signal output terminal G(n).

[0067] In some embodiments, the gate driving circuit 100 further includes a capacitor Cb. Two electrodes of the capacitor Cb are connected between the first node Q(n) and the gate signal output terminal G(n). When the gate signal output terminal G(n) outputs a high-level scanning signal, the capacitor Cb raises the voltage level of the first node Q(n) through its own coupling effect, thereby improving the stability of the first output transistor T21 outputting a high-level scanning signal.

[0068] In some embodiments, the first maintenance circuit 302 includes a first maintenance transistor (T42, T43). The source and drain of the first maintenance transistor (T42, T43) are connected between the first node Q(n) and the touch signal input terminal TP. The gate of the first maintenance transistor (T42, T43) is connected to the second node (K(n), P(n)). When switching from the pre-charge period of the display stage to the touch stage, the source and drain of the first maintenance transistor (T42, T43) are respectively the high level of the first node Q(n) and the first level of the touch signal, and the voltage difference between the two is small, which reduces the risk of leakage of the first node Q(n) through the first maintenance circuit 302 during the touch stage.

[0069] Furthermore, in the display stage, when the voltage level of the first node Q(n) is high and the voltage level of the second node (K(n), P(n)) is low, the first maintenance transistor (T42, T43) is in a closed state to maintain the high level state of the first node Q(n). When the voltage level of the first node Q(n) is low and the voltage level of the second node (K(n), P(n)) is high, the first maintenance transistor (T42, T43) is in a conducting state, which outputs the touch signal of the second level as a low level to the first node Q(n) to maintain the low level state of the first node Q(n).

[0070] In some other embodiments, the first maintenance circuit 302 includes a first maintenance transistor (T42, T43). The source and drain of the first maintenance transistor (T42, T43) can be connected between the first node Q(n) and the first voltage input terminal VGL. The gate of the first maintenance transistor (T42, T43) is connected to the second node (K(n), P(n)). In this way, in the display stage, when the voltage level of the first node Q(n) is low and the voltage level of the second node (K(n), P(n)) is high, the first maintenance transistor (T42, T43) is in a conducting state, which outputs the first level signal as a low level to the first node Q(n) to maintain the low level state of the first node Q(n).

[0071] In some embodiments, the first sustaining circuit 302 may include one or more first sustaining transistors ( T42 , T43 ).

[0072] In an exemplary embodiment, the first maintenance circuit 302 may include a first maintenance transistor T42 and a first maintenance transistor T43. The first maintenance transistor T42 and the first maintenance transistor T43 work alternately periodically. The source and drain of the first maintenance transistor T42 are connected between the first node Q(n) and the touch signal input terminal TP. The gate of the first maintenance transistor T42 is connected to the second node K(n). The first maintenance transistor T42 and the first node voltage regulator transistor T91 work in the same cycle. The source and drain of the first maintenance transistor T43 are connected between the first node Q(n) and the touch signal input terminal TP. The gate of the first maintenance transistor T43 is connected to the second node P(n). The first maintenance transistor T43 and the first node voltage regulator transistor T92 work in the same cycle.

[0073] In some embodiments, see Figure 2 As shown, the gate driving circuit 100 further includes a reset circuit 305. The reset circuit 305 is configured to connect the touch signal input terminal TP and the first node Q(n) according to the reset signal of the third level inputted by the reset signal input terminal Reset in the display stage, so as to reset the voltage level of the first node Q(n) and improve the performance influence of the first node Q(n) on the gate driving circuit. Therefore, the touch signal of the second level inputted by the touch signal input terminal TP is fully utilized as the reset signal of the first node in the display stage.

[0074] In some embodiments, the reset circuit 305 is further configured to disconnect the first node from the touch signal input terminal TP according to a reset signal of a fourth level input from the reset signal input terminal Reset during the touch period. The fourth level is lower than the third level. In this way, the reset circuit 305 is turned on in the display stage according to a high-level reset signal, and is turned off in the touch stage according to a low-level reset signal, so as to make full use of the touch signal of the first level or the touch signal of the second level output from the touch signal input terminal TP. In addition, when switching from the pre-charge period of the display stage to the touch stage, the high level and the first level touch signals of the first node Q(n) are respectively connected to the two ends of the closed reset circuit 305, and the voltage difference between the two is small, which reduces the risk of leakage of the first node Q(n) through the reset circuit 305 during the touch stage.

[0075] In some embodiments, the reset circuit 305 includes a reset transistor TrQ. The source and drain of the reset transistor TrQ are connected between the first node Q(n) and the touch signal input terminal TP. The gate of the reset transistor TrQ is connected to the reset signal input terminal Reset. In this way, the reset transistor TrQ can reset the voltage level of the first node in the display stage, and reduce the risk of leakage of the first node Q(n) through it in the touch stage.

[0076] In some other embodiments, the reset circuit 305 includes a reset transistor TrQ. The source and drain of the reset transistor TrQ are connected between the first node Q(n) and the first voltage input terminal VGL. The gate of the reset transistor TrQ is connected to the reset signal input terminal Reset. In this way, when the reset transistor TrQ is turned on in the display stage according to the high-level reset signal, the first-level signal is output to the first node Q(n) to achieve the reset of the first node Q(n).

[0077] In some embodiments, see Figure 2 As shown, the gate driving circuit 100 further includes a second maintaining circuit 306. The second maintaining circuit 306 is configured to connect the touch signal input terminal TP and the first node Q(n) according to the first level transmission signal ST(N+j) of the fifth level input from the first level transmission signal input terminal ST(n+j) in the display stage to maintain the potential of the first node Q(n). Therefore, in the display stage, when the voltage level Q(n) of the first node is at a low level, the second maintaining circuit 306 is turned on to output the touch signal of the second level to the first node Q(n), maintaining the low level state of the first node Q(n).

[0078] In some embodiments, the second maintenance circuit 306 is further configured to disconnect the first node Q(n) from the touch signal input terminal TP according to the first-level transmission signal ST(N+j) of the sixth level input from the first-level transmission signal input terminal ST(n+j) during the touch period. The sixth level is less than the fifth level. Therefore, when switching from the pre-charge period of the display stage to the touch stage, the two ends of the closed second maintenance circuit 306 are respectively connected to the high level of the first node and the first level of the touch signal, and the voltage difference between the two is small, thereby reducing the risk of leakage of the first node Q(n) through the second maintenance circuit 306 during the touch stage.

[0079] In some embodiments, the second maintenance circuit 306 includes a second maintenance transistor T41. The source and drain of the second maintenance transistor T41 are connected between the first node Q(n) and the touch signal input terminal TP. The gate of the second maintenance transistor T41 is connected to the first-level transmission signal input terminal ST(n+j). In this way, the second maintenance transistor T41 connects or disconnects the touch signal input terminal TP and the first node according to the first-level transmission signal ST(N+j) of the fifth level or the first-level transmission signal ST(N+j) of the sixth level input by the first-level transmission signal input terminal ST(n+j).

[0080] In some other embodiments, the second maintenance circuit 306 includes a second maintenance transistor T41. The source and drain of the second maintenance transistor T41 can be connected between the first node Q(n) and the first voltage input terminal VGL. The gate of the second maintenance transistor T41 is connected to the first-level signal input terminal ST(n+j). In this way, in the display stage, when the voltage level of the first node Q(n) is low, the second maintenance transistor T41 is turned on according to the first-level signal ST(N+j) of the fifth level to output the first-level signal to the first node Q(n) to maintain the low-level state of the first node Q(n).

[0081] In some embodiments, see Figure 2 As shown, the gate drive circuit 100 further includes a second node control circuit 307. The second node control circuit 307 is configured to make the phase of the voltage level of the second node (K(n), P(n)) opposite to the phase of the voltage level of the first node Q(n) according to the voltage level of the first node Q(n). Therefore, the second node control circuit 307 can function as an inverter.

[0082] In some embodiments, the second node control circuit 307 includes a first transistor (T51, T61) and a second transistor (T52, T62). The source and drain of the first transistor (T51, T61) are connected between the second node (K(n), P(n)) and the second voltage input terminal (LC1, LC2). The gate of the first transistor (T51, T61) is connected to the second voltage input terminal (LC1, LC2). The source and drain of the second transistor (T52, T62) are connected between the second node (K(n), P(n)) and the first voltage input terminal VGL, and the gate of the second transistor (T52, T62) is connected to the first node Q(n). In the display stage and the touch stage, when the voltage level of the first node Q(n) is high, the second transistor (T52, T62) is turned on and outputs the first level signal to the second node (K(n), P(n)), so that the voltage level of the second node (K(n), P(n)) is low. In the display stage and the touch stage, when the voltage level of the first node Q(n) is at a low level, the second thin film transistor (T52, T62) is turned off, and the first transistor (T51, T61) is turned on, and the second level signal is output to the second node (K(n), P(n)), so that the voltage level of the second node (K(n), P(n)) is at a high level.

[0083] In some embodiments, the second voltage input terminal (LC1, LC2) outputs a second level signal. In the display stage, the second level signal may be a high level signal. In the touch stage, the second level signal may be a low level signal.

[0084] In some embodiments, see Figure 2 As shown, the second node control circuit 307 may further include a fourth transistor (T53, T63). The source and drain of the fourth transistor (T53, T63) are connected between the second node (K(n), P(n)) and one of the source and drain of the first transistor (T51, T61). The gate of the fourth transistor (T53, T63) is connected to the second voltage input terminal (LC1, LC2). In this way, the driving capability of the fourth transistor (T53, T63) and the first transistor (T51, T61) can be reduced, ensuring that the second transistor (T52, T62) can achieve the pull-down of the voltage level of the second node (K(n), P(n)).

[0085] In an exemplary embodiment, the second node control circuit 307 may include a first inverter 3071 and a second inverter 3072. The first inverter 3071 and the second inverter 3072 operate alternately and periodically.

[0086] The first inverter 3071 includes a first transistor T51, a fourth transistor T53 and a second transistor T52. The gates of the first transistor T51 and the fourth transistor T53 are connected to the second voltage input terminal LC1. The source and drain of the first transistor T51 and the source and drain of the fourth transistor T53 are connected between the second voltage input terminal LC1 and the second node K(n). The source and drain of the second transistor T52 are connected between the second node K(n) and the first voltage input terminal VGL, and the gate of the second transistor T52 is connected to the first node Q(n).

[0087] The second inverter 3072 includes a first transistor T61, a fourth transistor T63 and a second transistor T62. The gates of the first transistor T61 and the fourth transistor T63 are connected to the second voltage input terminal LC2. The source and drain of the first transistor T61 and the source and drain of the fourth transistor T63 are connected between the second voltage input terminal LC2 and the second node P(n). The source and drain of the second transistor T62 are connected between the second node P(n) and the first voltage input terminal VGL, and the gate of the second transistor T52 is connected to the first node Q(n).

[0088] In some embodiments, see Figure 2 As shown, the second node control circuit 307 is further configured to pull down the voltage level of the second node (K(n), P(n)) according to the second-level transmission signal ST(Ni) before the voltage level of the first node Q(n) is pulled up. Before the voltage level of the first node Q(n) is pulled up, the voltage level of the second node (K(n), P(n)) is pulled down, which can reduce the risk of leakage of the first node Q(n) through the first maintenance circuit 302, etc., so as to ensure the charging rate of the first node Q(n) by the first node control circuit 301 according to the second-level transmission signal ST(Ni).

[0089] In some embodiments, the second node control circuit 307 further includes a third transistor (T54, T64). The source and drain of the third transistor (T54, T64) are connected between the second node (K(n), P(n)) and the first voltage input terminal VGL, and the gate of the third transistor (T54, T64) is connected to the second-level signal input terminal ST(ni). In this way, the third transistor (T54, T64) pulls down the voltage level of the second node (K(n), P(n)) according to the second-level signal ST(Ni) before the voltage level of the first node Q(n) is pulled up, which can reduce the risk of leakage of the first node Q(n) through the first maintenance circuit 302, etc., so as to ensure the charging rate of the first node Q(n) by the first node control circuit 301 according to the second-level signal ST(Ni).

[0090] In some embodiments, the number of the third transistors ( T54 , T64 ) may be one or more.

[0091] In an exemplary embodiment, the second node control circuit 307 includes a third transistor T54 and a third transistor T64. The third transistor T54 and the third transistor T64 work alternately periodically. The source and drain of the third transistor T54 are connected between the second node K(n) and the first voltage input terminal VGL. The source and drain of the third transistor T64 are connected between the second node P(n) and the first voltage input terminal VGL.

[0092] In some embodiments, any one of the first transistor (T51, T61) to the fourth transistor (T53, T63) is an N-type transistor or a P-type transistor. Any one of the first transistor (T51, T61) to the fourth transistor (T53, T63) is selected from any one of a low-temperature polysilicon transistor, a metal oxide transistor, and a single crystal silicon transistor. Exemplarily, the first transistor (T51, T61) to the fourth transistor (T53, T63) is an N-type low-temperature polysilicon transistor.

[0093] In some embodiments, the gate drive circuit 100 further includes a third maintenance circuit 308. The third maintenance circuit 308 is configured to maintain the level voltage of the gate signal output terminal G(n) according to the voltage level of the second node (K(n), P(n)). In the display stage, when the voltage level of the second node (K(n), P(n)) is low, the third maintenance circuit 308 is turned off to ensure that the gate signal output terminal G(n) stably outputs a high voltage level. In the display stage, when the voltage level of the second node (K(n), P(n)) is high, the third maintenance circuit 308 is turned on, and the third maintenance circuit 308 pulls down the level voltage of the gate signal output terminal G(n) to maintain the level voltage of the gate signal output terminal G(n) at a low voltage.

[0094] In some embodiments, the third maintenance circuit 308 includes a third maintenance transistor (T32, T33). The source and drain of the third maintenance transistor (T32, T33) are connected between the gate signal output terminal G(n) and the first voltage input terminal VGL, and the gate of the third maintenance transistor (T32, T33) is connected to the second node (K(n), P(n)).

[0095] In an exemplary embodiment, the third maintenance circuit 308 includes a third maintenance transistor T32 and a third maintenance transistor T33. The third maintenance transistor T32 and the third maintenance transistor T33 work alternately periodically. The source and drain of the third maintenance transistor T32 are connected between the second node K(n) and the first voltage input terminal VGL. The source and drain of the third maintenance transistor T33 are connected between the second node P(n) and the first voltage input terminal VGL.

[0096] In some embodiments, the gate driving circuit 100 further includes a second output circuit 309. The second output circuit 309 is configured to output a third-level transmission signal ST(N) from the third-level transmission signal output terminal ST(n) according to the voltage level of the first node Q(n). In this way, the second output circuit 309 outputs the third-level transmission signal ST(N) as the current-level transmission signal to be used as a signal for other-level gate driving circuits 100.

[0097] In some embodiments, the second output circuit 309 includes a third output transistor T22. The source and drain of the third output transistor T22 are connected between the third-stage signal output terminal ST(n) and the clock signal input terminal CK(n), and the gate of the third output transistor T22 is connected to the first node Q(n). In this way, the third output transistor T22 connects or disconnects the third-stage signal output terminal ST(n) and the clock signal input terminal CK(n) according to the voltage level of the first node Q(n).

[0098] In some embodiments, any one of the first output transistor T21 and the third output transistor T22 is an N-type transistor or a P-type transistor. Any one of the first output transistor T21 and the third output transistor T22 is selected from any one of a low-temperature polysilicon transistor, a metal oxide transistor, and a single crystal silicon transistor. Exemplarily, the first output transistor T21 to the third output transistor T22 are all N-type low-temperature polysilicon transistors.

[0099] In some embodiments, the gate driving circuit 100 further includes a fourth maintenance circuit 310. The fourth maintenance circuit 310 is configured to maintain the level voltage of the third-level signal output terminal ST(n) according to the level voltage of the second node (K(n), P(n)). Thus, in the display stage, when the voltage level of the second node (K(n), P(n)) is low, the fourth maintenance circuit 310 is turned off to maintain the third-level signal output terminal ST(n) outputting a high-level third-level signal ST(N). In the display stage, when the voltage level of the second node (K(n), P(n)) is high, the fourth maintenance circuit 310 is turned on to pull down the third-level signal ST(N) and maintain the third-level signal ST(N) at a low voltage level.

[0100] In some embodiments, the fourth maintenance circuit 310 includes a fourth maintenance transistor (T72, T73). The source and drain of the fourth maintenance transistor (T72, T73) are connected between the third-stage signal output terminal ST(n) and the first voltage input terminal VGL for inputting the first level signal, and the gate of the fourth maintenance transistor T72, T73 is connected to the second node (K(n), P(n)).

[0101] In some embodiments, the fourth sustaining circuit 310 may include one or more fourth sustaining transistors ( T72 , T73 ).

[0102] In an exemplary embodiment, the fourth sustaining circuit 310 includes a fourth sustaining transistor T72 and a fourth sustaining transistor T73. The source and drain of the fourth sustaining transistor T72 are connected between the third-stage signal output terminal ST(n) and the first voltage input terminal VGL, and the gate of the fourth sustaining transistor T72 is connected to the second node K(n). The source and drain of the fourth sustaining transistor T73 are connected between the third-stage signal output terminal ST(n) and the first voltage input terminal VGL, and the gate of the fourth sustaining transistor T73 is connected to the second node P(n).

[0103] In some embodiments, any one of the first maintenance transistor (T42, T43) to the fourth maintenance transistor (T72, T73) is an N-type transistor or a P-type transistor. Any one of the first maintenance transistor (T42, T43) to the fourth maintenance transistor (T72, T73) is selected from any one of a low-temperature polysilicon transistor, a metal oxide transistor, and a single crystal silicon transistor. Exemplarily, any one of the first maintenance transistor (T42, T43) to the fourth maintenance transistor (T72, T73) is an N-type low-temperature polysilicon transistor.

[0104] It should be noted that the first node voltage-stabilizing transistor T91, the first inverter 3071, the third transistor T54, the first maintenance transistor T42, the fourth maintenance transistor T72 and the third maintenance transistor T32 constitute a first maintenance circuit group. The transistors in the first maintenance circuit group work in coordination in one cycle. The first node voltage-stabilizing transistor T92, the second inverter 3072, the third transistor T64, the first maintenance transistor T43, the fourth maintenance transistor T73 and the third maintenance transistor T33 constitute a second maintenance circuit group. The transistors in the second maintenance circuit group work in coordination in one cycle. The first maintenance circuit group and the second maintenance circuit group work alternately periodically, for example, work alternately with 100 frames as a cycle, thereby extending the service life of the first maintenance circuit group and the second maintenance circuit group, thereby improving the service life of the gate drive circuit 100.

[0105] In some embodiments, the gate drive circuit 100 further includes a touch voltage stabilizing circuit 311. The touch voltage stabilizing circuit 311 is configured to be turned on during the touch period according to a touch signal of a first level to stabilize the voltage level of the gate signal output terminal G(n). The touch voltage stabilizing circuit 311 is also configured to be turned off during the display phase according to a touch signal of a second level input from the touch signal input terminal TP, and the second level is lower than the first level. In this way, during the display phase, the touch voltage stabilizing circuit 311 is turned off to reduce its impact on the display process. During the touch phase, the touch voltage stabilizing circuit 311 is turned on to lower the voltage level of the gate signal output terminal G(n) and pause the process of the gate drive circuit 100 selecting the scan line.

[0106] In some embodiments, the touch voltage stabilizing circuit 311 includes a touch voltage stabilizing transistor T81. The source and drain of the touch voltage stabilizing transistor T81 are connected between the gate signal output terminal G(n) and the first voltage input terminal VGL. The gate of the touch voltage stabilizing transistor T81 is connected to the touch signal input terminal TP.

[0107] In some embodiments, the touch control voltage stabilizing transistor T81 is an N-type transistor or a P-type transistor. The touch control voltage stabilizing transistor T81 is selected from any one of a low temperature polysilicon transistor, a metal oxide transistor, and a single crystal silicon transistor. Exemplarily, the touch control voltage stabilizing transistor T81 is an N-type low temperature polysilicon transistor.

[0108] The following combination Figure 2 and Figure 3 The gate driving circuit 100 of the present application embodiment is in the display stage (for example Figure 3 The display stage may include a first period, a second period, a third period, a fourth period, and a fifth period.

[0109] In the first period, ie, the reset period, the reset signal input terminal Reset outputs a reset signal of the third level, the reset transistor TrQ is turned on and outputs a touch signal of the second level to the first node, thereby resetting the first node.

[0110] In the second period, i.e., the pre-charge period, the second-stage signal input terminal ST(ni) inputs a high-level second-stage signal, and the first node control transistor T11 is turned on and charges the first node Q(n) to increase the voltage level of the first node Q(n).

[0111] In the third stage, i.e., the pull-up period, the first node Q(n) has a high voltage level, and the clock signal input terminal CK(n) inputs a high-level clock signal, the first output transistor T21 outputs the high-level clock signal as the first-stage transmission signal ST(N+j) to the first-stage transmission signal input terminal ST(n+j), and the third output transistor T22 outputs the high-level clock signal as the gate signal to the gate signal output terminal G(n). In addition, the capacitor Cb, through its own coupling effect, bootstraps the voltage level of the first node Q(n) according to the high-level clock signal output by the gate signal, and further pulls up the voltage level of the first node Q(n). Therefore, the voltage levels of the gate signal output terminal G(n) and the first-stage transmission signal input terminal ST(n+j) are pulled up to a high level.

[0112] In the fourth stage, i.e., the pull-down period, the first node Q(n) has a high voltage level, and the clock signal input terminal CK(n) inputs a low-level clock signal, the first output transistor T21 outputs the low-level clock signal as the first-stage transmission signal ST(N+j) to the first-stage transmission signal input terminal ST(n+j), and the third output transistor T22 outputs the low-level clock signal as the gate signal to the gate signal output terminal G(n). Therefore, the voltage levels of the gate signal output terminal G(n) and the first-stage transmission signal input terminal ST(n+j) are both pulled down to a low level.

[0113] In the fifth stage, i.e., the pull-down maintenance period, the second voltage input terminal LC1 outputs a high-level second-level signal, the first transistor T51 and the fourth transistor T53 are turned on, and the voltage level of the second node K(n) is pulled up. The first maintenance transistor T42 and the second maintenance transistor T41 are turned on according to the high level of the second node K(n), and the voltage level of the first node Q(n) is pulled down to the first-level signal of the low level. The third maintenance transistor T32 is turned on according to the high level of the second node K(n), and the voltage level of the gate signal output terminal G(n) is pulled down to the first-level signal of the low level. The fourth maintenance transistor T72 is turned on according to the high level of the second node, and the voltage level of the third-level transmission signal output terminal ST(n) is pulled down to the first-level signal of the low level. Therefore, the voltage levels of the first node Q(n), the gate signal output terminal G(n), and the third-level transmission signal output terminal ST(n) are all maintained at a low level.

[0114] In addition, during the entire display stage, the touch signal of the second level inputted from the touch signal input terminal TP causes the first node voltage regulator transistors (T91, T92) to be in a turned-off state.

[0115] In the touch stage, the clock signal input terminal CK(n) outputs a low-level pulse signal, for example, CK1 to CK8 are all low-level pulse signals. In addition, the reset signal input terminal Reset, the first voltage input terminal VGL, and the second voltage input terminal LC1 also output low-level pulse signals. Therefore, the gate drive unit stops outputting a high-level scan signal. At the same time, the touch signal input terminal TP inputs a first-level touch signal, and the touch voltage-stabilizing transistor T81 is turned on, and the low-level pulse signal input by the first voltage input terminal VGL is output to the gate signal output terminal G(n), stabilizing the voltage level of the gate signal output terminal G(n) at a low level.

[0116] Based on the same inventive concept, please refer to Figure 4 As shown, the embodiment of the present application also provides a display device 400. The display device 400 includes a display panel 500 and a touch layer 600. The touch layer 600 can be used with a stylus pen and sense a touch signal from the stylus pen to display information input by a user through the stylus pen on the display panel 500.

[0117] The touch layer 600 includes a plurality of touch electrodes. In some embodiments, the touch electrodes may be self-capacitive touch electrodes or mutual-capacitive touch electrodes. In an exemplary embodiment, the touch electrodes are self-capacitive touch electrodes.

[0118] In some embodiments, see Figure 4 As shown, the touch layer 600 may be integrated into the display panel 500 to reduce the thickness of the display device 400 .

[0119] In some embodiments, when the touch layer 600 is integrated into the display panel 500 , the touch layer 600 can be reused as an electrode layer.

[0120] In some embodiments, the touch layer 600 can be reused as a common electrode layer. In this case, multiple touch electrodes are reused as multiple common electrodes. By adopting the design of the gate drive circuit 100, when multiple touch electrodes are reused as multiple common electrodes, the display abnormality problem caused by stopping the selection of the scan line during the touch stage can be improved.

[0121] In some embodiments, the display panel 500 further includes a substrate 501. In the case where the touch layer 600 can be integrated inside the display panel 500, the touch layer 600 can be located on the substrate 501.

[0122] In some embodiments, the display panel 500 may include a pixel electrode layer 503 , and the pixel electrode layer 503 is insulated from the common electrode layer by an insulating layer. The pixel electrode layer 503 is located on the substrate 501 .

[0123] In some embodiments, the display panel 500 may further include a driving circuit layer 504 . The driving circuit layer 504 includes a pixel driving circuit. The driving circuit layer 504 is located between the pixel electrode layer 503 and the substrate 501 and between the common electrode layer and the substrate 501 .

[0124] In some embodiments, the display panel 500 may further include an opposing substrate 502. The substrate 501 and the opposing substrate 502 are disposed opposite to each other.

[0125] In some embodiments, a liquid crystal layer (not shown in the figure) may be disposed between the counter substrate 502 and the substrate 501. In this case, the display panel 500 is a liquid crystal display panel.

[0126] In some embodiments, the touch layer 600 may be located outside the display panel 500. The touch layer 600 may be formed on the display panel 500 through a panel manufacturing process, or may be bonded to the display panel 500 through an adhesive layer.

[0127] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: include: A first node control circuit configured to control a voltage level of the first node; a first maintaining circuit configured to maintain a voltage level of the first node according to a voltage level of the second node; a first output circuit configured to output a gate signal from a gate signal output terminal according to a voltage level of the first node; as well as The first node voltage stabilizing circuit is configured to be turned on during a touch period according to a touch signal of a first level input from a touch signal input terminal to control the voltage level of the second node to turn off the first maintaining circuit, thereby stabilizing the voltage level of the first node.

2. The gate driving circuit according to claim 1, characterized in that: The first node voltage stabilizing circuit is further configured to be turned off in a display phase according to a touch signal of a second level input from the touch signal input terminal, where the second level is lower than the first level.

3. The gate driving circuit according to claim 2, characterized in that: The first node voltage stabilizing circuit includes a first node voltage stabilizing transistor, a source and a drain of the first node voltage stabilizing transistor are connected between the second node and the first voltage input terminal, and a gate of the first node voltage stabilizing transistor is connected to the touch signal input terminal.

4. The gate drive circuit according to claim 1 or 2, characterized in that: The first sustaining circuit includes a first sustaining transistor, a source and a drain of the first sustaining transistor are connected between the first node and the touch signal input terminal, and a gate of the first sustaining transistor is connected to the second node.

5. The gate drive circuit according to claim 1 or 2, characterized in that: The gate driving circuit further includes a reset circuit, wherein the reset circuit is configured to connect the first node with the touch signal input terminal according to a reset signal of a third level input from the reset signal input terminal in a display stage, so as to reset the voltage level of the first node; and / or, The reset circuit is further configured to disconnect the first node from the touch signal input terminal according to a reset signal of a fourth level inputted from the reset signal input terminal during the touch period, wherein the fourth level is lower than the third level.

6. The gate driving circuit according to claim 5, characterized in that: The reset circuit includes a reset transistor, a source and a drain of the reset transistor are connected between the first node and the touch signal input terminal, and a gate of the reset transistor is connected to the reset signal input terminal.

7. The gate drive circuit according to claim 1 or 2, characterized in that: The gate driving circuit further includes a second maintaining circuit, wherein the second maintaining circuit is configured to connect the touch signal input terminal with the first node according to the first-level transmission signal of the fifth level inputted from the first-level transmission signal input terminal in the display stage, so as to maintain the potential of the first node; and / or, The second maintaining circuit is further configured to disconnect the first node from the touch signal input terminal according to a first-level transmission signal of a sixth level inputted from the first-level transmission signal input terminal during the touch period, wherein the sixth level is less than the fifth level.

8. The gate driving circuit according to claim 7, characterized in that: The second sustaining circuit includes a second sustaining transistor, a source and a drain of the second sustaining transistor are connected between the first node and the touch signal input terminal, and a gate of the second sustaining transistor is connected to the first-stage transmission signal input terminal.

9. The gate drive circuit according to claim 1 or 2, characterized in that: The gate driving circuit further includes a second node control circuit configured to make a phase of a voltage level of the second node opposite to a phase of a voltage level of the first node according to a voltage level of the first node.

10. The gate driving circuit according to claim 9, characterized in that: The second node control circuit includes a first transistor and a second transistor; The source and drain of the first transistor are connected between the second node and a second voltage input terminal, and the gate of the first transistor is connected to the second voltage input terminal; A source and a drain of the second transistor are connected between the second node and the first voltage input terminal, and a gate of the second transistor is connected to the first node.

11. The gate driving circuit according to claim 10, characterized in that: The second node control circuit also includes a third transistor, a source and a drain of the third transistor are connected between the second node and the first voltage input terminal, and a gate of the third transistor is connected to the second-stage signal input terminal.

12. The gate driving circuit according to claim 1 or 2, characterized in that: The first node control circuit comprises a first node control transistor, the source and drain of the first node control transistor are connected between the first node and the second-stage signal transmission input terminal or the start signal input terminal, and the gate of the first node control transistor is connected to the second-stage signal transmission input terminal or the start signal input terminal; and / or, The first output circuit comprises a first output transistor, a source and a drain of the first output transistor are connected between a clock signal input terminal for inputting a clock signal and the gate signal output terminal, and a gate of the first output transistor is connected to the first node; and / or, The first output circuit includes a second output transistor, the source and drain of the second output transistor are connected between the first voltage input terminal for inputting the first level signal and the gate signal output terminal, and the gate of the second output transistor is connected to the first level signal input terminal for inputting the first level signal; and / or, The gate driving circuit further includes a capacitor, and two electrodes of the capacitor are connected between the first node and the gate signal output terminal.

13. The gate driving circuit according to claim 1 or 2, characterized in that: The gate driving circuit further includes a third maintaining circuit configured to maintain a level voltage of the gate signal output terminal according to a voltage level of the second node.

14. The gate driving circuit according to claim 13, characterized in that: The third sustaining circuit includes a third sustaining transistor, a source and a drain of the third sustaining transistor are connected between the gate signal output terminal and the first voltage input terminal, and a gate of the third sustaining transistor is connected to the second node.

15. The gate driving circuit according to claim 1 or 2, characterized in that: The gate driving circuit further includes a second output circuit configured to output a third-level transmission signal from a third-level transmission signal output terminal according to a voltage level of the first node.

16. The gate driving circuit according to claim 15, characterized in that: The gate driving circuit further includes a fourth maintaining circuit, and the fourth maintaining circuit is configured to maintain the level voltage of the third-stage signal output terminal according to the level voltage of the second node.

17. The gate driving circuit according to claim 16, characterized in that: The second output circuit comprises a third output transistor, the source and drain of the third output transistor are connected between the third stage signal output terminal and the clock signal input terminal, and the gate of the third output transistor is connected to the first node; and / or, The fourth sustaining circuit comprises a fourth sustaining transistor, a source and a drain of the fourth sustaining transistor are connected between the third-stage signal output terminal and the first voltage input terminal, and a gate of the fourth sustaining transistor is connected to the second node.

18. The gate driving circuit according to claim 1 or 2, characterized in that: The gate driving circuit also includes a touch voltage stabilization circuit, which is configured to be turned on during the touch period according to the touch signal of the first level to stabilize the voltage level of the gate signal output terminal; the touch voltage stabilization circuit is also configured to be turned off during the display stage according to the touch signal of the second level input from the touch signal input terminal, and the second level is lower than the first level.

19. The gate driving circuit according to claim 18, characterized in that: The touch voltage stabilizing circuit includes a touch voltage stabilizing transistor, a source and a drain of the touch voltage stabilizing transistor are connected between the gate signal output terminal and the first voltage input terminal, and a gate of the touch voltage stabilizing transistor is connected to the touch signal input terminal.

20. A display device, characterized in that: The display device comprises the gate driving circuit according to any one of claims 1 to 19.

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