Semiconductor structure and array display chip
By using temporary substrates adapted to thermal expansion coefficient to fix the sapphire chip array, the bonding offset between sapphire and silicon-based CMOS device substrate is solved, and the bonding accuracy and product yield are improved.
Patent Information
- Application Number
- CN202421319929.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-11
- Publication Date
- 2025-03-21
- Estimated Expiration
- 2034-06-11
AI Technical Summary
The offset is large when aligned and bonded between sapphire and silicon-based CMOS device substrate, resulting in poor pixel leakage and heat dissipation, affecting the yield of the final product.
A temporary substrate is used, and the difference between the thermal expansion coefficient and the thermal expansion coefficient of the substrate of the semiconductor driver device is within a preset range, and is used to fix the sapphire chip array to avoid bonding offsets caused by the difference in thermal expansion coefficient between the sapphire substrate and the semiconductor driver device substrate.
The accuracy of bonding alignment is improved, wafer-level alignment bonding is achieved, and pixel leakage and heat dissipation are avoided, thereby greatly improving the yield of the final product.
Smart Images
Figure CN222655679U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a semiconductor device, in particular to a semiconductor structure and an array display chip. Background Art
[0002] In the current production process of micro array chips or AR display chips, sapphire substrates, as a substrate that can grow micro array chips with high quality, have become the preferred choice of technicians in the field.
[0003] Micro array chips are usually integrated with CMOS devices as the final chip products. In the production process of the final chip products, it usually involves the transfer bonding process between the wafer-level array chip and the CMOS device substrate. The usual practice is to directly bond the sapphire substrate to the substrate of the CMOS device to form the final required chip product.
[0004] However, the large offset during alignment and bonding between sapphire and the silicon-based CMOS device substrate will cause pixel leakage and poor heat dissipation, thus affecting the final product yield. Utility Model Content
[0005] The technical problem solved by the utility model is that a large offset during alignment and bonding between sapphire and a silicon-based CMOS device substrate causes pixel leakage and poor heat dissipation. A semiconductor structure and an array display chip are provided to solve the problem that a large offset during alignment and bonding between sapphire and a silicon-based CMOS device substrate causes pixel leakage and poor heat dissipation.
[0006] In order to solve the above technical problems, an embodiment of the utility model provides a semiconductor structure for bonding with a substrate having a semiconductor driver device formed thereon, comprising:
[0007] A temporary substrate, wherein the difference between the thermal expansion coefficient of the temporary substrate and the thermal expansion coefficient of the substrate of the semiconductor driving device is within a preset range;
[0008] The sapphire chip array bonded to the temporary substrate includes: a plurality of pixel units;
[0009] An N-bonding electrode and a P-bonding electrode located on the pixel unit;
[0010] A passivation layer wraps the pixel unit, and the N-bonding electrode and the P-bonding electrode are exposed on the surface of the passivation layer.
[0011] Optionally, the preset range is 0 μm to 0.5 μm.
[0012] Optionally, the thermal expansion coefficient of the temporary substrate is the same as the thermal expansion coefficient of the substrate inside the semiconductor driving device.
[0013] Optionally, the material of the temporary substrate is the same as the material of the substrate inside the semiconductor driver device.
[0014] Optionally, the temporary substrate and the semiconductor driver device inner substrate are both silicon substrates, or the temporary substrate and the semiconductor driver device inner substrate are both glass substrates.
[0015] Optionally, the temporary substrate and the sapphire chip array are temporarily bonded via a temporary bonding layer.
[0016] Optionally, the temporary bonding layer is organic glue or a bonding medium.
[0017] Optionally, each of the pixel units includes an N-type epitaxial layer located on the temporary substrate, a quantum well light-emitting layer located on the N-type epitaxial layer, a P-type epitaxial layer located on the quantum well light-emitting layer, and a metal reflective layer located on the P-type epitaxial layer; the N-bonding electrode is located on the N-type epitaxial layer, and the P-bonding electrode is located on the P-type epitaxial layer.
[0018] Optionally, an N interconnection conductive structure is also included, and the N interconnection conductive structure is used to connect a plurality of N bonding electrodes in a plurality of the pixel units.
[0019] Optionally, the sapphire chip array is a micro LED sapphire chip array.
[0020] An embodiment of the present invention further provides an array display chip, which is prepared using the semiconductor structure described in the foregoing embodiment of the present invention, and the array display chip also includes a semiconductor driving device bonded to the semiconductor structure.
[0021] Compared with the prior art, the technical solution of the embodiment of the utility model has the following beneficial effects:
[0022] The utility model provides a semiconductor structure, which ensures the growth quality of the sapphire chip array by using a sapphire chip array grown on a sapphire substrate. The utility model provides a temporary substrate that is adapted to the substrate expansion coefficient of a desired semiconductor driver device, so that when the sapphire chip array and the temporary substrate are transferred together and bonded to the desired driver device, the problem of bonding offset caused by the difference in substrate expansion coefficients between the sapphire substrate and the desired driver device is avoided, thereby improving the accuracy of bonding alignment, realizing wafer-level alignment bonding, and further avoiding the problems of leakage and poor heat dissipation of each pixel unit in the array chip caused by the bonding offset of the sapphire chip array, thereby greatly improving the yield of the final product after the bonding transfer.
[0023] Furthermore, when the sapphire chip array is a micro LED chip, compared with gallium nitride and silicon substrates, micro LED chips grown epitaxially using sapphire substrates can better meet quality requirements. During the transfer process of the micro LED sapphire chip array, the problem of bonding offset caused by the difference in expansion coefficient between the sapphire substrate and the substrate of the required driving device is more prominent and cannot be ignored. The subsequent transfer bonding process provided by the embodiment of the utility model on the temporary substrate with a micro LED chip structure has a more obvious improvement in the accuracy of bonding alignment, and thus the improvement of the leakage and heat dissipation problems of each pixel unit in the micro LED chip caused by the bonding offset is more prominent, thereby greatly improving the yield of the final micro LED array product after the bonding transfer. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 It is a structural schematic diagram of a semiconductor structure provided by an embodiment of the utility model;
[0025] Figure 2 It is a structural schematic diagram of a semiconductor structure provided by another embodiment of the utility model. DETAILED DESCRIPTION
[0026] As described in the background art, there is a large offset between sapphire and a silicon-based CMOS device substrate during alignment and bonding, which leads to problems of pixel leakage and poor heat dissipation.
[0027] In the traditional transfer bonding process, the sapphire substrate is directly bonded to the substrate of the CMOS device to form the final desired chip product. However, due to the large thermal expansion difference between sapphire and the silicon-based CMOS device substrate, it will cause a large alignment and bonding offset, which will lead to pixel leakage and poor heat dissipation, affecting the final product yield.
[0028] In order to solve the above problems, an embodiment of the utility model provides a semiconductor structure for bonding to a substrate formed with a semiconductor driver device, including: a temporary substrate, the difference between the thermal expansion coefficient of the temporary substrate and the thermal expansion coefficient of the substrate of the semiconductor driver device is within a preset range; a sapphire chip array bonded to the temporary substrate, including: a plurality of pixel units; an N-bonding electrode and a P-bonding electrode located on the pixel units; a passivation layer wrapping the pixel unit, and the N-bonding electrode and the P-bonding electrode are exposed on the surface of the passivation layer.
[0029] By fixing the sapphire chip array on a temporary substrate selected to match the thermal expansion coefficient of the substrate of the desired semiconductor driver device, the problem of bonding offset caused by the difference in thermal expansion coefficient between the sapphire substrate for growing the sapphire chip array and the substrate of the semiconductor driver device is avoided.
[0030] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0031] Figure 1 It is a schematic diagram of a semiconductor structure according to an embodiment of the utility model.
[0032] Please refer to Figure 1 The semiconductor structure is used to include: a temporary substrate 101. The difference between the thermal expansion coefficient of the temporary substrate 101 and the thermal expansion coefficient of the substrate of the semiconductor driving device is within a preset range.
[0033] The preset range is 0 μm to 0.5 μm.
[0034] In a typical implementation, the temporary substrate 101 and the substrate of the semiconductor driver device are made of the same material. In some specific examples, the temporary substrate 101 and the substrate of the semiconductor driver device are both silicon substrates, or the temporary substrate 101 and the substrate of the semiconductor driver device are both glass substrates.
[0035] The temporary substrate is used to temporarily carry the sapphire chip array. The utility model adapts the temporary substrate to the material of the substrate of the semiconductor driver device to be integrated, so that the temporary substrate and the substrate of the semiconductor driver device have the same or similar thermal expansion coefficient, avoiding the problem of bonding offset caused by direct bonding of the sapphire substrate with a large difference in thermal expansion coefficients to the silicon substrate or glass substrate of the semiconductor driver device, achieving wafer-level precision bonding of the sapphire chip array and the semiconductor driver device, eliminating the problems of leakage and poor heat dissipation of each pixel unit in the sapphire chip array caused by bonding offset, thereby improving the yield of the bonded product.
[0036] The sapphire chip array bonded to the temporary substrate 101 includes a plurality of pixel units, each of which includes an N-type epitaxial layer 103, a quantum well light-emitting layer 104 located on the N-type epitaxial layer 103, a P-type epitaxial layer 105 located on the quantum well light-emitting layer 104, and a metal reflective layer 106 located on the P-type epitaxial layer 105.
[0037] An N-bonding electrode 107 located on the N-type epitaxial layer 103 , and a P-bonding electrode 110 located on a portion of the P-type epitaxial layer 105 .
[0038] The metal reflective layer 106 is used to form a good ohmic contact between the P-type epitaxial layer 105 and the P bonding electrode 110 and produce a good reflection effect.
[0039] The sapphire chip array is formed on a sapphire substrate and then transferred to a temporary substrate by chemical stripping, thereby ensuring the epitaxial growth quality of the sapphire chip array.
[0040] The semiconductor structure further includes: an N bonding electrode 107 and a P bonding electrode 110 located on the pixel unit.
[0041] A passivation layer 108 wraps the pixel unit, and the surface of the passivation layer 108 exposes the surface of the P bonding electrode 110 and the N bonding electrode 107 .
[0042] An N interconnection conductive structure 109 is provided to connect a plurality of the N-type epitaxial layers 103. The N interconnection conductive structure 109 is used to form a circuit connection bridge inside the array chip, so as to form a complete circuit structure.
[0043] In a specific example, in a single pixel unit, the N-type epitaxial layer 103 is an N-GaN layer, the P-type epitaxial layer 105 is a P-GaN layer, and the quantum dot light-emitting layer 104 is an MQW layer for emitting blue light. Before being transferred to a temporary substrate, the pixel unit formed on a sapphire substrate is a sapphire chip.
[0044] Of course, the sapphire chip array provided by the present invention is not only applicable to the vertical chip structure, but also to the flip-chip structure. The specific structures of the vertical chip structure or the flip-chip structure are technologies that those skilled in the art should know, and the present invention will not elaborate on them here.
[0045] In a typical example, the sapphire chip array is a micro LED sapphire chip array. Since the size of each pixel unit in the micro LED sapphire chip array is smaller, the aforementioned bonding offset is more obvious. Therefore, when the semiconductor structure provided by the utility model is applicable to the transfer bonding of the micro LED sapphire chip array, the effect is more obvious and the control of the bonding accuracy is more significant. Of course, the scope of the sapphire chip array in the semiconductor structure provided by the utility model is not limited to the micro LED sapphire chip array, and can also be other sapphire chip arrays that can be used to improve the bonding alignment accuracy. The utility model will not list them specifically here.
[0046] The sapphire chip array is bonded to the temporary substrate via a temporary bonding layer 102. This temporary bonding method is not affected by the thermal expansion coefficient and will not have any impact on subsequent bonding.
[0047] The temporary bonding layer 102 is a bonding layer that is easy to peel off. Any implementation of the temporary bonding layer 102 is within the protection scope of the present invention, and the present invention does not limit it.
[0048] In some specific examples, the temporary bonding layer 102 can be selected to be an organic glue or a dielectric material according to the material of the temporary substrate.
[0049] In a specific example, the organic glue or dielectric material can be removed by dissolving with acetone or washing with water.
[0050] In summary, the semiconductor structure provided by the utility model provides a sapphire chip array located on a temporary substrate, so that the temporary substrate can select a substrate type that matches the thermal expansion coefficient of the semiconductor driver device, thereby solving the problem of transfer bonding deviation caused by the large thermal expansion coefficient between the sapphire substrate and the semiconductor driver device. The utility model still ensures that the sapphire chip array is a high-quality sapphire chip array grown on the sapphire substrate. Therefore, the semiconductor structure provided by the utility model not only achieves a significant improvement in the subsequent bonding transfer accuracy, but also greatly ensures the improvement of product yield.
[0051] Figure 2 It is a structural schematic diagram of a semiconductor structure provided by another embodiment of the utility model.
[0052] In another embodiment of the present invention, another semiconductor structure is provided. The difference between the semiconductor structure in this embodiment and the semiconductor structure in the aforementioned embodiment is only the difference in the connection method of the N electrode in the sapphire chip array.
[0053] In this embodiment, no N-interconnect conductive interconnect structure is provided, but an N-bonding electrode is provided in each pixel unit, and the passivation layer exposes all the N-bonding electrodes and the P-bonding electrodes.
[0054] Please refer to Figure 2 Similarly, the present embodiment also includes a temporary substrate 101; a sapphire chip array bonded to the temporary substrate 101 through a temporary bonding layer 102, including a plurality of pixel units, each of which includes an N-type epitaxial layer 103, a quantum well light-emitting layer 104 located on the N-type epitaxial layer 102, a P-type epitaxial layer 105 located on the quantum well light-emitting layer 104, and a metal reflective layer 106 located on the P-type epitaxial layer 105; an N-bonding electrode 107 located on the N-type epitaxial layer 103. A passivation layer 108 located on the temporary substrate 101, the passivation layer 108 exposing all of the N-bonding electrode 107 and the P-bonding electrode 110.
[0055] The electrode bonding structure provided in this embodiment makes the subsequent electrical interconnection method more flexible and has a wider scope of application.
[0056] In summary, the semiconductor structure provided by the present invention also solves the problem of transfer bonding deviation caused by the large thermal expansion coefficient between the sapphire substrate and the semiconductor driver device, achieves a significant improvement in the subsequent bonding transfer accuracy, greatly ensures the improvement of product yield, and the electrical interconnection method between pixel units in the sapphire chip array provided by this embodiment is more flexible and has a wider range of applications.
[0057] Although the utility model is disclosed as above, the utility model is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the utility model. Therefore, the protection scope of the utility model shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure for bonding to a substrate having a semiconductor driver device formed thereon, characterized in that: include: A temporary substrate, wherein the difference between the thermal expansion coefficient of the temporary substrate and the thermal expansion coefficient of the substrate of the semiconductor driving device is within a preset range; The sapphire chip array bonded to the temporary substrate includes: a plurality of pixel units; An N-bonding electrode and a P-bonding electrode located on the pixel unit; A passivation layer wraps the pixel unit, and the N-bonding electrode and the P-bonding electrode are exposed on the surface of the passivation layer.
2. The semiconductor structure according to claim 1, wherein: The preset range is 0 μm to 0.5 μm.
3. The semiconductor structure according to claim 1, wherein: The thermal expansion coefficient of the temporary substrate is the same as the thermal expansion coefficient of the substrate in the semiconductor driving device.
4. The semiconductor structure according to claim 3, characterized in that The material of the temporary substrate is the same as that of the substrate inside the semiconductor driving device.
5. The semiconductor structure according to claim 4, characterized in that The temporary substrate and the semiconductor driver device inner substrate are both silicon substrates, or the temporary substrate and the semiconductor driver device inner substrate are both glass substrates.
6. The semiconductor structure according to claim 1, wherein: The temporary substrate and the sapphire chip array are temporarily bonded via a temporary bonding layer.
7. The semiconductor structure according to claim 6, wherein: The temporary bonding layer is organic glue or bonding medium.
8. The semiconductor structure according to claim 1, wherein: Each of the pixel units includes an N-type epitaxial layer located on the temporary substrate, a quantum well light-emitting layer located on the N-type epitaxial layer, a P-type epitaxial layer located on the quantum well light-emitting layer, and a metal reflective layer located on the P-type epitaxial layer; the N-bonding electrode is located on the N-type epitaxial layer, and the P-bonding electrode is located on the P-type epitaxial layer.
9. The semiconductor structure according to claim 1 or 8, characterized in that: It also includes an N interconnection conductive structure, which is used to connect a plurality of N bonding electrodes in a plurality of the pixel units.
10. The semiconductor structure according to claim 1, wherein: The sapphire chip array is a micro LED sapphire chip array.
11. An array display chip, prepared using the semiconductor structure according to any one of claims 1 to 10, and the array display chip further comprises a semiconductor driving device bonded to the semiconductor structure.