Filter shaping circuit applied to enable port, low dropout regulator and power management unit

Abstract

The invention provides a filter shaping circuit applied to an enable port, a low dropout regulator and a power management unit, and relates to the technical field of integrated circuit design, the output end of a first phase inverter is connected with the input end of a NOR gate, and the grid electrode of a second NMOS tube is connected with the input end of a NAND gate through a second phase inverter; the grid electrode of the first NMOS tube is connected with the output end of the NOR gate, and the drain electrode is connected with power supply voltage through a grid voltage adjusting circuit; the drain electrode of the second NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode and the grid electrode of the first PMOS tube are respectively connected with a power supply voltage and a grid voltage adjusting circuit; two ends of the charging and discharging device are respectively connected with a power supply voltage and a drain electrode of the first PMOS tube; the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube and connected with the grid electrode of the third NMOS tube through a third phase inverter. The output end of the third inverter is connected with the input end of the NOR gate and the input end of the NAND gate. The beneficial effect is that burr signals are effectively filtered.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a filter shaping circuit, a low voltage dropout regulator and a power management unit applied to an enable port. Background Art

[0002] In highly integrated modern electronic systems, enable ports are key interfaces that connect control signals to functional circuits, and their stability and reliability are critical to the normal operation of the entire system. Enable signals are transmitted through these ports to activate or disable specific circuit modules, such as power management units, data converters, communication interfaces, etc.

[0003] However, with the increasing complexity of the system and the variability of the working environment, the enable signal on the enable port faces more and more interference and challenges. These interferences may come from other circuit modules inside the system or from the external environment. Internal interference may include power supply noise, digital circuit noise, analog circuit interference, etc. These interferences are coupled to the enable port through the power line, ground line or signal line, resulting in instability of the enable signal. External interference may include electromagnetic interference (EMI), electrostatic discharge (ESD) and instability of the external power supply, etc. These interferences enter the electronic system through antenna effect, direct conduction or coupling, further affecting the accuracy of the enable signal.

[0004] The impact of the fluctuation of the enable port on the subsequent circuit cannot be ignored. On the one hand, the fluctuating enable signal may cause the circuit module to trigger falsely or work in an unstable state, thus affecting the performance and stability of the entire system. On the other hand, long-term fluctuations may also accelerate the aging of circuit components and shorten the life of the equipment. Therefore, reducing the fluctuation of the enable port and improving the stability and reliability of the enable signal have become urgent problems to be solved. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides a filtering and shaping circuit applied to an enabling port, comprising:

[0006] A first inverter, wherein an input end of the first inverter is connected to an external enable signal, an output end of the first inverter is connected to an input end of a NOR gate, and is connected to an input end of a NAND gate through a second inverter;

[0007] A first NMOS transistor, wherein the gate of the first NMOS transistor is connected to the output end of the NOR gate, the drain is connected to the power supply voltage through a gate voltage regulating circuit, and the source is grounded;

[0008] a second NMOS transistor, wherein the gate of the second NMOS transistor is connected to the output end of the first inverter, the source is grounded, the drain is connected to the drain of the first PMOS transistor, and the source and gate of the first PMOS transistor are respectively connected to the power supply voltage and the gate voltage regulating circuit;

[0009] A charge-discharge device, one end of which is connected to the power supply voltage, and the other end of which is connected to the drain of the first PMOS tube;

[0010] a second PMOS tube, wherein the gate of the second PMOS tube is connected to the drain of the first PMOS tube, the source is connected to the power supply voltage, the drain is respectively connected to the drains of the third NMOS tube and the fourth NMOS tube, the sources of the third NMOS tube and the fourth NMOS tube are grounded, the gate of the fourth NMOS tube is connected to the gate voltage regulating circuit, and the drain of the second PMOS tube is also connected to the gate of the third NMOS tube through a third inverter;

[0011] The output end of the third inverter is respectively connected to the input end of the NOR gate and the input end of the NAND gate, and the output end of the NAND gate is connected to the enable port.

[0012] Preferably, the gate voltage regulating circuit comprises:

[0013] a third PMOS tube, wherein a source of the third PMOS tube is connected to the power supply voltage, a drain of the third PMOS tube is connected to the drain of the first NMOS tube via a first resistor, and the drain of the third PMOS tube is also connected to the gate of the first PMOS tube;

[0014] a fourth PMOS tube, wherein a source of the fourth PMOS tube is connected to the power supply voltage, and a gate is respectively connected to the gate and the drain of the third PMOS tube, and is connected to the gate of the first PMOS tube;

[0015] A fifth NMOS tube, wherein the source of the fifth NMOS tube is grounded, the gate and the drain are short-circuited, and the drain of the fifth NMOS tube is also connected to the drain of the fourth PMOS tube.

[0016] Preferably, it further comprises a fifth PMOS tube, wherein the source of the fifth PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the second NMOS tube;

[0017] The output end of the third inverter is connected to the gate of the fifth PMOS tube through the fourth inverter.

[0018] Preferably, the charging and discharging device is a capacitor.

[0019] Preferably, the charging and discharging device is a sixth PMOS tube, the source and drain of the sixth PMOS tube are short-circuited and connected to the power supply voltage, and the gate of the sixth PMOS tube is connected to the drain of the second NMOS tube.

[0020] Preferably, the enable port is effective when at a high level, and is invalid when at a low level or when left floating.

[0021] The present invention also provides a low voltage dropout regulator, wherein an enable port of the low voltage dropout regulator is connected to the above-mentioned filtering and shaping circuit.

[0022] The present invention also provides a power management unit, comprising the above-mentioned low voltage dropout regulator.

[0023] The above technical solution has the following advantages or beneficial effects: when the external enable signal changes from a low level to a high level, a certain signal delay can be generated by charging the charge-discharge device, thereby achieving a delayed flip of the signal output to the enable port, thereby effectively filtering the glitch signal and reducing functional errors. At the same time, it has the advantages of simple structure, small chip area and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A circuit diagram of a filter shaping circuit applied to an enabling port in a preferred embodiment of the present invention;

[0025] Figure 2 A circuit diagram of a filter shaping circuit applied to an enabling port in a preferred embodiment of the present invention;

[0026] Figure 3 A schematic diagram for verifying the filtering and shaping results of the filtering and shaping circuit in a preferred embodiment of the present invention;

[0027] Figure 4 FIG. 1 is a circuit diagram of a low voltage dropout regulator in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0029] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a filtering and shaping circuit applied to an enabling port is provided, such as Figure 1 and Figure 2 As shown, including:

[0030] A first inverter INV1, wherein an input end of the first inverter INV1 is connected to an external enable signal EN_L, an output end of the first inverter INV1 is connected to an input end of a NOR gate NOR, and is connected to an input end of a NAND gate NAND through a second inverter INV2;

[0031] A first NMOS transistor NM1, wherein the gate of the first NMOS transistor NM1 is connected to the output end of the NOR gate NOR, the drain is connected to the power supply voltage VDD through the gate voltage regulating circuit 100, and the source is grounded;

[0032] A second NMOS transistor NM2, the gate of the second NMOS transistor NM2 is connected to the output end of the first inverter INV1, the source is grounded, the drain is connected to the drain of the first PMOS transistor PM1, and the source and gate of the first PMOS transistor PM1 are respectively connected to the power supply voltage VDD and the gate voltage regulating circuit 100;

[0033] A charge-discharge device 200, one end of which is connected to a power supply voltage VDD, and the other end of which is connected to a drain of a first PMOS transistor PM1;

[0034] a second PMOS transistor PM2, wherein the gate of the second PMOS transistor PM2 is connected to the drain of the first PMOS transistor PM1, the source is connected to the power supply voltage VDD, the drain is respectively connected to the drains of the third NMOS transistor NM3 and the fourth NMOS transistor NM4, the sources of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are grounded, the gate of the fourth NMOS transistor NM4 is connected to the gate voltage regulating circuit 100, and the drain of the second PMOS transistor PM2 is also connected to the gate of the third NMOS transistor NM3 through the third inverter INV3;

[0035] The output end of the third inverter INV3 is respectively connected to the input end of the NOR gate NOR and the input end of the NAND gate NAND, and the output end of the NAND gate NAND is connected to the enable port.

[0036] Specifically, in this embodiment, when the circuit is normal, the external enable signal EN_L is at a low level, and the output signal A is at a high level after passing through the first inverter INV1, and the output signal A is connected to the gate of the second NMOS tube NM2, and the second NMOS tube NM2 is turned on. Since the source of the second NMOS tube NM2 is grounded, and the drain is connected to the gate of the second PMOS tube PM2, the low level is connected to the gate of the second PMOS tube PM2, and the second PMOS tube PM2 is turned on. Since the source of the second PMOS tube PM2 is connected to the power supply voltage, the output signal D of the second PMOS tube PM2 is at a high level. After the output signal D passes through the third inverter INV3, the output signal C is at a low level, and then the two inputs of the NAND gate NAND are both at a low level, and the output signal EN_H at the output end of the NAND gate NAND is at a high level.

[0037] When the external enable signal EN_L jumps from a low level to a high level, the output signal A jumps from a high level to a low level, and the output signal C remains at a low level. At this time, both inputs of the NOR gate NOR are at a low level, and then the output signal B is at a high level, so that the first NMOS tube NM1 is turned on. Since the output signal A is at a low level, it is connected to the gate of the second NMOS tube NM2, and the second NMOS tube NM2 is not turned on. Since the source of the first NMOS tube NM1 is grounded, the gate of the first PMOS tube PM1 is connected to a low level and turned on, so that the charging and discharging device 200 is charged, a certain signal delay is generated, so that the gate voltage of the second PMOS tube PM2 is delayed to reach a high level, that is, delayed shutdown, and then the output signal D can be delayed to jump, so that the output signal C can be delayed to jump, and finally the output signal EN_H is delayed to jump to a low level, so that the burrs can be effectively filtered, and there is a certain anti-disturbance ability. The overall circuit is implemented based on logic gates and MOS tubes, and has the advantages of simple structure, small chip area, and low power consumption.

[0038] like Figure 3 As shown, the upper part of the figure is the external enable signal, and it can be seen that it contains two glitches. The filtering and shaping circuit based on the present invention can obtain the signal waveform of the lower part of the figure, and can filter the two glitches.

[0039] In a preferred embodiment of the present invention, the gate voltage regulating circuit 100 comprises:

[0040] a third PMOS transistor PM3, wherein the source of the third PMOS transistor PM3 is connected to the power supply voltage VDD, the drain of the third PMOS transistor PM3 is connected to the drain of the first NMOS transistor NM1 through the first resistor R1, and the drain of the third PMOS transistor PM3 is also connected to the gate of the first PMOS transistor PM1;

[0041] a fourth PMOS transistor PM4, wherein the source of the fourth PMOS transistor PM4 is connected to the power supply voltage VDD, and the gate is respectively connected to the gate and drain of the third PMOS transistor PM3, and is connected to the gate of the first PMOS transistor PM1;

[0042] A fifth NMOS tube NM5 , a source of the fifth NMOS tube NM5 is grounded, a gate and a drain are short-circuited, and a drain of the fifth NMOS tube NM5 is also connected to a drain of the fourth PMOS tube PM4 .

[0043] Specifically, in this embodiment, the gate voltage regulating circuit 100 is used to provide corresponding gate voltages for the first PMOS transistor PM1 and the fourth NMOS transistor NM4 .

[0044] In a preferred embodiment of the present invention, a fifth PMOS transistor PM5 is further included, wherein the source of the fifth PMOS transistor PM5 is connected to the power supply voltage, and the drain is connected to the drain of the second NMOS transistor NM2;

[0045] The output end of the third inverter INV3 is connected to the gate of the fifth PMOS transistor PM5 through the fourth inverter INV4.

[0046] Specifically, in this embodiment, by providing a fifth PMOS tube, when the output signal C jumps to a high level, a low level acts on the gate of the fifth PMOS tube to turn it on, thereby ensuring that the second PMOS tube is completely turned off, further saving power consumption.

[0047] In a preferred embodiment of the present invention, the charge-discharge device 200 is a capacitor.

[0048] In a preferred embodiment of the present invention, the charge and discharge device 200 is a sixth PMOS tube, the source and drain of the sixth PMOS tube are short-circuited and connected to the power supply voltage VDD, and the gate of the sixth PMOS tube is connected to the drain of the second NMOS tube NM2.

[0049] In a preferred embodiment of the present invention, the enable port is effective when the high level is high, and is ineffective when the low level or the port is suspended.

[0050] The present invention also provides a low voltage dropout regulator, such as Figure 4 As shown, the enable port of the low voltage dropout regulator is connected to the above-mentioned filter shaping circuit. Among them, the enable port EN is connected to the output end of the NAND gate NAND of the filter shaping circuit, V IN is the input voltage of the low dropout regulator, C IN is the input capacitance of the low dropout regulator, V OUT is the output voltage of the low dropout regulator, C OUT is the output capacitor of the low dropout regulator.

[0051] The present invention also provides a power management unit, comprising the above-mentioned low voltage dropout regulator.

[0052] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A filter shaping circuit applied to an enabling port, characterized in that: include: A first inverter, wherein an input end of the first inverter is connected to an external enable signal, an output end of the first inverter is connected to an input end of a NOR gate, and is connected to an input end of a NAND gate through a second inverter; A first NMOS transistor, wherein the gate of the first NMOS transistor is connected to the output end of the NOR gate, the drain is connected to the power supply voltage through a gate voltage regulating circuit, and the source is grounded; a second NMOS transistor, wherein the gate of the second NMOS transistor is connected to the output end of the first inverter, the source is grounded, the drain is connected to the drain of the first PMOS transistor, and the source and gate of the first PMOS transistor are respectively connected to the power supply voltage and the gate voltage regulating circuit; A charge-discharge device, one end of which is connected to the power supply voltage, and the other end of which is connected to the drain of the first PMOS tube; a second PMOS tube, wherein the gate of the second PMOS tube is connected to the drain of the first PMOS tube, the source is connected to the power supply voltage, the drain is respectively connected to the drains of the third NMOS tube and the fourth NMOS tube, the sources of the third NMOS tube and the fourth NMOS tube are grounded, the gate of the fourth NMOS tube is connected to the gate voltage regulating circuit, and the drain of the second PMOS tube is also connected to the gate of the third NMOS tube through a third inverter; The output end of the third inverter is respectively connected to the input end of the NOR gate and the input end of the NAND gate, and the output end of the NAND gate is connected to the enable port.

2. The filter shaping circuit according to claim 1, characterized in that: The gate voltage regulating circuit comprises: a third PMOS tube, wherein a source of the third PMOS tube is connected to the power supply voltage, a drain of the third PMOS tube is connected to the drain of the first NMOS tube via a first resistor, and the drain of the third PMOS tube is also connected to the gate of the first PMOS tube; a fourth PMOS tube, wherein a source of the fourth PMOS tube is connected to the power supply voltage, and a gate is respectively connected to the gate and the drain of the third PMOS tube, and is connected to the gate of the first PMOS tube; A fifth NMOS tube, wherein the source of the fifth NMOS tube is grounded, the gate and the drain are short-circuited, and the drain of the fifth NMOS tube is also connected to the drain of the fourth PMOS tube.

3. The filter shaping circuit according to claim 1, characterized in that: It also includes a fifth PMOS tube, wherein the source of the fifth PMOS tube is connected to the power supply voltage, and the drain is connected to the drain of the second NMOS tube; The output end of the third inverter is connected to the gate of the fifth PMOS tube through the fourth inverter.

4. The filter shaping circuit according to claim 1, characterized in that: The charging and discharging device is a capacitor.

5. The filter shaping circuit according to claim 1, characterized in that: The charging and discharging device is a sixth PMOS tube, the source and drain of the sixth PMOS tube are short-circuited and connected to the power supply voltage, and the gate of the sixth PMOS tube is connected to the drain of the second NMOS tube.

6. The filter shaping circuit according to claim 1, characterized in that: The enable port is effective when the high level is high, and is invalid when the low level or floating.

7. A low voltage dropout regulator, characterized in that: The enable port of the low voltage dropout regulator is connected to the filter shaping circuit as described in any one of claims 1-6.

8. A power management unit, characterized in that: The invention comprises the low voltage dropout regulator as claimed in claim 7.

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