CPLD-based CPU reset method, device and system and storage medium

Abstract

The invention provides a CPLD (Complex Programmable Logic Device)-based CPU (Central Processing Unit) resetting method, device and system and a storage medium, which solve the problems of DDR (Double Data Rate) data loss, long CPU resetting waiting time, incapability of responding to interruption in some states of a CPU, possibility of abnormal resetting of the CPU caused by the CPLD and the like in the prior art through collaborative design of hardware and software, realize accurate control on CPU resetting and improve the CPU resetting efficiency. The stability and reliability of the system are improved, and meanwhile key information before resetting is reserved so as to facilitate system maintenance and troubleshooting.

Description

Technical Field

[0001] The present application belongs to the field of industrial control technology, and specifically relates to a CPU reset method, device, system and storage medium based on CPLD. Background Art

[0002] When a serious error occurs during the operation of an embedded system, it is usually necessary to reset the CPU to restore the normal operation of the system. Error conditions are divided into two categories: one is an error that can be identified by the application or the CPU core. In this case, the reset signal can be triggered by an external reset chip (usually a watchdog chip) after performing the pre-reset preparation work, that is, the system actively resets; the other is an error that cannot be identified by the application and the CPU core. It is mostly caused by hidden bugs in the application or hardware environment factors. When this error occurs, reset preparation cannot be performed, and the reset signal is directly triggered by the external reset chip, that is, the system is passively reset.

[0003] In industrial control systems, especially in process industries, it is expected that the equipment can run stably and continuously for a long time and recover quickly after reset. However, the existing CPU reset technology has many shortcomings: 1. Directly use the watchdog reset to monitor the CPU operation. When the CPU is abnormal, the WDO outputs a pulse signal to reset the CPU and DDR at the same time, which will cause the DDR data to be lost during the reset, and all the information and data before the reset will be lost, which is not conducive to equipment maintenance and problem troubleshooting.

[0004] 2. Add a delay circuit to the WDO end of the watchdog reset, connect the WDO signal to the CPU's GPIO, and connect the delay circuit output to the CPU reset signal. This method has the problem of a long waiting time from the CPU exception to the reset, which requires waiting for the watchdog WDT timeout and the delay circuit time, and some CPU states (such as entering an abnormal interrupt) cannot respond to GPIO interrupts and cannot record relevant information.

[0005] 3. Add a CPLD chip to monitor the CPU, and connect the watchdog WDI signal to the CPLD at the same time. In passive reset, the CPLD outputs a pulse signal before the watchdog resets the CPU, and the GPIO interrupt allows the CPU to sense the reset event in advance. In active reset, the CPU directly writes to the CPLD register after processing the reset preparation work. The CPLD is directly connected to the CPU reset pin, and the CPLD outputs a pulse signal to reset the CPU. However, in this way, some states of the CPU cannot respond to the GPIO interrupt, and there are risks in reset. In addition, the CPLD requires logic programming. Once the CPLD is running, it may directly cause abnormal CPU reset because the CPLD is directly connected to the CPU reset pin.

[0006] Therefore, it is necessary to develop a new CPU resetting method and device to overcome the deficiencies in the prior art. Summary of the invention

[0007] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present application provides a CPU reset method, device, system and storage medium based on CPLD, which solves the problems existing in the prior art such as DDR data loss, long CPU reset waiting time, inability of CPU to respond to interrupts in certain states and possible abnormal CPU reset caused by CPLD through the collaborative design of hardware and software, realizes precise control of CPU reset, improves the stability and reliability of the system, and retains key information before reset to facilitate system maintenance and troubleshooting.

[0008] The present application discloses a CPU reset method based on CPLD, characterized in that it includes a CPLD for controlling CPU reset and a watchdog for controlling CPLD reset. The method includes: The CPLD receives the pulse signal sent by the CPU, determines whether the signal exceeds the first time threshold, and if so, sends a CPU reset pulse to the CPU; The watchdog receives the dog feeding signal sent by the CPLD, determines whether the dog feeding signal exceeds the second time threshold, and if so, sends a CPLD reset pulse to the CPLD and the CPU, wherein the CPU reset pulse and the CPLD reset pulse are independent of each other and do not interfere with each other.

[0009] Furthermore, after receiving the CPU reset pulse, the CPU is reset and restarted according to the register information on the CPLD.

[0010] Further, the CPLD register includes: Active reset control register: The CPU can write specific data to this register to make the CPLD output a pulse signal to trigger the CPU reset; DDR reset control register: The CPU can set it during normal operation, and it is cleared by the CPLD during abnormal reset or cold start of the entire board. The state of this register determines whether the DDR is reset when the CPU starts; CPU reset reason register: used for processing logic judgment after CPU restart. When the CPU is reset by writing CPLD register, it is marked as normal reset in this register. When CPLD judges that the CPU is reset by timeout, it is marked as abnormal reset. When the whole board is powered off and started, it is marked as power-off reset. CPLD status register: After the firmware is loaded and initialized, the CPLD switches the register from BUSY state to READY state. Only in the READY state can the CPU access other CPLD registers; Communication setting register: This register is used to configure the parameters of UART communication between CPLD and CPU, including baud rate, communication bit width and verification mode.

[0011] Furthermore, the CPU is provided with a high-priority monitoring task, which is triggered by a hardware timer, runs according to a preset cycle, and sends a pulse signal to the CPLD; The monitoring task sets a counter for other tasks. When the counter value of other tasks exceeds a preset threshold, the CPU identifies an abnormal state and initiates an active reset.

[0012] Furthermore, when the CPU identifies a program exception, it actively writes a program to the CPLD to trigger an active reset, and the active reset method includes: The main core refreshes the cache and updates the data in the cache to DDR; The master core notifies the slave core through an inter-core interrupt and waits for the slave core to shut down. After receiving the notification, the slave core shuts down the task scheduling and global interrupt, refreshes the cache, and shuts down the slave core. After the master core confirms that the slave core is shut down, it turns off the global interrupt, calls a specific service to suspend the CPU, and configures the DDR to enter self-refresh; An instruction is written into the active reset control register of the CPLD, so that the CPLD outputs a CPU reset pulse to the CPU to reset and restart the CPU.

[0013] Furthermore, the CPU passive reset method includes: The CPLD receives the pulse signal sent by the CPU and determines whether the signal exceeds a first time threshold; If so, the CPU reset cause register of the CPLD is marked as abnormal, and a CPU reset pulse is sent to the CPU; After receiving the CPU reset pulse sent by the CPLD, the CPU reads the CPU reset reason register on the CPLD. If it is marked as abnormal, the DDR is cleared and the CPU is reset and restarted according to the cold start.

[0014] Further, the CPLD reset method includes: The watchdog receives a dog feeding signal sent by the CPLD, determines whether the dog feeding signal exceeds a second time threshold, and if so, sends a CPLD reset pulse to the CPLD and the CPU; The CPLD receives a CPLD reset pulse from the watchdog, performs a reset, and clears register information; The CPU receives the CPLD reset pulse sent by the watchdog, waits for the CPLD to be reset and restarted, and then rewrites information to the register of the CPLD.

[0015] The present application also discloses a CPU reset device based on CPLD, comprising: CPU: used to monitor running tasks, initiate active reset pulses to CPLD according to monitoring anomalies, receive CPU reset pulses sent by CPLD, and reset and restart the CPU according to CPLD register information; CPLD: connected to the CPU, used to implement hardware dog logic to monitor the operation of the CPU; Watchdog: connected to the CPLD, used to monitor the operation of the CPLD; DDR: connected to the CPU, clearing data when the CPU is cold started or abnormally reset and restarted.

[0016] The present application also discloses a CPU reset system based on CPLD, comprising: one or more processors; A computer readable storage medium for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the steps of the method described in any one of claims 1 to 7.

[0017] The present application also discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 7 are implemented.

[0018] The beneficial effects of the present application are as follows: the present application discloses a CPU reset method, device, system and storage medium based on CPLD, which solves the problems existing in the prior art through the collaborative design of hardware and software, and realizes: 1. Design two-level monitoring in hardware to ensure that the reset of CPLD and the reset of CPU are independent of each other and do not interfere with each other, thus reducing the reset waiting time and reset risk.

[0019] 2. Actively identify CPU program feeding timeout through the software dog to ensure that the CPU can recognize all active reset situations including abnormal interrupts.

[0020] 3. Design a series of registers on the CPLD. When the CPU is actively reset, the DDR is not reset, and the information and data before the reset are retained. When the CPU is passively reset, the CPU and DDR are reset at the same time to ensure that the CPU can start normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present application is described with the aid of the following drawings: Figure 1 The flowchart of the CPU reset method of the present application is shown; Figure 2 The schematic diagram of the CPU reset circuit of the present application is shown; Figure 3 The flowchart of the active CPU reset method of the present application is shown; Figure 4 The flowchart of the CPLD reset method of the present application is shown. DETAILED DESCRIPTION

[0022] In order to better explain the present invention and facilitate understanding, the present invention is described in detail below in conjunction with the accompanying drawings through specific implementation methods. It is understood that the specific embodiments described below are only used to explain the relevant inventions, rather than to limit the invention. It should also be noted that the embodiments and features in the embodiments of this application can be combined with each other in the absence of conflict; for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0023] As known from the background technology, in the existing control system, the reset method of the CPU may easily cause the CPU to fail to shut down, or the CPU and DDR are all reset when resetting the CPU, and the key information before the CPU reset cannot be recorded, which increases the difficulty of system maintenance and troubleshooting.

[0024] In view of the above problems, the present application provides a CPU reset method based on CPLD, which solves the problems existing in the prior art such as DDR data loss, long CPU reset waiting time, inability of CPU to respond to interrupts in certain states, and possible abnormal CPU reset caused by CPLD through the collaborative design of hardware and software, and realizes precise control of CPU reset, improves the stability and reliability of the system, and retains key information before reset to facilitate system maintenance and troubleshooting. The method is as follows Figure 1 As shown, it includes a CPLD for controlling CPU reset and a watchdog for controlling CPLD reset. The specific method includes: The CPLD receives the pulse signal sent by the CPU, determines whether the signal exceeds the first time threshold, and if so, sends a CPU reset pulse to the CPU; The watchdog receives the dog feeding signal sent by the CPLD, determines whether the dog feeding signal exceeds the second time threshold, and if so, sends a CPLD reset pulse to the CPLD and the CPU, wherein the CPU reset pulse and the CPLD reset pulse are independent of each other and do not interfere with each other.

[0025] like Figure 2As shown, this is the circuit schematic diagram of the CPU reset method based on CPLD of the present application, wherein, during operation, the CPU sends a pulse signal to the CPLD through the CWDI signal, and the CPLD sends a pulse signal to the watchdog through WDI. When the CPLD does not receive the pulse signal from the CPU within the first time threshold, the CPLD sends a CPU reset pulse signal to the CPU through CWDO to reset the CPU; when the watchdog does not receive the dog feeding signal from the CPLD within the second time threshold, the watchdog sends a CPLD reset pulse signal to the CPLD and CPU through WDO to reset the CPLD, and the CPU reset pulse signal and the CPLD reset pulse signal are independent of each other and do not interfere with each other. The reset of the CPLD will not affect the signal of CWDO, that is, it will not cause the CPU to reset. Similarly, the reset of the CPU will not cause the reset of the CPLD.

[0026] Furthermore, after receiving the CPU reset pulse, the CPU is reset and restarted according to the register information on the CPLD.

[0027] Among them, the registers in CPLD include: Active reset control register: The CPU can write specific data to this register to make the CPLD output a pulse signal to trigger the CPU reset; DDR reset control register: The CPU can set it during normal operation, and it is cleared by the CPLD during abnormal reset or cold start of the entire board. The state of this register determines whether the DDR is reset when the CPU starts; CPU reset reason register: used for processing logic judgment after CPU restart. When the CPU is reset by writing CPLD register, it is marked as normal reset in this register. When CPLD judges that the CPU is reset by timeout, it is marked as abnormal reset. When the whole board is powered off and started, it is marked as power-off reset. CPLD status register: After the firmware is loaded and initialized, the CPLD switches the register from BUSY state to READY state. Only in the READY state can the CPU access other CPLD registers; Communication setting register: This register is used to configure the parameters of UART communication between CPLD and CPU, including baud rate, communication bit width and verification mode.

[0028] The CPU's read and write permissions for registers in the CPLD are shown in the following table: Among them, RW means that the CPU can read and write registers, and R means that the CPU can only read registers.

[0029] like Figure 2As shown in the figure, the CPU can read and write CPLD registers through UART communication to achieve specific functions. The active reset control register is like a "key". When the CPU writes specific data to it, it can accurately control the CPLD to immediately output a pulse signal, thereby triggering a CPU reset; the DDR reset control register can be set by the CPU autonomously when the CPU is operating normally, and in special circumstances such as abnormal reset or cold start of the entire board, it is cleared by the CPLD. Its state directly determines whether the DDR is reset by hardware when the CPU starts, providing a flexible control method for the system's DDR processing in different reset scenarios; the CPU reset cause register is like the system's "black box", which can mark the CPU reset cause in detail. When the CPU is reset by writing instructions to the CPLD, it will be marked as a normal reset. When the C When the PLD resets the CPU based on a timeout judgment, it is marked as an abnormal reset. When the entire board is powered off and started, it is marked as a power-off reset. This provides valuable information for system troubleshooting and subsequent analysis. The CPLD status register is in the BUSY state during the initial stage of CPLD firmware loading. After the firmware is loaded and a series of initialization actions are completed, it switches to the READY state. Only in the READY state can the CPU have access to the CPLD register, ensuring the security and stability of the CPLD internal data. The communication setting register focuses on configuring various parameters for communication between the CPLD and the CPU, such as baud rate, communication bit width, and verification method, ensuring the accuracy and efficiency of information exchange between the two.

[0030] During the normal operation of the system, a high-priority monitoring task is configured in the CPU. The monitoring task is triggered by a hardware timer, runs according to a preset cycle, and sends a pulse signal to the CPLD. When the CPU is operating normally, the CPLD will receive the pulse sent by the CPU within the time threshold. At this time, the CPLD realizes the role of a hardware watchdog and monitors the CPU.

[0031] At the same time, the CPU sets counters for other tasks by monitoring tasks. If other tasks encounter unexpected situations during operation, such as blockage caused by resource competition or exceptions caused by data transmission errors, causing their corresponding counters to exceed the preset threshold, or if the CPU core encounters hardware-level exceptions such as prefetch instruction errors, access to illegal addresses, and instruction execution errors when executing complex instructions, the system will immediately trigger an active reset event.

[0032] In this embodiment, a dual-core CPU based on the ARMv8 architecture is used as an example for explanation. Figure 3 As shown, including: S11: The main core refreshes the cache and updates the data in the cache to the DDR. When the CPU identifies an abnormality through the monitoring task, the main core will immediately start the data protection mechanism to quickly update the video data and related decoding status information in the cache to the DDR to ensure that these important data will not be lost due to the reset operation.

[0033] S12: The master core notifies the slave core through the inter-core interrupt and waits for the slave core to shut down. After receiving the notification, the slave core shuts down the task scheduling and global interrupt, refreshes the cache and shuts down the slave core. The master core sends a notification to the slave core through the inter-core interrupt. After receiving the notification, the slave core will quickly stop the current task scheduling and global interrupt processing to prevent new data from entering or erroneous operations from occurring. Next, the slave core will refresh its own cache, save any unprocessed data that may exist in the DDR, and then call the SMC service to shut down the slave core and put it into sleep mode to avoid interference with the system during the reset process.

[0034] S13: After the master core confirms that the slave core is shut down, it turns off the global interrupt, calls a specific service to suspend the CPU, and configures the DDR to enter self-refresh. After the master core confirms that the slave core has been successfully shut down, it turns off the global interrupt, calls the SMC service to suspend itself, and configures the DDR to enter the self-refresh state to reduce the risk of data loss.

[0035] S14: Write an instruction to the active reset control register of the CPLD, so that the CPLD outputs a CPU reset pulse to the CPU to reset and restart the CPU. The CPU writes specific reset instruction data to the active reset control register of the CPLD. After receiving the instruction, the CPLD sends a pulse signal to the CPU through CWDO to accurately reset the CPU.

[0036] After the CPU is restarted, it will communicate with the CPLD immediately to obtain the status information of the CPLD register. If the DDR reset control register is set, it means that the data in the DDR is complete and valid before the reset. At this time, the CPU will process according to the hot reset process, and quickly resume the video decoding task based on the video data and decoding status information retained in the DDR, and continue the decoding operation from the last interruption, which greatly reduces the video playback jam or interruption time caused by the system reset, and improves the user experience and the overall performance of the system.

[0037] When an exception that the program cannot recognize occurs during CPU operation, such as a sudden hardware failure (such as partial damage to the memory chip, short circuit in the CPU internal circuit, etc.) or strong external interference (such as electromagnetic pulse interference, electrostatic discharge, etc.), causing the program to be unable to recognize the error and failing to send a pulse signal to the CPLD for more than the first time threshold (for example, 1 second), the CPLD will respond quickly, accurately mark the CPU reset mode as abnormal reset in the internal CPU reset cause register, and send a pulse signal to the CPU through CWDO to force the CPU to reset.

[0038] When the CPU is passively reset, the DDR cannot enter self-refresh before the reset. The data in the DDR may be lost during the reset process, and the data in the DDR after the restart is unreliable. Therefore, during the CPU reset and restart process, the status information of the CPLD register will be read. After the abnormal reset mark is identified, in order to ensure the stability of the system and the consistency of the data, the DDR will be reset and the DDR data will be cleared. Subsequently, the application will be processed according to the cold start process, reinitializing various parameters in the industrial control system to ensure that the system can restart in a stable state and ensure the safety and stability of the industrial production process.

[0039] At the same time, the present invention also designs a secondary watchdog monitoring for CPLD, and the CPLD periodically sends a feeding signal to the watchdog to ensure the normal operation of the CPLD, and at the same time ensures that the reset of the CPLD and the reset of the CPU are independent of each other and do not interfere with each other. Figure 4 As shown in the figure, the watchdog reset method for CPLD includes: S21: The watchdog receives the dog feeding signal sent by the CPLD, determines whether the dog feeding signal exceeds the second time threshold, and if so, sends a CPLD reset pulse to the CPLD and the CPU. After the CPLD dog feeding signal times out, the watchdog sends a CPLD reset pulse WDO to the CPU and the CPLD. The WDO reset pulse of the watchdog does not affect the CPU and does not cause the CPU to reset.

[0040] S22: The CPLD receives the CPLD reset pulse of the watchdog, resets and clears the register information. During the reset process, the CPLD interrupts the interaction with the CPU, clears the internal register information, adjusts the CPLD status register state to the BUSY state, and performs firmware loading and initialization operations. After the status loading is completed, the status of the CPLD status register is adjusted to the READY state, at which point the CPU can access the CPLD register.

[0041] S23: The CPU receives the CPLD reset pulse sent by the watchdog, waits for the CPLD to reset and restart, and then rewrites information to the CPLD register. During the reset and restart process, the CPLD will disconnect the communication with the CPU, and the CPLD status register is in the BUSY state. The CPU cannot directly access it and needs to wait for the CPLD to complete the reset. When the CPLD status register returns to the READY state, the CPU will rewrite the backed-up CPLD register information into the CPLD to ensure that the CPLD can be restored to its previous normal working state and maintain the stability and continuity of the system.

[0042] A stable connection is established between the CPU and CPLD through the UART communication link. During system operation, the CPU performs precise read and write operations on the CPLD register according to the baud rate, communication bit width and verification mode configured in the communication setting register, thereby achieving flexible control of the CPLD and efficient information exchange. For example, at the beginning of system startup, the CPU can read the status of the CPLD status register to determine whether the CPLD has completed initialization and is in the READY state, so as to determine whether subsequent register configuration operations can be performed. During system operation, the CPU can read the information of the CPU reset reason register as needed to understand the previous reset status of the system, so as to perform troubleshooting and system status analysis. At the same time, the CPU can also trigger active reset by writing data to the active reset control register.

[0043] In summary, the present application discloses a CPU reset method based on CPLD, which solves the problems existing in the prior art through the collaborative design of hardware and software, and realizes: 1. Design two-level monitoring in hardware to ensure that the reset of CPLD and the reset of CPU are independent of each other and do not interfere with each other, thus reducing the reset waiting time and reset risk.

[0044] 2. Actively identify CPU program feeding timeout through the software dog to ensure that the CPU can recognize all active reset situations including abnormal interrupts.

[0045] 3. Design a series of registers on the CPLD. When the CPU is actively reset, the DDR is not reset, and the information and data before the reset are retained. When the CPU is passively reset, the CPU and DDR are reset at the same time to ensure that the CPU can start normally.

[0046] Another embodiment of the present invention, a CPU reset device based on CPLD includes: CPU: used to monitor running tasks, initiate active reset pulses to CPLD according to monitoring anomalies, receive CPU reset pulses sent by CPLD, and reset and restart the CPU according to CPLD register information; CPLD: connected to the CPU, used to implement hardware dog logic to monitor the operation of the CPU; Watchdog: connected to the CPLD, used to monitor the operation of the CPLD; DDR: connected to the CPU, clearing data when the CPU is cold started or abnormally reset and restarted.

[0047] A third embodiment of the present invention is a CPU reset system based on CPLD, comprising: one or more processors; A computer readable storage medium for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the steps of the method described in any one of claims 1 to 7.

[0048] A fourth embodiment of the present invention is a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 7 are implemented.

[0049] It should be noted that in the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention may be implemented by means of hardware comprising several distinct components and by means of a suitably programmed computer. The use of the words first, second, third, etc., is for convenience of expression only and does not imply any order. These words may be understood as part of the component name.

[0050] In addition, it should be noted that, in the description of this specification, the description of the terms "one embodiment", "some embodiments", "embodiment", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0051] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments after knowing the basic creative concept. Therefore, the claims should be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0052] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention should also include these modifications and variations.

Claims

1. A CPU reset method based on CPLD, characterized in that: The method comprises a CPLD for controlling CPU reset and a watchdog for controlling CPLD reset, and the method comprises: The CPLD receives the pulse signal sent by the CPU, determines whether the signal exceeds the first time threshold, and if so, sends a CPU reset pulse to the CPU; The watchdog receives the dog feeding signal sent by the CPLD, determines whether the dog feeding signal exceeds the second time threshold, and if so, sends a CPLD reset pulse to the CPLD and the CPU, wherein the CPU reset pulse and the CPLD reset pulse are independent of each other and do not interfere with each other.

2. The CPU reset method based on CPLD according to claim 1, characterized in that: After receiving the CPU reset pulse, the CPU is reset and restarted according to the register information on the CPLD.

3. The CPU reset method based on CPLD according to claim 2, characterized in that: The CPLD registers include: Active reset control register: The CPU can write specific data to this register to make the CPLD output a pulse signal to trigger the CPU reset; DDR reset control register: The CPU can set it during normal operation, and it is cleared by the CPLD during abnormal reset or cold start of the entire board. The state of this register determines whether the DDR is reset when the CPU starts; CPU reset reason register: used for processing logic judgment after CPU restart. When the CPU is reset by writing CPLD register, it is marked as normal reset in this register. When CPLD judges that the CPU is reset by timeout, it is marked as abnormal reset. When the whole board is powered off and started, it is marked as power-off reset. CPLD status register: After the firmware is loaded and initialized, the CPLD switches the register from BUSY state to READY state. Only in the READY state can the CPU access other CPLD registers; Communication setting register: This register is used to configure the parameters of UART communication between CPLD and CPU, including baud rate, communication bit width and verification mode.

4. The CPU reset method based on CPLD according to claim 3, characterized in that: The CPU is provided with a high-priority monitoring task, which is triggered by a hardware timer, runs according to a preset cycle, and sends a pulse signal to the CPLD; The monitoring task sets a counter for other tasks. When the counter value of other tasks exceeds a preset threshold, the CPU identifies an abnormal state and initiates an active reset.

5. The CPU reset method based on CPLD according to claim 4, characterized in that: When the CPU identifies a program exception, it actively writes a program to the CPLD to trigger an active reset. The active reset method includes: The main core refreshes the cache and updates the data in the cache to DDR; The master core notifies the slave core through an inter-core interrupt and waits for the slave core to shut down. After receiving the notification, the slave core shuts down the task scheduling and global interrupt, refreshes the cache, and shuts down the slave core. After the master core confirms that the slave core is shut down, it turns off the global interrupt, calls a specific service to suspend the CPU, and configures the DDR to enter self-refresh; An instruction is written into the active reset control register of the CPLD, so that the CPLD outputs a CPU reset pulse to the CPU to reset and restart the CPU.

6. The CPU reset method based on CPLD according to claim 5, characterized in that: The CPU passive reset method comprises: The CPLD receives the pulse signal sent by the CPU and determines whether the signal exceeds a first time threshold; If so, the CPU reset cause register of the CPLD is marked as abnormal, and a CPU reset pulse is sent to the CPU.

7. The CPU reset method based on CPLD according to claim 3, characterized in that: The reset method of the CPLD includes: The watchdog receives a dog feeding signal sent by the CPLD, determines whether the dog feeding signal exceeds a second time threshold, and if so, sends a CPLD reset pulse to the CPLD and the CPU; The CPLD receives a CPLD reset pulse from the watchdog, performs a reset, and clears register information; The CPU receives the CPLD reset pulse sent by the watchdog, waits for the CPLD to be reset and restarted, and then rewrites information to the register of the CPLD.

8. A CPU reset device based on CPLD, characterized in that: include: CPU: used to monitor running tasks, initiate active reset pulses to CPLD according to monitoring anomalies, receive CPU reset pulses sent by CPLD, and reset and restart the CPU according to CPLD register information; CPLD: connected to the CPU, used to implement hardware dog logic to monitor the operation of the CPU; Watchdog: connected to the CPLD, used to monitor the operation of the CPLD; DDR: connected to the CPU, clearing data when the CPU is cold started or abnormally reset and restarted.

9. A CPU reset system based on CPLD, characterized in that: include: one or more processors; A computer readable storage medium for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the steps of the method described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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