A Y-type three-phase arc high-voltage discharge system for optical fiber fusion splicers

Abstract

The present invention belongs to the field of optical fiber supporting equipment and discloses a Y-shaped three-phase arc high-voltage discharge system for an optical fiber fusion splicer. A ZYNQ development board generates two signals, which serve as drive signals for the switching tubes of a Boost circuit module and a Flyback circuit module, respectively. The ZYNQ development board boosts the input DC voltage through the Boost circuit module. The boosted voltage serves as the input voltage for three groups of Flyback circuit modules, thereby obtaining three groups of three-phase DC high voltages with the same voltage amplitude and a phase difference of 120°. The three groups of Flyback circuit modules are connected to a three-phase discharge device. The three-phase DC high voltage breaks through the air to form a three-phase "Y-shaped" arc. The radiant heat zone generated by the arc is used to fuse optical fibers. The system has a large-area thermal radiation field and high heat generation power, which is conducive to the welding of large-diameter optical fibers. The temperature in the thermal radiation field is radially and symmetrically distributed, and the center of the temperature zone is heated evenly, resulting in a good heating effect.

Description

Technical Field

[0001] The present invention relates to the field of optical fiber supporting equipment, and in particular to a Y-shaped three-phase arc high-voltage discharge system for an optical fiber fusion splicer, which can also be used for the preparation of optical fiber related devices. Background Art

[0002] As fiber-optic communications enter a period of rapid development, demand for high-end fiber fusion splicing equipment has increased significantly, placing higher demands on these equipment. China has long been a leader in the research and development of fiber fusion splicers. Fiber fusion splicers are key devices for connecting optical fibers, and their performance directly impacts the quality and reliability of fiber-optic communications.

[0003] The high-voltage discharge system in a fiber fusion splicer is a key component in achieving fiber fusion splicing. China is also conducting a series of research and innovations in this area. Researchers are continuously working to improve the efficiency and stability of high-voltage discharge technology. By optimizing the design of the high-voltage power supply and the control algorithm, they are striving to achieve more precise and reliable high-voltage discharge to ensure the quality of fiber fusion splices.

[0004] Fiber fusion splicers typically use two electrodes. These electrodes are responsible for transmitting the current required for high-voltage discharge and providing heat to melt the fiber during the fiber fusion splicing process. However, this method only heats the fiber through the high-temperature zone in the middle of the high-voltage spindle-shaped arc generated by the discharge between the two electrodes. The high-temperature zone is small and the heat generated is relatively low, making it difficult to splice large-diameter fibers. While the two-electrode design is simple and easy to operate and maintain, it may have certain limitations for certain complex fiber fusion splicing requirements. In specific application scenarios, more electrodes or different designs may be required to meet higher fiber fusion splice quality requirements. Summary of the Invention

[0005] The purpose of the present invention is to solve the deficiencies in the prior art and to provide a Y-type three-phase arc high-voltage discharge system for an optical fiber fusion splicer.

[0006] In order to achieve the above object, the present invention is implemented through the following technical solutions: including a ZYNQ development board, a Boost circuit module, three sets of Flyback circuit modules, and a three-phase discharge device.

[0007] The ZYNQ development board generates two PWM signals, which serve as drive signals for the MOS transistors of the Boost circuit module and the Flyback circuit module, respectively. First, the ZYNQ development board boosts the input DC voltage through the Boost circuit module. The boosted DC voltage serves as the input voltage for three sets of Flyback circuit modules, generating three sets of three-phase DC high voltages with the same voltage amplitude and a phase difference of 120 degrees. The three sets of Flyback circuit modules are connected to a three-phase discharge device. The three-phase DC high voltage breaks through the air to form a three-phase "Y-shaped" arc, and the radiant heat zone generated by the arc is used to fuse the optical fibers.

[0008] The ZYNQ development board integrates a PL end and a PS end, and the PL end and the PS end are connected via an AXI bus;

[0009] The Boost circuit module includes an input capacitor, an inductor L1, a MOS tube Q1, a diode D1, an output capacitor and a gate drive module A. The gate drive module A amplifies the current of the PWM output of the ZYNQ development board to drive the MOS tube Q1. When the MOS tube Q1 is in the on state, the inductor L1 is grounded and the diode D1 is cut off. When the MOS tube Q1 is in the off state, the diode D1 is forward-conducted, and the input DC voltage is increased and output through the output capacitor;

[0010] The Flyback circuit includes a transformer T1, a MOS transistor Q5, a high-voltage diode D6, a high-voltage diode D8, an output capacitor C20, and a gate drive module B. The gate drive module B amplifies the PWM current output by the ZYNQ development board to drive the MOS transistor Q5. Through the periodic on-off of the MOS transistor Q5, the transformer T1 can store and transfer energy under different working states. The input DC voltage is then increased through rectification by the high-voltage diodes D6 and D8 and filtering by the output capacitor C20.

[0011] The three-phase discharge device includes three copper pillars, which form a "Y"-shaped structure. An electrode rod is set on each copper pillar. Three groups of DC high voltages are connected in sequence using high-voltage diodes, that is, the low potential end of the first group is connected to the high potential end of the second group, the low potential end of the second group is connected to the high potential end of the third group, and the low potential end of the third group is connected to the high potential end of the first group. The three ports are respectively connected to the three-phase discharge device.

[0012] Preferably, the ZYNQ development board generates four PWM waves, namely PWM0, PWM1, PWM2, and PWM3, where the duty cycle of PWM0 is 50% and the frequency is 300KHz, and is used to control the amplitude of the boost circuit module; the duty cycle of PWM1, PWM2, and PWM3 is 66%, the frequency is 30KHz, and the phases differ by 120°, and are used to control three identical Flyback circuit modules to convert the output voltage of the Boost circuit into three groups of full-wave pulse high voltages with equal amplitudes and phases differing by 120°.

[0013] Preferably, in the Boost circuit module, when the MOS tube Q1 is in the on state, the relationship is as follows:

[0014]

[0015] When the MOS tube Q1 is in the off state, the relationship is as follows:

[0016]

[0017] The initial and final values ​​of the inductor current are equal, and the integral of the voltage across the two terminals with respect to time is 0, which yields the following relationship:

[0018]

[0019] Among them, V s is the input voltage, V O is the output voltage, L is the self-inductance coefficient, t is the time, i L is the inductor current, T off is the cut-off time of MOS tube Q1, T on is the conduction time of MOS tube Q1, D is the duty cycle of PWM signal, Δi L+ is the current change when the MOS tube Q1 is turned on, Δi L- It is the current change when the MOS tube Q1 is turned off.

[0020] Preferably, the gate drive module A includes a gate driver chip U1, resistors R1, R2, R3 and capacitor C2. When the MOS tube Q1 is in the on state, the inductor L1 is grounded, the diode D1 is cut off, and the power supply voltage charges the inductor L1 after being stabilized by the input capacitor, and at the same time provides voltage to the gate drive chip U1. The waveform of the PWMA output by the ZYNQ development board remains unchanged after passing through the gate drive chip U1, and the current becomes larger. The appropriate switching speed is obtained through the parallel resistors R1 and R2 to control the on and off of the MOS tube Q1. The function of the resistor R3 is to pull the gate-source voltage of the MOS tube Q1 down to 0V when the input signal is open.

[0021] Preferably, in the Flyback circuit module, the ratio of the output voltage to the input voltage is:

[0022]

[0023] Among them, N1 is the number of turns of the primary coil, N2 is the number of turns of the secondary coil, V S1 is the input voltage, V O1 is the output voltage, and D is the duty cycle of the PWM signal.

[0024] Preferably, the gate drive module B shown includes a gate drive chip U6, a resistor R17, a resistor R18, a resistor R20 and a capacitor C21. The power supply voltage provides voltage to the gate drive chip U6 after being stabilized by the capacitor C21. The waveform of the PWM-A output by the ZYNQ development board remains unchanged after passing through the gate drive chip U6, and the current becomes larger. The appropriate switching speed is obtained through the parallel resistors R17 and R18 to control the opening and closing of the MOS tube Q1. The function of the resistor R20 is to pull the gate-source voltage of the MOS tube Q5 down to 0V when the input signal is open.

[0025] Preferably, a set of RCD circuits is provided on the primary side of the transformer T1 of the Flyback circuit module for absorbing the leakage inductance energy of the primary side of the transformer T1 to prevent damage to the MOS tube Q5. The RCD circuit includes a diode D7, a resistor R15 and a capacitor C19. The resistor R15 and the capacitor C19 are connected in parallel and then in series with the diode D7.

[0026] Preferably, in order to obtain a PWM wave with a smooth waveform, the clock IP core of the ZYNQ development board is called with a clock frequency of 50M. The register is defined as a counter, and the rising edge of the clock is used as the trigger point. The counter value increases sequentially. When the value accumulates to a certain level, it is compared with the preset value to generate PWM. When the counter value is less than the duty cycle, the PWM output is a high level; otherwise, it is a low level, realizing a PWM wave with adjustable duty cycle.

[0027] This system boasts a large heat radiation field, high heat generation power, and a wide controllable discharge power range, facilitating the splicing of large-diameter fibers with low splicing losses and fast splicing speeds. The three-electrode design provides greater parameter adjustment, enabling more flexible control of the splicing process. This is advantageous for adapting to different fiber types and diameters, as well as varying splicing requirements. The three-electrode system can more easily accommodate a wide range of fiber types, including those with varying diameters, thereby expanding the device's applicability. By enabling more precise control of splicing parameters such as temperature and current, the three-electrode design improves splice quality and minimizes optical signal transmission losses. For applications requiring more complex splices, such as multi-core fibers or fibers with specialized structures, the three-electrode design is better suited to these complex splicing requirements. This greater flexibility in parameter adjustment enables faster and more efficient fiber splicing, improving production efficiency. The use of three electrodes also allows for a higher degree of alignment, ensuring more accurate fiber position and angle during the splicing process.

[0028] The present invention has the following beneficial effects: (1) The Y-type three-phase discharge system provided by the present invention has significant advantages over bipolar discharge. It has higher power, higher temperature, more uniform thermal field distribution in the arc zone, and excels in splicing large-core optical fibers, thus having good application prospects.

[0029] (2) 1. The three-phase discharge electrode used has a large area of ​​thermal radiation field, high heat generation power, and a wide controllable range of discharge power, which is conducive to the welding of large-diameter optical fibers; 2. The temperature in the thermal radiation field formed by Y-type discharge is radially symmetrically distributed, the intensity of the three arcs is the same, the center of the temperature zone is heated evenly, and the heating effect is good; 3. It has low welding loss and fast welding speed, which greatly shortens the welding time; 4. It is suitable for the welding of large-core diameter and small-core diameter optical fibers, as well as the preparation of optical fiber-related devices, and has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a physical picture of the Y-type three-phase arc high-voltage discharge system.

[0031] Figure 2 It is a structural diagram of the Boost circuit module in an embodiment of the present invention.

[0032] Figure 3 FIG. 4 is a structural diagram of a Flyback circuit module in an embodiment of the present invention.

[0033] Figure 4 It is the ZYNQ development board in the embodiment of the present invention.

[0034] Figure 5 2 is a structural diagram of a three-phase discharge electrode in an embodiment of the present invention.

[0035] Figure 6 This is a diagram showing the actual effect of the three-phase discharge electrode in an embodiment of the present invention.

[0036] Figure 7 4 is a flow chart of a system circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be further described below with reference to the examples, but they are not intended to limit the present invention.

[0038] A Y-type three-phase arc high-voltage discharge system for optical fiber fusion splicers, such as Figure 1 The figure shows, from left to right, the Venus ZYNQ 7010 development board, the boost circuit module, the flyback circuit module, and the three-phase discharge device. The ZYNQ development board, as the control module, primarily generates one 300kHz PWM signal and three 30kHz PWM signals, which serve as the driving signals for the boost and flyback circuit switches, respectively. The hardware first boosts the 12V DC input voltage to 24V via the boost circuit (MOSFET switching frequency: 300kHz, duty cycle: 50%). The 24V output from the boost circuit module then serves as the input voltage for the three flyback circuit modules, resulting in three sets of three-phase DC high voltages with the same voltage amplitude of 4800V and a 120° phase shift (MOSFET switching frequency: 30kHz, duty cycle: 66%, phase shift: 120°). Finally, these are connected to the three-phase discharge device, where the high voltage breaks through the air to form a three-phase "Y-shaped" arc. The radiant heat generated by the arc is then used to fuse the optical fibers. The ZYNQ development board generates a PWM wave with a variable duty cycle to control the DC voltage amplitude of the Boost boost and the AC voltage amplitude of the Flyback output.

[0039] like Figure 1As shown in the figure, to accommodate situations where the driver chip's supply voltage is lower than the required DC power, a boost circuit is selected as the primary boost circuit. The boost circuit comprises input capacitors, inductor L1, MOSFET Q1, diode D1, output capacitors, and gate driver module A. The input capacitors include electrolytic capacitors E1 and C1 in parallel, while the output capacitors include electrolytic capacitors E2, E3, and capacitors C3, C4, and C5 in parallel. Gate driver module A includes gate driver chip U1, resistors R1, R2, R3, and capacitor C2. This module amplifies the PWM current output from the ZYNQ development board to better drive MOSFET Q1. Its function is to boost the input voltage based on the PWM signal's duty cycle. When MOSFET Q1 is on, inductor L1 is grounded, diode D1 is off, and the power supply voltage (+12V-IN) is regulated by the input capacitors (electrolytic capacitor E1 and capacitor C1) before charging inductor L1. The inductor current increases linearly over time. The PWMA output from the ZYNQ development board maintains its waveform after passing through gate driver chip U1, but the current increases. Passing through parallel resistors R1 and R2, the appropriate switching speed is achieved to control the on and off of MOS transistor Q1. The +12V-IN power supply voltage, after being stabilized by capacitor C2, provides voltage to gate driver chip U1. R3 lowers the gate-source voltage of MOS transistor Q1 to 0V when the input signal is open. When MOS transistor Q1 is off, the current across inductor L1 remains constant and decreases linearly over time. Diode D1 then conducts forward, supplying power to the load and charging the capacitors across the load. When MOS transistor Q1 turns on again, the charging process repeats. Diode D1 is reverse-blocked, preventing the voltage across the capacitors across the load from changing suddenly, allowing discharge to continue.

[0040] In the Boost circuit module, when the MOS tube Q1 is in the on state, the following relationship exists:

[0041]

[0042] When the MOS tube Q1 is in the off state, the following relationship exists:

[0043]

[0044] According to the volt-second balance law of inductor voltage, when the switching power supply is working stably, the initial and final values ​​of the inductor current are equal, and the integral of the voltage across the two ends over time is 0. This gives the following relationship:

[0045]

[0046] Among them, V s is the input voltage, V O is the output voltage, L is the self-inductance coefficient, t is the time, ΔiL+ is the ripple increment of the upper half of the inductor current, Δi L- is the ripple increment in the lower half of the inductor current, T off is the cut-off time of MOS tube Q1, T on is the on-time of MOS tube Q1, and D is the duty cycle of PWM signal.

[0047] In the Boost circuit module, the GPIO on the ZYNQ development board outputs a control signal, which in turn controls the on / off state of MOS transistor Q1. Given the limited drive capability of the GPIO and its inability to directly drive the gate of MOS transistor Q1, a gate driver chip U1 is added to amplify the current and meet the driving conditions for the on / off state of MOS transistor Q1. The resistors between the gate driver modules A reduce the impact of reverse impulses on the chip caused by impulse voltage and ripple current, thus protecting the circuit.

[0048] To effectively reduce the output voltage ripple of the Boost circuit, multiple output capacitors (E2, E3, C3, C4, C5) are connected in parallel to increase the capacitance. At the same time, these output capacitors (E2, E3, C3, C4, C5) have the advantage of low ESR. These two points can effectively reduce voltage ripple, make the arc more stable, make the fiber fusion more complete, and reduce fusion loss.

[0049] like Figure 2 As shown, the secondary boost circuit uses a Flyback circuit module. The Flyback circuit module includes a transformer T1, a MOS transistor Q5, high-voltage diodes D6 and D8, an output capacitor C20, and a gate driver module B. The gate driver module B includes a gate driver chip U6, resistors R17, R18, R20, and a capacitor C21. This module amplifies the PWM current output by the ZYNQ development board to better drive the MOS transistor Q5. Its main function is to store and transfer energy in transformer T1 under different operating states through the periodic on-off of the MOS transistor Q5. The input DC voltage (the voltage after being boosted by the Boost circuit module) is then increased to the required output DC voltage through rectification by high-voltage diodes D6 and D8 and filtering by output capacitor C20.

[0050] The PWM-A output from the ZYNQ development board maintains a constant waveform after passing through gate driver chip U6, while the current increases. This waveform is then controlled by parallel resistors R17 and R18 to achieve the appropriate switching speed, controlling the on and off of MOS transistor Q1. The +12V-IN power supply voltage, after being stabilized by capacitor C21, provides voltage to gate driver chip U1. Resistor R20 pulls the gate-source voltage of MOS transistor Q5 down to 0V when the input signal is open. When MOS transistor Q5 is on, current flows from the same-name terminals of transformer T1's primary winding. Because the primary and secondary windings are out of phase, the unidirectional conduction of high-voltage diodes D6 and D8 in the secondary winding reduces the current to zero when current flows through the primary winding. Electrical energy is converted into magnetic energy and stored in the transformer's primary winding. When MOS transistor Q5 is off, the magnetic energy in the primary winding is converted into electrical energy, forming an electric field of opposite polarity, turning high-voltage diodes D6 and D8 on. Current flows through high-voltage diodes D6 and D8 to the load, allowing the energy of transformer T1 to be released promptly, providing the load with voltage and current. The ratio of output to input voltage is:

[0051]

[0052] Among them, N1 is the number of turns of the primary coil, N2 is the number of turns of the secondary coil, V S1 is the input voltage, V O1 is the output voltage, D is the duty cycle of the PWM signal;

[0053] In order to simplify the circuit design, a gate drive module B is added so that the GPIO of the ZYNQ development board can directly control the duty cycle and frequency of the on and off of the MOS tube Q5.

[0054] Compared to the classic flyback circuit, this system adds an RCD circuit on the primary side of transformer T1. This RCD circuit comprises diode D7, resistor R15, and capacitor C19. It absorbs the leakage energy on the primary side of transformer T1 and prevents damage to MOSFET Q5. Resistor R15 and capacitor C19 are connected in parallel and in series with diode D7. Due to the high output voltage, the secondary side rectifier circuit of transformer T1 consists of high-voltage diodes D6 and D8 and output capacitor C20. When MOSFET Q5 is off in the flyback circuit template, the energy stored in transformer T1 charges output capacitor C20 through high-voltage diodes D6 and D8. When MOSFET Q5 is on, transformer T1 is charged, while output capacitor C20 is discharged through the electrode pins. In the connection to the three-phase discharge device, the copper pillars are directly connected to the electrode pins via red and black wires. The output voltage of each phase is connected to the output terminal of the transformer of the next phase, for example, PowerAA is connected to PBB, PowerBB is connected to PCC, and PowerCC is connected to PAA. To ensure consistent discharge direction and prevent interference between the three arc segments, a high-voltage diode is connected in series between each two-phase voltage. Using Vivado, the phases of the three-phase PWM signals driving the three flyback circuits are set to 120° apart. This three-phase PWM wave drives the flyback circuit modules, ensuring that only one arc is discharged at any given moment, while the other two flyback circuit modules charge output capacitor C20.

[0055] like Figure 3As shown, the ZYNQ-7000 series is a Xilinx SoC (System on Chip) device that integrates programmable logic (PL) and a dual-core ARM Cortex-A9 processor system (PS). The xc7z010 is one of these models. The following briefly describes the FPGA components and functions of each module on the PL side of the xc7z010 model: Logic units (LUTs) implement various logic functions, including Boolean logic and arithmetic operations. Registers store intermediate results and control signals. On-chip DSP resources implement digital signal processing functions, including multipliers and accumulators. IOBs (Input / Output Blocks) connect to external devices and include input / output pins and clocks. Distributed RAM: Small RAM distributed between logic units for temporary data storage. Block RAM: Used to implement larger-scale memory, it can be used to store data, programs, etc. The clock management unit (CMU) generates and distributes various clock signals, including the PL clock. I / O resources connect to external devices and components. Configuration logic is used to load the FPGA configuration bitstream. The debug interface provides debugging capabilities, including the JTAG interface. In the Zynq series, the PL and PS (processor system) are interconnected via a high-performance AXI bus, achieving a close integration of hardware and software, allowing developers to implement hybrid designs of hardware acceleration and processor processing on the same chip.

[0056] like Figure 4 As shown, the three full-wave pulse high voltages generated by the Flyback circuit module are rectified into half-wave pulse high voltages to generate three copper column outputs. These three outputs are then connected to the electrode pins to form a Y-type three-phase discharge.

[0057] Figure 5 This is the actual discharge effect of a three-phase arc high-voltage discharge system. The three arc sections have the same intensity, and the equilateral triangle heating radiation field formed is uniform, with excellent heating and melting effects.

[0058] like Figure 6 As shown in the figure, this design uses the ZYNQ development board of model xc7z010 and the Vivado design suite of Xilinx. After selecting the corresponding chip, the software control program of the PWM wave hardware description circuit of the overall discharge module is written in Verilog language.

[0059] To obtain a smooth PWM waveform, a clock IP core was used with a clock frequency of 50 MHz. A register was defined as a counter. Triggered by the rising edge of the clock, the counter value increments sequentially. When the accumulated value reaches a certain level, it is compared with a preset value to generate a PWM waveform. When the counter value is less than the duty cycle, the PWM output is high; otherwise, it is low. This creates a PWM waveform with adjustable duty cycle. Cycle control adjusts the PWM period by adjusting the cycle constant parameter. Reset processing resets the counter and PWM registers to their initial states when the reset signal is high. This software design uses the PL terminal (FPGA) on the ZYNQ development board to generate four PWM waveforms: one driving the boost circuit at a frequency of 300 kHz and a duty cycle of 50%, and the other three driving the three-phase flyback circuit at a frequency of 30 kHz and a duty cycle of 66%.

[0060] The above shows and describes the basic principles, main features, and advantages of the present invention. However, the above is only a specific embodiment of the present invention, and the technical features of the present invention are not limited thereto. Any other implementation methods derived by any person skilled in the art without departing from the technical solution of the present invention should be included in the patent scope of the present invention.

Claims

1. A Y-type three-phase arc high-voltage discharge system for optical fiber fusion splicers, characterized in that: Including ZYNQ development board, Boost circuit module, three sets of Flyback circuit modules, and three-phase discharge device. The ZYNQ development board generates two PWM signals, which serve as drive signals for the MOS transistors of the Boost circuit module and the Flyback circuit module, respectively. First, the ZYNQ development board boosts the input DC voltage through the Boost circuit module. The boosted DC voltage serves as the input voltage for three sets of Flyback circuit modules, generating three sets of three-phase DC high voltages with the same voltage amplitude and a phase difference of 120 degrees. The three sets of Flyback circuit modules are connected to a three-phase discharge device. The three-phase DC high voltage breaks through the air to form a three-phase "Y-shaped" arc, and the radiant heat zone generated by the arc is used to fuse the optical fibers. The ZYNQ development board integrates a PL end and a PS end, and the PL end and the PS end are connected via an AXI bus; The Boost circuit module includes an input capacitor, an inductor L1, a MOS tube Q1, a diode D1, an output capacitor and a gate drive module A. The gate drive module A amplifies the current of the PWM output of the ZYNQ development board to drive the MOS tube Q1. When the MOS tube Q1 is in the on state, the inductor L1 is grounded and the diode D1 is cut off. When the MOS tube Q1 is in the off state, the diode D1 is forward-conducted, and the input DC voltage is increased and output through the output capacitor; The Flyback circuit includes a transformer T1, a MOS transistor Q5, a high-voltage diode D6, a high-voltage diode D8, an output capacitor C20, and a gate drive module B. The gate drive module B amplifies the PWM current output by the ZYNQ development board to drive the MOS transistor Q5. Through the periodic on-off of the MOS transistor Q5, the transformer T1 can store and transfer energy under different working states. The input DC voltage is then increased through rectification by the high-voltage diodes D6 and D8 and filtering by the output capacitor C20. The three-phase discharge device includes three copper pillars, which form a "Y"-shaped structure. An electrode rod is set on each copper pillar. Three groups of DC high voltages are connected in sequence using high-voltage diodes, that is, the low potential end of the first group is connected to the high potential end of the second group, the low potential end of the second group is connected to the high potential end of the third group, and the low potential end of the third group is connected to the high potential end of the first group. The three ports are respectively connected to the three-phase discharge device.

2. The Y-type three-phase arc high-voltage discharge system for optical fiber fusion splicer according to claim 1, characterized in that: The ZYNQ development board generates four PWM waves, namely PWM0, PWM1, PWM2, and PWM3. The duty cycle of PWM0 is 50% and the frequency is 300KHz, which is used to control the amplitude of the boost circuit module; the duty cycle of PWM1, PWM2, and PWM3 is 66%, the frequency is 30KHz, and the phase difference between them is 120°. They are used to control three identical Flyback circuit modules, converting the output voltage of the Boost circuit into three groups of full-wave pulse high voltages with equal amplitudes and phase difference of 120°.

3. The Y-type three-phase arc high-voltage discharge system for optical fiber fusion splicer according to claim 1, characterized in that: In the Boost circuit module, when the MOS tube Q1 is in the on state, the relationship is as follows: When the MOS tube Q1 is in the off state, the relationship is as follows: The initial and final values ​​of the inductor current are equal, and the integral of the voltage across the two terminals with respect to time is 0, which yields the following relationship: Among them, V s is the input voltage, V O is the output voltage, L is the self-inductance coefficient, t is the time, i L is the inductor current, T off is the cut-off time of MOS tube Q1, T on is the conduction time of MOS tube Q1, D is the duty cycle of PWM signal, Δi L+ is the current change when the MOS tube Q1 is turned on, Δi L- It is the current change when the MOS tube Q1 is turned off.

4. The Y-type three-phase arc high-voltage discharge system for optical fiber fusion splicer according to claim 1, characterized in that: The gate drive module A includes a gate driver chip U1, resistors R1, R2, R3 and capacitor C2. When the MOS tube Q1 is in the on state, the inductor L1 is grounded and the diode D1 is cut off. The power supply voltage charges the inductor L1 after being stabilized by the input capacitor, and at the same time provides voltage to the gate drive chip U1. The PWMA output by the ZYNQ development board remains unchanged after passing through the gate drive chip U1, and the current increases. The appropriate switching speed is obtained through the parallel resistors R1 and R2 to control the on and off of the MOS tube Q1. The function of the resistor R3 is to pull the gate-source voltage of the MOS tube Q1 down to 0V when the input signal is open.

5. The Y-type three-phase arc high-voltage discharge system for optical fiber fusion splicer according to claim 1, characterized in that: In the Flyback circuit module, the ratio of output to input voltage is: Among them, N1 is the number of turns of the primary coil, N2 is the number of turns of the secondary coil, V S1 is the input voltage, V O1 is the output voltage, and D is the duty cycle of the PWM signal.

6. The Y-type three-phase arc high-voltage discharge system for optical fiber fusion splicer according to claim 1, characterized in that: The gate drive module B shown includes a gate drive chip U6, resistors R17, R18, R20, and capacitor C21. The power supply voltage provides voltage to the gate drive chip U6 after being stabilized by capacitor C21. The PWM-A output by the ZYNQ development board has an unchanged waveform after passing through the gate drive chip U6, but the current increases. The appropriate switching speed is obtained through the parallel resistors R17 and R18 to control the on and off of the MOS tube Q1. The function of the resistor R20 is to pull the gate-source voltage of the MOS tube Q5 down to 0V when the input signal is open.

7. The Y-type three-phase arc high-voltage discharge system for optical fiber fusion splicer according to claim 1, characterized in that: The primary side of the transformer T1 of the flyback circuit module is provided with an RCD circuit for absorbing the leakage inductance energy of the primary side of the transformer T1 to prevent damage to the MOS transistor Q5. The RCD circuit includes a diode D7, a resistor R15, and a capacitor C19. The resistor R15 and the capacitor C19 are connected in parallel and then in series with the diode D7.

8. The Y-type three-phase arc high-voltage discharge system for optical fiber fusion splicer according to claim 1, characterized in that: In order to obtain a PWM wave with a smooth waveform, the clock IP core of the ZYNQ development board is called with a clock frequency of 50M. The register is defined as a counter. The rising edge of the clock is used as the trigger point, and the counter value increases sequentially. When the value accumulates to a certain level, it is compared with the preset value to generate PWM. When the counter value is less than the duty cycle, the PWM output is high; otherwise, it is low, realizing a PWM wave with adjustable duty cycle.

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