Prefetch-based processor instruction fetching acceleration method and device

Abstract

The invention discloses a processor instruction fetching acceleration method and device based on prefetching, and relates to the technical field of computer processors. Pre-decoding the instruction to obtain a first category of the instruction; according to the execution type, classifying part of the instructions of the first category to obtain a second category of the instructions; according to a preset processing method, the instructions of the first category and the instructions of the second category are skipped to update target addresses of the instructions, and the instruction fetching process is achieved. According to the invention, the required instruction can be quickly obtained, and a processing device with high performance, low power consumption, small area and simple structure is realized, so that the processor has good engineering practicability.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer processors, and in particular relates to a method and device for accelerating processor instruction fetching based on prefetching. Background Art

[0002] In the operation of modern computer processors, pipeline design is a necessary technology for processor operations. The instruction pipeline divides the execution process of instructions into multiple stages in a parallel manner, such as fetch, decode, and execute, thereby improving the throughput of the processor. Instruction fetch is located at the front of the modern processor pipeline, and its main function is to fetch instructions from the instruction cache to the instruction register in the instruction fetch stage.

[0003] In the operation process of modern computer processors, the instruction fetch stage has a crucial impact on the performance of the entire processor. When facing branch jump instructions, the traditional processor instruction fetch method often needs to wait for the conditional judgment result of the execution stage to determine the address of the next instruction, which leads to the generation of instruction fetch bubbles, reduces the instruction fetch efficiency, and further affects the operation speed of the entire processor. Therefore, how to effectively reduce instruction fetch bubbles and improve instruction fetch efficiency has become a problem that needs to be solved in processor design. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a method and device for accelerating instruction fetching of a processor based on prefetching. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In a first aspect, the present invention provides a method for accelerating processor instruction fetching based on prefetching, comprising:

[0006] Get instructions;

[0007] The instructions are pre-decoded to obtain the first category of instructions; according to the execution type, some of the instructions of the first category are classified to obtain the second category of instructions; according to the preset processing method, the instructions of the first category and the instructions of the second category are jumped to update the target address of the instructions to realize the instruction fetching process.

[0008] In a second aspect, the present invention further provides a processor accelerated instruction fetching device based on prefetching, comprising:

[0009] The instruction fetch unit is used to obtain instructions. The instruction fetch unit includes a pre-decoding module, which is used to pre-decode instructions to obtain a first category of instructions; classify some of the first category of instructions according to the execution type to obtain a second category of instructions; and jump to the first category of instructions and the second category of instructions according to a preset processing method to update the target address of the instruction to implement the instruction fetch process.

[0010] Beneficial effects of the present invention:

[0011] The present invention provides a method and device for accelerating instruction fetching of a processor based on prefetching, which pre-decodes instructions to obtain a first category of instructions; classifies some instructions of the first category according to the execution type to obtain a second category of instructions; jumps to the instructions of the first category and the instructions of the second category according to a preset processing method to update the target address of the instruction and implement the instruction fetching process; the required instructions can be quickly acquired to implement a high-performance, low-power, small-area, and simple-structured processing device, so that the processor has good engineering practicality.

[0012] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a flow chart of a method for accelerating processor instruction fetching based on prefetching provided by an embodiment of the present invention;

[0014] Figure 2 is a schematic diagram of an instruction fetching approach provided by an embodiment of the present invention;

[0015] Figure 3 It is a schematic diagram of a processor accelerated instruction fetch device based on prefetching provided by an embodiment of the present invention;

[0016] Figure 4 It is a schematic diagram of branch jump instruction types and instruction formats provided by an embodiment of the present invention;

[0017] Figure 5 It is a schematic diagram of pre-decoding and branch prediction provided by an embodiment of the present invention;

[0018] Figure 6 It is a schematic diagram of a micro-architecture module of an instruction fetch method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0020] In order to overcome the shortcomings of slow instruction fetching speed in the instruction fetching stage of traditional processors and the waiting period of instruction fetching bubble period generated for branch jump instruction judgment, the instruction fetching method proposed in the present invention has the characteristics of higher instruction fetching efficiency and lower power consumption.

[0021] See also Figure 1 , Figure 1 1 is a flow chart of a method for accelerating processor instruction fetching based on prefetching provided by an embodiment of the present invention. The method for accelerating processor instruction fetching based on prefetching provided by the present invention comprises:

[0022] S101. Get instructions.

[0023] Specifically, in this embodiment, see Figure 2 , Figure 2 1 is a schematic diagram of an instruction fetching method provided by an embodiment of the present invention, wherein fetching instructions includes:

[0024] fetching instructions from an instruction tightly coupled memory;

[0025] Alternatively, instructions are fetched from external memory via a bus.

[0026] In this embodiment, instructions come from two paths, one path is to fetch instructions from the on-chip instruction tightly coupled memory ITCM (Instruction Tightly Coupled Memory), and the other path is to fetch instructions from the external memory through the system bus. In this embodiment, most of the instruction fetching occurs in ITCM. The proposed processor is a small-area processor designed for embedded and ultra-low power consumption scenarios. It does not use instruction cache and mainly uses ITCM for storage to meet real-time requirements. For some special cases, instructions need to be read from external memory (for example, the boot program after the system is powered on may need to be read from external flash memory). For these few use cases, no acceleration optimization design is performed.

[0027] The instruction tightly coupled memory of this embodiment uses a smaller capacity SRAM configurable by customers to store instructions. It is physically closer to the processor core and is exclusively used by the processor core, which can achieve smaller access delay and speed up the instruction fetching process.

[0028] S102, pre-decode the instructions to obtain the first category of instructions; classify some of the first category of instructions according to the execution type to obtain the second category of instructions; jump the first category of instructions and the second category of instructions according to a preset processing method to update the target address of the instructions and implement the instruction fetching process.

[0029] Specifically, in this embodiment, see Figure 3 , Figure 3 This is a schematic diagram of a pre-fetch-based processor acceleration instruction fetch device provided by an embodiment of the present invention. The solution of this embodiment is designed based on the RV32IM subset of the RISC-V instruction set architecture. This embodiment adds a pre-decoding module to the instruction fetch unit. In order to facilitate the maintenance of the project and reduce the logic synthesis of other irrelevant circuits, the pre-decoding module pre-decodes the fetched instructions to obtain partial information of the instructions. The pre-decoding module instantiates the complete decoder module of the decoding unit, connects its irrelevant input signals to zero, suspends the output signals, and optimizes irrelevant circuits through logic synthesis.

[0030] In this embodiment, the first category includes common instructions and branch jump instructions. Figure 4 , Figure 4 It is a schematic diagram of the branch jump instruction types and instruction formats provided by an embodiment of the present invention. The second category includes conditional direct branch jump instructions, unconditional direct branch jump instructions and unconditional indirect branch jump instructions.

[0031] In this embodiment, the preset processing methods include a processing method for ordinary instructions, a processing method for conditional direct branch jump instructions, a processing method for unconditional direct branch jump instructions, and a processing method for unconditional indirect branch jump instructions.

[0032] It should be noted that the instruction decoding classification of the opcode segment can be performed according to the instruction encoding structure characteristics of the RISC-V instruction set architecture. In this embodiment, the instruction is decoded to determine whether the current instruction is a normal instruction or a branch jump instruction, and the branch jump instruction is classified according to the execution type, and the current instruction is translated as a conditional direct branch jump instruction (respectively beq, bne, blt, bge, bltu, bgeu instructions), or an unconditional direct branch jump instruction (jal instruction), or an unconditional indirect branch jump instruction (jalr instruction). Different types of instructions are processed differently. For specific operations, please refer to the following content, please refer to Figure 5 , Figure 5 It is a schematic diagram of pre-decoding and branch prediction provided by an embodiment of the present invention.

[0033] Furthermore, the processing method for common instructions includes: taking the target address of the next instruction plus a threshold value according to a preset instruction fetching order as the target address of the updated instruction for jumping; wherein the threshold value is the number of instruction bits in the instruction set pre-implemented by the processor divided by 8; it should be noted that, since the instruction is 32 bits, for common instructions, the target address of the updated instruction is directly generated by the target address generation module, that is, for common instructions, taking the target address of the next instruction plus 4 according to the preset instruction fetching order as the target address of the updated instruction;

[0034] The processing method for conditional direct branch jump instructions includes: performing branch prediction on conditional direct branch jump instructions, if the prediction is to jump according to the first jump order, adding the offset represented by the immediate number to the target address of the current instruction is used as the updated target address of the instruction to jump; if the prediction is to jump according to the second jump order, no jump is performed; wherein the first jump order includes that the target address to be jumped by the instruction is smaller than the current target address of the instruction, and the first jump order is opposite to the second jump order; optionally, the first jump order is a backward jump, and the second jump order is a backward jump; it should be noted that this method is based on the fact that the situation in which branches jump backward is more than the situation in which branches jump forward in actual assembly programs, such as the assembly instructions generated by common for loops often use branch instructions for backward jumps, and the use of this method increases the prediction accuracy and speeds up the instruction fetching process;

[0035] The processing method for the unconditional direct branch jump instruction includes: predicting the unconditional direct branch jump instruction as a certain jump, without predicting the jump direction, adding the offset represented by the immediate number to the current target address of the instruction as the target address of the updated instruction to jump; it should be noted that the content to be executed by all types of jump instructions is the source target address (PC value) + offset, but the jalr instruction is different. Its base address is not the source PC value, but the operand indexed from the source operand 1 (rs1), rs1. The offset of each instruction is composed of an immediate number, which is specified in the RISC-V manual. For example, the beq instruction executes if (x[rs1] == x[rs2]), pc + = sext (offset). Specifically, when the value of register x[rs1] is exactly equal to the value of x[rs2], the program counter pc will be added with the offset offset after the sign extension (sext), and this offset offset is the immediate number.

[0036] The processing method for unconditional indirect branch jump instructions includes: predicting the unconditional indirect branch jump instruction as a certain jump, without predicting the jump direction, according to the base address read from the general register group, the base address may form a data conflict with the instruction in the execution stage, the base address comes from the operand indexed by the source operand 1, the processor uses different methods to optimize it according to the index value of different source operands 1, and obtains the target address of the updated instruction for jumping.

[0037] Further, the unconditional indirect branch jump instruction is predicted as a certain jump, and the target address of the updated instruction is obtained according to the base address read from the general register group, including:

[0038] If the index value of source operand 1 is the value of the first register, that is, the value of the x0 register, according to the RISC-V architecture definition, the constant 0 is directly used without reading the value from the register group, and 0 plus the offset represented by the immediate value is used as the target address of the updated instruction to jump;

[0039] If the index value of source operand 1 is the value of the second register, that is, the value of the x1 register, according to the RISC-V instruction set architecture assembly language rules, the x1 register is used to make the function return to the jump instruction, so the x1 register is directly taken out from the general register group in the decoding stage, without occupying the general register group read port, and the value read from the second register plus the offset represented by the immediate number is used as the target address of the updated instruction to jump;

[0040] If the index value of source operand 1 is the value of the xnth (x2-x31)th register, no acceleration is performed. It is necessary to determine whether there is a data conflict. If there is a conflict, it is read out from the register group read port in the execution stage after the data conflict is contacted, and the value read from the xnth register plus the offset represented by the immediate number is used as the target address of the updated instruction to jump, that is, it is not accelerated; wherein, x represents a register, and n represents a register other than the first and second registers. For example, x0, x1...xn...x31, a total of 32 registers, are the names set for each register in the RISC-V instruction set architecture manual, and n represents any number from 2 to 31 except 0 / 1.

[0041] It can be understood that the data conflict mentioned above refers to two data, one is the data that jalr wants to read from register xn, and there is a conflict with the data of the subsequent instruction that is not written back.

[0042] In summary, the present invention provides a method for accelerating instruction fetching of a processor based on prefetching, which obtains instructions, pre-decodes the instructions, and obtains a first category of instructions; classifies some of the first category of instructions according to the execution type to obtain a second category of instructions; jumps to the first category of instructions and the second category of instructions according to a preset processing method to update the target address of the instruction and implement the instruction fetching process; the required instructions can be quickly obtained to realize a high-performance, low-power, small-area, and simple-structured processing device, so that the processor has good engineering practicality.

[0043] Based on the same invention concept, please continue to refer to Figure 3 The present invention further provides a pre-fetch-based processor accelerated instruction fetching device, which is used to implement a pre-fetch-based processor accelerated instruction fetching method provided by the above embodiment of the present invention. The embodiment of the method is referred to above and will not be repeated here. The device includes:

[0044] The instruction fetch unit is used to obtain instructions. The instruction fetch unit includes a pre-decoding module, which is used to pre-decode instructions to obtain a first category of instructions; classify some of the first category of instructions according to the execution type to obtain a second category of instructions; and jump to the first category of instructions and the second category of instructions according to a preset processing method to update the target address of the instruction to implement the instruction fetch process.

[0045] Specifically, in this embodiment, the instruction fetch unit (IFU) is a module in the CPU responsible for fetching instructions. The instruction fetch unit includes a pre-decoding module. The pre-decoding module instantiates a complete decoder module of the decoding unit, connects its irrelevant input signals to zero, leaves the output signals floating, and optimizes irrelevant circuits through logic synthesis.

[0046] In this embodiment, a pre-decoding module is added to the processor instruction fetching stage to pre-decode the fetched instruction, and decode it based on the RV32IM subset rule of the RISC-V instruction set architecture to implement partial decoding functions, including decoding whether the instruction is a common instruction or a branch jump instruction, and whether the branch jump instruction is a conditional direct jump instruction, a conditional indirect jump instruction, an unconditional direct jump instruction, or an unconditional indirect jump instruction. Further instruction fetching processing is performed according to different instruction types; thus, a fast instruction fetching process is implemented.

[0047] In an optional embodiment of the present invention, please continue to refer to Figure 3 The instruction fetch unit also includes a branch prediction module, which is used to perform branch prediction on conditional direct branch jump instructions, predict unconditional direct branch jump instructions as certain jumps, and predict unconditional indirect branch jump instructions as certain jumps.

[0048] Specifically, in this embodiment, considering that in various instruction sets, branch instructions are an indispensable type of instruction in each instruction set system. Since branch instructions will cause control hazards, the processor may cause the pipeline to be refreshed when running branch instructions. In addition, in general program codes, branch instructions account for about 1 / 4; in view of this, a branch prediction module is introduced in this embodiment to perform special processing on branch instructions and improve the performance of the processor.

[0049] This embodiment adopts the RISC-V instruction set. In the RISC-V instruction set, branch instructions are mainly divided into two categories: conditional branch instructions and unconditional branch instructions. For the program segment of the loop, in a processor with a long pipeline, the predictor generally needs to perform multiple learning to accurately predict the program segment of the loop, and it is impossible to achieve accurate prediction. In this embodiment, a branch prediction module (Branch Prediction Unit) is added in the instruction fetch stage to predict the direction of branch jumps and load possible instructions in advance to reduce waiting time. The branch prediction module predicts whether the current branch instruction will jump and the target address of the jump based on historical data and the behavior of branch instructions. In this way, the processor can continue to load the predicted instructions without pausing when encountering branch instructions, thereby improving the execution efficiency of the instruction pipeline.

[0050] In an optional embodiment of the present invention, please continue to refer to Figure 3 , the branch prediction module is a static branch prediction module.

[0051] Specifically, considering that the pipeline in the common instruction fetch module cannot know whether the condition of the instruction is established during the instruction fetching stage, it is impossible to decide whether the next target address is to jump or not. Only after the execution stage is completed, the final jump result can be parsed; if the processor's instruction fetching is suspended and the instruction fetching is continued after the execution stage is completed, a large number of pipeline vacuoles will be caused, thereby affecting the performance. In this embodiment, a static branch prediction method is used in the instruction fetching stage to improve the processor performance. Based on the fact that the branch jumps backward in the actual assembler program more than the forward jump, the branch prediction module (lite-bpu) of this embodiment adopts a static branch prediction method, and the prediction rule is that the backward jump is predicted as a jump, and the forward jump is predicted as no jump. For the prediction of the jump address, this embodiment adopts the return address stack technology (Return Address Stack, RAS), which refers to the use of a hardware stack with limited capacity to store the return address of the function call. In the RISC-V architecture, indirect jump / branch instructions can be used for function calls and returns. Function calls and returns often appear in pairs in a program, so when calling a function, the current PC value can be increased by 4, that is, the PC value of the next instruction to be executed by the function can be pushed into RAS, and the value in RAS can be popped out when the function returns, so that the target address can be quickly predicted for the branch jump instruction returned by the function. The instruction fetching device in this embodiment is suitable for embedded products that do not require high main frequency but require low power consumption and area.

[0052] In an optional embodiment of the present invention, please continue to refer to Figure 3 , also includes a target address generator module for generating a target address of the updated instruction.

[0053] In an optional embodiment of the present invention, it is considered that in the existing storage architecture, there is a bottleneck in the data transmission speed between the processor and the storage device. Although the main memory (such as DRAM) has a large capacity, the access speed is relatively slow, and although the cache (such as the traditional cache) can alleviate the speed difference to a certain extent, there are still some problems. For example, the storage content and management method of the cache are based on hardware automatic control, and its data replacement strategy and hit situation have certain statistical characteristics. For some application scenarios with extremely high requirements for real-time and determinism, this uncertainty may cause performance fluctuations.

[0054] At the same time, computer systems need more accurate and efficient storage solutions when handling complex tasks, such as real-time control, encryption and decryption, multimedia processing, etc. These applications often require fast and predictable access to specific code or data. In real-time control systems, interrupt handlers must be executed at precise times, and any delay or uncertainty in storage access may cause system failure. For encryption algorithms, not only high performance is required, but also security risks caused by predictability issues in the storage system (such as cache analysis attacks that may use the behavioral characteristics of the cache to obtain encrypted information) must be avoided.

[0055] The cache of the instruction fetch unit is a tightly coupled memory TCM (Tightly Coupled Memory), including the instruction tightly coupled memory ITCM (Instruction Tightly Coupled Memory) and the data tightly coupled memory DTCM (Data Tightly Coupled Memory). As a special high-speed cache, TCM is designed to solve the above-mentioned technical problems. TCM is tightly coupled with the processor and provides a high-speed storage mechanism between the processor registers and the main memory. By allowing program code to precisely control which functions or codes are stored in TCM (located in a specific area of ​​RAM), TCM achieves precise management of storage content. Unlike traditional cache, TCM will not be easily replaced from the main memory, and its performance is preset by the user according to specific application requirements, thereby providing stable and predictable storage access for applications with high performance and determinism requirements, and meeting the special requirements of modern computer systems for storage systems in complex application scenarios.

[0056] This embodiment uses the TCM tightly coupled memory architecture, which is divided into an instruction tightly coupled memory and a data tightly coupled memory. Using SRAM as the instruction tightly coupled memory, and setting it physically close to the processor core and exclusively belonging to the processor core, can achieve a smaller access delay.

[0057] In this embodiment, TCM has significant application value and is indispensable in a variety of specific code scenarios. For foreseeable real-time processing situations, such as interrupt processing, TCM can ensure the timeliness and accuracy of processing and meet real-time requirements; in scenarios where time is foreseeable, such as the execution of encryption algorithms, TCM can ensure the predictability of algorithm execution in time; in situations where cache analysis needs to be avoided, especially for encryption algorithms, TCM can effectively prevent security risks that may be caused by cache characteristics; in addition, for those codes that only require high performance, such as code related to encoding and decoding functions, TCM can provide them with a stable and high-performance operating environment to ensure efficient execution of the code, thereby improving the performance and security of the entire system in these key application scenarios.

[0058] In an optional embodiment of the present invention, see Figure 6 , Figure 6 It is a schematic diagram of a micro-architecture module of an instruction fetch method provided in an embodiment of the present invention, wherein a bus includes an AHB bus slave and an AHB bus master, which are used to obtain instructions from a memory.

[0059] In an optional embodiment of the present invention, please continue to refer to Figure 3 and Figure 6 The transfer registers include the PC register and the IR register, which are used to implement the storage and transfer of instructions after instruction fetching.

[0060] In an optional embodiment of the present invention, please continue to refer to Figure 6 The decoding unit includes a general register group module, a decoder module and an external instruction tracking FIFO module. The decoding unit is used to decode the instruction after fetching.

[0061] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0062] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0063] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A processor accelerated instruction fetch method based on prefetching, characterized in that: include: Get instructions; Pre-decoding the instruction to obtain a first category of the instruction; Classifying some of the first category of instructions according to the execution type to obtain a second category of the instructions; According to a preset processing method, the instructions of the first category and the instructions of the second category are jumped to update the target addresses of the instructions to implement the instruction fetching process.

2. The method for accelerating processor instruction fetching based on prefetching according to claim 1, characterized in that: The acquisition instruction includes: fetching instructions from an instruction tightly coupled memory; Alternatively, instructions are fetched from external memory via a bus.

3. The method for accelerating processor instruction fetching based on prefetching according to claim 1, characterized in that: The first category includes common instructions and branch jump instructions.

4. The method for accelerating processor instruction fetching based on prefetching according to claim 1, characterized in that: The second category includes conditional direct branch instructions, unconditional direct branch instructions, and unconditional indirect branch instructions.

5. The method for accelerating processor instruction fetching based on prefetching according to claim 3 or 4, characterized in that: The preset processing methods include a processing method for common instructions, a processing method for conditional direct branch jump instructions, a processing method for unconditional direct branch jump instructions, and a processing method for unconditional indirect branch jump instructions.

6. The method for accelerating processor instruction fetching based on prefetching according to claim 5, characterized in that: The processing method for common instructions includes: taking the target address of the next instruction plus a threshold value according to a preset instruction fetching order as the target address of the updated instruction to jump; wherein the threshold value is the number of instruction bits in the instruction set pre-implemented by the processor divided by 8; The processing method for the conditional direct branch jump instruction includes: performing branch prediction on the conditional direct branch jump instruction, if the prediction is to jump according to a first jump order, adding an offset represented by an immediate number to the target address of the current instruction, as the updated target address of the instruction, to jump; if the prediction is to jump according to a second jump order, not jumping; wherein the first jump order includes that the target address to be jumped by the instruction is smaller than the current target address of the instruction, and the first jump order is opposite to the second jump order; The processing method for the unconditional direct branch jump instruction includes: predicting that the unconditional direct branch jump instruction will definitely jump, adding the offset represented by the immediate number to the current target address of the instruction as the updated target address of the instruction to jump; The processing method for the unconditional indirect branch jump instruction includes: predicting the unconditional indirect branch jump instruction as a certain jump, and obtaining the updated target address of the instruction according to the base address read from the general register group, the base address comes from the operand indexed by the source operand 1, to perform the jump.

7. The method for accelerating processor instruction fetching based on prefetching according to claim 6, characterized in that: The predicting of the unconditional indirect branch jump instruction as a certain jump, and obtaining an updated target address of the instruction according to a base address read from a general register group, comprises: If the index value of source operand 1 is the value of the first register, the offset represented by the immediate value is used as the target address of the instruction to update for jumping; If the index value of source operand 1 is the value of the second register, the value read from the second register plus the offset represented by the immediate value is used as the target address of the instruction to be updated for jumping; If the index value of source operand 1 is the value of the xnth (x2-x31)th register, determine whether there is a data conflict. If there is a conflict, add the value read from the xnth register to the offset represented by the immediate number as the updated target address of the instruction for jumping; wherein x represents a register, and n represents a register other than the first and second registers.

8. A processor acceleration instruction fetching device based on prefetching, characterized in that: include: An instruction fetch unit, used for fetching instructions, the instruction fetch unit comprising a pre-decoding module, used for pre-decoding the instructions to obtain a first category of the instructions; Classifying some of the instructions of the first category according to the execution type to obtain a second category of the instructions; According to a preset processing method, the instructions of the first category and the instructions of the second category are jumped to update the target addresses of the instructions to implement the instruction fetching process.

9. The processor accelerated instruction fetching device based on prefetching according to claim 8, characterized in that: The instruction fetch unit also includes a branch prediction module, which is used to perform branch prediction on conditional direct branch jump instructions, predict unconditional direct branch jump instructions as certain jumps, and predict unconditional indirect branch jump instructions as certain jumps.

10. The processor accelerated instruction fetching device based on prefetching according to claim 9, characterized in that: The branch prediction module is a static branch prediction module.

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