Memory device and control method thereof
By maintaining a preset charge on the global data line and complementary global data line of the memory device, the problems of large energy consumption of read and write data and long reading time in the prior art are solved, and the effect of reducing energy consumption and duration is achieved, and memory performance is improved.
Patent Information
- Application Number
- CN202411749103.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-03-21
AI Technical Summary
The existing memory devices consume a lot of energy during reading and writing data, resulting in an increase in reading time and affecting memory performance.
By maintaining a preset charge on the global data line and the complementary global data line, the potential stability is achieved by using the charge conservation of the data line itself, thereby reducing the energy consumption and reading time of the global amplifier circuit.
It effectively reduces the energy consumption and duration of the memory device during the reading of data, and improves memory performance.
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Figure CN119673243A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory device and a control method thereof. Background Art
[0002] With the popularity of electronic devices such as mobile phones, tablets, and personal computers, the technology related to memory devices has also developed rapidly. Among them, improving the performance of memory reading and writing data is an important research direction. For example, in dynamic random access memory (DRAM), a multi-stage amplifier circuit is provided, which amplifies the voltage difference through the multi-stage amplifier circuit to realize reading or writing data in the storage unit. However, the multi-stage discharge circuit consumes a lot of energy in the process of reading and writing data. Summary of the invention
[0003] In view of this, the embodiments of the present disclosure provide a memory device and a control method thereof, which can reduce the data transmission reading time, reduce the energy consumption in the data reading process, and improve the performance of the memory device.
[0004] On the one hand, some embodiments of the present application provide a control method for a memory device. The memory device includes a plurality of memory cells arranged in an array and a peripheral circuit coupled to the plurality of memory cells; the peripheral circuit includes a global data line and a complementary global data line, and a global amplifier circuit and a local amplifier circuit coupled through the global data line and the complementary global data line.
[0005] The control method includes: the global amplification circuit maintains the target signal of the target storage unit on the global data line and the complementary global data line for a preset time length in response to the first global control signal being in the off state and the first local control signal being in the off state, and outputs the target signal in response to the first global control signal being in the enabled state when the difference between the voltage on the global data line and the voltage on the complementary global data line meets the preset value.
[0006] In some examples, the global amplifier circuit amplifies the voltage difference between the target signal transmitted by the global data line and the reference signal transmitted by the complementary global data line to a full swing in response to the second global control signal being in an enabled state and the first global control signal being in an off state, thereby obtaining a target voltage difference; and, based on the target voltage difference being greater than or equal to the preset value, outputs the target signal in response to the first global control signal being in an enabled state.
[0007] The preset value is related to the length of the global data line and the complementary global data line, and the preset time length, and is a minimum voltage difference for driving the global amplifier circuit to output the target signal.
[0008] In some examples, the peripheral circuit includes a local data line and a complementary local data line, and a local amplification circuit coupled to the local data line and the complementary local data line; the local amplification circuit couples the plurality of storage units through the local data line and the complementary local data line.
[0009] The control method includes: in response to the first local control signal being in an enabled state, the local amplification circuit processes the signals on the local data line and the complementary local data line and transmits the processed signals to the global data line and the complementary global data line.
[0010] In some examples, the peripheral circuit further includes a sensitive amplifier circuit; the sensitive amplifier circuit is coupled to the local amplifier circuit through the local data line and the complementary local data line, and is coupled to the storage unit through a bit line and a complementary bit line.
[0011] The control method comprises: the sensitive amplifier circuit responds to an enable signal, and transmits the data stored in the storage unit obtained on the bit line and the complementary bit line to the local data line and the complementary local data line after processing.
[0012] In some examples, the multiple memory cells include a first memory cell and a second memory cell coupled to a bit line; during a read operation, the first memory cell is one of the memory cells close to the global amplifier circuit along the signal transmission direction of the global data line and the complementary global data line; the second memory cell is one of the memory cells away from the global amplifier circuit along the signal transmission direction of the global data line and the complementary global data line.
[0013] The control method includes: determining that the difference between the voltage of the first storage unit on the global data line and the voltage on the complementary global data line is a first voltage difference; determining that the difference between the voltage of the second storage unit on the global data line and the voltage on the complementary global data line is a second voltage difference; the first voltage difference and the second voltage difference are in a trend of approaching each other.
[0014] In some examples, the control method further includes: the global amplification circuit pre-charging the global data line and the complementary global data line in response to the third global control signal being in an enabled state;
[0015] In some examples, the control method further includes: the local amplification circuit pre-charging the local data line and the complementary local data line in response to the second local control signal being in an enabled state.
[0016] In the above control method, in the process of reading the target signal stored in the target storage unit, before the global amplifier circuit outputs the target signal and after the global amplifier circuit receives the target signal transmitted by the local amplifier circuit, the potential on the global data line and the complementary global data line is balanced for a preset time, that is, the charge conservation of the data line itself is used to achieve the stability of the potential at both ends of the data line, which is beneficial to improving the accuracy of the signal received by the global amplifier circuit. Moreover, it can solve the problem of high energy consumption and long time consumption for the global amplifier circuit to pre-charge the potential on the global data line and the complementary global data line due to the long global data line and the complementary global data line causing the transmission signal delay and the large potential difference at both ends of the data line, thereby achieving the purpose of reducing the reading time and energy consumption in the process of the memory device reading data.
[0017] On the other hand, an embodiment of the present application provides a memory device, including:
[0018] A memory cell array, comprising a plurality of memory cells;
[0019] A peripheral circuit includes a global data line and a complementary global data line, and a global amplifier circuit and a local amplifier circuit coupled through the global data line and the complementary global data line; the global amplifier circuit is configured to maintain a target signal of a target storage unit on the global data line and the complementary global data line for a preset time in response to a first global control signal being in an off state and a first local control signal being in an off state, and output the target signal in response to the first global control signal being in an enabled state when the difference between the voltage on the global data line and the voltage on the complementary global data line meets a preset value; the target storage unit is a storage unit close to the global amplifier circuit along the transmission direction of the signal on the global data line and the complementary global data line; the preset value is related to the length of the global data line and the complementary global data line, and the preset time.
[0020] In some examples, the global amplification circuit includes: a first control transistor, a second control transistor, and an amplification circuit.
[0021] The first control transistor is coupled to the global data line and the local data line, and is configured to receive a first signal transmitted by the local data line in response to a second global control signal being in an enabled state; the global amplifier circuit is configured to equalize the potential of the first signal on the complementary global data line in response to the second global control signal being in an enabled state, the first global control signal being in an off state, and the first local control signal being in an off state.
[0022] The second control transistor is coupled to the complementary global data line and the complementary local data line, and is configured to receive a second signal transmitted by the complementary local data line in response to the second global control signal being in an enabled state; the global amplification circuit is configured to equalize the potential of the second signal on the complementary global data line in response to the second global control signal being in an enabled state, the first global control signal being in an off state, and the first local control signal being in an off state.
[0023] The amplifier circuit is coupled to the first control transistor and the second control transistor, and is configured to amplify and output the first signal and the second signal after equalization processing in response to the first global control signal being in an enabled state.
[0024] In some examples, the peripheral circuit includes: a sensitive amplifier circuit, a local amplifier circuit, and a global amplifier circuit.
[0025] One of the storage cells is coupled to one of the sensitive amplifier circuits, and the sensitive amplifier circuit is configured to read the target signal stored in the target storage cell through a bit line, and output the target signal after determining a reference voltage through a complementary bit line.
[0026] The local amplifier circuit is coupled to the bit line through the local data line and to the complementary bit line through the complementary local data line, and is configured to process the target signal and then output it;
[0027] The global amplifier circuit is coupled to the local data line through the global data line and to the complementary local data line through the complementary global data line, and is configured to output the target signal after equalizing the potentials of the signals on the global data line and the complementary global data line for a preset time.
[0028] The beneficial effects of the above-mentioned memory device are the same as the beneficial effects of the control method of the memory device provided in any of the above-mentioned examples, and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In the accompanying drawings, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.
[0030] Figure 1 A schematic diagram of the structure of a memory device provided in one embodiment of the present application;
[0031] Figure 2 A schematic diagram of the peripheral circuit structure of a memory device provided in one embodiment of the present application;
[0032] Figure 3A schematic diagram of the structure of a multi-stage amplifier circuit of a memory device provided in one embodiment of the present application;
[0033] Figure 4 A schematic diagram of the structure of a global amplifier circuit provided in one embodiment of the present application;
[0034] Figure 5 A schematic diagram of the circuit principle structure of a global amplifier circuit provided in an embodiment of the present application;
[0035] Figure 6 A schematic diagram of the circuit principle structure of a local amplification circuit provided in one embodiment of the present application;
[0036] Figure 7 A schematic diagram of a flow chart of a method for controlling a memory device provided in one embodiment of the present application;
[0037] Figure 8 The use provided by an embodiment of the present application Figure 5 and Figure 6 A timing diagram of reading data of the circuit;
[0038] Fig. 9 A schematic diagram of the structure of a memory system provided in one embodiment of the present application;
[0039] Fig.10 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION
[0040] The technical solution of the present disclosure is further elaborated in detail below in conjunction with the accompanying drawings and specific embodiments of the specification.
[0041] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, but are not used to describe a specific order or sequence.
[0042] In the embodiments of the present disclosure, the term “A is in contact with B” includes the situation where A is in direct contact with B, or the situation where A is in indirect contact with B with other components interposed between A and B.
[0043] It should be understood that the "some embodiments" or "some examples" mentioned throughout the specification mean that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, "in some embodiments" or "in some examples" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.
[0044] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0045] It will be understood that the meaning of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning of “on” something with intervening features or layers.
[0046] It should be noted that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
[0047] With the popularization of electronic devices such as mobile phones, tablets, and personal computers, the technology related to memory devices has also developed rapidly. Among them, improving the performance of memory reading and writing data is an important research direction.
[0048] For example, in a dynamic random access memory (DRAM), a multi-stage amplifier circuit is provided to amplify the voltage difference to realize reading or writing data in the storage unit. The amplifier circuit can sample the information on the bit line of the storage unit, make a judgment through level comparison, and obtain a high or low level (logical state "1" or "0") signal after amplification. The performance of the amplifier circuit directly affects the speed of reading and writing data.
[0049] As the storage density and capacity of memory devices increase, the number of memory cells connected to each bit line in the memory cell array is increasing, and the parasitic capacitance on a single bit line is also increasing, which can easily lead to a decrease in the reading speed of the amplifier circuit, increase signal delay, and increase the energy consumption of the amplifier circuit in transmitting the signal.
[0050] For example, when the voltage difference after amplification of the signal on the bit line and the signal on the complementary bit line reaches a preset value, the amplifier circuit outputs the target data to realize data reading and writing. Among them, if the difference between the voltage difference and the preset value is large, it takes a long time to perform the pre-charging operation, and the amount of charge required for the voltage difference to reach the preset value is large, which means that in the process of reading data, the reading speed is slow and the energy consumption is large. Therefore, the requirements for amplifier circuits are getting higher and higher. Low-voltage, low-power, high-speed, and high-stability amplifier circuits and driving methods are currently important research directions for memory devices.
[0051] In order to solve the above problems, the present application provides a memory device and a control method thereof, which can reduce the data transmission reading time, reduce the energy consumption in the data reading process, and improve the performance of the memory device.
[0052] In some embodiments, Figure 1 and Figure 2 As shown, the present application provides a memory device 100 .
[0053] For example, the memory device 100 may include, but is not limited to, one or more memories of NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (NRAM), etc. For example, the present application takes the memory device 100 as a DRAM semiconductor memory as an example for exemplary description.
[0054] In some examples, such as Figure 1 As shown, the memory device 100 includes a memory cell array 110 and a peripheral circuit 120 coupled to the memory cell array 110 .
[0055] The memory cell array 110 includes a plurality of memory cells 111 arranged in an array. For example, the memory cells are DRAM memory cells.
[0056] Furthermore, the peripheral circuit 120 may include various types of circuit structures formed using metal-oxide-semiconductor (MOS) transistors and configured to transmit electrical signals to the memory cell array. Figure 2 As shown, the peripheral circuit 120 may include a row decoder, a sense amplifier, a column decoder, and a data input / output buffer. The row decoder is coupled to the word line WL. The column decoder is coupled to the bit line BL. The storage unit 111 can store charge and realize data reading and writing under the drive of the word line and the bit line. For example, the sense amplifier may include a multi-stage amplification circuit, such as Figure 3 The sensitive amplifier circuit 123, the local amplifier circuit 122 and the global amplifier circuit 121 are shown.
[0057] In some examples, such as Figure 3As shown, the peripheral circuit 120 includes a global data line GDL and a complementary global data line GDLn, and a global amplifier circuit 121 and a local amplifier circuit 122 coupled through the global data line GDL and the complementary global data line GDLn.
[0058] The global amplifier circuit 121 is configured to maintain the target signal of the target storage unit on the global data line GDL and the complementary global data line GDLn for a preset time in response to the first global control signal Msa_en being in the off state and the first local control signal Lsa_en being in the off state, and output the target signal (for example, outputting the target signal) in response to the first global control signal Msa_en being in the enabled state when the difference between the voltage on the global data line GDL and the voltage on the complementary global data line GDLn satisfies the preset value. Figure 4 signal in giomsa).
[0059] The target storage unit is a storage unit close to the global amplifier circuit 121 along the transmission direction of the signal on the global data line GDL and the complementary global data line GDLn. The preset value is related to the length of the global data line GDL and the complementary global data line GDLn, and the preset time.
[0060] The above-mentioned memory device 100 maintains the target signal of the target storage unit on the global data line GDL and the complementary global data line GDLn for a preset period of time, and then reads out the target signal stored in the target storage unit. In this way, by maintaining the charge for a preset period of time, the charge conservation on the global data line GDL and the charge conservation on the complementary global data line GDLn are realized. Based on this process, the global amplifier circuit 121 is driven to perform signal amplification processing, which can reduce the energy consumption of the global amplifier circuit 121, reduce the output delay of the target signal, and improve the accuracy of the target signal.
[0061] In some examples, such as Figure 3 As shown, the peripheral circuit 120 includes: a sensitive amplifier circuit 123 , a local amplifier circuit 122 and a global amplifier circuit 121 .
[0062] A memory cell 111 is coupled to a sensitive amplifier circuit 123. The sensitive amplifier circuit 123 is configured to read a target signal stored in a target memory cell through a Byte Line (BL), and output the target signal after determining a reference voltage through a complementary bit line BLn.
[0063] The local amplifier circuit 122 is coupled to the bit line BL through the local data line LDL and to the complementary bit line BLn through the complementary local data line LDLn, and is configured to process the target signal and then output it.
[0064] It can be understood that “the local data line LDL is coupled to the bit line BL” means that the local amplifier circuit 122 is coupled to the sensitive amplifier circuit 123 through the local data line LDL to receive the signal transmitted on the bit line BL. And, “the complementary local data line LDLn is coupled to the complementary bit line BLn” means that the local amplifier circuit 122 is coupled to the sensitive amplifier circuit 123 through the complementary local data line LDLn to receive the signal transmitted on the complementary bit line BLn. It is not limited to the local data line LDL being directly electrically connected to the bit line BL, and the complementary local data line LDLn being directly electrically connected to the complementary bit line BLn.
[0065] The global amplifier circuit 121 is coupled to the local data line LDL through the global data line GDL and to the complementary local data line LDLn through the complementary global data line GDLn, and is configured to output a target signal after equalizing the potentials of the signals on the global data line GDL and the complementary global data line GDLn for a preset time length T.
[0066] It can be understood that “the global data line GDL is coupled to the local data line LDL” means that the global amplifier circuit 121 is coupled to the local amplifier circuit 122 through the global data line GDL, and receives the signal transmitted on the local data line LDL. And “the complementary global data line GDLn is coupled to the complementary local data line LDLn” means that the global amplifier circuit 121 is coupled to the local amplifier circuit 122 through the complementary global data line GDLn, and receives the signal transmitted on the complementary local data line LDLn. It is not limited to the global data line GDL and the local data line LDL being directly electrically connected, and the complementary global data line GDLn and the complementary local data line LDLn being directly electrically connected.
[0067] In some examples, such as Figure 4 and Figure 5 As shown, the global amplifier circuit 121 includes: a first control transistor M1 , a second control transistor M3 , and an amplifier circuit 1211 .
[0068] The first control transistor M1 is coupled to the global data line GDL and the local data line LDL, and is configured to receive the first signal giomsa transmitted by the local data line LDL in response to the second global control signal Gpass being in an enabled state.
[0069] The global amplifier circuit 121 is configured to equalize the potential of the first signal on the complementary global data line GDLn in response to the second global control signal Gpass being enabled, the first global control signal Msa_en being disabled, and the first local control signal Lsa_en being disabled.
[0070] The second control transistor M3 is coupled to the complementary global data line GDLn and the complementary local data line LDLn, and is configured to receive the second signal giomsa_n transmitted by the complementary local data line LDLn in response to the second global control signal Gpass being in an enabled state.
[0071] The global amplifier circuit 121 is configured to equalize the potential of the second signal giomsa_n on the complementary global data line LDLn in response to the second global control signal Gpass being enabled, the first global control signal Msa_en being disabled, and the first local control signal Lsa_en being disabled.
[0072] The amplifier circuit 1211 is coupled to the first control transistor M1 and the second control transistor M3 , and is configured to amplify and output the equalized first signal giomsa and the second signal giomsa_n in response to the first global control signal Msa_en being in an enabled state.
[0073] For example, Figure 5 As shown, the amplifier circuit 1211 includes a transistor M3, a transistor M4, a transistor M5, a transistor M6 and a transistor M7.
[0074] Continue reading Figure 4 and Figure 5 The global amplifier circuit 121 further includes a precharge circuit 1212. The precharge circuit 1212 is configured to equalize the potentials on the global data line GDL and the complementary global data line GDLn, which is beneficial to reducing the error of the subsequent global data line GDL receiving signal gio and the complementary global data line GDLn receiving signal gio_n.
[0075] For example, Figure 5 As shown, the precharge circuit 1212 includes a transistor M8, a transistor M9, and a transistor M10.
[0076] Based on the connection relationship between the global amplifier circuit 121 and the global data line GDL and the complementary global data line GDLn, combined with the following Figure 6 The local amplifier circuit 122 is shown to illustrate how the global data line GDL and the complementary global data line GDLn receive the signal transmitted by the local amplifier circuit 122 through the local data line LDL and the complementary local data line LDLn.
[0077] It should be noted that, in order to more clearly explain the transmission process of the target signal of the reading storage unit 111, as shown in FIG. Figure 3 to Figure 6As shown, the present application illustrates a circuit schematic diagram of a local amplifier circuit 122 and a global amplifier circuit 121, and does not limit the number and connection relationship of specific electronic components of the local amplifier circuit 122 and the global amplifier circuit 121, as long as the same function can be achieved.
[0078] For example, Figure 6 As shown, the local amplifier circuit 122 outputs the processed signal to the global data line GDL and the complementary global data line GDLn via the local data line LDL and the complementary local data line LDLn respectively under the control of the first local control signal Lsa_en.
[0079] In this way, the local amplifier circuit 122 and the global amplifier circuit 121 can respond to different control signals (for example, the first local control signal Lsa_en and the first global control signal Msa_en) to keep the charge on the global data line GDL and the complementary global data line GDLn for a preset period of time, thereby achieving the effect of charge sharing on the data line.
[0080] Among them, the data and connection relationship of the transistors included in the local amplifier circuit 122 are only examples to reflect that the local amplifier circuit 122 can realize the function of signal amplification. The examples provided in this application do not make specific restrictions on the data and connection relationship of the transistors, as long as the same function can be achieved.
[0081] In addition, the peripheral circuit 120 includes circuits with other structures to drive the storage unit 111 to perform read and write operations, and this application does not impose specific limitations on this.
[0082] Based on the above example, the peripheral circuit 120 of the memory device controls the memory cell array 110 to perform data read and write operations, such as Figure 7 and Figure 8 As shown, some embodiments of the present application provide a control method for a memory device, combined with Figure 8 The timing diagram of multiple signals shown is Figure 5 and Figure 6 The circuit schematic diagram shown is used as an example to illustrate how the signal transmission of the multi-stage amplifier circuit can achieve the purpose of reducing the data transmission reading time, reducing the energy consumption in the data reading process, and improving the reading performance of the memory device.
[0083] In some examples, such as Figure 1 As shown, the memory device 100 includes a plurality of memory cells 111 arranged in an array and a peripheral circuit 120 coupled to the plurality of memory cells 111. Figure 3 As shown, the peripheral circuit 120 includes a global data line GDL and a complementary global data line GDLn, and a global amplifier circuit 121 and a local amplifier circuit 122 coupled through the global data line GDL and the complementary global data line GDLn.
[0084] like Figure 7 As shown, the control method includes S100 and S200.
[0085] S100 : the global amplifier circuit 121 maintains the target signal of the target memory cell on the global data line GDL and the complementary global data line GDLn for a preset time period T in response to the first global control signal Mse_en being in the off state and the first local control signal Lse_en being in the off state.
[0086] For example, Figure 5 and Figure 8 As shown, the global amplifier circuit 121 receives the target signal of the target storage unit in response to the first global control signal Mse_en being in the enabled state and the first local control signal Lse_en being in the disabled state. Then, in response to the first global control signal Mse_en being in the disabled state and the first local control signal Lse_en being in the disabled state, the global amplifier circuit 121 keeps the target signal on the global data line GDL and the complementary global data line GDLn, and keeps it for a preset time, so that the charges on the global data line GDL and the complementary global data line GDLn are shared, and the potentials at both ends of the data lines are stable.
[0087] S200: When the voltage difference between the global data line GDL and the complementary global data line GDLn satisfies a preset value, in response to the first global control signal Mse_en being in an enabled state, a target signal (eg Figure 8 mid signal giomsa).
[0088] For example, based on the above-mentioned balanced charge on the global data line GDL and the complementary global data line GDLn, after determining that the difference in voltage between the global data line GDL and the complementary global data line GDLn meets the enabling condition of the global amplifier circuit output signal, the first global control signal Mse_en is driven to be in an enabled state, and the global amplifier circuit 121 is controlled to output the target signal (for example, signal gio).
[0089] In the above control method, in the process of reading the target signal stored in the target storage unit 111, before the global amplifier circuit 121 outputs the target signal and after the global amplifier circuit 121 receives the target signal transmitted by the local amplifier circuit 122, the potentials on the global data line GDL and the complementary global data line GDLn are balanced for a preset time length T, that is, the charge conservation of the data line itself is used to achieve the stability of the potentials at both ends of the data line, which is beneficial to improving the accuracy of the signal received by the global amplifier circuit 121. In addition, it can solve the problem that the global amplifier circuit 121 has high energy consumption and long time consumption for pre-charging the potential on the global data line GDL and the complementary global data line GDLn due to the long global data line GDL and the complementary global data line GDLn causing the transmission signal delay and the large potential difference at both ends of the data line, thereby achieving the purpose of reducing the reading time and energy consumption in the process of the memory device 100 reading data, and further, it can reduce the voltage difference of the output target signal and improve the accuracy of reading the target signal.
[0090] In some examples, such as Figure 5 and Figure 8 As shown, the global amplifier circuit 121 responds to the second global control signal Gpass being in an enabled state and the first global control signal Msa_en being in an off state, amplifies the voltage difference between the target signal transmitted by the global data line GDL and the reference signal transmitted by the complementary global data line GDLn to a full swing, and obtains a target voltage difference; and, based on the target voltage difference being greater than or equal to a preset value, outputs the target signal in response to the first global control signal Msa_en being in an enabled state.
[0091] The preset value is related to the lengths of the global data line GDL and the complementary global data line GDLn, and a preset duration, and is the minimum voltage difference for driving the global amplifier circuit 121 to output a target signal.
[0092] It is understandable that the longer the data line is, the different potentials represented by the charges transmitted on the data line at different positions are different, especially the potential difference between the two ends of the data line is large. When the minimum voltage difference (i.e., the target voltage difference) for driving the global discharge circuit to output the target signal is reached, the energy consumption of the global amplifier circuit 121 for reading data is minimized.
[0093] For example, when the target voltage difference is equal to the preset value, the target signal is output in response to the first global control signal Msa_en being in the enabled state, which is beneficial to reducing the energy consumption of reading data by the global amplifier circuit 121. In particular, based on the process of sharing the preset time length of the charges on the global data line GDL and the complementary global data line GDLn, the potential difference at both ends of the data line can be reduced, and the energy consumption of the global amplifier circuit 121 in the pre-charging stage is reduced, and the energy consumption of the global amplifier circuit 121 in reading data is further reduced.
[0094] In addition, considering the charge loss in the actual integrated circuit, the target voltage difference can be set to be greater than the preset value to ensure that the global amplifier circuit 121 can read the data of all memory cells 111 in the memory cell array 110. The difference between the specific target voltage difference and the preset value can be adjusted according to the actual circuit.
[0095] In some examples, the peripheral circuit 120 includes a local data line LDL and a complementary local data line LDLn, and a local amplifier circuit 122 coupled to the local data line LDL and the complementary local data line LDLn. The local amplifier circuit 122 is coupled to the plurality of memory cells 111 through the LDL and the complementary local data line LDLn.
[0096] The control method includes: the local amplification circuit 122 is in an enabled state in response to the first local control signal Lsa_en, and processes and transmits the signals on the local data line LDL and the complementary local data line LDLn to the global data line GDL and the complementary global data line GDLn.
[0097] For example, Figure 6 and Figure 8 As shown, the first local control signal Lsa_en is in an enabled state (for example, a high level), and the signal gio obtained after processing the signal lio on the local data line LDL is transmitted to the global data line GDL, and the signal gio_n obtained after processing the signal lio_n on the complementary local data line LDLn is transmitted to the complementary local data line GDLn.
[0098] In some examples, the peripheral circuit 120 further includes a sense amplifier circuit 123. The sense amplifier circuit 123 is coupled to the local amplifier circuit 122 through the local data line LDL and the complementary local data line LDLn, and is coupled to the memory cell 111 through the bit line BL and the complementary bit line BLn.
[0099] The control method includes: the sensitive amplifier circuit 123 responds to the enable signal, and transmits the data stored in the target storage unit 111 obtained on the bit line BL and the complementary bit line BLn to the local data line LDL and the complementary local data line LDLn after processing.
[0100] It is understandable that, considering that the signal transmission between the sensitive amplifier circuit 123 and the local amplifier circuit 122 is relatively fast, the present application does not impose any specific restrictions on the signal transmission process between the sensitive amplifier circuit 123 and the local amplifier circuit 122 .
[0101] However, without increasing the total time for reading data from the target storage unit 111, the signal transmission process between the local amplifier circuit 122 and the global amplifier circuit 121 provided in the above example can be referred to for driving, which will not be repeated here.
[0102] In some examples, the plurality of memory cells 111 include a first memory cell 111 a and a second memory cell 111 b coupled to one bit line BL.
[0103] During the read operation, the first storage unit 111a is a storage unit 111 close to the global amplifier circuit 121 along the signal transmission direction of the global data line GDL and the complementary global data line GDLn (e.g., a storage unit coupled to the far end of the data line). The second storage unit 111b is a storage unit 111 far from the global amplifier circuit 121 along the signal transmission direction of the global data line GDL and the complementary global data line GDLn (e.g., a storage unit coupled to the near end of the data line).
[0104] The control method includes: determining that the difference between the voltage of the first storage unit 111 a on the global data line GDL and the voltage on the complementary global data line GDLn is a first voltage difference V1.
[0105] The difference between the voltage of the second storage unit 111b on the global data line GDL and the voltage on the complementary global data line GDLn is determined to be a second voltage difference V2; the first voltage difference V1 and the second voltage difference V2 are approaching each other.
[0106] For example, the data stored in different storage cells 111 on the same bit line BL can be read separately. Based on the setting of the row address and the column address of the storage cell array 110, different storage cells 111 coupled to a bit line BL can be selected. For example, during the reading operation, the first storage cell 111a is a storage cell 111 close to the global amplifier circuit 121 along the signal transmission direction of the global data line GDL and the complementary global data line GDLn (for example, a storage cell coupled to the far end of the data line). The second storage cell 111b is a storage cell 111 far from the global amplifier circuit 121 along the signal transmission direction of the global data line GDL and the complementary global data line GDLn (for example, a storage cell coupled to the near end of the data line).
[0107] In the process of reading the data stored in the first storage unit 111a, the voltage of the signal transmitted from the first storage unit 111a to the global amplifier circuit 121 is Va1. Case 1: If the charges on the global data line GDL and the complementary global data line GDLn are not balanced for a preset time, the voltage of the signal actually amplified by the global amplifier circuit 121 is Va2 ( Figure 8 Case 2: If the charges on the global data line GDL and the complementary global data line GDLn are balanced for a preset time period T (see Figure 8 In the stage P3 of the signal gio / gio_n (far), the voltage of the signal actually amplified by the global amplifier circuit 121 is Va3 (see Figure 8In the above, the charge loss and charge transfer delay on the data line are taken into consideration. After receiving the same duration of the signal transmitted by the global data line GDL and the complementary global data line GDLn, for these two cases, in the stage P4, the voltage Va2 of the signal amplified and output by the global amplifier circuit 121 is less than Va3. Then, the voltage difference between Va1 and Va2 (in the first case) is greater than the voltage difference between Va1 and Va3 (i.e., the first voltage difference V1) (in the second case). After the equalization preset duration T, the voltage difference required for driving the global amplifier circuit 121 to output the target signal is reduced.
[0108] Similarly, in the process of reading the data stored in the second storage unit 111b, the voltage of the signal transmitted from the second storage unit 111b to the global amplifier circuit 121 is Vb1. Case 1: If the charges on the global data line GDL and the complementary global data line GDLn are not balanced for a preset time, the voltage of the signal actually amplified by the global amplifier circuit 121 is Vb2 ( Figure 8 Case 2: If the charges on the global data line GDL and the complementary global data line GDLn are balanced for a preset time period T (see Figure 8 In the phase P3 of the middle signal gio / gio_n(near), the voltage of the signal actually amplified by the global amplifier circuit 121 is Vb3 (see Figure 8 In these two cases, considering the charge loss and charge transfer delay on the data line, after receiving the same length of time of the signal transmitted by the global data line GDL and the complementary global data line GDLn, in the stage P4, the voltage Vb2 of the signal amplified and output by the global amplifier circuit 121 is greater than Vb3, then the voltage difference between Vb1 and Vb2 (in the first case) is less than the voltage difference between Vb1 and Vb3 (i.e., the second voltage difference V2) (in the second case), and after the equalization preset time length T, the voltage difference required for driving the global amplifier circuit 121 to output the target signal increases.
[0109] In this way, referring to the relationship between the voltage difference between Va1 and Va2 and the voltage difference between Vb1 and Vb2 in case one, and comparing the voltage difference between Va1 and Va3 and the voltage difference between Vb1 and Vb3 in case two of the example of the present application, it can be seen that the first voltage difference V1 and the second voltage difference V2 are approaching each other.
[0110] That is to say, in order to meet the reading conditions of all memory cells 111 in the memory cell array 110, the minimum voltage difference between the transmission signals of the global data line GDL and the complementary global data line GDLn is determined to be a preset value, that is, the preset value can be the voltage difference between the transmission signals gio and gio_n of the global data line GDL and the complementary global data line GDLn coupled to the second memory cell 111b.
[0111] In the related art (i.e., case 1), the voltage difference between the transmission signals gio and gio_n of the global data line GDL and the complementary global data line GDLn coupled to the first storage unit 111a is larger than the voltage difference between the transmission signals gio and gio_n of the global data line GDL and the complementary global data line GDLn coupled to the second storage unit 111b. Under the premise of driving the global amplifier circuit 121 to output the target signal (i.e., based on the voltage difference on the data line coupled to the second storage unit 111b), in the pre-charging stage (e.g., stage P1), the energy consumption required to pull the potential of the transmission signals gio and gio_n of the data line GDL and the complementary global data line GDLn coupled to the first storage unit 111a (or the storage unit other than the second storage unit 111b) to VDD is larger.
[0112] The example provided in the present application is mainly for the case 2, in which the first voltage difference V1 of the global data line GDL and the complementary global data line GDLn transmission signals gio and gio_n coupled to the first storage unit 111a is close to the second voltage difference V2 of the global data line GDL and the complementary global data line GDLn transmission signals gio and gio_n coupled to the second storage unit 111b. In this way, under the premise of satisfying the drive of the global amplifier circuit 121 to output the target signal (i.e. based on the voltage difference on the data line coupled to the second storage unit 111b), in the pre-charging stage (e.g., stage P1), the energy consumption required to pull the potential of the data line GDL and the complementary global data line GDLn transmission signals gio and gio_n coupled to the first storage unit 111a (or the storage unit other than the second storage unit 111b) to VDD is significantly reduced compared with the related art. Moreover, since the first voltage difference V1 and the second voltage difference V2 are close to each other, it is also beneficial to reduce the duration of the common signal driving during the reading operation and improve the reading speed of the memory device.
[0113] In some examples, the control method further includes: the global amplification circuit 121 pre-charges the global data line GDL and the complementary global data line GDLn in response to the third global control signal Msa_eq being in an enabled state.
[0114] For example, Figure 5 and Figure 8As shown, the global amplifier circuit 121 precharges the global data line GDL and the complementary global data line GDLn to the voltage VDD in response to the third global control signal Msa_eq being in an enabled state (e.g., low level). In this way, in the next read cycle, the problem of an error in the potential of the target signal due to the initial potential difference between the global data line GDL and the complementary global data line GDLn during the process of transmitting the target signal (e.g., signal giomsa) from the local data line LDL to the global data line GDL can be avoided, thereby improving the accuracy of the signal received by the global amplifier circuit 121 and the accuracy of the output signal (i.e., the accuracy of reading the storage unit data).
[0115] In some examples, the control method further includes: the local amplification circuit 122 pre-charges the local data line LDL and the complementary local data line LDLn in response to the second local control signal Lsa_eq being in an enabled state.
[0116] For example, Figure 6 and Figure 8 As shown, the local amplifier circuit 122 precharges the local data line LDL and the complementary local data line LDLn to the voltage VDD in response to the second local control signal Lsa_eq being in an enabled state (e.g., high level). In this way, in the next read cycle, the problem of an error in the potential of the target signal due to the initial potential difference between the local data line LDL and the complementary local data line LDLn during the process of the bit line BL transmitting the target signal to the local data line LDL can be avoided, thereby improving the accuracy of the signal received by the local amplifier circuit 122 and the accuracy of the output signal.
[0117] In some embodiments, Fig. 9 As shown, the embodiment of the present application shows a memory system 200. The memory system 200 includes a memory controller (Memory Controller) 210 and one or more memory devices 100, and other integrated circuit structures for signal transmission. The memory controller 210 is configured to control the memory device 100.
[0118] For example, the memory controller 210 and one or more memory devices 100 may be integrated and packaged in the same storage device, which is conducive to applying the memory system 200 to different types of terminal electronic products.
[0119] In some embodiments, Fig.10As shown, the embodiment of the present application shows an electronic device 300. For example, the electronic device 300 may include but is not limited to a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device 100 therein.
[0120] In some examples, such as Fig.10 As shown, the electronic device 300 may include a host 310 and a memory system 200. The host 310 may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device. The host 310 may be configured to send data to the memory system 200 or receive data from the memory system 200.
[0121] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.
Claims
1. A method for controlling a memory device, characterized in that: The memory device includes a plurality of memory cells arranged in an array and a peripheral circuit coupled to the plurality of memory cells; the peripheral circuit includes a global data line and a complementary global data line, and a global amplifier circuit and a local amplifier circuit coupled through the global data line and the complementary global data line; the control method includes: The global amplifier circuit maintains the target signal of the target storage unit on the global data line and the complementary global data line for a preset period of time in response to the first global control signal being in the off state and the first local control signal being in the off state, and outputs the target signal in response to the first global control signal being in the enabled state when the difference between the voltage on the global data line and the voltage on the complementary global data line meets the preset value.
2. The control method according to claim 1, characterized in that: The global amplifier circuit amplifies the voltage difference between the target signal transmitted by the global data line and the reference signal transmitted by the complementary global data line to a full swing to obtain a target voltage difference in response to the second global control signal being in an enabled state and the first global control signal being in an off state; and outputs the target signal in response to the first global control signal being in an enabled state based on the target voltage difference being greater than or equal to the preset value; The preset value is related to the length of the global data line and the complementary global data line, and the preset time length, and is a minimum voltage difference for driving the global amplifier circuit to output the target signal.
3. The control method according to claim 1, characterized in that: The peripheral circuit includes a local data line and a complementary local data line, and a local amplifier circuit coupled to the local data line and the complementary local data line; the local amplifier circuit is coupled to a plurality of the storage units through the local data line and the complementary local data line; The control method comprises: In response to the first local control signal being in an enabled state, the local amplification circuit processes the signals on the local data line and the complementary local data line and transmits the processed signals to the global data line and the complementary global data line.
4. The control method according to claim 1, characterized in that: The peripheral circuit further comprises a sensitive amplifier circuit; the sensitive amplifier circuit is coupled to the local amplifier circuit through the local data line and the complementary local data line, and is coupled to the storage unit through a bit line and a complementary bit line; The control method comprises: The sensitive amplifier circuit responds to the enable signal to process the data stored in the storage unit obtained from the bit line and the complementary bit line and transmit it to the local data line and the complementary local data line.
5. The control method according to claim 1, characterized in that: The plurality of storage cells include a first storage cell and a second storage cell coupled to a bit line; during a read operation, the first storage cell is a storage cell close to the global amplifier circuit along the signal transmission direction of the global data line and the complementary global data line; the second storage cell is a storage cell far from the global amplifier circuit along the signal transmission direction of the global data line and the complementary global data line; The control method comprises: Determine that a difference between a voltage of the first storage unit on the global data line and a voltage on the complementary global data line is a first voltage difference; Determine that the difference between the voltage of the second storage unit on the global data line and the voltage on the complementary global data line is a second voltage difference; The first pressure difference and the second pressure difference are approaching each other.
6. The control method according to claim 1, characterized in that: The control method further includes: the global amplification circuit pre-charging the global data line and the complementary global data line in response to a third global control signal being in an enabled state.
7. The control method according to claim 1, characterized in that: The control method further includes: the local amplification circuit pre-charging the local data line and the complementary local data line in response to the second local control signal being in an enabled state.
8. A memory device, characterized in that: include: A memory cell array, comprising a plurality of memory cells; A peripheral circuit includes a global data line and a complementary global data line, and a global amplifier circuit and a local amplifier circuit coupled through the global data line and the complementary global data line; the global amplifier circuit is configured to maintain a target signal of a target storage unit on the global data line and the complementary global data line for a preset time in response to a first global control signal being in an off state and a first local control signal being in an off state, and output the target signal in response to the first global control signal being in an enabled state when the difference between the voltage on the global data line and the voltage on the complementary global data line meets a preset value; the target storage unit is a storage unit close to the global amplifier circuit along the transmission direction of the signal on the global data line and the complementary global data line; the preset value is related to the length of the global data line and the complementary global data line, and the preset time.
9. The memory device according to claim 8, wherein: The global amplification circuit comprises: a first control transistor coupled to the global data line and the local data line, and configured to receive a first signal transmitted by the local data line in response to a second global control signal being in an enabled state; the global amplifier circuit is configured to equalize a potential of the first signal on the complementary global data line in response to the second global control signal being in an enabled state, the first global control signal being in an off state, and the first local control signal being in an off state; The second control transistor is coupled to the complementary global data line and the complementary local data line, and is configured to receive a second signal transmitted by the complementary local data line in response to the second global control signal being in an enabled state; the global amplifier circuit is configured to equalize the potential of the second signal on the complementary global data line in response to the second global control signal being in an enabled state, the first global control signal being in an off state, and the first local control signal being in an off state. The amplifier circuit is coupled to the first control transistor and the second control transistor, and is configured to amplify and output the first signal and the second signal after equalization processing in response to the first global control signal being in an enabled state.
10. The memory device according to claim 8, wherein: The peripheral circuit comprises: Sensitive amplifier circuit; one of the storage units is coupled to one of the sensitive amplifier circuits, and the sensitive amplifier circuit is configured to read the target signal stored in the target storage unit through the bit line, and output it respectively after determining the reference voltage through the complementary bit line; The local amplifier circuit is coupled to the bit line through the local data line and coupled to the complementary bit line through the complementary local data line, and is configured to process the target signal and then output it; The global amplifier circuit is coupled to the local data line through the global data line and to the complementary local data line through the complementary global data line, and is configured to output the target signal after equalizing the potentials of the signals on the global data line and the complementary global data line for a preset time.