Semiconductor device with nanosheet transistor and

Abstract

The invention discloses a semiconductor device with a nanosheet transistor and a manufacturing method thereof. The method includes forming a sacrificial layer between a first stacked layer and a second stacked layer, the first stacked layer including first semiconductor layers and second semiconductor layers alternately stacked, the second stacked layer including third semiconductor layers and fourth semiconductor layers alternately stacked, and the sacrificial layer including a semiconductor metal oxide; forming a sacrificial gate structure over a portion of the second stack layer; removing parts of the first stack layer and the second stack layer which are not covered by the sacrificial gate structure; removing the sacrificial layer to form a cavity; filling the cavity with a dielectric to form an isolation layer; and forming a first source / drain feature and a second source / drain feature on opposite sides of the sacrificial gate structure, where the first source / drain feature is disposed lower than the second source / drain feature, the first source / drain feature and the second source / drain feature being in contact with the isolation layer, the first semiconductor layer, and the third semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices having nanosheet transistors and methods of manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. This shrinking presents new challenges.

[0003] In pursuit of higher device density, higher performance and lower cost, challenges from both manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field effect transistors (FETs), including nanosheet FETs. In nanosheet FETs, all sides of the channel are surrounded by gate electrodes, which allows for more complete depletion in the channel and produces shorter short channel effects and better gate control. As transistor size continues to shrink, further improvements in nanosheet FETs are needed. Summary of the invention

[0004] According to a first aspect of the present disclosure, a method for forming a semiconductor device structure is provided, comprising: forming a sacrificial layer between a first stacked layer and a second stacked layer arranged above the first stacked layer, wherein the first stacked layer includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, and the second stacked layer includes a plurality of third semiconductor layers and a plurality of fourth semiconductor layers stacked alternately, and wherein the sacrificial layer includes a semiconductor metal oxide; forming a sacrificial gate structure above a portion of the second stacked layer; removing portions of the first stacked layer and the second stacked layer not covered by the sacrificial gate structure; removing the sacrificial layer to form a cavity; filling the cavity with a dielectric material to form an isolation layer; and forming a first source / drain feature and a second source / drain feature on opposite sides of the sacrificial gate structure, wherein the first source / drain feature is arranged lower than the second source / drain feature, and the first source / drain feature and the second source / drain feature are in contact with the isolation layer, the first semiconductor layer and the third semiconductor layer.

[0005] According to a second aspect of the present disclosure, a method for forming a semiconductor device structure is provided, comprising: forming a plurality of fin structures from a substrate, each fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; forming a sacrificial layer between two adjacent first semiconductor layers, wherein the sacrificial layer comprises a semiconductor metal oxide; diffusing a metal element from the sacrificial layer into the first semiconductor layer disposed adjacent to the sacrificial layer; and replacing the sacrificial layer with a dielectric material to form an isolation layer.

[0006] According to a third aspect of the present disclosure, a semiconductor device structure is provided, including: a first transistor, including a plurality of first semiconductor layers stacked vertically, each first semiconductor layer being surrounded by a first gate electrode layer; a second transistor, arranged above the first transistor, the second transistor including a plurality of second semiconductor layers stacked vertically, and each second semiconductor layer being surrounded by a second gate electrode layer different from the first gate electrode layer; an isolation layer, arranged between the topmost first semiconductor layer of the first transistor and the bottommost second semiconductor layer of the second transistor; a first source / drain feature, contacting a portion of the isolation layer and the first semiconductor layer; and a second source / drain feature, arranged above the first source / drain feature, and contacting a portion of the isolation layer and the second semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1-Figure 12 is a perspective view of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0009] Figure 13A-Figure 25A and Figure 31A-Figure 32A According to some embodiments, Fig.12 The cross-sectional side views of various stages of manufacturing a semiconductor device structure are taken at cross section AA.

[0010] Figure 13B-Figure 25B and Figure 31B-Figure 32B According to some embodiments, Fig.12 Cross-sectional side views of various stages of manufacturing a semiconductor device structure taken from cross section BB.

[0011] Figure 13C - Figure 25C and Figure 31C-Figure 32C According to some embodiments, Fig.12 Cross-sectional side views of various stages of manufacturing a semiconductor device structure taken through cross section CC.

[0012] Fig.13D An enlarged view of a portion of a semiconductor layer stack is shown in accordance with some embodiments.

[0013] Figure 14A-1 An enlarged view of a portion of a semiconductor device structure showing an outline of a cavity is illustrated in accordance with some embodiments.

[0014] Figure 26-Figure 30 is a diagram showing various stages of manufacturing a semiconductor device structure according to some embodiments Fig.25B Magnified view of the area in .

[0015] Fig.31D is an enlarged view showing a portion of a semiconductor device structure of a first nanosheet transistor and a second nanosheet transistor.

[0016] Figure 31D-1 yes Fig.31D An enlarged view of a region of a semiconductor device structure is shown.

[0017] Figure 31D-2 is based on Figure 14A-1 The embodiment shown Fig.31D An enlarged view of a region of a semiconductor device structure is shown. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various embodiments. This repetition is for simplicity and clarity and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0020] Although the embodiments of the present disclosure are discussed with respect to nanosheet channel FETs, implementations of some aspects of the present disclosure may be used for other processes and / or other devices, such as planar FETs, fin FETs, horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices. It will be readily understood by those skilled in the art that other modifications may be considered within the scope of the present disclosure. In the case of a gate all around (GAA) transistor structure, the GAA transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes (including a double patterning process or a multi-patterning process). Generally, a double patterning process or a multi-patterning process combines a photolithography process with a self-alignment process, allowing the following patterns to be produced: the spacing of these patterns is less than the spacing that can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A spacer is formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and next, the remaining spacers may be used to pattern the GAA structure.

[0021] Figure 1-32C FIG. 1 shows an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that Figure 1-32C Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for other embodiments of the method. The order of the operations / processes is not limited and may be interchanged.

[0022] Figure 1-Figure 12 1 is a perspective view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1 As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium arsenide (GaAs), gallium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), gallium arsenide (InAlAs), gallium arsenide (InGaAs), gallium phosphide (GaSbP), gallium arsenide (GaAsSb) and indium phosphide (InP). In one embodiment, the substrate 101 is made of silicon. In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one aspect, the insulating layer is an oxygen-containing layer.

[0023] The substrate 101 may include one or more buffer layers (not shown) on the surface of the substrate 101. The buffer layer may gradually change the lattice constant from the lattice constant of the substrate to the lattice constant of the source / drain (S / D) region to be grown on the substrate 101. The buffer layer may be formed of an epitaxially grown single crystalline semiconductor material, such as but not limited to Si, Ge, germanium tin (GeSn), SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In one embodiment, the substrate 101 includes a SiGe buffer layer epitaxially grown on the silicon substrate 101. The germanium concentration of the SiGe buffer layer may increase from 30 atomic percent germanium in the bottommost buffer layer to 70 atomic percent germanium in the topmost buffer layer.

[0024] The substrate 101 may include various regions doped with impurities (eg, dopants having p-type or n-type conductivity) Depending on the circuit design, these dopants may be boron for n-type FETs (NFETs) and phosphorus for p-type FETs (PFETs).

[0025] The semiconductor layer stack 104 includes semiconductor layers made of different materials to form a nanosheet channel in a multi-gate device (e.g., a nanosheet channel FET). In some embodiments, the semiconductor layer stack 104 includes first semiconductor layers 106a and 106b (collectively referred to as 106) and second semiconductor layers 108a and 108b (collectively referred to as 108). In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 can be made of Si, and the second semiconductor layer 108 can be made of SiGe. In some embodiments, the first semiconductor layer 106 can be made of SiGe, and the second semiconductor layer 108 can be made of Si. Alternatively, in some embodiments, any of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0026] The first semiconductor layer 106 or a portion thereof may form (one or more) nanosheet channels of the semiconductor device structure 100 in a later manufacturing stage. The term "nanosheet" as used herein refers to any material portion having nanometer-scale or even micrometer-scale dimensions, and regardless of the cross-sectional shape of the portion, it is elongated. Therefore, the term refers to both elongated material portions with circular and substantially circular cross-sections, and also to beam-shaped or bar-shaped material portions, for example, including cylindrical or substantially rectangular cross-sections. (One or more) nanosheet channels of the semiconductor device structure 100 may be surrounded by a gate. The semiconductor device structure 100 may include a nanosheet transistor. The nanosheet transistor may be referred to as a nanowire transistor, a gate all around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 will be further discussed below.

[0027] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be achieved by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0028] In some embodiments, the semiconductor device structure 100 includes a complementary FET (CFET), in which two or more nanosheet FETs are stacked vertically on top of each other. In this case, the first semiconductor layer 106 may include a channel for the two or more nanosheet FETs. For example, Figure 1 In the illustrated embodiment, the first semiconductor layer 106a can define a channel for a first FET (e.g., an n-type FET (N-FET)), and the first semiconductor layer 106b can define a channel for a second FET (e.g., a p-type FET (P-FET)). The thickness of the first semiconductor layer 106 is selected based on device performance considerations. In some embodiments, the thickness of each first semiconductor layer 106 ranges from about 3 nanometers (nm) to about 10 nm. The second semiconductor layer 108 can eventually be removed and used to define a space in which a gate stack is to be formed. Likewise, depending on device performance considerations, the thickness of each second semiconductor layer 108 can be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In one aspect, the thickness of each second semiconductor layer 108 (e.g., 108a and 108b) is equal to the thickness of the first semiconductor layer 106 (e.g., 106a and 106b).

[0029] In various embodiments, a sacrificial layer 109 is formed between the first semiconductor layer 106a of the first FET (e.g., n-channel FET) and the first semiconductor layer 106b of the second FET (e.g., p-channel FET). The sacrificial layer 109 will be replaced with a dielectric material at a later stage and form an isolation layer for isolation purposes. The material of the sacrificial layer 109 is selected so that it can be grown on silicon (or the material used for the immediately adjacent layer (e.g., the first semiconductor layer 106b)) and has minimal or no lattice mismatch between the sacrificial layer 109 and the adjacent layers (e.g., the first semiconductor layers 106a and / or 106b). As a result, dislocation issues that may occur due to lattice mismatch between the sacrificial layer 109 and the adjacent layers are alleviated. The material of the sacrificial layer 109 should also have a high etch selectivity relative to silicon (or the material used for the adjacent layers) so that it can be easily removed at a later stage without significantly affecting the adjacent layers.

[0030] In some embodiments, the sacrificial layer 109 is made of a semiconductor metal oxide, for example, an alkaline earth titanate. Suitable materials may include, but are not limited to, strontium titanate (SrTiO3), barium titanate (BaTiO3), barium strontium titanate (BaSrTiO3), lanthanum titanate (LaTiO3), etc. The semiconductor metal oxide may be grown on the first semiconductor layer 106 by any suitable deposition process. In some embodiments, the semiconductor metal oxide is grown on the first semiconductor layer 106 (e.g., the first semiconductor layer 106b) by molecular beam epitaxy (MBE). In embodiments where SrTiO3 is required, a first metal solid source containing Sr (e.g., elemental Sr) and a second metal solid source containing Ti (e.g., elemental titanium, or titanium tetraisopropoxide [Ti(OC3H7)4 or TTIP]) may be supplied to an MBE chamber, in which the first metal source and the second metal solid source are heated and evaporated onto the first semiconductor layer 106 (e.g., the first semiconductor layer 106b). Oxygen may be supplied to the MBE chamber during growth. The sacrificial layer 109 may be formed at about 10 -10 The sacrificial layer 109 is grown on the first semiconductor layer 106b at a temperature range of about 400 degrees Celsius to about 800 degrees Celsius (e.g., about 500 degrees Celsius to about 700 degrees Celsius) under a chamber pressure of 100 to 400 °C (i.e., ultra-high vacuum). If the temperature is higher than about 800 degrees Celsius, the deposited film may relax too quickly. On the other hand, if the temperature is lower than about 400 degrees Celsius, the quality of the deposited film may be compromised (e.g., polycrystalline or even amorphous). A sacrificial layer 109 deposited outside the above temperature range may produce an amorphous film. The growth rate may be in the range of about 1 nm / minute to about 3 nm / minute.

[0031] In some embodiments, the semiconductor metal oxide can be grown on the first semiconductor layer 106 (e.g., the first semiconductor layer 106b) by metal organic chemical vapor deposition (MOCVD). In embodiments where SrTiO3 is required, a first metal organic compound precursor containing Ti (e.g., titanium tetraisopropoxide (TPT)) and a second metal organic compound precursor containing Sr (e.g., Sr (hfa) 2 tetraethylene glycol dimethyl ether, hfa = hexafluoroacetylacetone) can be supplied to the corresponding reactor source area of ​​the MOCVD reactor and heated. Each of the first metal organic compound precursor and the second metal organic compound precursor is transported to the reaction zone using a carrier gas (e.g., argon). Oxygen bubbled through deionized water can be used as a reactant gas. The total pressure of the MOCVD reactor can be in the range of about 1 torr to about 20 torr (e.g., about 4 torr), and the growth temperature of the MOCVD reactor can be in the range of about 700 degrees Celsius to about 900 degrees Celsius (e.g., about 800 degrees Celsius). The total reactor pressure and the oxygen partial pressure can be controlled by a set flow rate. The total flow rate of the metal organic compound precursor may be about 100 sccm to about 150 sccm, and the flow rate of oxygen may be about 40 sccm to about 60 sccm. The growth rate may be in the range of about 4 nm / min to about 12 nm / min.

[0032] In some embodiments, the semiconductor metal oxide can be grown on the first semiconductor layer 106 (e.g., the first semiconductor layer 106b) by atomic layer deposition (ALD) (e.g., a plasma-assisted ALD process). In embodiments where SrTiO3 is desired, the first semiconductor layer (e.g., the first semiconductor layer 106b) can be exposed to a deposition cycle comprising pulses of: a first metal precursor containing Sr (e.g., strontium bis(triisopropylcyclopentadienyl) (Sr(C5 i Pr3H2)2), a second metal precursor containing Ti (e.g., titanium tetraisopropoxide (Ti(O i Pr)4), and the use of water vapor as an oxidant in the ALD chamber. The pulse sequence can be repeated as (Sr(C5 i Pr3H2)2)-H2O-(Ti(O i Pr)4)-H2O and can be carried out at a temperature of about 225 degrees Celsius to about 325 degrees Celsius. A purge gas using an inert gas and vacuum pumping can be applied between reactant exposures. The deposition rate can be about 1000 μm per cycle. Up to about each cycle within the range.

[0033] In any case, the sacrificial layer 109 may have a thickness greater than that of the first semiconductor layer or the second semiconductor layer to enhance the isolation between the first FET and the second FET at a later stage. The thickness of the sacrificial layer 109 may be about 1.5 to about 3 times thicker than the first semiconductor layer 106 (e.g., 106a and 106b) or the second semiconductor layer 108 (e.g., 108a and 108b). In some embodiments, the thickness of the sacrificial layer 109 is about 3nm to about 50nm. If the deposited thickness is less than about 3nm, it may be difficult to grow a large amount of sacrificial layer 109 in a later process, and the isolation effect may be reduced. On the other hand, if the deposited thickness is greater than about 50nm, the sacrificial layer 109 may relax.

[0034] Although the six first semiconductor layers 106 and the six second semiconductor layers 108 are Figure 1 An alternating arrangement is shown, but it is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104 , depending on a predetermined number of nanosheet channels required for each FET of the semiconductor device structure 100 .

[0035] Figure 2 is a perspective view of one of the various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 2 As shown, the fin structure 112 is formed from the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108, a well portion 116 formed from the substrate 101, and a portion of the mask structure 110. Before forming the fin structure 112, a mask structure 110 is formed on the semiconductor layer stack 104. The mask structure 110 may include an oxygen-containing layer 110a and a nitrogen-containing layer 110b. The oxygen-containing layer 110a may be a pad oxide layer, such as a silicon dioxide layer. The nitrogen-containing layer 110b may be a pad nitride layer, such as Si3N4. The mask structure 110 may be formed by any suitable deposition process, such as a chemical vapor deposition (CVD) process.

[0036] The fin structure 112 can be manufactured using a suitable process, including a double patterning process or a multi-patterning process. Generally, a double patterning process or a multi-patterning process combines a photolithography process with a self-alignment process, allowing the following patterns to be produced: the spacing of these patterns is smaller than the spacing that can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A spacer is formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and then the remaining spacers or mandrels can be used to pattern the fin structure 112 by etching the semiconductor layer stack 104 and the substrate 101. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. Although two fin structures 112 are shown, the number of fin structures is not limited to two.

[0037] In some embodiments, the fin structure 112 may be manufactured using a suitable process including a photolithography process and an etching process. The photolithography process may include forming a photoresist layer (not shown) over the mask structure 110, exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a patterned resist. In some embodiments, an electron beam (e-beam) photolithography process may be used to pattern the resist to form a patterned resist. The patterned resist may be used to protect areas of the substrate 101 and layers formed thereon, while the etching process passes through the mask structure 110, the semiconductor layer stack 104, and enters the substrate 101 to form a trench 114 in an unprotected area, thereby leaving an extended fin structure 112. The trench 114 may be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0038] exist Figure 3 In the embodiment of the present invention, a liner 115 is formed over the substrate 101 and the fin structure 112. The liner 115 may be formed of a semiconductor material, such as Si. In some embodiments, the liner 115 is made of the same material as the substrate 101. The liner 115 may be a conformal layer formed by any suitable process, such as an atomic layer deposition (ALD) process. The term "conformal" is used herein to simply describe a layer having substantially the same thickness over different regions.

[0039] exist Figure 4In the embodiment of the present invention, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-K dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0040] exist Figure 5 In the embodiment of the present invention, the insulating material 118 is recessed to form an isolation region 120. The recess of the insulating material 118 exposes a portion of the fin structure 112. The recess of the insulating material 118 exposes the trench 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108 (e.g., 108b) that contacts the well portion 116.

[0041] exist Figure 6 In the lining 115( Figure 5 ) is formed on the exposed surface of the liner 115. In some embodiments, during the formation of the cladding layer 117, the liner 115 can diffuse into the cladding layer 117, causing the cladding layer 117 to contact the semiconductor layer stack 104. The cladding layer 117 can be or include a semiconductor material, which allows the cladding layer 117 to grow on the semiconductor material without growing on the dielectric material. For example, the cladding layer 117 can be SiGe and grow on the Si of the liner 115 without growing on the dielectric material of the insulating material 118. In some embodiments, the cladding layer 117 can be formed by first forming a semiconductor layer on the liner 115 and the insulating material 118. Then an etching process is performed to remove the portion of the semiconductor layer formed on the insulating material 118. In some embodiments, the cladding layer 117 and the second semiconductor layer 108 include the same material with the same etching selectivity. For example, the cladding layer 117 and the second semiconductor layers 108a, 108b can be or include SiGe. The cladding layer 117 and the second semiconductor layers 108a, 108b may then be removed to create space for a gate electrode layer.

[0042] exist Figure 7In the embodiment of the present invention, a liner 119 is formed on the top surface of the cladding layer 117 and the insulating material 118. The liner 119 may include a low-k dielectric material (e.g., a material having a k value less than 7), such as SiO2, SiN, SiCN, SiOC, or SiOCN. The liner 119 may be formed by a conformal process, such as an ALD process. The liner 119 may serve as a shell to protect the trench 114 ( Figure 6 ) formed in a flowable oxide material.

[0043] In groove 114 ( Figure 6 ) and forming a dielectric material 121 on the liner 119, such as Figure 7 As shown. The dielectric material 121 may be an oxygen-containing material formed by FCVD, for example, an oxide. The K value of the oxygen-containing material may be less than about 7, for example, less than about 3. A planarization process (e.g., a CMP process) may be performed to remove the liner 119 and the portion of the dielectric material 121 formed on the fin structure 112. After the planarization process, a portion of the cladding layer 117 disposed on the nitrogen-containing layer is exposed.

[0044] exist Figure 8 In the embodiment of the present invention, the liner 119 and the dielectric material 121 are recessed to the level of the topmost second semiconductor layer 108a. For example, in some embodiments, after the recessing process, the dielectric material 121 may include a top surface 121a that is substantially flush with the top surface 108a-1 of the topmost second semiconductor layer 108a. The top surface 108a-1 of the topmost second semiconductor layer 108a may be in contact with the mask structure 110, for example, in contact with the oxygen-containing layer 110a. Similarly, the liner 119 may be recessed to the same level as the dielectric material 121. The recessing of the liner 119 and the dielectric material 121 may be performed by any suitable process, for example, dry etching, wet etching, or a combination thereof. The etching process may be a selective etching process that does not remove the semiconductor material of the cladding layer 117. As a result of the recessing process, a trench 123 is formed between the fin structures 112.

[0045] exist Fig. 9 In the embodiment, the dielectric material 125 is formed in the trench 123 ( Figure 8) and on the dielectric material 121 and the liner 119. The dielectric material 125 may include SiO, SiN, SiC, SiCN, SiON, SiOCN, AlO, AlN, AlON, ZrO, ZrN, ZrAlO, HfO, or other suitable dielectric materials. In some embodiments, the dielectric material 125 includes a high-k dielectric material (e.g., a material having a k value greater than 7). The dielectric material 125 may be formed by any suitable process, such as a CVD, PECVD, FCVD, or ALD process. A planarization process (e.g., a CMP process) is performed until the nitrogen-containing layer 110b of the mask structure 110 is exposed. The planarization process removes portions of the dielectric material 125 and the cladding layer 117 disposed above the mask structure 110. The liner 119, the dielectric material 121, and the dielectric material 125 may be collectively referred to as a dielectric feature 127. The dielectric features 127 serve as dielectric fins that separate adjacent source / drain (S / D) epitaxial features and an adjacent gate electrode layer.

[0046] exist Fig.10 In the embodiment of the present invention, the cladding layer 117 is recessed and the mask structure 110 is removed. The recessing of the cladding layer 117 can be performed by any suitable process, for example, dry etching, wet etching or a combination thereof. The recessing process can be controlled so that the remaining cladding layer 117 is at substantially the same level as the top surface 108a-1 of the topmost second semiconductor layer 108a in the semiconductor layer stack 104. The etching process can be a selective etching process that does not remove the dielectric material 125.

[0047] exist Fig.11 In the embodiment of the present invention, one or more sacrificial gate structures 130 are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, followed by a patterning process and an etching process.

[0048] By patterning the sacrificial gate structure 130, the semiconductor layer stack 104 of the fin structure 112 is partially exposed on the opposite side of the sacrificial gate structure 130. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100. The fin structure 112 partially exposed on the opposite side of the sacrificial gate structure 130 defines a source / drain (S / D) region of the semiconductor device structure 100. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be arranged along the X direction.

[0049] Next, a gate spacer 138 is formed on the sidewalls of the sacrificial gate structure 130. The gate spacer 138 can be formed by first depositing a conformal layer, which is then etched back to form the sidewall gate spacer 138. For example, a spacer material layer can be conformally disposed on the exposed surface of the semiconductor device structure 100. Subsequently, an anisotropic etching is performed on the spacer material layer using, for example, RIE. During the anisotropic etching process, most of the spacer material layer is removed from the horizontal surfaces (e.g., the top of the fin structure 112, the cladding layer 117, the dielectric material 125), leaving the gate spacer 138 on the vertical surfaces (e.g., the sidewalls of the sacrificial gate structure 130). The gate spacer 138 can be made of a dielectric material, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0050] exist Fig.12 In the embodiment, the exposed portion of the fin structure 112, the exposed portion of the cladding layer 117, and the exposed portion of the dielectric material 125 are selectively recessed by using one or more suitable etching processes. In some embodiments, the exposed portion of the semiconductor layer stack 104 of the fin structure 112 is removed to expose a portion of the well portion 116. Fig.12 As shown, the exposed portion of the fin structure 112 is recessed to or below the level of the top surface 118a of the insulating material 118. The recessing process may include an etching process that recesses the exposed portion of the fin structure 112 and the exposed portion of the cladding layer 117.

[0051] Figure 13A-Figure 25A and Figure 31A-Figure 32A According to some embodiments, Fig.12 1 and 2 are cross-sectional side views of various stages of fabricating the semiconductor device structure 100 , taken at cross section AA. Figure 13B-Figure 25B and Figure 31B-Figure 32B According to some embodiments, Fig.12 BB is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 100. Figure 13C - Figure 25C and Figure 31C-Figure 32C According to some embodiments, Fig.12 The cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 are taken from the cross-sectional view CC. The cross-sectional view AA is at the fin structure 112 ( Fig.12 ) along the X direction. Cross section BB is in a plane perpendicular to cross section AA and is in the sacrificial gate structure 130 along the Y direction. Cross section CC is in a plane perpendicular to cross section AA and is in the S / D feature 146 ( Fig.16A )middle.

[0052] Fig.13D An enlarged view of a portion of the semiconductor layer stack 104 according to some embodiments is shown. Various processes (cleaning, deposition or etching processes, etc.) performed after forming the sacrificial layer 109 may cause the atoms in the sacrificial layer 109 to diffuse into adjacent layers. In some embodiments, the atoms (e.g., alkaline elements Sr or Ti) in the sacrificial layer 109 may have a profile that gradually changes along the thickness of the sacrificial layer 109, and the atoms may further diffuse into the first semiconductor layers 106a, 106b, respectively. In some embodiments, the atoms (e.g., alkaline elements Sr or Ti) are uniformly distributed throughout the thickness of the sacrificial layer 109. In some embodiments, the atoms (e.g., alkaline elements Sr or Ti) in the sacrificial layer 109 are distributed to have a gradient profile after various processes. For example, the atoms in the sacrificial layer 109 may have a first element concentration at and / or near the central region of the sacrificial layer 109, and a second element concentration at and / or near the interface 106a-1, 106b-1 between the sacrificial layer 109 and the first semiconductor layer 106a, 106b, wherein the first element concentration is less than the second element concentration. The atoms diffuse into the adjacent layers (e.g., the first semiconductor layers 106a, 106b) along arrows S1 and S2, and may also have a progressive gradient distribution. For example, the first semiconductor layer 106a may have a first element concentration at and / or near the interface 106a-1 between the sacrificial layer 109 and the first semiconductor layer 106a, and a second element concentration at and / or near the central region of the first semiconductor layer 106a, wherein the first element concentration is greater than the second element concentration. Similarly, the first semiconductor layer 106b may have a first element concentration at and / or near the interface 106b-1 between the sacrificial layer 109 and the first semiconductor layer 106b, and a second element concentration at and / or near the central region of the first semiconductor layer 106b, wherein the first element concentration is greater than the second element concentration.

[0053] exist Figure 14A-Figure 14CIn the embodiment of the present invention, the sacrificial layer 109 is selectively removed, thereby creating a cavity 111 between the first semiconductor layer 106a in the first FET and the first semiconductor layer 106b in the second FET. The removal of the sacrificial layer 109 can be performed using an etchant 113, which selectively removes the sacrificial layer 109 without substantially affecting the first semiconductor layer 106 and the second semiconductor layer 108. In some embodiments, the sacrificial layer 109 is removed by hydrogen fluoride (HF) (vapor or liquid). Other suitable fluorides, such as boron tetrafluoride (HBF4) or ammonium fluoride (NH4F), can also be used. The removal process may cause some atoms previously in the sacrificial layer 109 (e.g., alkaline elements Sr or Ti) to diffuse into adjacent layers (e.g., the first semiconductor layers 106a, 106b).

[0054] In some embodiments, a portion of the first semiconductor layer 106 and a portion of the second semiconductor layer 108 are slightly removed. In some examples, the first semiconductor layer 106 may be removed by a first amount, and the second semiconductor layer 108 may be removed by a second amount greater than the first amount. In this case, the sidewall surface of each second semiconductor layer 108 (e.g., 108a, 108b) of the semiconductor layer stack 104 is horizontally recessed by a first distance along the X direction relative to the sidewall surface of the gate spacer 138, and the sidewall surface of each first semiconductor layer 106 (e.g., 106a, 106b) of the semiconductor layer stack 104 is horizontally recessed by a second distance along the X direction relative to the sidewall surface of the gate spacer 138, wherein the first distance is greater than the second distance.

[0055] In some embodiments, the first semiconductor layer 106a in the first FET can be removed by a first amount, and due to the high aspect ratio of the trench, the first semiconductor layer 106b in the second FET can be removed by a second amount that is less than the first amount. Similarly, the second semiconductor layer 108a in the first FET can be removed by a third amount, and the second semiconductor layer 108b in the second FET can be removed by a fourth amount that is less than the third amount.

[0056] Figure 14A-1An enlarged view of a portion 137 of a semiconductor device structure 100 showing an outline of a cavity 111 according to some embodiments is shown. In one embodiment, the sacrificial layer 109 is removed so that the edge portions of the first semiconductor layers 106a, 106b may suffer more losses than at the central portion, resulting in the cavity 111 being wider at the edges and narrower at the center. In other words, the first semiconductor layers 106a, 106b may have a slope in which the thickness of the first semiconductor layers 106a, 106b decreases from the center to the edge. For example, each first semiconductor layer 106a, 106b may have a first thickness D1 measured at the center and a second thickness D2 measured at the edge, wherein the first thickness D1 is greater than the second thickness D2.

[0057] After removing the sacrificial layer 109, a pre-cleaning process may be performed to remove any debris or residue generated by removing the sacrificial layer 109. The pre-cleaning process may use an etchant that does not significantly affect the first semiconductor layer 106 and the second semiconductor layer 108 and the sacrificial gate structure 130. In some embodiments, the pre-cleaning may use a diluted HF solution. Other suitable wet etching processes may also be used. For example, the pre-cleaning process may be any suitable wet cleaning process, such as an APM process including at least water (H2O), ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2); an HPM process including at least H2O, H2O2 and hydrogen chloride (HCl); an SPM process (also known as piranha clean) including at least H2O2 and sulfuric acid (H2SO4); or any combination thereof.

[0058] exist Figure 15A-Figure 15C In the embodiment of the present invention, the edge portion of each second semiconductor layer 108 (e.g., 108a, 108b) of the semiconductor layer stack 104 is horizontally removed along the X direction. The removal of the edge portion of the second semiconductor layer 108 forms a cavity. In some embodiments, a portion of the second semiconductor layer 108 is removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine phthalate (EDP), or potassium hydroxide (KOH) solution can be used to selectively etch the second semiconductor layer 108.

[0059] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer (or referred to as an internal spacer) 144. A dielectric layer is also deposited in the cavity 111 to form an isolation layer 139. The isolation layer 139 and the dielectric spacer 144 may be made of a dielectric material, for example, SiON, SiCN, SiOC, SiOCN, SiN, etc. The isolation layer 139 and the dielectric spacer 144 may be formed by first forming a conformal dielectric layer using a conformal deposition process such as ALD, and then performing anisotropic etching to remove portions of the conformal dielectric layer except the isolation layer 139 and the dielectric spacer 144. During the anisotropic etching process, the isolation layer 139 and the dielectric spacer 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 (e.g., 108a, 108b) is covered between the dielectric spacers 144 along the X direction.

[0060] exist Figure 16A-16C In the embodiment, an epitaxial S / D feature 146 is formed on the well portion 116 of the fin structure 112. The epitaxial S / D feature 146 may include or be made of one or more Si, SiP, SiC, and SiCP layers for n-channel FETs, or one or more Si, SiGe, and Ge layers for p-channel FETs. For p-channel FETs, p-type dopants (e.g., boron (B)) may also be included in the epitaxial S / D feature 146. In some embodiments, the epitaxial S / D feature 146 uses one or more Si, SiGe, and Ge layers for p-channel FETs. The epitaxial S / D feature 146 may be formed by an epitaxial growth method using CVD, ALD, or MBE. The epitaxial S / D feature 146 may be grown vertically and horizontally to form facets, which may correspond to crystallographic planes of the material used for the substrate 101. The epitaxial S / D feature 146 is in contact with the first semiconductor layers 106a, 106b, the isolation layer 139, and the dielectric spacer 144, as shown in FIG. Fig.15A As shown. The epitaxial S / D feature 146 may be an S / D region. In the present disclosure, source region and drain region may be used interchangeably and their structures are substantially the same.

[0061] exist Figure 17A-Figure 17C In the embodiment of the present invention, the epitaxial S / D features 146 are recessed by removing a portion of each epitaxial S / D feature 146. The recessing of the epitaxial S / D features 146 can be performed by any suitable process, such as dry etching or wet etching, which selectively removes a portion of each epitaxial S / D feature 146 but does not remove the gate spacer 138, the dielectric material 125, and the liner 119. After the removal process, the epitaxial S / D features 146 remain in contact with the first semiconductor layer 106b and the dielectric spacer 144, as shown in FIG. Fig.17AAs shown. In some embodiments, the epitaxial S / D feature 146 can be located at or near the interface of the isolation layer 139 and the topmost first semiconductor layer 106b of the second FET. In some embodiments, an etching process can be performed so that the lower portion of the isolation layer 139 is in contact with the epitaxial S / D feature 146. In any case, the semiconductor device structure 100 includes a nanosheet p-channel FET having a source epitaxial feature / terminal 146 and a drain epitaxial feature / terminal 146 in contact with one or more first semiconductor layers 106b, or one or more channels.

[0062] exist Figures 18A-18C In the embodiment of the present invention, a liner 145 is formed on the exposed surface of the semiconductor device structure 100. In some embodiments, the liner 145 is formed on at least the epitaxial S / D features 146, the sidewalls of the sacrificial gate structure 130, the sidewalls of the exposed isolation layer 139, the dielectric spacer 144, and the second semiconductor layer 108. The liner 145 may include a semiconductor material, such as Si. In some embodiments, the liner 145 includes the same material as the first semiconductor layer 106. The liner 145 may be a conformal layer and may be formed by a conformal process, such as an ALD process. In the dielectric material 147 ( Fig.19A ), the liner 145 protects the mask layer 136, the gate spacer 138, the second semiconductor layer 108, the isolation layer 139 and the dielectric spacer 144 during the subsequent recessing of the dielectric layer 144.

[0063] A dielectric material 147 is formed over the epitaxial S / D features 146. The dielectric material 147 may include the same material as the insulating material 118 and may be formed by the same method as the insulating material 118. In some embodiments, the dielectric material 147 includes an oxide formed by FCVD. The dielectric material 147 may be recessed to a level below the level of the first semiconductor layer 106a, such as Fig.17A The recessing of the dielectric material 147 may be performed by any suitable process, such as dry etching or wet etching, which selectively removes a portion of the dielectric material 147 but does not remove the gate spacer 138 , the first semiconductor layer 106 a , and the dielectric spacer 144 .

[0064] exist Figure 19A-Figure 19C In the embodiment of the present invention, dielectric material 147 is formed on liner 145 and over epitaxial S / D features 146. Dielectric material 147 may include the same material as insulating material 118 and may be formed by the same method as insulating material 118. In some embodiments, dielectric material 147 includes an oxide formed by FCVD.

[0065] exist Figure 20A-20CIn the embodiment of the present invention, the dielectric material 147 is recessed to a level below the level of the bottommost first semiconductor layer 106a of the first FET. The recessing of the dielectric material 147 can be performed by any suitable process, such as dry etching or wet etching, which selectively removes a portion of the dielectric material 147 but does not remove the liner 145. Next, the exposed liner 145 is removed, such as Fig. 20A As shown. The removal of the exposed liner 145 can be performed by any suitable process, such as dry etching or wet etching, which selectively removes a portion of the liner 145 but does not remove the dielectric material 125, the gate spacer 138, the mask layer 136, and the dielectric material 147. Because the thickness of the liner 145 is less than about 1.5 nm, the etching process for removing the portion of the liner 145 can be performed in a short time, and thus the exposed second semiconductor layer 108b is substantially not affected by the etching process.

[0066] The remaining liner 145 may be flush with the recessed dielectric material 147. The liner 145 may maintain contact with the topmost second semiconductor layer 108b, the isolation layer 139, and the epitaxial S / D features 146. Therefore, the remaining liner 145 may surround five surfaces of the recessed dielectric material 147.

[0067] exist Figure 21A-Figure 21C In the embodiment, an epitaxial S / D feature 149 is formed on the dielectric material 147. The epitaxial S / D feature 149 may include one or more Si, SiP, SiC, and SiCP layers for n-channel FETs, or one or more Si, SiGe, Ge layers for p-channel FETs. In some embodiments, the epitaxial S / D feature 149 uses one or more Si, SiP, SiC, and SiCP layers for n-channel FETs. The epitaxial S / D feature 149 may be formed from the first semiconductor layer 106a ( Fig.17A ) is formed. The epitaxial S / D features 149 can be grown vertically and horizontally to form facets, which can correspond to the crystallographic planes of the material used for the first semiconductor layer 106a. The epitaxial S / D features 149 can be formed by an epitaxial growth method using CVD, ALD or MBE. Likewise, the epitaxial S / D features 149 can be S / D regions.

[0068] like Fig.21A and Fig. 21CAs shown, the source regions of the n-channel FET and the p-channel FET can be vertically stacked and aligned, the drain regions of the n-channel FET and the p-channel FET can be vertically stacked and aligned, and the source of the n-channel FET and the source of the p-channel FET can be separated by the liner 145 and the dielectric material 147. The vertical stacking of the n-channel FET and the p-channel FET can increase the density of the FET while reducing the cell active area footprint of the semiconductor device (e.g., SRAM).

[0069] exist Figure 22A-22C In the embodiment of the present invention, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the exposed surfaces of the epitaxial S / D features 146, the gate spacers 138, the dielectric material 125, and the semiconductor layer stack 104. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material for the ILD layer 164 may include tetraethylorthosilicate (TEOS) oxide; undoped silicate glass; or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG)); and / or other suitable dielectric materials including Si, O, C and / or H. The ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 164, the semiconductor device structure 100 may be subjected to a heat treatment to anneal the ILD layer 164.

[0070] exist Figure 23A-23C In the embodiment, after forming the ILD layer 164 , a planarization operation such as CMP is performed on the semiconductor device structure 100 to remove portions of the ILD layer 164 , the CESL 162 , and the mask layer 136 until the sacrificial gate electrode layer 134 is exposed.

[0071] exist Figure 24A-Figure 24C, the sacrificial gate structure 130 is removed. The removal of the sacrificial gate structure 130 forms a trench 166 in the area where the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132 are removed. The trench 166 exposes a portion of the cladding layer 117 and the top of the second semiconductor layer 108a. During the removal of the sacrificial gate structure 130, the ILD layer 164 protects the epitaxial S / D features 146. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process (e.g., dry etching, wet etching, or a combination thereof), and then the sacrificial gate dielectric layer 132 is removed, which can also be performed by any suitable process (e.g., dry etching, wet etching, or a combination thereof). In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacers 138, the dielectric material 125, and the CESL 162. In some embodiments, the gate spacers 138 may be recessed by an etchant used to remove the sacrificial gate electrode layer 134 and / or the sacrificial gate dielectric layer 132 .

[0072] exist Figure 25A-Figure 25C In the embodiment of the present invention, the cladding layer 117 and the second semiconductor layer 108 (e.g., 108a, 108b) are removed. The removal of the cladding layer 117 and the second semiconductor layer 108 exposes the isolation layer 139, the dielectric spacer 144, and the first semiconductor layer 106 (e.g., 106a, 106b). The removal process may be any suitable etching process, such as dry etching, wet etching, or a combination thereof. The etching process may be a selective etching process that removes the cladding layer 117 and the second semiconductor layer 108 but does not remove the gate spacer 138, the CESL 162, the dielectric material 125, and the first semiconductor layer 106. As a result, an opening 151 is formed around the first semiconductor layer 106, such as Fig.25A and Fig.25B That is, the portion of the first semiconductor layer 106 not covered by the dielectric spacer 144 is exposed to the opening 151 .

[0073] Figure 26-Figure 30 is a diagram showing various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Fig.25B For clarity, the Figure 26-Figure 30 The dielectric material 125 is omitted. Fig.26In the illustrated embodiment, each first semiconductor layer 106b can be a nanosheet channel of a first nanosheet transistor 155 (e.g., a p-channel FET), and each first semiconductor layer 106a can be a nanosheet channel of a second nanosheet transistor 153 (e.g., an n-channel FET). The second nanosheet transistor (e.g., 106a) is disposed above and aligned with the first nanosheet transistor (e.g., 106b) along the Z direction. Depending on the application, a nanosheet transistor with a higher thermal budget (e.g., a p-channel FET) can be disposed below a nanosheet transistor with a lower thermal budget (e.g., an n-channel FET).

[0074] exist Fig.26 , the semiconductor device structure 100 may be subjected to a pre-cleaning process to remove residues or unwanted films from the exposed surfaces of the first nanolayer 106 b of the first nanosheet transistor 155 and the first semiconductor layer 106 a of the second nanosheet transistor 153. The pre-cleaning process may be any suitable wet cleaning process, such as those discussed above after removing the sacrificial layer 109.

[0075] Next, an interfacial layer (IL) 148 is formed to surround the exposed surfaces of the first semiconductor layers 106a and 106b. Fig.26 In some embodiments, IL 148 may also be formed on well portion 116 of substrate 101. IL 148 may include or be made of an oxygen-containing material or a silicon-containing material, such as silicon oxide, silicon oxynitride, oxynitride, hafnium silicate, etc. IL 148 may be formed by CVD, ALD, or any suitable conformal deposition technique.

[0076] exist Fig. 27 In the embodiment of the present invention, a high-K (HK) dielectric layer 160 is formed on the exposed surface of the semiconductor device structure 100. In some embodiments, the HK dielectric layer 160 is formed to surround the exposed surface of the IL 148, the sacrificial layer 139, the liner 119, the insulating material 118, and the liner 115. The HK dielectric layer 160 may include or be made of hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), or other suitable high-k materials. The HK dielectric layer 160 may be a conformal layer formed by a conformal process, such as an ALD process or a CVD process.

[0077] exist Fig.28 In each opening 151 ( Fig.25B ) and form a first gate electrode layer 172 on the HK dielectric layer 160. The first gate electrode layer 172 is formed on the HK dielectric layer 160 to surround a portion of each of the first semiconductor layers 106b and 106a, respectively. The first gate electrode layer 172 includes one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The first gate electrode layer 172 may be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, the first gate electrode layer 172 includes a p-type gate electrode layer, such as TiN, TaN, TiTaN, TiAlN, WCN, W, Ni, Co, or other suitable materials, and the first gate electrode layer 172 is a gate electrode layer of a PFET. The first gate electrode layer 172 may be formed by first forming a gate electrode layer filling the opening 151, and then performing an etch-back process to recess the gate electrode layer to a level at or near a central region of the isolation layer 139. In some embodiments, the first gate electrode layer 172 is recessed so that a top surface of the first gate electrode layer 172 is located at a level slightly above an interface defined by a bottom surface of the isolation layer 139 and a top surface of the topmost first semiconductor layer 106b, such as Fig.28 The top surface of the first gate electrode layer 172 generally defines a boundary between the first nanosheet transistor 155 and the second nanosheet transistor 153 .

[0078] exist Fig.29 In each opening 151, an isolation material layer 157 is formed on the first gate electrode layer 172. The isolation material layer 157 may include one or more dielectric material layers, such as a metal oxide, such as a refractory metal oxide. The isolation material layer 157 may be formed by PVD, CVD, PECVD, ALD, electroplating, or other suitable methods. The isolation material layer 157 may be formed by first forming a dielectric layer filling the opening 151, and then performing an etch-back process to recess the dielectric layer to a level below the interface defined by the bottom surface of the bottommost first semiconductor layer 106a of the second nanosheet transistor 153 and the top surface of the isolation layer 139.

[0079] exist Fig.30In the embodiment, the second gate electrode layer 179 is formed on the isolation material layer 157 and is filled in the opening 151 exposed by the recess of the isolation material layer 157. The second gate electrode layer 179 includes one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The first gate electrode layer 172 and the second gate electrode layer 179 may include the same or different materials. The second gate electrode layer 179 may be formed by PVD, CVD, ALD, electroplating or other suitable methods. In some embodiments, the second gate electrode layer 179 includes an n-type gate electrode layer, such as TiAlC, TaAlC, TiSiAlC, TiC, TaSiAlC or other suitable materials. Therefore, the second gate electrode layer 179 functions as a gate electrode layer of the n-channel FET, and the first gate electrode layer 172 functions as a gate electrode layer of the p-channel FET.

[0080] Although the first nanosheet transistor 155 (e.g., a p-channel FET) and the second nanosheet transistor 153 (e.g., an n-channel FET) are shown as having the same number of channel layers (e.g., first semiconductor layers 106a, 106b), it should be understood that a non-uniform number of channel layers is contemplated. For example, the first nanosheet transistor 155 may have a first number of channel layers, and the second nanosheet transistor 153 may have a second number of channel layers that is less than or greater than the first number of channel layers.

[0081] Fig.31A , Fig.31B and Fig. 31C A cross-sectional side view of the semiconductor device structure 100 is shown after forming the first gate electrode layer 172 and the second gate electrode layer 179 . Fig.31D is an enlarged view of a portion of the semiconductor device structure 100 showing the first nanosheet transistor 155 and the second nanosheet transistor 153 . Figure 31D-1 yes Fig.31D FIG. 2 is an enlarged view of a region 222 of the semiconductor device structure 100. Fig.13DAs discussed, the atoms in the first semiconductor layers 106a, 106b may have a progressive gradient distribution. For example, the first semiconductor layer 106a may have a first element concentration at and / or near the interface 106a-2 between the isolation layer 139 and the first semiconductor layer 106a, and a second element concentration at and / or near the central region of the first semiconductor layer 106a, wherein the first element concentration is greater than the second element concentration. Similarly, the first semiconductor layer 106b may have a first element concentration at and / or near the interface 106b-2 between the isolation layer 139 and the first semiconductor layer 106b, and a second element concentration at and / or near the central region of the first semiconductor layer 106b, wherein the profile of the atomic distribution gradually decreases from the first element concentration to the second element concentration. In this case, the atoms previously diffused from the sacrificial layer 109 (e.g., alkaline elements Sr or Ti) may form material layers 302a, 302b containing Sr or Ti at and / or near the interfaces 106a-2, 106b-2, respectively.

[0082] Figure 31D-2 is based on Figure 14A-1 The embodiment shown Fig.31D 1 is an enlarged view of the region 222 of the semiconductor device structure 100 shown. In this case, the material layers 302a, 302b and the isolation layer 139 are deposited to follow the contours of the first semiconductor layers 106a, 106b, which have a thickness that decreases from the center to the edge. Therefore, the isolation layer 139 forms a larger thickness at the edge and a smaller thickness at the center.

[0083] In some embodiments, atoms (e.g., alkaline elements Sr or Ti) in the material layers 302a, 302b may diffuse back into the isolation layer 139, so that the isolation layer 139 has an element concentration of Sr or Ti different from that of the material layers 302a, 302b. For example, the first semiconductor layers 106a, 106b may include a first element concentration, the material layers 302a, 302b may have a second element concentration greater than the first element concentration, and the isolation layer 139 may have a third element concentration less than the second element concentration.

[0084] exist Figure 32A-32C , source / drain (S / D) contacts 176 are formed in the ILD layer 164. Prior to forming the S / D contacts 176, contact openings are formed in the ILD layer 164 to expose the epitaxial S / D features 149. Suitable photolithography and etching techniques are used to form contact openings through various layers (including the ILD layer 164 and the CESL 162) to expose the epitaxial S / D features 149.

[0085] After forming the contact opening, a silicide layer 178 is formed on the epitaxial S / D feature 149. The silicide layer 178 electrically couples the epitaxial S / D feature 149 to the subsequently formed S / D contact 176. The silicide layer 178 can be formed by depositing a metal source layer on the epitaxial S / D feature 149 and performing a rapid thermal annealing process. During the rapid annealing process, the portion of the metal source layer on the epitaxial S / D feature 149 reacts with silicon in the epitaxial S / D feature 149 to form the silicide layer 178. The unreacted portion of the metal source layer is then removed. The material of the silicide layer 178 is selected based on the conductivity type of the second nanosheet transistor 153. For n-channel FETs, the silicide layer 178 may be made of a material including one or more of the following: TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, ScSi, YSi, HoSi, GdSi, LuSi, DySi, ErSi, or a combination thereof. For p-channel FETs, the silicide layer 178 may be made of a material including one or more of the following: NiSi, CoSi, MnSi, Wsi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, or a combination thereof. In some embodiments, the silicide layer 178 is made of a metal or metal alloy silicide, and the metal includes a noble metal, a refractory metal, a rare earth metal, an alloy thereof, or a combination thereof.

[0086] Next, a conductive material is formed in the contact opening, and an S / D contact 176 is formed. The conductive material may be made of a material including one or more of the following: Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. Although not shown, a barrier layer (e.g., TiN, TaN, etc.) may be formed on the sidewalls of the contact opening before forming the S / D contact 176. Then, a planarization process such as CMP is performed to remove excess deposition of the contact material and expose the top surface of the second gate electrode layer 179.

[0087] It is understood that the semiconductor device structure 100 may undergo further complementary metal oxide semiconductor (CMOS) and / or back-end of line (BEOL) processes to form various features, such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc. The semiconductor device structure 100 may also include a back contact (not shown) on the back side of the substrate 101, by flipping the semiconductor device structure 101, removing the substrate 101, and selectively connecting the source or drain feature / terminal of the epitaxial S / D feature 146 or 149 to a back power rail (e.g., a positive voltage VDD or a negative voltage VSS) through the back contact. Depending on the application, the source or drain feature / terminal of the epitaxial S / D feature 146 or 149 and the first gate electrode layer 172 and the second gate electrode layer 179 may be connected to a front power supply.

[0088] Embodiments of the present invention provide a semiconductor device structure including a CFET, each CFET having a first nanosheet transistor and a second nanosheet transistor disposed above the first nanosheet transistor. The first nanosheet transistor is separated from the second nanosheet transistor by an isolation layer, and each channel layer disposed adjacent to the isolation layer has alkaline atoms (e.g., Sr or Ti) diffused from a sacrificial layer that was previously formed and removed before forming source / drain features. Unlike the old method of using SiGe with a high Ge at.% (e.g., 50 at.%) as a sacrificial layer, the sacrificial layer of the present invention is made of a semiconductor metal oxide (e.g., an alkaline earth titanate). Alkaline earth titanates (e.g., SrTiO3) are wide bandgap semiconductors with good etching selectivity relative to silicon and can be grown on silicon with minimal or no lattice mismatch between the sacrificial layer and the adjacent channel layer. As a result, dislocation problems that may occur due to lattice mismatch between the sacrificial layer and the adjacent channel layer are alleviated.

[0089] A method for forming a semiconductor device structure is provided. The method includes: forming a sacrificial layer between a first stacked layer and a second stacked layer disposed on the first stacked layer, wherein the first stacked layer includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, and the second stacked layer includes a plurality of third semiconductor layers and a plurality of fourth semiconductor layers stacked alternately, and wherein the sacrificial layer includes a semiconductor metal oxide. The method also includes: forming a sacrificial gate structure on a portion of the second stacked layer; removing portions of the first stacked layer and the second stacked layer not covered by the sacrificial gate structure; removing the sacrificial layer to form a cavity; filling the cavity with a dielectric material to form an isolation layer; and forming a first source / drain feature and a second source / drain feature on opposite sides of the sacrificial gate structure, wherein the first source / drain feature is disposed lower than the second source / drain feature, and the first source / drain feature and the second source / drain feature are in contact with the isolation layer, the first semiconductor layer, and the third semiconductor layer.

[0090] Another embodiment is a method of forming a semiconductor device structure. The method includes: forming a plurality of fin structures from a substrate, each fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; forming a sacrificial layer between two adjacent first semiconductor layers, wherein the sacrificial layer includes a semiconductor metal oxide. The method also includes: diffusing a metal element from the sacrificial layer into a first semiconductor layer disposed adjacent to the sacrificial layer; and replacing the sacrificial layer with a dielectric material to form an isolation layer.

[0091] Another embodiment is a semiconductor device structure. The structure includes: a first transistor, including a plurality of first semiconductor layers stacked vertically, each of which is surrounded by a first gate electrode layer; a second transistor, disposed above the first transistor, the second transistor including a plurality of second semiconductor layers stacked vertically, and each of which is surrounded by a second gate electrode layer different from the first gate electrode layer; an isolation layer, disposed between the topmost first semiconductor layer of the first transistor and the bottommost second semiconductor layer of the second transistor; a first source / drain feature, contacting a portion of the isolation layer and the first semiconductor layer; and a second source / drain feature, disposed above the first source / drain feature, and contacting a portion of the isolation layer and the second semiconductor layer.

[0092] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0093] Example

[0094] Example 1. A method for forming a semiconductor device structure, comprising: forming a sacrificial layer between a first stacked layer and a second stacked layer arranged above the first stacked layer, wherein the first stacked layer includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, and the second stacked layer includes a plurality of third semiconductor layers and a plurality of fourth semiconductor layers stacked alternately, and wherein the sacrificial layer includes a semiconductor metal oxide; forming a sacrificial gate structure above a portion of the second stacked layer; removing portions of the first stacked layer and the second stacked layer not covered by the sacrificial gate structure; removing the sacrificial layer to form a cavity; filling the cavity with a dielectric material to form an isolation layer; and forming a first source / drain feature and a second source / drain feature on opposite sides of the sacrificial gate structure, wherein the first source / drain feature is arranged lower than the second source / drain feature, and the first source / drain feature and the second source / drain feature are in contact with the isolation layer, the first semiconductor layer and the third semiconductor layer.

[0095] Example 2. The method of Example 1, wherein the semiconductor metal oxide comprises an alkaline earth titanate.

[0096] Example 3. The method according to Example 2, wherein the alkaline earth titanate includes strontium titanate (SrTiO3), barium titanate (BaTiO3), barium strontium titanate (BaSrTiO3), lanthanum titanate (LaTiO3), etc.

[0097] Example 4. The method according to Example 3, wherein the first semiconductor layer and the third semiconductor layer disposed adjacent to the isolation layer have an alkaline element.

[0098] Example 5. The method according to Example 4, wherein the alkaline element forms a material layer disposed between the isolation layer and the first and third semiconductor layers, respectively.

[0099] Example 6. The method according to Example 1 further includes: removing the sacrificial gate structure and portions of the multiple second semiconductor layers and the multiple fourth semiconductor layers to expose portions of each of the multiple first semiconductor layers and the multiple third semiconductor layers; forming an interface layer on the exposed surfaces of the first semiconductor layers and the third semiconductor layers; and forming a high-k dielectric layer over the interface layer and the isolation layer.

[0100] Example 7. The method of Example 6, further comprising: forming a first gate electrode layer to surround an exposed portion of each of the plurality of first semiconductor layers.

[0101] Example 8. A method for forming a semiconductor device structure, comprising: forming a plurality of fin structures from a substrate, each fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; forming a sacrificial layer between two adjacent first semiconductor layers, wherein the sacrificial layer comprises a semiconductor metal oxide; diffusing a metal element from the sacrificial layer into the first semiconductor layer disposed adjacent to the sacrificial layer; and replacing the sacrificial layer with a dielectric material to form an isolation layer.

[0102] Example 9. The method according to Example 8 further includes: forming a first source / drain feature and a second source / drain feature on opposite sides of the sacrificial gate structure, wherein the first source / drain feature is set lower than the second source / drain feature, and the first source / drain feature and the second source / drain feature are in contact with the isolation layer and the first semiconductor layer.

[0103] Example 10. The method of Example 8, wherein the semiconductor metal oxide comprises an alkaline earth titanate.

[0104] Example 11. The method of Example 10, wherein the first semiconductor layer disposed adjacent to the sacrificial layer includes an alkaline element distributed in a gradual gradient profile.

[0105] Example 12. The method of Example 8, further comprising: removing edge portions of the plurality of second semiconductor layers to form a cavity; and forming a dielectric spacer in the cavity.

[0106] Example 13. The method of Example 12, wherein the dielectric spacer and the isolation layer are formed of the same material.

[0107] Example 14. The method according to Example 8, wherein the sacrificial layer is formed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, or an epitaxial growth process.

[0108] Example 15. The method of Example 14, wherein the sacrificial layer is formed by an MBE process at a temperature range of about 400 degrees Celsius to about 800 degrees Celsius.

[0109] Example 16. A semiconductor device structure, comprising: a first transistor, comprising a plurality of first semiconductor layers stacked vertically, each first semiconductor layer being surrounded by a first gate electrode layer; a second transistor, disposed above the first transistor, the second transistor comprising a plurality of second semiconductor layers stacked vertically, and each second semiconductor layer being surrounded by a second gate electrode layer different from the first gate electrode layer; an isolation layer, disposed between the topmost first semiconductor layer of the first transistor and the bottommost second semiconductor layer of the second transistor; a first source / drain feature, contacting a portion of the isolation layer and the first semiconductor layer; and a second source / drain feature, disposed above the first source / drain feature and contacting a portion of the isolation layer and the second semiconductor layer.

[0110] Example 17. The semiconductor device structure according to Example 16, wherein the isolation layer comprises SiON, SiCN, SiOC, SiOCN, SiN, etc.

[0111] Example 18. The semiconductor device structure of Example 16, wherein a topmost first semiconductor layer of the first transistor and a bottommost second semiconductor layer of the second transistor include an alkaline element.

[0112] Example 19. A semiconductor device structure according to Example 18, wherein the topmost first semiconductor layer has a first element concentration at and / or near the interface between the isolation layer and the topmost first semiconductor layer of the first transistor, and the topmost first semiconductor layer has a second element concentration at and / or near the central region of the topmost first semiconductor layer, wherein the first element concentration is greater than the second element concentration.

[0113] Example 20. According to the semiconductor device structure in Example 18, it also includes: a dielectric material arranged between the first source / drain feature and the second source / drain feature, wherein the top surface of the dielectric material is located at an elevation between the top surface of the isolation layer and the bottom surface of the isolation layer.

Claims

1. A method for forming a semiconductor device structure, comprising: forming a sacrificial layer between a first stacked layer and a second stacked layer disposed on the first stacked layer, wherein the first stacked layer includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked, and the second stacked layer includes a plurality of third semiconductor layers and a plurality of fourth semiconductor layers that are alternately stacked, and wherein the sacrificial layer includes a semiconductor metal oxide; forming a sacrificial gate structure on a portion of the second stacked layer; removing portions of the first stacked layer and the second stacked layer not covered by the sacrificial gate structure; removing the sacrificial layer to form a cavity; filling the cavity with a dielectric material to form an isolation layer; and A first source / drain feature and a second source / drain feature are formed on opposite sides of the sacrificial gate structure, wherein the first source / drain feature is disposed lower than the second source / drain feature, and the first source / drain feature and the second source / drain feature are in contact with the isolation layer, the first semiconductor layer, and the third semiconductor layer.

2. The method according to claim 1, wherein: The semiconducting metal oxide includes an alkaline earth titanate.

3. The method according to claim 2, wherein: The alkaline earth titanate includes strontium titanate (SrTiO3), barium titanate (BaTiO3), barium strontium titanate (BaSrTiO3), lanthanum titanate (LaTiO3), and the like.

4. The method according to claim 3, wherein: The first semiconductor layer and the third semiconductor layer disposed adjacent to the isolation layer have an alkaline element.

5. The method according to claim 4, wherein: The alkaline element forms a material layer disposed between the isolation layer and the first and third semiconductor layers, respectively.

6. The method according to claim 1, further comprising: removing the sacrificial gate structure and portions of the plurality of second semiconductor layers and the plurality of fourth semiconductor layers to expose portions of each of the plurality of first semiconductor layers and the plurality of third semiconductor layers; forming an interface layer on exposed surfaces of the first semiconductor layer and the third semiconductor layer; as well as A high-k dielectric layer is formed over the interface layer and the isolation layer.

7. The method according to claim 6, further comprising: A first gate electrode layer is formed to surround an exposed portion of each of the plurality of first semiconductor layers.

8. A method for forming a semiconductor device structure, comprising: forming a plurality of fin structures from a substrate, each fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; forming a sacrificial layer between two adjacent first semiconductor layers, wherein the sacrificial layer comprises a semiconductor metal oxide; diffusing the metal element from the sacrificial layer into the first semiconductor layer disposed adjacent to the sacrificial layer; and The sacrificial layer is replaced with a dielectric material to form an isolation layer.

9. The method according to claim 8, further comprising: A first source / drain feature and a second source / drain feature are formed on opposite sides of the sacrificial gate structure, wherein the first source / drain feature is disposed lower than the second source / drain feature and the first source / drain feature and the second source / drain feature are in contact with the isolation layer and the first semiconductor layer.

10. A semiconductor device structure, comprising: A first transistor including a plurality of first semiconductor layers stacked vertically, each of the first semiconductor layers being surrounded by a first gate electrode layer; a second transistor disposed above the first transistor, the second transistor comprising a plurality of second semiconductor layers stacked vertically, and each second semiconductor layer being surrounded by a second gate electrode layer different from the first gate electrode layer; an isolation layer, disposed between a topmost first semiconductor layer of the first transistor and a bottommost second semiconductor layer of the second transistor; a first source / drain feature in contact with a portion of the isolation layer and the first semiconductor layer; as well as A second source / drain feature is disposed over the first source / drain feature and contacts a portion of the isolation layer and the second semiconductor layer.

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