LED chip and manufacturing method thereof

Abstract

The invention provides an LED chip and a manufacturing method thereof. The LED chip comprises a substrate; the first type semiconductor layer, the active layer, the second type semiconductor layer, the first passivation layer, the reflecting layer and the second passivation layer are arranged on the surface of one side of the substrate and are sequentially arranged in the first direction; the first direction is perpendicular to the substrate and points to the active layer from the substrate; a plurality of grooves arranged in an array are formed in one side, close to the first passivation layer, of the reflecting layer, the opening of each groove faces the first passivation layer, and the groove wall of each groove is a curved surface, so that light entering the grooves is shaped and collected and then is reflected to the light emitting surface; a first electrode electrically connected to the first type semiconductor layer; and a second electrode electrically connected with the second type semiconductor layer. According to the LED chip, the incident angle of light on the light emitting surface of the LED chip can be reduced, so that the probability that the light is totally reflected is reduced, and the light extraction efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of light emitting diodes, and more specifically, to an LED chip and a manufacturing method thereof. Background Art

[0002] At present, light-emitting diodes (LEDs) based on the third-generation semiconductor material GaN have been widely used in the fields of communications, lighting, and display due to their advantages of high efficiency, high brightness, long life, and small size. However, since GaN materials have a large refractive index (about 2.29) and a small critical angle for total reflection of the material, the light extraction efficiency (LEE) of the LED chip is limited, which in turn affects the chip performance. In addition, as the size of LED chips is getting smaller and smaller, the edge effect of the chip cross section is gradually increasing, further increasing the LEE loss. Therefore, improving LEE by designing the structure of the LED chip is the key to improving chip performance.

[0003] Current LED chips mostly use PSS substrates (i.e., patterned substrates) to change the incident angle between light and the interface to improve light extraction efficiency. However, on the one hand, the transmittance of the PSS substrate itself is very high, and the proportion of scattered light is limited. On the other hand, the effect of this scattering structure is bidirectional, so that the light that could have been output is totally reflected at the material interface due to the change in the optical path and cannot be output, further offsetting part of the LEE.

[0004] This case was created to overcome the problem of limited light extraction efficiency in the prior art. Summary of the invention

[0005] In view of this, the present invention provides an LED chip and a manufacturing method thereof capable of improving light extraction efficiency.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows: an LED chip comprises:

[0007] substrate;

[0008] A first-type semiconductor layer, an active layer, a second-type semiconductor layer, a first passivation layer, a reflective layer, and a second passivation layer are arranged on a surface of one side of the substrate and arranged in sequence along a first direction; the first direction is perpendicular to the substrate and points from the substrate to the active layer; a plurality of grooves arranged in an array are arranged on one side of the reflective layer close to the first passivation layer, the opening of each groove faces the first passivation layer, and the groove wall of each groove is a curved surface, so as to shape and converge the light entering the groove and then reflect it to the light emitting surface;

[0009] a first electrode electrically connected to the first-type semiconductor layer;

[0010] A second electrode is electrically connected to the second-type semiconductor layer.

[0011] Furthermore, a surface of the first passivation layer facing away from the active layer is provided with a plurality of first protrusions arranged in an array, and each of the first protrusions protrudes along the first direction;

[0012] The reflective layer contacts each of the first protrusions of the first passivation layer to form the groove.

[0013] Furthermore, the groove wall of the groove is a parabola.

[0014] Further, the surface of the first protrusion is formed by rotating the first line segment around its axis of symmetry;

[0015] The first line segment is selected from a line segment of a parabola including a vertex, and the axis of symmetry coincides with the axis of symmetry of the parabola.

[0016] Furthermore, it also includes an intermediate layer located on the surface of the substrate away from the active layer; the refractive index of the intermediate layer is smaller than the refractive index of the substrate and larger than the refractive index of the air;

[0017] A plurality of second protrusions arranged in an array are provided on the surface of the intermediate layer away from the active layer; the second protrusions protrude in a direction away from the first direction; after the outgoing light enters the intermediate layer, the second protrusions make the reflection direction of the outgoing light that meets the reflection condition deviate toward the focus of the groove wall in the reflecting layer, so as to reduce the incident angle of the outgoing light when it reaches the intermediate layer for the second time so that it can be output.

[0018] Further, the surface of the second protrusion is formed by rotating the second line segment around the first axis;

[0019] The second line segment is selected from an off-axis segment of the parabola located on one side of the symmetry axis; the first axis intersects with the endpoint of the second line segment close to the symmetry axis and is parallel to the symmetry axis.

[0020] Furthermore, in a projection plane parallel to the first direction, endpoints of projection contour lines of two adjacent grooves coincide.

[0021] Furthermore, in a projection plane parallel to the first direction, endpoints of projection contour lines of two adjacent second protrusions coincide with each other.

[0022] Furthermore, the reflective layer is a metal reflective mirror or a dielectric reflective mirror.

[0023] Furthermore, when the reflective layer is the metal reflective mirror, it can be a combination of one or more of a gold mirror, a silver mirror, an aluminum mirror, and a molybdenum mirror; when the reflective layer is the dielectric reflective mirror, it can be a distributed Bragg reflector or a photonic crystal structure with a wide bandgap.

[0024] The present invention also provides a method for manufacturing an LED chip, comprising the following steps:

[0025] providing a substrate;

[0026] A first-type semiconductor layer, an active layer, a second-type semiconductor layer, a first passivation layer, a reflective layer, and a second passivation layer are sequentially grown on a surface of one side of the substrate along a first direction; the first direction is perpendicular to the substrate and points from the substrate to the active layer; a plurality of grooves arranged in an array are made on a side of the reflective layer close to the first passivation layer, the opening of each of the grooves faces the first passivation layer, and the groove wall of each of the grooves is a curved surface, so that light entering the groove is shaped and focused and then reflected to a light-emitting surface;

[0027] Making a first electrode electrically connected to the first-type semiconductor layer;

[0028] A second electrode electrically connected to the second-type semiconductor layer is fabricated.

[0029] Furthermore, the groove wall of the groove is a parabola.

[0030] Furthermore, it also includes forming an intermediate layer on the surface of the substrate away from the active layer; the refractive index of the intermediate layer is smaller than the refractive index of the substrate and larger than the refractive index of the air;

[0031] A plurality of second protrusions arranged in an array are provided on the surface of the intermediate layer away from the active layer; the second protrusions protrude in a direction away from the first direction; after the outgoing light enters the intermediate layer, the second protrusions make the reflection direction of the outgoing light that meets the reflection condition deviate toward the focus of the groove wall in the reflecting layer, so as to reduce the incident angle of the outgoing light when it reaches the intermediate layer for the second time so that it can be output.

[0032] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0033] 1. The LED chip comprises: a substrate; a first-type semiconductor layer, an active layer, a second-type semiconductor layer, a first passivation layer, a reflective layer, and a second passivation layer arranged on the surface of one side of the substrate and arranged in sequence along a first direction; the first direction is perpendicular to the substrate and points from the substrate to the active layer; the reflective layer is provided with a plurality of grooves arranged in an array on one side of the first passivation layer, the opening of each groove faces the first passivation layer, and the groove wall of each groove is a curved surface, so as to shape and converge the light entering the groove and reflect it to the light-emitting surface; a first electrode electrically connected to the first-type semiconductor layer; and a second electrode electrically connected to the second-type semiconductor layer. Due to the above-mentioned structural setting, the LED chip of the present application forms a groove on the reflective layer, and the groove wall of the groove can shape and converge the light entering the groove and reflect it to the light-emitting surface, thereby reducing the incident angle of the light on the light-emitting surface of the LED chip, thereby reducing the probability of the light being totally reflected and improving the light extraction efficiency. The second passivation layer acts as a protective layer of the LED chip to increase the reliability of the core particle.

[0034] 2. The principle of reflection of light by a parabola is as follows Figure 2 As shown in the figure, when a beam of parallel light is incident on a parabola, the light reflected at different positions will eventually converge at the same point, which is called the focus. According to the reversibility principle of the optical path, when a point light source is located at the focus of the parabola, the divergent light emitted by the point light source will become parallel light after reflection. According to the Huygens-Fresnel principle, we can decompose the active layer into individual face elements and regard a single face element as a point light source. After the light emitted by the point light source enters the groove of the reflective layer, it is shaped and converged by the parabolic groove wall, reducing the incident angle of the light on the light-emitting surface of the LED chip, thereby reducing the probability of the light being totally reflected and improving the light extraction efficiency.

[0035] 3. An intermediate layer is provided and a plurality of second protrusions arranged in an array are provided on the intermediate layer to improve the light extraction efficiency. At the same time, in order to avoid the patterned arrangement on the intermediate layer so that the light that could have been output is totally reflected at the material interface due to the change in the light path and cannot be output, thereby offsetting part of the LEE; the inventor of the present application designs the second protrusion so that the reflection direction of the outgoing light that meets the reflection condition is biased toward the focus of the parabolic groove wall of the groove in the reflecting layer, so as to reduce the incident angle of the outgoing light when it reaches the intermediate layer for the second time so that it can be output and reduce the offset part of the LEE. In addition, due to the large difference in refractive index between the substrate and the air, the refractive index of the intermediate layer is located between the substrate and the air, which reduces the backflow of light into the LED chip. Combined with the above-mentioned structural design, the number of light reflections is reduced, thereby reducing the loss of light in the chip and improving the light extraction efficiency.

[0036] 4. In the projection plane parallel to the first direction, the endpoints of the projection contour lines of two adjacent grooves coincide, that is, the grooves are continuous with no gaps in between, so that as many grooves as possible are formed on the reflective layer, which has a better effect on light shaping and focusing, and can better improve the light extraction efficiency of the LED chip.

[0037] 5. In the projection plane parallel to the first direction, the endpoints of the projection contour lines of two adjacent second protrusions coincide, that is, the second protrusions are continuous with no gaps in between, so that as many second protrusions as possible are formed on the middle layer, which can better improve the light extraction efficiency of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0039] Figure 1 This is a schematic diagram of the structure of an embodiment of the LED chip of the present application;

[0040] Figure 2 This is the schematic diagram of parabolic reflection;

[0041] Figure 3 is a schematic diagram for selecting the first line segment and the second line segment;

[0042] Figure 4 is a projection contour line of the first protrusion on a projection plane parallel to the first direction;

[0043] Figure 5 is a partial schematic diagram of a first protrusion array on the surface of the first passivation layer;

[0044] Figure 6 is a projection contour line of the second protrusion on a projection plane parallel to the first direction;

[0045] Figure 7 is a partial schematic diagram of the second protrusion array on the surface of the intermediate layer;

[0046] Figure 8 This is a schematic structural diagram of another embodiment of the LED chip of the present application;

[0047] Figure 9-17 for Figure 8 Schematic diagram of the steps in the LED chip manufacturing process.

[0048] Reference numerals:

[0049] Substrate 1; first-type semiconductor layer 2; active layer 3; second-type semiconductor layer 4; first passivation layer 5; first protrusion 51; reflective layer 6; second passivation layer 7; intermediate layer 8; second protrusion 81; current spreading layer 9; first electrode 10; second electrode 20; first contact electrode 30; second contact electrode 40; parabola 50; symmetry axis 501; first line segment 502; second line segment 503; first axis 60; insulating channel 80; first direction D. DETAILED DESCRIPTION

[0050] To make the content of the present invention clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0052] Secondly, the present application is described in detail with reference to the schematic diagram. When describing the embodiments of the present application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0053] like Figure 1 As shown, the present application provides an LED chip, which includes a substrate 1, a first-type semiconductor layer 2, an active layer 3, a second-type semiconductor layer 4, a first passivation layer 5, a reflective layer 6, and a second passivation layer 7, which are arranged on a surface of one side of the substrate 1 and arranged in sequence along a first direction D; the first direction D is perpendicular to the substrate 1 and points from the substrate 1 to the active layer 3; a first electrode 10 electrically connected to the first-type semiconductor layer 2 and a second electrode 20 electrically connected to the second-type semiconductor layer 4. Among them, a plurality of grooves arranged in an array are provided on one side of the reflective layer 6 close to the first passivation layer 5, the opening of each groove faces the first passivation layer 5, and the groove wall of each groove is a curved surface, so as to shape and converge the light entering the groove and reflect it to the light-emitting surface.

[0054] Due to the above-mentioned structural setting, the LED chip of the present application forms a groove on the reflective layer 6, and the groove wall of the groove can shape and focus the light entering the groove and then reflect it to the light-emitting surface, thereby reducing the incident angle of the light on the light-emitting surface of the LED chip and improving the light extraction efficiency. The second passivation layer 7 serves as a protective layer for the LED chip to increase the reliability of the core particle.

[0055] Among them, one of the first-type semiconductor layer 2 and the second-type semiconductor layer 4 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. In this application, the first-type semiconductor layer 2 is an N-type semiconductor layer, and the second-type semiconductor layer 4 is a P-type semiconductor layer. For example, the first-type semiconductor layer 2 can be N-GaN, and the second-type semiconductor layer 4 can be P-GaN.

[0056] The material of the first passivation layer 5 is preferably a material with a refractive index close to that of GaN (about 2.29), which can reduce the refractive index difference between the first passivation layer 5 and the GaN layer and improve the light transmittance; the first passivation layer 5 includes but is not limited to silicon nitride. Preferably, the first passivation layer of silicon nitride is prepared by PECVD method, and the refractive index of silicon nitride prepared by PECVD method is in the range of 1.8-2.5. In the process of preparing the first passivation layer 5, the refractive index of silicon nitride can be adjusted within the range of 2-2.2 by adjusting the process parameters, so that the refractive index is closer to that of GaN; for example, the refractive index of silicon nitride can be adjusted by adjusting the molar ratio of the gas in the reaction chamber and the radio frequency power parameters.

[0057] The substrate 1 includes but is not limited to a sapphire substrate 1, preferably a flat sapphire substrate 1, which can improve the quality of the epitaxial layer during the growth of the epitaxial layer, reduce defects and uneven growth of the epitaxial layer, and thus improve the reliability of the device.

[0058] Among them, Figure 1 As shown, in the present application, the LED chip is provided with a groove for etching the second-type semiconductor layer 4 and the active layer 3 to form a table and an exposed portion of the first-type semiconductor layer 2; and is also provided with an insulating trench 80 for etching the second-type semiconductor layer 4, the active layer 3 and the first-type semiconductor layer 2 to expose a portion of the substrate 1, and the insulating trench 80 is used to separate each core particle. The first passivation layer 5 covers the exposed surface of the second-type semiconductor layer 4, the active layer 3 and the first-type semiconductor layer 2 of each core particle of the LED chip. The reflective layer 6 covers the exposed surface of the first passivation layer 5, and the second passivation layer 7 covers the exposed surface of the reflective layer 6.

[0059] In a preferred embodiment, the surface of the first passivation layer 5 facing away from the active layer 3 is provided with a plurality of first protrusions 51 arranged in an array, and each first protrusion 51 protrudes along the first direction D; the reflective layer 6 contacts each first protrusion 51 of the first passivation layer 5 to form a groove. Figure 5 It is a partial schematic diagram of the array of first protrusions 51 on the surface of the first passivation layer 5.

[0060] In a preferred embodiment, the groove wall of the groove is a parabola. The reflection principle of the parabola on light is as follows Figure 2 As shown, when a beam of parallel light is incident on a parabola, the light reflected at different positions will eventually converge at the same point, which is called the focus. According to the reversibility principle of the optical path, when a point light source is located at the focus of the parabola, the divergent light emitted by the point light source will become parallel light after reflection. According to the Huygens-Fresnel principle, we can decompose the active layer 3 into individual face elements and regard a single face element as a point light source. After the light emitted by the point light source enters the groove of the reflective layer 6, it is shaped and converged by the parabolic groove wall, reducing the incident angle of the light on the light-emitting surface of the LED chip, thereby reducing the probability of the light being totally reflected and improving the light extraction efficiency.

[0061] In a preferred embodiment, if Figure 3 As shown, the surface of the first protrusion 51 is formed by rotating the first line segment 502 around its symmetry axis; the first line segment 502 is selected from the line segment including the vertex of the parabola 50, and the symmetry axis coincides with the symmetry axis 501 of the parabola 50. The present application exemplarily shows that the first line segment is Figure 3 The line segment selected by the dotted frame indicated by 502. Figure 4 The projection contour of the first protrusion 51 on the projection plane parallel to the first direction D is shown, and its projection contour is also the first line segment 502. In the present application, the surface of the first protrusion 51 is formed by rotating the first line segment 502 around its symmetry axis to form a parabolic surface, so that the groove wall of the groove is parabolic.

[0062] Preferably, if Figure 1 As shown, the width A of the bottom of each first protrusion 51 ranges from 1 μm to 4 μm, including the end values.

[0063] In a preferred embodiment, if Figure 1 As shown, the LED chip further includes an intermediate layer 8 located on the surface of the substrate 1 away from the active layer 3; the refractive index of the intermediate layer 8 is less than the refractive index of the substrate 1 and greater than the refractive index of the air. The surface of the intermediate layer 8 away from the active layer 3 is provided with a plurality of second protrusions 81 arranged in an array; the second protrusions 81 protrude in a direction away from the first direction D; after the outgoing light enters the intermediate layer 8, the second protrusions 81 make the reflection direction of the outgoing light that meets the reflection condition deviate to the focus of the groove wall of the groove in the reflective layer 6, so as to reduce the incident angle of the outgoing light when it reaches the intermediate layer 8 for the second time so that it can be output. Among them, the material of the intermediate layer 8 can be one of silicon oxide, aluminum oxide, silicon aluminum oxide mixture, barium fluoride, magnesium fluoride, etc., but is not limited thereto as long as it can meet the above requirements.

[0064] An intermediate layer 8 is provided and a plurality of second protrusions 81 arranged in an array are provided on the intermediate layer 8 to improve the light extraction efficiency. At the same time, in order to avoid the patterned setting on the intermediate layer 8 so that the light that could have been output is totally reflected at the material interface due to the change in the light path and cannot be output, thereby offsetting part of the LEE; the inventor of the present application designs the second protrusion 81 so that the reflection direction of the outgoing light that meets the reflection condition is biased toward the focus of the parabolic groove wall of the groove in the reflecting layer 6, so as to reduce the incident angle of the outgoing light when it reaches the intermediate layer 8 for the second time so that it can be output and reduce the LEE of the offset part. In addition, due to the large difference in refractive index between the substrate 1 and the air, the refractive index of the intermediate layer 8 is located between the substrate 1 and the air, which reduces the backflow of light into the LED chip. Combined with the above-mentioned structural design, the number of light reflections is reduced, thereby reducing the loss of light in the chip and improving the light extraction efficiency.

[0065] Preferably, if Figure 3 As shown, the surface of the second protrusion 81 is formed by rotating the second line segment 503 around the first axis 60; the second line segment 503 is selected from the off-axis segment of the parabola 50 located on one side of the symmetry axis 501, that is, the selected second line segment 503 does not intersect the symmetry axis 501 of the parabola 50. The present application exemplarily shows that the second line segment is Figure 3 The dashed line segment indicated by 503 is selected. Figure 6 The projection contour line of the second protrusion 81 on the projection plane parallel to the first direction D is shown. Figure 6 The first axis 60 intersects with the endpoint of the second line segment 503 close to the symmetry axis 501 and is parallel to the symmetry axis 501. The first line segment 502 and the second line segment 503 can be selected from the same parabola 50 or from different parabolas 50, as long as the above-defined requirements are met. This application takes the first line segment 502 and the second line segment 503 selected from the same parabola 50 as an example for explanation.

[0066] Preferably, if Figure 1 As shown, the width B of the bottom of the second protrusion 81 ranges from 1 μm to 4 μm, including the end values.

[0067] In a preferred embodiment, if Figure 1 As shown, in the projection plane parallel to the first direction D, the endpoints of the projection contour lines of two adjacent grooves coincide. That is, the grooves are continuous, with no gaps in between, so that as many grooves as possible are formed on the reflective layer 6, which has a better light shaping and focusing effect, and can better improve the light extraction efficiency of the LED chip. That is, as Figure 5 As shown, during the manufacturing process, continuous first protrusions 51 are provided so that the grooves on the reflective layer are continuous.

[0068] In a preferred embodiment, if Figure 1 , 7As shown, in the projection plane parallel to the first direction D, the endpoints of the projection contour lines of two adjacent second protrusions 81 coincide. That is, the second protrusions 81 are continuous without any gaps in between, so that as many second protrusions 81 as possible are formed on the intermediate layer 8, which can better improve the light extraction efficiency of the LED chip.

[0069] In a preferred embodiment, the reflective layer 6 is a metal reflective mirror or a dielectric reflective mirror. Preferably, when the reflective layer 6 is a metal reflective mirror, it can be a combination of one or more of a gold mirror, a silver mirror, an aluminum mirror, and a molybdenum mirror; when the reflective layer 6 is a dielectric reflective mirror, it can be a distributed Bragg reflector or a photonic crystal structure with a wide bandgap.

[0070] In a preferred embodiment, if Figure 8 As shown, the LED chip further includes a current spreading layer 9 located below the first passivation layer 5 and covering the surface of the second semiconductor layer 4 facing away from the active layer 3. The current spreading layer 9 includes but is not limited to ITO.

[0071] In a preferred embodiment, if Figure 1 , 8 As shown, the LED chip also includes a first contact electrode 30 and a second contact electrode 40. The first contact electrode 30 is located on the surface of the first semiconductor layer 2 away from the active layer 3; the second contact electrode 40 is located on the surface of the second semiconductor layer 4 away from the active layer 3 or the surface of the current spreading layer 9 away from the active layer 3. The first electrode 10 is connected to the first contact electrode 30 through a through hole penetrating the first passivation layer 5, the reflective layer 6 and the second passivation layer 7; the second electrode 20 is connected to the second contact electrode 40 through a through hole penetrating the first passivation layer 5, the reflective layer 6 and the second passivation layer 7. It should be understood that the illustration of this application is an example of a reflective layer being a distributed Bragg reflector. In the remaining embodiments, when the reflective layer is a metal reflector, the first electrode 10 and the second electrode 20 should be insulated and isolated from the reflective layer 6.

[0072] The present application also provides a method for manufacturing an LED chip, such as Figure 8 -17, which includes the following steps:

[0073] S01: Provide a substrate 1. The substrate 1 includes but is not limited to a sapphire substrate 1, and is preferably a flat sapphire substrate 1.

[0074] S02: A first-type semiconductor layer 2, an active layer 3, a second-type semiconductor layer 4, a first passivation layer 5, a reflective layer 6, and a second passivation layer 7 are sequentially grown on the surface of one side of the substrate 1 along a first direction D; the first direction D is perpendicular to the substrate 1 and points from the substrate 1 to the active layer 3. A plurality of grooves arranged in an array are made on the side of the reflective layer 6 close to the first passivation layer 5, the opening of each groove faces the first passivation layer 5, and the groove wall of each groove is a curved surface, so as to shape and converge the light entering the groove and then reflect it to the light-emitting surface. .

[0075] Preferably, a plurality of first protrusions 51 arranged in an array are formed on the surface of the first passivation layer 5 facing away from the active layer 3 , and each first protrusion 51 protrudes along the first direction D; the reflective layer 6 contacts each first protrusion 51 of the first passivation layer 5 to form a groove.

[0076] Preferably, the groove wall of the groove is a parabola.

[0077] Preferably, the reflective layer 6 is a metal reflective mirror or a dielectric reflective mirror. When the reflective layer 6 is a metal reflective mirror, it can be a combination of one or more of a gold mirror, a silver mirror, an aluminum mirror, and a molybdenum mirror; when the reflective layer 6 is a dielectric reflective mirror, it can be a distributed Bragg reflector or a photonic crystal structure with a wide bandgap.

[0078] Preferably, a current spreading layer 9 is provided below the first passivation layer 5 , and the current spreading layer 9 covers the surface of the second-type semiconductor layer 4 facing away from the active layer 3 .

[0079] Further optionally, a first contact electrode 30 is provided on the first-type semiconductor layer 2 , and a second contact electrode 40 is provided on the current spreading layer 9 .

[0080] S03: manufacturing a first electrode 10 electrically connected to the first-type semiconductor layer 2 .

[0081] S04: manufacturing a second electrode 20 electrically connected to the second-type semiconductor layer 4 .

[0082] In a preferred embodiment, the method for manufacturing the LED chip further includes:

[0083] S05: an intermediate layer 8 is formed on the surface of the substrate 1 away from the active layer 3; the refractive index of the intermediate layer 8 is less than the refractive index of the substrate 1 and greater than the refractive index of air. A plurality of second protrusions 81 arranged in an array are provided on the surface of the intermediate layer 8 away from the active layer 3; the second protrusions 81 protrude in a direction away from the first direction D; after the outgoing light enters the intermediate layer 8, the second protrusions 81 make the reflection direction of the outgoing light that meets the reflection condition deviate to the focus of the groove wall of the groove in the reflective layer 6, so as to reduce the incident angle of the outgoing light when it reaches the intermediate layer 8 for the second time so that it can be output.

[0084] Taking the LED chip further provided with a current spreading layer 9, a first contact electrode 30 and a second contact electrode 40 as an example, step S02 specifically includes:

[0085] S021: Fig. 9 As shown, a first-type semiconductor layer 2 , an active layer 3 and a second-type semiconductor layer 4 are grown on a substrate 1 .

[0086] S022: Spin-coat photoresist on the upper surface of the second semiconductor layer 4, prepare a MESA pattern after exposure and development, and then use inductively coupled plasma etching (ICP) to etch the area of ​​the epitaxial layer surface not covered by the photoresist to expose the first semiconductor layer 2. The etching depth is 5000-25000 angstroms. The gases used for etching are: chlorine (Cl2), boron trichloride (BCl3), argon (Ar). After the etching is completed, remove the remaining photoresist. Fig.10 As shown, a groove exposing the first type semiconductor layer 2 is formed by etching.

[0087] S023: Fig.11 As shown, a layer of photoresist is spin-coated on the exposed surface of the epitaxial layer, and after exposure and development, a dry deep etching is performed using an ICP machine until the substrate 1 is exposed, forming an insulating trench 80 (ISO) to separate each core particle. The etching depth is 40000-60000 angstroms, including the end value. Chlorine (Cl2), boron trichloride (BCl3), and argon (Ar) are selected as etching gases, and the remaining photoresist is removed after the etching is completed.

[0088] S024: Fig.12 As shown, a layer of current spreading layer material is sputtered on the surface of the second semiconductor layer 4 by plasma magnetron sputtering; then, photoresist is spin-coated, and a current spreading layer 9 pattern is prepared after exposure and development; excess current spreading layer material is wet-etched by etching liquid to complete the preparation of the current spreading layer 9, and excess photoresist is removed after the preparation is completed. Among them, the current spreading layer 9 includes but is not limited to ITO.

[0089] S025: Fig.13 As shown, a layer of photoresist is prepared by spin coating, and the patterns of the first contact electrode 30 and the second contact electrode 40 are prepared through exposure and development. The first contact electrode 30 and the second contact electrode 40 are evaporated by electron beam evaporation. The evaporated material will evenly cover the entire surface. The electrostatic film tearing method is used to remove excess evaporated material, leaving only the first contact electrode 30 and the second contact electrode 40. Then, a stripping procedure is performed to remove the residual photoresist.

[0090] S026: Fig.14As shown, the first passivation layer 5 is prepared by enhanced plasma chemical vapor deposition (PECVD), with a thickness of 10000-14000 angstroms, including endpoint values. The first passivation layer 5 can be silicon nitride, and the refractive index of silicon nitride is controlled to be between 2-2.2 by adjusting the gas molar ratio and radio frequency power parameters in the reaction chamber. Afterwards, a layer of photoresist is prepared by spin coating and part of the solvent is removed by soft baking to form a plastic glue layer. The hard template (silicon material or sapphire material) used to make the first protrusion 51 array is used again to carry out nanoimprinting to transfer the morphology on the template to the photoresist, and the photoresist is hardened by baking. Then, the photoresist morphology is transferred to the first passivation layer 5 by ICP dry etching, and the first protrusion 51 arranged in array is formed thereon. The etching gases selected are carbon tetrafluoride CF4, trifluoromethane CHF3, argon Ar and oxygen O2. High vertical etching selectivity is achieved by adjusting the ratio of CHF3 and Ar gases, and a suitable etching selectivity is achieved by adjusting the O2 ratio, so that the photoresist morphology can be completely transferred to the first passivation layer 5.

[0091] Preferably, if Figure 3 , 4 As shown in FIG. 5 , the surface of the first protrusion 51 is formed by rotating the first line segment 502 around its axis of symmetry; the first line segment 502 is selected from the line segment of the parabola 50 including the vertex, and the axis of symmetry coincides with the axis of symmetry 501 of the parabola 50 .

[0092] S027: Fig.15 As shown, a reflective layer 6 is deposited on the first passivation layer 5 by reactive plasma deposition (RPT) or electron beam thermal evaporation. In this application, a distributed Bragg reflector is taken as an example. The reflective layer 6 is alternately deposited layer by layer with a high refractive index Ti3O5 and a low refractive index SiO2. The thickness of each layer is about 1000 angstroms. 39 layers are alternately deposited to form a distributed Bragg reflector, and finally a curved reflective surface with grooves is formed on the surface of the reflective layer 6 facing the active layer 3. Similarly, metal reflectors such as gold mirrors, silver mirrors and aluminum mirrors can be prepared by thermal evaporation. Afterwards, a second passivation layer is deposited by PECVD with a thickness of 3000-3500 angstroms, including the end point value, as a core protection layer to increase the reliability of the core. Among them, the number of alternating layers and the thickness of each layer of the distributed Bragg reflector are only exemplary descriptions, which can be adjusted according to actual needs.

[0093] Preferably, in a projection plane parallel to the first direction D, endpoints of projection contour lines of two adjacent grooves coincide.

[0094] Step S03 specifically includes: etching the first passivation layer 5, the reflective layer 6 and the second passivation layer 7 to form a through hole exposing the first contact electrode 30, and forming the first electrode 10 in the through hole.

[0095] Step S04 specifically includes: etching the first passivation layer 5, the reflective layer 6 and the second passivation layer 7 to form a through hole exposing the second contact electrode 40, and forming the second electrode 20 in the through hole.

[0096] Among them, Fig.16 , 17 As shown, steps S03 and S04 can also be performed together, that is, a layer of photoresist is spin-coated on the surface of the second passivation layer 7, and a through-hole pattern is prepared after exposure and development. The first passivation layer 5, the reflective layer 6 and the second passivation layer 7 are dry-etched using ICP to etch through holes that expose the first contact electrode 30 and the second contact electrode 40 respectively, and the photoresist is removed by a stripping procedure. After that, a photoresist is spin-coated on the surface again, and the first electrode 10 and the second electrode 20 pattern are prepared by exposure and development, and then a metal layer is prepared by electron beam evaporation, and excess metal is removed by a lift-off method to form the first electrode 10 and the second electrode 20.

[0097] Step S05 specifically includes: thinning and smoothing the side of the substrate 1 away from the active layer 3 by grinding and polishing. Then, a layer of intermediate layer material is first deposited on the surface of the substrate 1 away from the active layer 3, and then a layer of photoresist is spin-coated, and an array pattern of second protrusions 81 is prepared by exposure and development. Then, each second protrusion 81 is prepared by ICP dry etching to form a Figure 8 The intermediate layer 8 is shown. Etching gases include carbon tetrafluoride CF4, trifluoromethane CHF3, and argon Ar. The residual photoresist is then removed by a stripping process.

[0098] Preferably, the surface of the second protrusion 81 is formed by rotating the second line segment 503 around the first axis 60; the second line segment 503 is selected from the off-axis segment of the parabola 50 located on one side of the symmetry axis 501; the first axis 60 intersects with the endpoint of the second line segment 503 close to the symmetry axis 501 and is parallel to the symmetry axis 501.

[0099] Preferably, in the projection plane parallel to the first direction D, the endpoints of the projection contour lines of two adjacent second protrusions 81 coincide with each other.

[0100] Those skilled in the art should understand that, in the disclosure of the present invention, the terms "horizontal", "vertical", "upper", "lower", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.

[0101] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0102] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized in that: include: substrate; A first-type semiconductor layer, an active layer, a second-type semiconductor layer, a first passivation layer, a reflective layer, and a second passivation layer are arranged on a surface of one side of the substrate and arranged in sequence along a first direction; the first direction is perpendicular to the substrate and points from the substrate to the active layer; A plurality of grooves arranged in an array are provided on one side of the reflective layer close to the first passivation layer, the opening of each groove faces the first passivation layer, and the groove wall of each groove is a curved surface, so as to shape and converge the light entering the groove and reflect it to the light emitting surface; a first electrode electrically connected to the first-type semiconductor layer; A second electrode is electrically connected to the second-type semiconductor layer.

2. The LED chip according to claim 1, characterized in that: A surface of the first passivation layer facing away from the active layer is provided with a plurality of first protrusions arranged in an array, each of the first protrusions protruding along the first direction; The reflective layer contacts each of the first protrusions of the first passivation layer to form the groove.

3. The LED chip according to claim 1, characterized in that: The groove wall of the groove is a parabola.

4. The LED chip according to claim 2, characterized in that: The surface of the first protrusion is formed by rotating the first line segment around its axis of symmetry; The first line segment is selected from a line segment of a parabola including a vertex, and the axis of symmetry coincides with the axis of symmetry of the parabola.

5. The LED chip according to claim 3, characterized in that: It also includes an intermediate layer located on the surface of the substrate away from the active layer; the refractive index of the intermediate layer is smaller than the refractive index of the substrate and larger than the refractive index of the air; A surface of the intermediate layer facing away from the active layer is provided with a plurality of second protrusions arranged in an array; The second protrusion protrudes in a direction away from the first direction; after the outgoing light enters the intermediate layer, the second protrusion makes the reflection direction of the outgoing light that meets the reflection condition deviate toward the focus of the groove wall in the reflective layer, so as to reduce the incident angle of the outgoing light when it reaches the intermediate layer for the second time so that it can be output.

6. The LED chip according to claim 5, characterized in that: The surface of the second protrusion is formed by rotating the second line segment around the first axis; The second line segment is selected from an off-axis segment of the parabola located on one side of the symmetry axis; the first axis intersects with the endpoint of the second line segment close to the symmetry axis and is parallel to the symmetry axis.

7. The LED chip according to claim 1, characterized in that: In a projection plane parallel to the first direction, endpoints of projection contour lines of two adjacent grooves coincide.

8. The LED chip according to claim 5, characterized in that: In a projection plane parallel to the first direction, endpoints of projection contour lines of two adjacent second protrusions coincide.

9. The LED chip according to claim 1, characterized in that: The reflective layer is a metal reflective mirror or a dielectric reflective mirror.

10. The LED chip according to claim 9, characterized in that: When the reflective layer is the metal reflective mirror, it can be a combination of one or more of a gold mirror, a silver mirror, an aluminum mirror, and a molybdenum mirror; when the reflective layer is the dielectric reflective mirror, it can be a distributed Bragg reflector or a photonic crystal structure with a wide bandgap.

11. A method for manufacturing an LED chip, characterized in that: The following steps are involved: providing a substrate; A first-type semiconductor layer, an active layer, a second-type semiconductor layer, a first passivation layer, a reflective layer, and a second passivation layer are sequentially grown on a surface of one side of the substrate along a first direction; the first direction is perpendicular to the substrate and points from the substrate to the active layer; a plurality of grooves arranged in an array are made on a side of the reflective layer close to the first passivation layer, the opening of each groove faces the first passivation layer, and the groove wall of each groove is a curved surface, so as to shape and converge the light entering the groove and then reflect it to the light emitting surface; Making a first electrode electrically connected to the first-type semiconductor layer; A second electrode electrically connected to the second-type semiconductor layer is fabricated.

12. The method for manufacturing an LED chip according to claim 11, characterized in that: The groove wall of the groove is a parabola.

13. A method for manufacturing an LED chip according to claim 12, characterized in that: The method further comprises manufacturing an intermediate layer on a surface of the substrate away from the active layer; the refractive index of the intermediate layer is smaller than the refractive index of the substrate and larger than the refractive index of the air; A surface of the intermediate layer facing away from the active layer is provided with a plurality of second protrusions arranged in an array; The second protrusion protrudes in a direction away from the first direction; after the outgoing light enters the intermediate layer, the second protrusion makes the reflection direction of the outgoing light that meets the reflection condition deviate toward the focus of the groove wall in the reflective layer, so as to reduce the incident angle of the outgoing light when it reaches the intermediate layer for the second time so that it can be output.

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