Memory controller, memory system, method and storage medium for managing logical-to-physical mapping table

Abstract

In certain aspects, a memory controller includes a logical-to-physical (L2P) search engine. The L2P search engine is configured to maintain an L2P mapping table that maps logical addresses to physical addresses, respectively. The L2P search engine is further configured to organize the physical addresses mapped by the L2P mapping table into address categories based on the at least one address boundary.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method of operating the memory device. Background Art

[0002] A solid-state drive (SSD) is a non-volatile data storage device that has gained popularity in recent years due to its many advantages over traditional hard disk drives (HDDs), such as faster read and write speeds, durability and reliability, reduced power consumption, silent operation, and smaller form factors. SSDs typically use NAND flash memory for non-volatile storage. Some SSDs (e.g., enterprise-class SSDs) may also use volatile memory (e.g., dynamic random-access memory (DRAM)) to enhance their performance, allowing faster access to data and more efficient processing of read and write operations. Summary of the invention

[0003] In one aspect, the memory controller includes a logical-to-physical (L2P) search engine. The L2P search engine is configured to maintain an L2P mapping table that maps logical addresses to physical addresses, respectively. The L2P search engine is further configured to organize physical addresses mapped by the L2P mapping table into address categories based on at least one address boundary.

[0004] In some implementations, the at least one address boundary includes a first address boundary; and the memory controller further includes a first register configured to store the first address boundary.

[0005] In some implementations, the address categories include: a first category of user data addresses mapped to a storage area of ​​a user zone of a non-volatile memory device; and a second category of volatile memory addresses mapped to a storage block of a volatile memory device.

[0006] In some implementations, the L2P mapping table maps a first group of logical addresses in the logical addresses to a first group of physical addresses associated with a storage area of ​​a user area of ​​a non-volatile memory device, and the first category of user data addresses includes the first group of physical addresses associated with the storage area of ​​the user area of ​​the non-volatile memory device. The L2P mapping table also maps a second group of logical addresses in the logical addresses to identifiers (IDs) of storage blocks of a volatile memory device, and the second category of volatile memory addresses includes the IDs of storage blocks of the volatile memory device.

[0007] In some implementations, each user data address in the first category is greater than a first address boundary; and each volatile memory address in the second category is less than the first address boundary.

[0008] In some implementations, the at least one address boundary further includes a second address boundary lower than the first address boundary; and the memory controller further includes a second register configured to store the second address boundary.

[0009] In some implementations, the address categories further include: a third category of dedicated memory addresses mapped to a storage area of ​​the system area of ​​the non-volatile memory device. The L2P mapping table further maps a third group of logical addresses in the logical address to a third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device, and the third category of dedicated memory addresses includes a third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device.

[0010] In some implementations, each volatile memory address in the second category is greater than or equal to the second address boundary and less than or equal to the first address boundary; and each special memory address in the third category is less than the second address boundary.

[0011] In some implementations, the memory controller further includes: a volatile memory device interface operably coupled to the volatile memory device; and a nonvolatile memory device interface operably coupled to the nonvolatile memory device.

[0012] In some implementations, the volatile memory device includes dynamic random access memory (DRAM) and the non-volatile memory device includes NAND flash memory.

[0013] In some implementations, in response to a read request indicating retrieval of a segment of data associated with a logical address, the L2P search engine is further configured to: determine an address of an entry in the L2P mapping table based on the logical address; identify a physical address stored in the entry in the L2P mapping table based on the address of the entry; determine an address category into which the physical address is classified based on the first address boundary and the second address boundary; and indicate, based on the address category, to obtain the segment of data from one of the volatile storage device and the non-volatile storage device.

[0014] In some implementations, to determine the address category, the L2P search engine is further configured to: in response to the physical address being greater than the first address boundary, determine that the physical address is classified as a first category of user data addresses, wherein the first category of user data addresses are mapped to a storage area of ​​a user zone of a non-volatile memory device. In response to the physical address being lower than the second address boundary, the L2P search engine is further configured to: determine that the physical address is classified as a third category of dedicated memory addresses, wherein the third category of dedicated memory addresses are mapped to a storage area of ​​a system zone of a non-volatile memory device. Or in response to the physical address being equal to or greater than the second address boundary and equal to or less than the first address boundary, the L2P search engine is further configured to: determine that the physical address is classified as a second category of volatile memory addresses, wherein the second category of volatile memory addresses are mapped to a storage block of a volatile memory device.

[0015] In some implementations, in order to instruct to obtain a segment of data, the L2P search engine is further configured to: in response to the physical address being classified as a dedicated memory address of the third category or a user data address of the first category, instruct to read the segment of data from the non-volatile memory device using the physical address. Or in response to the physical address being classified as a volatile memory address of the second category, the L2P search engine is further configured to: instruct to obtain the segment of data from the volatile memory device using the physical address.

[0016] In another aspect, a memory system includes: a non-volatile memory device including storage areas, each of the storage areas being associated with a physical address; and a memory controller operably coupled to the non-volatile memory device. The memory controller is configured to control the non-volatile memory device. The memory controller includes an L2P search engine. The L2P search engine is configured to: maintain an L2P mapping table that maps logical addresses to physical addresses, respectively; and organize physical addresses mapped by the L2P mapping table into address categories based on at least one address boundary.

[0017] In some implementations, the at least one address boundary includes a first address boundary; and the memory controller further includes a first register configured to store the first address boundary.

[0018] In some implementations, the address categories include: a first category of user data addresses mapped to a storage area of ​​a user zone of a non-volatile memory device; and a second category of volatile memory addresses mapped to a storage block of a volatile memory device.

[0019] In some implementations, the L2P mapping table maps a first group of logical addresses in the logical address to a first group of physical addresses associated with a storage area of ​​a user area of ​​the non-volatile memory device, and the first category of user data addresses includes the first group of physical addresses associated with the storage area of ​​the user area of ​​the non-volatile memory device. The L2P mapping table also maps a second group of logical addresses in the logical address to an ID of a storage block of a volatile memory device, and the second category of volatile memory addresses includes the ID of the storage block of the volatile memory device.

[0020] In some implementations, each user data address in the first category is greater than a first address boundary; and each volatile memory address in the second category is less than the first address boundary.

[0021] In some implementations, the L2P mapping table is stored in a volatile storage device.

[0022] In some implementations, the at least one address boundary further includes a second address boundary lower than the first address boundary; and the memory controller further includes a second register configured to store the second address boundary.

[0023] In some implementations, the address categories further include: a third category of dedicated memory addresses mapped to a storage area of ​​the system area of ​​the non-volatile memory device. The L2P mapping table further maps a third group of logical addresses in the logical address to a third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device, and the third category of dedicated memory addresses includes a third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device.

[0024] In some implementations, each volatile memory address in the second category is greater than or equal to the second address boundary and less than or equal to the first address boundary; and each special memory address in the third category is less than the second address boundary.

[0025] In some implementations, the memory controller further includes: a volatile memory device interface operably coupled to the volatile memory device; and a nonvolatile memory device interface operably coupled to the nonvolatile memory device.

[0026] In some implementations, the volatile storage device includes DRAM and the non-volatile storage device includes NAND flash memory.

[0027] In some implementations, in response to a read request indicating retrieval of a segment of data associated with a logical address, the L2P search engine is further configured to: determine an address of an entry in the L2P mapping table based on the logical address; identify a physical address stored in the entry in the L2P mapping table based on the address of the entry; determine an address category into which the physical address is classified based on the first address boundary and the second address boundary; and indicate, based on the address category, to obtain the segment of data from one of the volatile storage device and the non-volatile storage device.

[0028] In some implementations, to determine the address category, the L2P search engine is further configured to: in response to the physical address being greater than the first address boundary, determine that the physical address is classified as a first category of user data addresses, wherein the first category of user data addresses are mapped to a storage area of ​​a user zone of a non-volatile memory device. In response to the physical address being lower than the second address boundary, the L2P search engine is further configured to: determine that the physical address is classified as a third category of dedicated memory addresses, wherein the third category of dedicated memory addresses are mapped to a storage area of ​​a system zone of a non-volatile memory device. Or in response to the physical address being equal to or greater than the second address boundary and equal to or less than the first address boundary, the L2P search engine is further configured to: determine that the physical address is classified as a second category of volatile memory addresses, wherein the second category of volatile memory addresses are mapped to a storage block of a volatile memory device.

[0029] In some implementations, in order to instruct to obtain a segment of data, the L2P search engine is further configured to: in response to the physical address being classified as a dedicated memory address of the third category or a user data address of the first category, instruct to read the segment of data from the non-volatile memory device using the physical address. Or in response to the physical address being classified as a volatile memory address of the second category, the L2P search engine is further configured to: instruct to obtain the segment of data from the volatile memory device using the physical address.

[0030] In another aspect, a method for operating a memory controller is provided. An L2P mapping table is maintained, and the L2P mapping table maps logical addresses to physical addresses respectively. The physical addresses mapped by the L2P mapping table are organized into address categories based on at least one address boundary.

[0031] In some implementations, the at least one address boundary includes a first address boundary stored in a first register.

[0032] In some implementations, the address categories include: a first category of user data addresses mapped to a storage area of ​​a user zone of a non-volatile memory device; and a second category of volatile memory addresses mapped to a storage block of a volatile memory device.

[0033] In some implementations, the L2P mapping table maps a first group of logical addresses in the logical address to a first group of physical addresses associated with a storage area of ​​a user area of ​​the non-volatile memory device, and the first category of user data addresses includes the first group of physical addresses associated with the storage area of ​​the user area of ​​the non-volatile memory device. The L2P mapping table also maps a second group of logical addresses in the logical address to an ID of a storage block of a volatile memory device, and the second category of volatile memory addresses includes the ID of the storage block of the volatile memory device.

[0034] In some implementations, each user data address in the first category is greater than a first address boundary; and each volatile memory address in the second category is less than the first address boundary.

[0035] In some implementations, the at least one address boundary further includes a second address boundary that is lower than the first address boundary.

[0036] In some implementations, the address categories further include: a third category of dedicated memory addresses mapped to a storage area of ​​the system area of ​​the non-volatile memory device. The L2P mapping table further maps a third group of logical addresses in the logical address to a third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device, and the third category of dedicated memory addresses includes a third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device.

[0037] In some implementations, each volatile memory address in the second category is greater than or equal to the second address boundary and less than or equal to the first address boundary; and each special memory address in the third category is less than the second address boundary.

[0038] In some implementations, the volatile storage device includes DRAM and the non-volatile storage device includes NAND flash memory.

[0039] In some implementations, in response to a read request indicating retrieval of a segment of data associated with a logical address, an address of an entry in an L2P mapping table is determined based on the logical address. A physical address stored in the entry in the L2P mapping table is identified based on the address of the entry. An address category into which the physical address is classified is determined based on a first address boundary and a second address boundary. Based on the address category, an indication is given to fetch the segment of data from one of a volatile storage device and a non-volatile storage device.

[0040] In some implementations, determining the address category includes: in response to the physical address being greater than a first address boundary, determining that the physical address is classified as a first category of user data addresses, wherein the first category of user data addresses are mapped to a storage area of ​​a user zone of a non-volatile memory device. In response to the physical address being lower than a second address boundary, determining the address category includes: determining that the physical address is classified as a third category of dedicated memory addresses, wherein the third category of dedicated memory addresses are mapped to a storage area of ​​a system zone of a non-volatile memory device. Or in response to the physical address being equal to or greater than the second address boundary and equal to or less than the first address boundary, determining the address category includes: determining that the physical address is classified as a second category of volatile memory addresses, wherein the second category of volatile memory addresses are mapped to a storage block of a volatile memory device.

[0041] In some implementations, indicating to obtain a fragment of data includes: in response to the physical address being classified as a dedicated memory address of the third category or a user data address of the first category, indicating to use the physical address to read the fragment of data from a non-volatile memory device; or in response to the physical address being classified as a volatile memory address of the second category, indicating to use the physical address to obtain a fragment of data from a volatile memory device.

[0042] In another aspect, a non-transitory computer-readable storage medium is disclosed that stores instructions. The instructions, when executed by a memory controller of a memory system, cause the memory controller to perform a method. The method includes maintaining an L2P mapping table that maps logical addresses to physical addresses, respectively. The method also includes organizing physical addresses mapped by the L2P mapping table into address categories based on at least one address boundary. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated herein and constitute a part of the specification, illustrate various aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the relevant art to make and use the disclosure.

[0044] Figure 1 A block diagram of a system including a memory system according to some aspects of the present disclosure is shown.

[0045] Figure 2A A diagram showing a memory card having a storage device according to some aspects of the present disclosure is shown.

[0046] Figure 2B A diagram showing an SSD having a storage device according to some aspects of the present disclosure.

[0047] Figure 3 A block diagram of a memory controller according to some aspects of the present disclosure is shown.

[0048] Figure 4 A schematic diagram of a NAND flash memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0049] Figure 5 A schematic diagram of a DRAM device including peripheral circuits according to some aspects of the present disclosure is shown.

[0050] Figure 6 A detailed schematic diagram of a memory system that manages an L2P mapping table and performs data searches based on the L2P mapping table according to some aspects of the present disclosure is shown.

[0051] Figure 7 An L2P mapping table according to some aspects of the present disclosure is shown.

[0052] Figure 8 A flow chart of a method for operating a memory controller according to some aspects of the present disclosure is shown.

[0053] Fig. 9 A flow chart of a method for processing a write request according to some aspects of the present disclosure is shown.

[0054] Fig.10 A flow chart of a method for processing a read request according to some aspects of the present disclosure is shown.

[0055] Fig.11A An example of organizing physical addresses mapped by an L2P mapping table according to some aspects of the present disclosure is shown.

[0056] Fig. 11B Another example of organizing physical addresses mapped by an L2P mapping table according to some aspects of the present disclosure is shown.

[0057] Fig.12 A flow chart of another method for operating a memory controller according to some aspects of the present disclosure is shown.

[0058] Fig.13A The use of some aspects of the present disclosure is shown Fig.11A An example method is a flow chart of an implementation of a method for processing a read request when a physical address mapped by an L2P mapping table is organized.

[0059] Fig. 13B The use of some aspects of the present disclosure is shown Fig. 11B An example method is a flow chart of an implementation of another method for processing a read request when a physical address mapped by an L2P mapping table is organized.

[0060] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0061] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, again, terms such as "a", "an", or "the" can be understood to convey singular usage or to convey plural usage, which depends at least in part on the context. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can instead allow the presence of additional factors that are not necessarily explicitly described, again, which depends at least in part on the context.

[0062] In an SSD scenario (eg, an enterprise-class SSD), the mapping relationship between a logical address and a physical address is recorded by an L2P mapping table, which may be stored on a DRAM of the SSD for data tracking purposes. Logical addresses (e.g., logical block addresses (LBAs)) may be used as indexes for various entries of the L2P mapping table. The content of each entry of the L2P mapping table may be a physical address (e.g., a physical page address (PPA)) corresponding to the logical address of the entry. In some examples, the size of the L2P mapping table is equal to 1 / 1024 of the drive capacity of the SSD, which is large and may occupy a large amount of storage space of the DRAM. The ratio of the size of the L2P mapping table to the drive capacity of the SSD is 1 / 1024, because the L2P mapping table may use a 4-byte address data width to represent 4KiB of user data on the SSD. For a small-capacity SSD, a 4-byte address data width may be sufficient to represent the physical address of the corresponding physical space of the SSD. However, for a large-capacity (e.g., 2TB, 4TB, etc.) SSD (e.g., an enterprise-class SSD), a 4-byte address data width may not be sufficient to represent the physical address of the corresponding physical space of the SSD, especially when a portion of the 4 bytes (e.g., one bit of the 32 bits) is reserved for marking the type of the physical address.

[0063] In order to solve one or more of the above problems, the present disclosure introduces an address management scheme for an L2P mapping table, which does not require any bits to be reserved for marking the type or purpose of a physical address. For example, an L2P mapping table can map multiple logical addresses to multiple physical addresses. The address management scheme disclosed herein can organize multiple physical addresses mapped by an L2P mapping table into multiple address categories based on at least one address boundary (e.g., a first address boundary and a second address boundary). The multiple address categories may include at least one of the following: (1) a first category of user data addresses mapped to a storage area of ​​a user area of ​​a non-volatile memory device, (2) a second category of volatile memory addresses (e.g., an ID of a storage block of a cache or DRAM), or (3) a third category of dedicated memory addresses mapped to a storage area of ​​a system area of ​​a non-volatile memory device. Since the first address boundary and the second address boundary can be used to determine the category of the physical address, there is no need to reserve bits for distinguishing different categories of physical addresses. Therefore, all bits in the address data width (e.g., 32 bits) can be used to represent a larger physical space. The size of the L2P mapping table can be reduced, and thus the size of DRAM in an enterprise-level SSD can also be reduced, thereby reducing the cost of DRAM.

[0064] Figure 1 1 shows a block diagram of a system 100 including a memory system 102 according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, the system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data to or receive data (also known as user data or host data) from the memory system 102. The memory system 102 may be a storage device product (e.g., an SSD) integrating a memory controller 106 and one or more memory devices 104.

[0065] The memory device 104 may be any memory device disclosed in the present disclosure, including a non-volatile memory device (e.g., a NAND flash memory device). In some implementations, the memory device 104 also includes one or more volatile memory devices (e.g., a DRAM device or a static random access memory (SRAM) device).

[0066] According to some implementations, the memory controller 106 is operably coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the memory controller 106 is designed to operate in a high duty cycle environment, where an SSD or an embedded multimedia card (eMMC) is used as a data storage device for mobile devices (e.g., smart phones, tablet computers, laptop computers, etc.) and enterprise-level storage device arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, program / write, and / or erase operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, L2P address translation, wear leveling, etc. In some implementations, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. Any other suitable functions (e.g., formatting the memory device 104) may also be performed by the memory controller 106. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with an external device through at least one of various interface protocols (for example, a non-volatile memory express (NVMe) protocol, an NVMe-over-fabric (NVMe-oF) protocol, a PCI-express (PCI-E) protocol, a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronic (IDE) protocol, a FireWire protocol, etc.).

[0067] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of final electronic products. Figure 2A In one example shown in FIG. 1 , the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The host 108 in the memory card connector 204 is coupled. Figure 2B In another example shown in FIG. 1 , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (eg, Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202. In some implementations, the memory system 102 is implemented as an SSD 206, which (e.g., an enterprise-class SSD) includes both a non-volatile memory device and a volatile memory device as the memory device 104.

[0068] Figure 3 1 shows a block diagram of a memory controller 300 according to some aspects of the present disclosure. The memory controller 300 may be Figure 1 An example of a memory controller 106 in FIG. Figure 3 As shown in FIG. 3 , the memory controller 300 may include a processing unit 308, a cache 310, and a read-only memory (ROM) 311. In some implementations, the processing unit 308 is implemented by a microprocessor (e.g., a digital signal processor (DSP)) or a microcontroller (also known as a microcontroller unit (MCU)) that executes firmware and / or software modules to perform various functions described herein. The various firmware modules in the memory controller 300 described herein may be implemented as firmware codes or instructions stored in the ROM 311 and executed by the processing unit 308. In some implementations, the processing unit 308 includes one or more hardware circuits, such as fixed logic units (e.g., logic gates), multiplexers, flip-flops, state machines, field-programmable gate arrays (FPGAs), and programmable logic devices (PLDs). For example, the hardware circuit may include a dedicated circuit (e.g., an application-specific integrated circuit (ASIC)) for a given logic function, which is known when the device is manufactured.

[0069] like Figure 3As shown in FIG. 1 , the memory controller 300 may further include various input / output (I / O) interfaces (interfaces, I / Fs), such as a flash memory interface 312 operably coupled to a flash memory 302 (e.g., an example of a non-volatile memory device), a DRAM interface 314 operably coupled to a DRAM 304 (e.g., an example of a volatile memory device), and a host interface 316 operably coupled to a host 306 (e.g., an example of the host 108). The flash memory interface 312, the DRAM interface 314, and the host interface 316 may be configured to transmit data, commands, clocks, or any suitable signals between the processing unit 308 and the flash memory 302, the DRAM 304, and the host 306, respectively. The flash memory interface 312, the DRAM interface 314, and the host interface 316 may implement any suitable communication protocol (e.g., NVMe protocol and PCI-E protocol, double data rate (DDR) protocol, to name a few) to facilitate data transmission, communication, and management.

[0070] As described above, both cache 310 and DRAM 304 can be considered as volatile memory devices that can be controlled and accessed by memory controller 300 in the memory system. Consistent with the scope of the present disclosure, cache can be implemented as part of the volatile memory device, for example, by cache 310 and / or DRAM 304. It is understood that although Figure 3 Cache 310 is shown as being located within memory controller 300 and DRAM 304 is shown as being located external to memory controller 300 , but in some examples, cache 310 and DRAM 304 may both be located within memory controller 300 or external to memory controller 300 .

[0071] Consistent with the scope of the present disclosure and as disclosed in detail below, the memory controller 300 may be configured to maintain an L2P mapping table that maps a plurality of logical addresses to a plurality of physical addresses, respectively. The memory controller 300 may also be configured to organize a plurality of physical addresses mapped by the L2P mapping table into a plurality of address categories based on at least one address boundary. In some implementations, the memory controller 300 may also include at least one register configured to store at least one address boundary. For example, the at least one address boundary may include a first address boundary and a second address boundary, and the at least one register may include a register 330 configured to store the first address boundary and a register 332 configured to store the second address boundary, respectively. In some other implementations, there may be no registers in the memory controller 300, and the memory controller 300 may receive the address boundaries from the host 306 via the host interface 316. In some other implementations, the at least one address boundary may be stored in the firmware of the memory controller 300, so that the memory controller 300 does not need to retrieve the at least one address boundary from any hardware device. The memory controller 300 will be referred to below. Figures 6 to 13B A more detailed description is given.

[0072] Figure 4 4 shows a schematic circuit diagram of a NAND flash memory device 400 including a peripheral circuit 402 according to some aspects of the present disclosure. The NAND flash memory device 400 may be Figure 3 An example of a flash memory 302 in the NAND flash memory device 400. The NAND flash memory device 400 may include a memory cell array 401 and a peripheral circuit 402 operably coupled to the memory cell array 401. The memory cells 406 in the memory cell array 401 are provided in the form of an array of memory strings 408, each of the memory strings 408 extending vertically above a substrate (not shown). In some implementations, each memory string 408 includes a plurality of memory cells 406 that are operably coupled in series and stacked vertically. Each memory cell 406 can hold a continuous analog value (e.g., a voltage or charge) that depends on the number of electrons trapped in the region of the memory cell 406. Each memory cell 406 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0073] In some implementations, each memory cell 406 is a single-level cell (SLC) having two possible levels (memory states), and can therefore store one bit of data. For example, the first state "0" can correspond to a first range of threshold voltages, and the second state "1" can correspond to a second range of threshold voltages. In some implementations, each memory cell 406 is an xLC capable of storing more than a single bit of data at more than four levels. For example, an xLC can store two bits per cell (aka, multi-level cell (MLC)), three bits per cell (aka, triple-level cell (TLC)), or four bits per cell (aka, quad-level cell (QLC)). Each xLC can be programmed to take a range of possible nominal storage values ​​(i.e., 2 of the N bits of data). N In some implementations, each storage unit 406 is set to 2 N One of the levels corresponds to a fragment of N-bit data, where N is an integer greater than 1. N may represent the total number of bits per cell. For example, for MLC, N=2, for TLC, N=3, or for QLC, N=4.

[0074] like Figure 4 As shown in , each storage string 408 may also include a source select gate (SSG) transistor 410 at its source end and a drain select gate (DSG) transistor 412 at its drain end. The SSG transistor 410 and the DSG transistor 412 may be configured to activate the selected storage string 408 (column of the array) during read and program operations. In some implementations, the sources of the storage strings 408 in the same block 404 are coupled through the same source line (SL) 414 (e.g., a common SL). In other words, according to some implementations, all storage strings 408 in the same block 404 have an array common source (ACS). According to some implementations, the drain of each storage string 408 is coupled to a corresponding bit line 416, and data can be read or written from the bit line 416 via an output bus (not shown). In some implementations, each storage string 408 is configured to be selected or deselected by applying a selection voltage or a deselection voltage to the gate of the corresponding DSG transistor 412 through one or more DSG lines 413 and / or applying a selection voltage or a deselection voltage to the gate of the corresponding SSG transistor 410 through one or more SSG lines 415.

[0075] like Figure 4 As shown in FIG. 4 , the memory string 408 can be organized into a plurality of blocks 404, each of which can have a common source line 414 (e.g., coupled to an ACS). In some implementations, each block 404 is a basic data unit for an erase operation, i.e., all memory cells 406 on the same block 404 are erased at the same time. To erase the memory cells 406 in a selected block 404, the source lines 414 coupled to the selected block 404 and to the unselected blocks 404 in the same plane as the selected block 404 can be biased with an erase voltage (Vers), e.g., a high positive bias voltage (e.g., 20 V or higher).

[0076] The memory cells 406 of adjacent memory strings 408 may be coupled by word lines 418, which select which row of memory cells 406 is affected by read and program operations. In some implementations, each word line 418 is coupled to a physical page 420 of memory cells 406, which is the basic data unit for read and write (program) operations. The size (in bits) of one physical page 420 may be related to the number of memory strings 408 coupled by word lines 418 in one block 404. Each word line 418 may include a plurality of control gates (gate electrodes) at each memory cell 406 in a corresponding physical page 420 and a gate line coupled to the control gates.

[0077] The peripheral circuit 402 may be operably coupled to the memory cell array 401 through the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 may include any suitable analog, digital, and mixed signal circuits to facilitate the operation of the memory cell array 401 by applying a voltage signal to each selected memory cell 406 through the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413 and / or sensing a current signal from each selected memory cell 406 through the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 may include various types of peripheral circuits formed using complementary metal-oxide-semiconductor (CMOS) technology.

[0078] Figure 5 5 shows a schematic circuit diagram of a DRAM device 500 including a peripheral circuit 502 according to some aspects of the present disclosure. The DRAM device 500 may be Figure 3500 is an example of a DRAM 304 in FIG. 500. DRAM device 500 may include a memory cell array 501 and a peripheral circuit 502 operably coupled to memory cell array 501. Memory cells 503 may be arranged in memory cell array 501 having rows and columns. DRAM device 500 requires periodic refreshing of memory cells 503. In some implementations, each memory cell 503 includes a capacitor 507 for storing 1 bit of data as a positive charge or a negative charge and a transistor 505 for controlling access to capacitor 507. That is, according to some implementations, as Figure 5 Each memory cell 503 shown in FIG. 5 is a one-transistor, one-capacitor (1T1C) cell.

[0079] The DRAM device 500 may include: a word line 504 coupling the peripheral circuit 502 and the memory cell array 501, the word line 504 being used to control the switch of the transistor 505 in the memory cell 503 located in one row; and a bit line 506 coupling the peripheral circuit 502 and the memory cell array 501, the bit line 506 being used to send data to the memory cell 503 located in one column and / or receive data from the memory cell 503 located in one column. That is, each word line 504 is coupled to a corresponding row of the memory cell 503, and each bit line 506 is coupled to a corresponding column of the memory cell 503. The gate of the transistor 505 may be coupled to the word line 504, one of the source and the drain of the transistor 505 may be coupled to the bit line 506, the other of the source and the drain of the transistor 505 may be coupled to one electrode of the capacitor 507, and the other electrode of the capacitor 507 may be coupled to the ground.

[0080] The peripheral circuit 502 may be coupled to the memory cell array 501 through the bit line 506, the word line 504, and any other suitable metal wiring. The peripheral circuit 502 may include any suitable circuit to facilitate the operation of the memory cell array 501 by applying a voltage signal to each memory cell 503 through the word line 504 and the bit line 506 and / or sensing a current signal from each memory cell 503 through the word line 504 and the bit line 506. The peripheral circuit 502 may include various types of peripheral circuits formed using CMOS technology.

[0081] Figure 6 A detailed schematic diagram of a memory system 600 for managing an L2P mapping table and performing data searches based on the L2P mapping table according to some aspects of the present disclosure is shown. The memory system 600 may be Figure 1 An example of a memory system 102 in FIG. Figure 6As shown in FIG. 6 , the memory system 600 may include a memory controller 601, a volatile memory device 602, and a non-volatile memory device 604. The memory controller 601 may be Figure 1 The volatile memory device 602 and the non-volatile memory device 604 may be an example of a memory controller 106 in FIG. Figure 1 In some implementations, the volatile memory device 602 includes a DRAM (e.g., Figure 5 DRAM device 500 in ), and non-volatile memory device 604 includes a NAND flash memory (e.g., Figure 4 In some implementations, the memory controller 601 is further configured to cache segments of host / user data in the volatile memory device 602 or flush the segments of the host / user data from the volatile memory device 602 to the non-volatile memory device 604.

[0082] In order to enable searching and accessing of data, the non-volatile memory device 604 may be divided into a plurality of storage areas 605, each of which has a unique physical address. In some implementations, each storage area 605 includes one or more logical pages (e.g., a portion (e.g., 1 / 2, 1 / 4, or 1 / 8) of a physical page 420 of the NAND flash memory device 400). For example, the size of each storage area 605 may be 4096 bytes. It will be appreciated that the storage area 605 may correspond to any suitable group of storage cells other than a page in the non-volatile memory device 604 (e.g., a portion of a page, a block (e.g., a block 404 of the NAND flash memory device 400), etc.). For example, the physical address of the storage area 605 may be referred to as a physical allocation address (PAA), and the logical address corresponding to the PAA may be referred to as a logical allocation address (LAA). In another example, when the storage area 605 corresponds to a page of the nonvolatile memory device 604, the physical address of the storage area 605 may be a physical page address (PPA), and the logical address corresponding to the PPA may be a logical block address (LBA).

[0083] Consistent with the scope of the present disclosure, in order to enable searching and accessing data, the cache 606 of the volatile memory device 602 may be divided into a plurality of memory blocks 607, each of which has a unique identifier (ID), also known as a memory block ID. In some implementations, each memory block 607 includes one or more pages (e.g., rows or columns of memory cells 503 of the DRAM device 500). In some implementations, in order to enable unified data searches between the non-volatile memory device 604 and the volatile memory device 602, the size of each storage area 605 and the size of each memory block 607 may be the same. It is understood that in some examples, the size of each storage area 605 and the size of each memory block 607 may be different. For example, the size of each memory block 607 may also be 4096 bytes. It is understood that the memory block 607 may correspond to any suitable group of memory cells (e.g., a portion of a page, a codeword, etc.) in the volatile memory device 602 other than a page.

[0084] The cache 606 may be a portion of the volatile memory device 602 that temporarily stores (caches) frequently used and / or recently accessed data to speed up read and write operations of the non-volatile memory device 604. Any suitable cache algorithm (including, for example, least recently used (LRU), most recently used (MRU), and first-in, first-out (FIFO)) may be used to determine which data should be stored in the cache 606 and when the data should be replaced. In some implementations, data from the host (host / user data) is first cached in the cache 606 of the volatile memory device 602 and flushed to the non-volatile memory device 604 under certain conditions based on the cache algorithm. For example, when the size of the data in the cache 606 reaches a preset threshold (maximum cache size), the data in the cache 606 may be flushed to the non-volatile memory device 604. The cache 606 may be accessed by any suitable type of volatile memory device 602 (e.g., Figure 3 This may be accomplished using DRAM 304 and / or cache 310 in the memory.

[0085] Consistent with the scope of the present disclosure, in order to enable unified search and access to data, a unified extended L2P mapping table 612 may be maintained and stored in the volatile memory device 602 to map the logical address of the data not only to the physical address 616 (e.g., PPA) of the storage area 605 in the non-volatile memory device 604, but also to the ID 614 of the storage block 607 in the cache 606 of the volatile memory device 602. The logical address may identify the host / user data and is known to the memory controller 601. In some implementations, the logical address (e.g., logical block address (LBA)) indicates the basic logical data unit for each read or write operation. In some implementations, in order to enable unified data search between the non-volatile memory device 604 and the volatile memory device 602, the size of each storage area 605, the size of each storage block 607, and the size of the data corresponding to each logical address may be the same. For example, the size of the data corresponding to each logical address may also be 4096 bytes. Since the memory controller 601 operates based on logical addresses rather than physical addresses (e.g., physical address 616 or ID 614), the L2P mapping table 612 can be used to enable conversion between logical addresses and physical addresses in a unified manner across both the non-volatile memory device 604 and the volatile memory device 602, as described in detail below.

[0086] In some implementations, the L2P mapping table 612 may be stored in the non-volatile storage device 604. In some other implementations, the L2P mapping table 612 may be stored in any suitable type of volatile storage device 602 (e.g., Figure 3 For example, the same volatile memory device 602 (e.g., Figure 3 DRAM 304 in the volatile memory device 602) includes both cache 606 and L2P mapping table 612. It will be appreciated that in some examples, cache 606 and L2P mapping table 612 may be included in different volatile memory devices 602. For example, cache 606 may be included in SRAM, while DRAM 304 may include L2P mapping table 612. Although L2P mapping table 612 is in Figure 6 6 as being outside of cache 606 , but it will be appreciated that in some examples, L2P mapping table 612 may also be stored in cache 606 .

[0087] In some implementations, the L2P mapping table 612 may be stored in the volatile memory device 602 using addresses in the volatile memory device 602. For example, Figure 7As shown in FIG. 1 , the L2P mapping table 612 may include addresses 704 (VM Add) in the volatile memory device 602, each of which is associated with a value 706. The value 706 may include two types of information: an ID 614 (e.g., ID1, ID2, ID3, etc.) of a storage block 607 in the cache 606, and a physical address 616 (PPA, e.g., PPA1, PPA2, PPA3, PPA4, etc.) of a storage area 605 in the non-volatile memory device 604. Figure 7 As shown in FIG. 1 , the L2P mapping table 612 may map a logical address 702 (LBA) of host / user data to an ID 614 of a storage block 607 in the cache 606 and a physical address 616 of a storage area 605 in the non-volatile storage device 604 via an address 704. For example, for each fragment of host / user data, a corresponding address 704 for an entry in the L2P mapping table 612 in the volatile storage device 602 may be determined based on a corresponding LBA 702 associated with the fragment of host / user data. Figure 7 In one example shown in FIG. 6 , a corresponding LBA 702 (e.g., 0, 1, 2, 3, 4, 5, 6, etc.) associated with an entry may be multiplied by an entry size Δ and then added to an address offset (OFF) to form a corresponding address 704 for the entry, where the entry size Δ may represent the length of a value 706 stored in the entry (e.g., Δ=4 bytes). The address offset may be determined, for example, based on the location where the L2P mapping table 612 is stored in the volatile memory device 602. Thus, a corresponding value 706 at the determined address 704 of the L2P mapping table 612 may be determined, indicating an ID 614 of a storage block 607 in the cache 606 or a physical address 616 of a storage region in the non-volatile memory device 604. Therefore, LBA 702 of host / user data may be respectively mapped to multiple physical addresses (eg, ID 614 of storage block 607 in cache 606 and physical address 616 of storage area 605 in nonvolatile memory device 604) through L2P mapping table 612.

[0088] Return to reference Figure 6 , the memory controller 601 may include a plurality of I / O interfaces, including a volatile memory interface 620 operatively coupled to the volatile memory device 602, a non-volatile memory interface 622 operatively coupled to the non-volatile memory device 604, and a host interface 618 operatively coupled to the cache 606 of the volatile memory device 602 and a host (not shown). Examples of these I / O interfaces may include Figure 3The DRAM interface 314, flash memory interface 312 and host interface 316 can implement any suitable communication protocol (e.g., NVMe protocol and PCI-E protocol, DDR protocol, to name a few) to facilitate data transfer, communication and management.

[0089] The host interface 618 may be configured to receive write requests and read requests from the host. Each write request may indicate a segment of data associated with a logical address (e.g., LBA) to be written to the memory system 600. Similarly, each read request may indicate a segment of data associated with a logical address (e.g., LBA) to be read from the memory system 600. In some implementations, in response to receiving a write request or a read request, the host interface 618 is also configured to obtain a segment of the data from the host to temporarily store (cache) the segment of the data in the cache 606, and vice versa. For example, the host interface 618 may include a direct memory access (DMA) unit that accesses data to and from the cache 606.

[0090] The non-volatile memory interface 622 may be configured to enable the memory controller 601 to access data stored in the non-volatile memory device 604 based on the physical address (e.g., PPA) of the storage area 605. The volatile memory interface 620 may be configured to enable the memory controller 601 to access data stored in the volatile memory device 602 (e.g., managing the L2P mapping table 612 and accessing the data in the cache 606). In some implementations, the volatile memory interface 620 is configured to convert the ID 614 of the storage block 607 in the cache 606 into a physical address of the volatile memory device 602, which can be used directly by the memory controller 601 to operate the storage unit of the volatile memory device 602. In other words, although the ID 614 of the storage block 607 in the cache 606 can be used to facilitate data search through the L2P mapping table 612, the memory controller 601 can still use the physical address of the volatile memory device 602 to access the data in the volatile memory device 602. Therefore, according to some implementations, the volatile memory device 602 does not need to be modified to accommodate data searches using the ID 614 of the memory block 607 .

[0091] like Figure 6 As shown in FIG. 1 , the memory controller 601 may further include a range partitioning accelerator 608 and one or more L2P search engines 610 operably coupled to the volatile memory device 602, the non-volatile memory interface 622, and the volatile memory interface 620. In some implementations, the range partitioning accelerator 608 and the L2P search engine 610 are composed of a memory device stored in a memory (e.g., Figure 3 ROM 311 or Figure 3 302 in the flash memory) and is implemented by the processing unit (e.g., Figure 3 The scope partitioning accelerator 608 and the L2P search engine 610 are firmware modules executed by the processing unit 308 in the scope partitioning accelerator 608. In some implementations, the scope partitioning accelerator 608 and the L2P search engine 610 are hardware modules implemented by dedicated circuits (e.g., ASICs) to perform the dedicated functions described herein. The hardware implementation of the scope partitioning accelerator 608 and the L2P search engine 610 can improve search parallelism and reduce firmware overhead, thereby further improving data search performance.

[0092] The range partitioning accelerator 608 may be configured to generate data search requests based on read and write requests from the host via the host interface 618, and to distribute the search requests to the L2P search engine 610. That is, the range partitioning accelerator 608 may, for example, divide the read request or the write request into search requests to be processed in parallel by a plurality of L2P search engines 610 based on different logical addresses associated with the data of the read request or the write request. For example, for each search request, the range partitioning accelerator 608 may identify an idle L2P search engine 610 to process the search request. In some implementations, in response to receiving a write request indicating a fragment of data associated with a logical address (e.g., an LBA), the range partitioning accelerator 608 is configured to assign the fragment of the data to one of the storage blocks 607 in the cache 606 having a unique ID in the ID 614, which triggers the host interface 618 to obtain the corresponding fragment of the data from the host to the corresponding storage block 607 in the cache 606.

[0093] The L2P search engine 610 may be configured to process the search request and, based on the processing of the search request, maintain the L2P mapping table 612 stored in the volatile memory device 602 through the volatile memory interface 620. In some implementations, a single L2P mapping table 612 is maintained for the memory system 600, and multiple L2P search engines 610 are configured to maintain the same L2P mapping table 612 and use the same L2P mapping table 612 for data searches. For example, the multiple L2P search engines 610 may be configured to search for multiple segments of data in parallel, respectively, based on the same L2P mapping table 612. It will be appreciated that, in some examples, a single L2P search engine 610 may be used to process the search request. In some implementations, in response to the host interface 618 retrieving a segment of data from the host to a corresponding storage block 607 in the cache 606 in response to a write request, the L2P search engine 610 can be configured to update the L2P mapping table 612 to map a logical address (e.g., LBA) associated with the segment of data to a unique ID 614 of the corresponding storage block 607. For example, Figure 7 As shown in , assuming that the LBA 702 of the fragment of data is "3", the value 706 may be updated by the search engine 610 to become "ID3", which is the unique ID 614 of the corresponding storage block 607. The value 706 may be stored at address 704 "OFF+3Δ" of the L2P mapping table 612 in the volatile storage device 602. In some implementations, in response to flushing the cached fragment of data in the cache 606 to a storage area having a unique physical address in the physical address 616 (e.g., PPA) in the storage area 605 in the non-volatile storage device 604, the L2P search engine 610 is further configured to update the L2P mapping table 612 to map the logical address (e.g., LBA) associated with the fragment of data to the unique physical address 616 of the corresponding storage area 605. For example, as Figure 7 As shown in , assuming that the LBA 702 of the fragment of the data is "3", the value 706 can be updated by the L2P search engine 610 to become "PPA5", which PPA5 is the unique physical address 616 of the corresponding storage area 605, because the fragment of the data associated with LBA3 has been moved from ID3 in the cache 606 to PPA5 in the non-volatile memory 604.

[0094] In some implementations, in response to receiving a search request indicating a read request for a segment of data having a logical address (e.g., an LBA), the L2P search engine 610 is configured to search for the segment of the data based on the logical address and the L2P mapping table 612. The L2P search engine 610 can be configured to determine an address of the L2P mapping table 612 in the volatile memory device 602 based on the logical address, and then determine a value at the address of the L2P mapping table 612. The L2P search engine 610 can be configured to perform a search similar to that described below with reference to Fig.11A and Fig. 11B The operation described is to identify whether the value is the ID 614 of the storage block 607 in the cache 606 or the physical address 616 of the storage area 605 in the non-volatile storage device 604.

[0095] In one example, if Figure 7 As shown in FIG. 6 , assuming that LBA 702 of the fragment of data is “0”, L2P search engine 610 may first add LBA 702 “0” multiplied by entry size Δ to address offset “OFF” to obtain address 704 “OFF”, and then identify value 706 at address 704 “OFF” as “ID1”, which means that the fragment of data to be read is data in storage block ID1 currently cached in cache 606. In another example, as Figure 7 As shown in , assuming that the LBA 702 of the data segment is “2”, the L2P search engine 610 can first add the LBA 702 “2” multiplied by the entry size Δ to the address offset “OFF” to obtain the address 704 “OFF+2Δ”, and then identify the value 706 at the address 704 “OFF+2Δ” as “PPA1”, which means that the segment of the data to be read is the data currently stored in the storage area PPA1 in the non-volatile memory device 604.

[0096] In some implementations, in response to identifying the ID 614 of the memory block 607 in the cache 606, the L2P search engine 610 provides the identified ID 614 to the volatile memory interface 620, and the volatile memory interface 620 converts the ID 614 to a corresponding physical address in the volatile memory device 602, so that the host interface 618 can, for example, use DMA to obtain the segment of the data from the corresponding physical address in the volatile memory device 602. In some implementations, in response to identifying the physical address 616 of the storage area 605 in the non-volatile memory device 604, the L2P search engine 610 provides the identified physical address 616 (e.g., PPA) to the non-volatile memory interface 622, so that the non-volatile memory interface 622 can obtain the segment of the data from the corresponding physical address in the non-volatile memory device 604.

[0097] Figure 8 A flow chart of a method 800 for operating a memory controller according to some aspects of the present disclosure is shown. The memory controller may be any suitable memory controller disclosed herein (e.g., memory controller 601). It will be appreciated that the operations shown in method 800 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Figure 8 The order shown in is executed.

[0098] The memory controller is operably coupled to the volatile memory device and the non-volatile memory device. The volatile memory device may include a cache. The cache is divided into a plurality of memory blocks, each of which has a corresponding unique ID in the ID. The non-volatile memory device is divided into memory areas, each of which has a corresponding unique physical address in the physical address. For example, Figure 6 As shown in the figure, the volatile memory device 602 may include a cache 606, which may be divided into storage blocks 607, each of which has a unique ID 614, and the non-volatile memory device 604 may be divided into storage areas 605, each of which has a unique physical address 616.

[0099] refer to Figure 8 , method 800 begins with operation 802, at which an L2P mapping table is generated and stored in a volatile memory device. Figure 6 As shown in FIG. 6 , the memory controller 601 may generate an L2P mapping table 612 during startup of the memory system 600 and store the L2P mapping table 612 in the volatile memory device 602 during operation of the memory system 600. For example, Figure 7 As shown in FIG. 6 , the L2P mapping table 612 may include a value 706 at each address 704 thereof, which value 706 may be mapped to an LBA 702 , respectively.

[0100] like Figure 8 As shown in FIG. 8 , method 800 proceeds to operation 804, at which a first set of data is cached in a memory block of the cache. The first set of data is respectively associated with a first set of logical addresses. For example, Figure 6As shown in FIG. 6 , the memory controller 601 can cache multiple fragments of host / user data in the storage block 607 in the cache 606, respectively. Each fragment of the host / user data can be associated with a corresponding one of the logical addresses (e.g., LBA). In one example, the host interface 618 of the memory controller 601 can use DMA to obtain the host / user data from the host to cache the host / user data in the storage block 607.

[0101] like Figure 8 As shown in FIG. 8 , method 800 proceeds to operation 806, where an L2P mapping table is maintained such that the L2P mapping table maps the first set of logical addresses to the IDs of the cached storage blocks, respectively. For example, Figure 6 and Figure 7 As shown in FIG. 6 , the memory controller 601 may maintain an L2P mapping table 612 such that a group of LBAs 702 may be mapped to IDs 614 of the memory blocks 607 via addresses 704 , respectively.

[0102] like Figure 8 As shown in FIG. 8 , method 800 proceeds to operation 808, where a second set of data is stored in a storage area of ​​the non-volatile memory device. The second set of data is respectively associated with a second set of logical addresses. For example, Figure 6 As shown in FIG. 6 , the memory controller 601 can store the segments of the host / user data separately in the storage area 605 in the non-volatile memory device 604. Each segment of the host / user data can be associated with a corresponding one of the logical addresses (e.g., LBA). In one example, the segments of the host / user data can be flushed from the cache 606 to the non-volatile memory device 604.

[0103] like Figure 8 As shown in FIG. 8 , method 800 proceeds to operation 810, where an L2P mapping table is maintained such that the L2P mapping table maps the second set of logical addresses to physical addresses of the storage area of ​​the nonvolatile memory device, respectively. Figure 6 and Figure 7 As shown in , the memory controller 601 may maintain an L2P mapping table 612 so that another set of LBAs 702 may be mapped to physical addresses 616 (eg, PPAs) of the storage region 605 via addresses 704 , respectively.

[0104] like Figure 8 As shown in FIG. 8 , method 800 proceeds to operation 812, where a segment of data is searched based on the L2P mapping table. Figure 6As shown in FIG. 6 , the plurality of L2P search engines 610 of the memory controller 601 may perform data searches on the plurality of fragments of data in parallel based on the logical addresses of the plurality of fragments of data and the L2P mapping table 612 .

[0105] In some implementations, to search for a segment of data, an address of an L2P mapping table in a volatile memory device is determined based on a logical address associated with the segment of data, and a value at the address of the L2P mapping table is determined. Figure 6 and Figure 7 As shown in , each L2P search engine 610 can calculate an address 704 of an L2P mapping table 612 based on the LBA 702 and the address offset, and identify a value 706 at the address 704 as an ID of a storage block of a volatile memory device or a physical address (e.g., PPA) of a storage area of ​​a non-volatile memory device. In some implementations, in order to search for a fragment of data, in response to a value being one of the IDs of a storage block in a volatile memory device, a fragment of the data is obtained from a storage block having the ID in the volatile memory device. In some implementations, in order to search for a fragment of data, in response to a value being one of the physical addresses of a storage area in a non-volatile memory device, a fragment of the data is obtained from a storage area having the physical address in the non-volatile memory device. For example, as Figure 6 and Figure 7 As shown in FIG. 6 , if the L2P search engine 610 identifies the value 706 at the address 704 as the ID 614, the host interface 618 can, for example, use DMA to obtain the fragment of data from the storage block 607 in the cache 606 having the identified ID 614. Conversely, if the L2P search engine 610 identifies the value 706 at the address 704 as the physical address 616 (e.g., PPA), the non-volatile memory interface 622 can obtain the fragment of data from the storage area 605 in the non-volatile memory device 604 having the identified physical address 616.

[0106] In some implementations, the write request may indicate a first fragment of data from a first set of data associated with a first set of logical addresses, wherein the first fragment of data is associated with a first logical address from the first set of logical addresses. In response to receiving the write request, the first fragment of data is assigned to a first storage block of the storage blocks having a first ID of the IDs (e.g., the first fragment of data is retrieved and cached in the first storage block). Fig. 9As shown in FIG. 1 , for example, at 902, a write request may be divided into a plurality of search requests by a range partitioning accelerator 608, each of which is associated with a fragment of host / user data and its logical address. For example, at 904, the range partitioning accelerator 608 may assign storage block IDs to the fragments of host / user data, respectively, so that each fragment of host / user data may be associated with a corresponding storage block ID. At 906, the range partitioning accelerator 608 may trigger the host interface 618 to use DMA to obtain each fragment of host / user data to a corresponding storage block.

[0107] In some implementations, in response to fetching the first segment of data to the first storage block, the L2P mapping table is updated to map the first logical address to the first ID. In response to flushing the first segment of data from the first storage block of the cache to a storage area having a physical address of the non-volatile storage device, the L2P mapping table is updated to map the first logical address to the physical address. For example, in Fig. 9 At 908, the storage block ID of the segment of cached host / user data can be updated in the L2P mapping table 612 by the L2P search engine 610 to be mapped to the logical address of the segment of the host / user data. At 910, it can be checked whether the programming of the non-volatile storage device is completed. The programming of the non-volatile storage device can be performed by flushing the cached host / user data from the cache to the non-volatile storage device. Once the programming of the non-volatile storage device is completed, each segment of the host / user data can be stored in a corresponding one of the storage areas, wherein each of the storage areas is associated with a PPA. If the answer to 910 is "yes", then at 912, the PPA of the segment of the storage host / user data in the non-volatile storage device can be updated in the L2P mapping table 612 by the L2P search engine 610 to be mapped to the logical address of the segment of the host / user data, thereby replacing the storage block ID. In some implementations, the update of the L2P mapping table using the PPA can be performed before the programming of the non-volatile storage device is completed. For example, the update of the L2P mapping table using the PPA may be performed when a command is generated to program a segment of host / user data into a non-volatile storage device (e.g., before the programming is actually completed). At 914, the memory controller (e.g., Figure 3 ) from a host (e.g., Figure 3 The host 306 in the process receives a new incoming write request to determine whether the process can continue again from 902 for the new incoming write request. If the answer to 910 is "no", the process can proceed directly to 914, bypassing 912 without updating the L2P mapping table 612.

[0108] In some implementations, the read request may indicate a second segment of data from a first set of data associated with a first set of logical addresses, wherein the second segment of data is associated with a second logical address from the first set of logical addresses. In response to receiving the read request, an address of an L2P mapping table in the volatile memory device may be determined based on the second logical address, and a second ID of a second memory block may be identified at the address of the L2P mapping table in the volatile memory device. For example, Fig.10 As shown in FIG. 1002 , at 1002 , a read request may be divided into a plurality of search requests by a range partitioning accelerator 608 , each of which is associated with a logical address. At 1004 , an idle L2P search engine 610 may be identified by the range partitioning accelerator 608 to execute the search request. At 1006 , a DRAM address may be located by the L2P search engine 610 based on the logical address (e.g., by multiplying the logical address by the entry size Δ to form a product, and then adding the product to the address offset to obtain the DRAM address). At 1008 , the value at the DRAM address may be obtained by the L2P search engine 610 .

[0109] In some implementations, in response to the value being one of the IDs of the storage blocks in the volatile memory device, a second fragment of the data is retrieved from a second storage block in the storage blocks in the cache based on the L2P mapping table. Fig.10 As shown in , at 1010, it can be determined whether the segment of host / user data is in the non-volatile storage device based on the obtained value (e.g., the storage block ID or PPA obtained at 1008). If the answer to 1010 is "no", this means that the segment of host / user data is still in the cache, and at 1014, the segment of host / user data can be obtained from the cache by the volatile memory interface 620 based on the storage block ID obtained at the DRAM address. If the answer to 1010 is "yes", this means that the segment of host / user data is in the non-volatile storage device, and at 1012, the segment of host / user data can be read from the non-volatile storage device by the non-volatile memory interface 622 based on the PPA obtained at the DRAM address. In either case, at 1016, the segment of host / user data can be sent to the host by the host interface 618.

[0110] Fig.11A An example method of organizing physical addresses mapped by an L2P mapping table according to some aspects of the present disclosure is shown. As described above, the L2P mapping table can be used to map multiple logical addresses to multiple physical addresses respectively. Fig.11AIn an example method, a plurality of physical addresses may be classified either as first-class volatile memory addresses (e.g., IDs of memory blocks of volatile memory devices (e.g., DRAM)) or as physical addresses of memory areas of second-class non-volatile memory addresses (e.g., PPAs of non-volatile memory devices (e.g., NAND memory devices)). In order to distinguish between first-class volatile memory addresses and second-class non-volatile memory addresses, at least 1 bit of the address data width may be reserved for marking the type of physical address.

[0111] For example, Fig.11A As shown in , each physical address can have an address data width of 32 bits. The most significant bits of the 32 bits can be reserved and used to mark the type of the physical address, and the remaining 31 bits can be used to represent a specific value of the physical address. For example, a first type of volatile memory address can be identified by marking the most significant bit of each address as "0", and a second type of non-volatile memory address can be identified by marking the most significant bit of each address as "1".

[0112] By reserving the most significant bit in each address for notation purposes, the possible sizes of the physical space that the address data width can represent range from (0,2 32 -1) is reduced to (0,2 31 -1). For SSDs with larger storage capacity (e.g., enterprise-class SSDs), the remaining bits of the address data width may not be sufficient to represent all physical addresses of the SSD. Figure 3 , Figure 6 and Fig. 11B Another example method of organizing a plurality of physical addresses mapped by an L2P mapping table is disclosed.

[0113] exist Fig. 11B In the example method, different Fig.11A The method of the example method is to organize multiple physical addresses mapped by the L2P mapping table. Specifically, Figure 6 The L2P search engine 610 shown in FIG. 6 may be configured to organize a plurality of physical addresses into a plurality of address categories based on at least one address boundary. Fig.11A , the multiple address categories may include at least one of the following: (1) a first category of user data addresses 1164 mapped to a storage area of ​​a user area 1172 of a non-volatile memory device; (2) a second category of volatile memory addresses 1162 mapped to a storage block of a volatile memory device; or (3) a third category of dedicated memory addresses 1160 mapped to a storage area of ​​a system area 1170 of a non-volatile memory device.

[0114] Each dedicated memory address 1160 in the third category may be dedicated to a specific purpose and may be mapped to a storage area in the system area 1170 of the non-volatile memory device. In some implementations, the dedicated memory address 1160 may be used to indicate relevant information (e.g., validity) related to the data stored in the physical address. For example, assume that a segment of user data has been stored in a specific physical address of the user area 1172 (e.g., PPA2 (e.g., the L2P mapping table has been updated to map the first logical address to PPA2)). Then, upon receiving an instruction from the host to delete a segment of user data, the memory controller may modify the L2P mapping table to map the first logical address to the dedicated memory address 1160, which is set to a specific physical address of the storage area in the system area 1170, e.g., PPA1. In this case, setting the dedicated memory address 1160 to PPA1 may be used to mark the invalidity of the segment of user data associated with the first logical address. The content or value of the entry mapped to the first logical address in the L2P mapping table is set to a specific physical address (eg, PPA1) of a storage area in the system area 1170, and the segment of user data associated with the first logical address is identified as invalid.

[0115] In some implementations, at least one address boundary may include a first address boundary 1168 stored in register 330 and a second address boundary 1166 stored in register 332, respectively. The second address boundary 1166 and / or the first address boundary 1168 may be used to determine the address category of each physical address and may be predetermined or configured by the memory controller. Each dedicated memory address 1160 in the third category may be less than the second address boundary 1166 (e.g., dedicated memory address 1160 < second address boundary 1166). Each user data address 1164 in the first category may be greater than the first address boundary 1168 (e.g., user data address 1164> first address boundary 1168). Each volatile memory address 1162 in the second category may be greater than or equal to the second address boundary 1166 and less than or equal to the first address boundary 1168 (e.g., second address boundary 1166 ≤ volatile memory address 1162 ≤ first address boundary 1168).

[0116] In some implementations, the L2P mapping table may map a first group of logical addresses among the plurality of logical addresses to a first group of physical addresses associated with a storage region of the user area 1172 of the non-volatile memory device, respectively. Then, the first category of user data addresses 1164 may include the first group of physical addresses associated with the storage region of the user area 1172 of the non-volatile memory device.

[0117] The L2P mapping table may also map a second group of logical addresses in the plurality of logical addresses to IDs of storage blocks of the volatile memory device, respectively. Then, the second category of volatile memory addresses 1162 may include IDs of storage blocks of the volatile memory device.

[0118] The L2P mapping table may map a third group of logical addresses among the plurality of logical addresses to a third group of physical addresses associated with a storage area of ​​the system area 1170 of the nonvolatile memory device, respectively. Then, the third category of dedicated memory addresses 1160 may include a third group of physical addresses associated with a storage area of ​​the system area 1170 of the nonvolatile memory device.

[0119] In some implementations, Figure 6 The range partitioning accelerator 608 can generate a search request based on the read request from the host via the host interface 618, and assign the search request to the L2P search engine 610. The read request can indicate to retrieve a segment of data associated with the logical address. In response to receiving the search request for the read request, the L2P search engine 610 can be configured to determine the address of the entry in the L2P mapping table based on the logical address (e.g., Figure 7 As shown in FIG. 1 , the address of the entry = logical address × Δ + OFF). The L2P search engine 610 may identify the physical address stored in the entry of the L2P mapping table based on the address of the entry. For example, the identified physical address may be the content or value stored in the entry of the L2P mapping table.

[0120] Then, the L2P search engine 610 may determine the address category into which the physical address is classified based on at least one of the first address boundary 1168 or the second address boundary 1166. For example, in response to the physical address being less than the second address boundary 1166, the L2P search engine 610 may determine that the physical address is classified as a third category of dedicated memory address 1160. Alternatively, in response to the physical address being greater than the first address boundary 1168, the L2P search engine 610 may determine that the physical address is classified as a first category of user data address 1164. Alternatively, in response to the physical address being equal to or greater than the second address boundary 1166 and equal to or less than the first address boundary 1168, the L2P search engine 610 may determine that the physical address is classified as a second category of volatile memory address 1162.

[0121] Then, the L2P search engine 610 may indicate to obtain a fragment of data from one of the volatile memory device and the non-volatile memory device based on the determined address category. Specifically, if the physical address is classified as a dedicated memory address 1160 of the third category or a user data address 1164 of the first category, the L2P search engine 610 may indicate to use the physical address to obtain a fragment of data from the non-volatile memory device. For example, the L2P search engine 610 may provide a physical address (e.g., PPA2) to the non-volatile memory interface 622 so that the non-volatile memory interface 622 may obtain a fragment of data from the corresponding physical address in the non-volatile memory device. Alternatively, if the physical address is classified as a volatile memory address 1162 of the second category, the L2P search engine 610 may indicate to use the physical address to obtain a fragment of data from the volatile memory device. For example, the L2P search engine 610 may provide a physical address (e.g., an identified ID) to the volatile memory interface 620 so that the host interface 618 may, for example, use DMA to obtain a fragment of data from the corresponding physical address in the volatile memory device 602.

[0122] Fig. 11B The example method shown in does not reserve any bits in the address data width to mark different types or categories of addresses or for other purposes of data, so that all bits (e.g., all 32 bits) in the address data width can be used to represent the physical address of the physical space corresponding to the non-volatile memory device or the volatile memory device. Alternatively, due to Fig. 11B In the example method of , there is no reserved bit, so a reduced address data width (e.g., 31 bits instead of 32 bits) can be used to represent the physical address of the physical space corresponding to the non-volatile memory device. In this case, the size of the L2P mapping table can be reduced because the physical address stored in the L2P mapping table is reduced to 31 bits. Therefore, the cost of the DRAM storing the L2P mapping table can be reduced.

[0123] Fig.12 1 is a flow chart of another method 1200 for operating a memory controller according to some aspects of the present disclosure. The memory controller may be any suitable memory controller disclosed herein (e.g., memory controller 601). It should be understood that the operations shown in method 1200 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Fig.12 The order shown in is executed.

[0124] refer to Fig.12, method 1200 begins with operation 1202, at which an L2P mapping table is maintained, which maps logical addresses to physical addresses respectively.

[0125] like Fig.12 As shown in FIG. 1 , method 1200 proceeds to operation 1204, at which physical addresses mapped by the L2P mapping table are organized into address categories based on at least one address boundary. For example, the at least one address boundary may include a first address boundary and a second address boundary. Based on the first address boundary and the second address boundary, the plurality of physical addresses are organized into the following address categories: (1) a first category of user data addresses mapped to a storage area of ​​a user area of ​​a non-volatile memory device; (2) a second category of volatile memory addresses mapped to a storage block of a volatile memory device; or (3) a third category of dedicated memory addresses mapped to a storage area of ​​a system area of ​​a non-volatile memory device.

[0126] Fig.13A The use of some aspects of the present disclosure is shown Fig.11A 1300 is a flowchart of an implementation of a method 1300 for processing a read request when a physical address mapped by an L2P mapping table is organized as an example method. The method 1300 may be performed by a memory controller, which may be any suitable memory controller disclosed herein, for example, the memory controller 601. It should be understood that the operations shown in the method 1300 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Fig.13A The order shown in is executed.

[0127] The memory controller is operably coupled to the volatile memory device and the non-volatile memory device. The volatile memory device may include a cache. The cache is divided into a plurality of memory blocks, each of which has a corresponding unique ID in the ID. The non-volatile memory device is divided into memory areas, each of which has a corresponding unique physical address in the physical address. For example, Figure 6 As shown in the figure, the volatile memory device 602 may include a cache 606, which may be divided into storage blocks 607, each of which has a unique ID 614, and the non-volatile memory device 604 may be divided into storage areas 605, each of which has a unique physical address 616.

[0128] refer to Fig.13AThe method 1300 begins at operation 1302 , where a read request may be partitioned by the range partitioning accelerator 608 into a plurality of search requests, each of which is associated with a logical address.

[0129] like Fig.13A As shown in , the method 1300 proceeds to operation 1304, where an idle L2P search engine 610 may be identified by the scope partitioning accelerator 608 to perform the search request. Then, the following operations 1306-1316 may be performed for each search request.

[0130] Specifically, for a specific search request associated with a logical address, such as Fig.13A As shown in FIG. 1 , method 1300 proceeds to operation 1306, where the L2P mapping table is searched based on the logical address to obtain a value (e.g., a physical address) stored in the L2P mapping table. For example, the DRAM address may be located based on the logical address by the L2P search engine 610 (e.g., the logical address is multiplied by the entry size Δ to form a product, and then the product is added to the address offset of the L2P mapping table to obtain the DRAM address). Then, the value at the DRAM address may be obtained by the L2P search engine 610.

[0131] like Fig.13A As shown in , the method 1300 proceeds to operation 1308, where the L2P search engine 610 resolves the value (eg, physical address). For example, the L2P search engine 610 extracts the most significant bits of the physical address from the resolved value.

[0132] like Fig.13A , method 1300 proceeds to operation 1310, where it is determined whether the most significant bit of the physical address is 0. If the most significant bit of the physical address is 0, then method 1300 may proceed to operation 1312. Otherwise (e.g., the most significant bit is 1), method 1300 may proceed to operation 1314.

[0133] At operation 1312, it is determined that the physical address represents a memory block ID of the volatile memory device because the most significant bit is 0. At operation 1313, the L2P search engine 610 may instruct to obtain a segment of data associated with the memory block ID from the volatile memory device. For example, the segment of data may be obtained from the cache based on the memory block ID by the volatile memory interface 620. At operation 1316, the segment of data may be sent to the host by the host interface 618.

[0134] On the other hand, at operation 1314, it is determined that the physical address represents a PPA in the non-volatile memory device because the most significant bit is 1. At operation 1315, the L2P search engine 610 may instruct to read a segment of data from the non-volatile memory device. For example, the segment of data may be read from the NAND flash memory device based on the PPA by the non-volatile memory interface 622. At operation 1316, the segment of data may also be sent to the host by the host interface 618.

[0135] Fig. 13B The use of some aspects of the present disclosure is shown Fig. 11B 1350 is a flowchart of an implementation of another method 1350 for processing a read request when a physical address mapped by an L2P mapping table is organized as an example method. Method 1350 may be performed by a memory controller, which may be any suitable memory controller disclosed herein (e.g., memory controller 601). It should be understood that the operations shown in method 1350 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Fig. 13B The order shown in the

[0136] Method 1350 may include a method similar to Fig.13A The operations are similar to those of method 1300, and descriptions of similar operations will not be repeated herein.

[0137] At operation 1308 of method 1350, the value (eg, physical address) is resolved by the L2P search engine 610. For example, the L2P search engine 610 may compare the value (eg, physical address) to at least one of a first address boundary or a second address boundary.

[0138] At operation 1311 of method 1350, L2P search engine 610 may determine whether a value (e.g., a physical address) is equal to or greater than a second address boundary and equal to or less than a first address boundary. If the value (e.g., the physical address) is equal to or greater than the second address boundary and equal to or less than the first address boundary, method 1350 may proceed to operation 1312 to determine that the value (e.g., the physical address) represents a storage block ID of the volatile memory device. Otherwise (e.g., the value is less than the second address boundary or greater than the first address boundary), method 1350 may proceed to operation 1314 to determine that the value (e.g., the physical address) represents a PPA in a non-volatile memory device.

[0139] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as instructions on a non-transitory computer-readable medium. Computer-readable media include computer storage media. The storage medium may be a computer program that can be accessed by a memory controller (e.g., Figure 6 Any available medium accessed by the memory controller 601 in the computer. By way of example and not limitation, such computer readable media may include RAM, ROM, electrically erasable programmable ROM (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage devices, hard disk drives (HDD) (e.g., magnetic disk storage devices or other magnetic storage devices), flash drives, SSDs, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures that can be accessed by a processing system (e.g., a mobile device or a computer). Disks and optical disks used herein include CDs, laser disks, optical disks, digital video discs (DVDs), and floppy disks, wherein disks typically reproduce data magnetically, while optical disks reproduce data optically using lasers. The above combinations should also be included within the scope of computer readable media.

[0140] The foregoing description of specific implementations can be easily modified and / or adapted to various applications. Therefore, based on the teaching and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed implementations.

[0141] The breadth and scope of the present disclosure should not be limited by any of the above-described example implementations, but should be defined only in accordance with the following claims and their equivalents.

[0142] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. Moreover, the subject matter described in the present disclosure may also be used for various other applications. The functions and structural features described in the present disclosure may be combined, adjusted, modified, and rearranged with each other in a manner consistent with the scope of the present disclosure.

Claims

1. A memory controller, comprising: A logical-to-physical (L2P) search engine, the L2P search engine being configured to: Maintaining an L2P mapping table, wherein the L2P mapping table maps logical addresses to physical addresses respectively; as well as The physical addresses mapped by the L2P mapping table are organized into address classes based on at least one address boundary.

2. The memory controller of claim 1 , wherein: The at least one address boundary comprises a first address boundary; and The memory controller also includes a first register configured to store the first address boundary.

3. The memory controller according to claim 2, wherein: The address categories include: a first category of user data addresses mapped to a storage area of ​​a user zone of a non-volatile memory device; and a second category of volatile memory addresses mapped to a storage block of a volatile memory device.

4. The memory controller of claim 3, wherein: The L2P mapping table maps a first group of logical addresses among the logical addresses to a first group of physical addresses associated with the storage area of ​​the user area of ​​the non-volatile memory device, respectively, and the first category of user data addresses includes the first group of physical addresses associated with the storage area of ​​the user area of ​​the non-volatile memory device; as well as The L2P mapping table further maps a second group of the logical addresses to identifiers (IDs) of the storage blocks of the volatile memory device, respectively, and the second category of volatile memory addresses includes the IDs of the storage blocks of the volatile memory device.

5. The memory controller according to claim 3 or 4, wherein: Each user data address in the first category is greater than the first address boundary; and Each volatile memory address in the second category is less than the first address boundary.

6. The memory controller according to any one of claims 3 to 5, wherein: The at least one address boundary further includes a second address boundary lower than the first address boundary; and The memory controller also includes a second register configured to store the second address boundary.

7. The memory controller of claim 6, wherein: The address categories further include: a third category of dedicated memory addresses mapped to a storage area of ​​a system zone of the nonvolatile memory device; and The L2P mapping table also maps a third group of logical addresses among the logical addresses to a third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device, respectively, and the third category of dedicated memory addresses includes the third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device.

8. The memory controller of claim 7, wherein: Each volatile memory address in the second category is greater than or equal to the second address boundary and less than or equal to the first address boundary; as well as Each dedicated memory address in the third category is less than the second address boundary.

9. The memory controller according to any one of claims 3 to 8, further comprising: a volatile memory device interface operably coupled to the volatile memory device; and a non-volatile memory device interface operably coupled to the non-volatile memory device.

10. The memory controller according to any one of claims 3 to 9, wherein: The volatile memory device includes a dynamic random access memory (DRAM), and the nonvolatile memory device includes a NAND flash memory.

11. The memory controller according to claim 8, wherein: In response to a read request indicating retrieval of a segment of data associated with a logical address, the L2P search engine is further configured to: Determine an address of an entry in the L2P mapping table based on the logical address; identifying, based on the address of the entry, a physical address stored in the entry of the L2P mapping table; determining, based on the first address boundary and the second address boundary, an address class into which the physical address is classified; as well as Based on the address category, it is instructed to fetch the segment of the data from one of the volatile memory device and the non-volatile memory device.

12. The memory controller according to claim 11, wherein: In order to determine the address category, the L2P search engine is further configured to: In response to the physical address being greater than the first address boundary, determining that the physical address is classified as a first category of user data addresses, wherein the first category of user data addresses is mapped to the storage area of ​​the user zone of the nonvolatile memory device; In response to the physical address being below the second address boundary, determining that the physical address is classified as a third category of special memory addresses, wherein the third category of special memory addresses is mapped to the storage area of ​​the system area of ​​the non-volatile memory device; or In response to the physical address being equal to or greater than the second address boundary and equal to or less than the first address boundary, determining that the physical address is classified as the second category of volatile memory addresses, wherein the second category of volatile memory addresses is mapped to the storage block of the volatile memory device.

13. The memory controller according to claim 12, wherein: In order to instruct to obtain the segment of the data, the L2P search engine is further configured to: In response to the physical address being classified as a dedicated memory address of the third category or a user data address of the first category, instructing to read the segment of the data from the non-volatile memory device using the physical address; or In response to the physical address being classified as a volatile memory address of the second category, an instruction is given to fetch the segment of the data from the volatile memory device using the physical address.

14. A memory system comprising: a non-volatile memory device, the non-volatile memory device comprising memory areas, each of the memory areas being associated with a physical address; a memory controller operably coupled to the non-volatile memory device and configured to control the non-volatile memory device, the memory controller comprising a logical-to-physical (L2P) search engine configured to: Maintaining an L2P mapping table, wherein the L2P mapping table maps logical addresses to physical addresses respectively; as well as The physical addresses mapped by the L2P mapping table are organized into address classes based on at least one address boundary.

15. The memory system of claim 14, wherein: The at least one address boundary comprises a first address boundary; and The memory controller also includes a first register configured to store the first address boundary.

16. The memory system of claim 15, wherein: The address categories include: a first category of user data addresses mapped to a storage area of ​​a user zone of a non-volatile memory device; and a second category of volatile memory addresses mapped to a storage block of a volatile memory device.

17. The memory system of claim 16, wherein: The L2P mapping table maps a first group of logical addresses among the logical addresses to a first group of physical addresses associated with the storage area of ​​the user area of ​​the non-volatile memory device, respectively, and the first category of user data addresses includes the first group of physical addresses associated with the storage area of ​​the user area of ​​the non-volatile memory device; as well as The L2P mapping table further maps a second group of the logical addresses to identifiers (IDs) of the storage blocks of the volatile memory device, respectively, and the second category of volatile memory addresses includes the IDs of the storage blocks of the volatile memory device.

18. The memory system according to claim 16 or 17, wherein: Each user data address in the first category is greater than the first address boundary; and Each volatile memory address in the second category is less than the first address boundary.

19. The memory system according to any one of claims 16 to 18, in, The L2P mapping table is stored in the volatile memory device.

20. The memory system according to any one of claims 16 to 19, wherein: The at least one address boundary further includes a second address boundary lower than the first address boundary; and The memory controller also includes a second register configured to store the second address boundary.

21. The memory system of claim 20, wherein: The address categories further include: a third category of dedicated memory addresses mapped to a storage area of ​​a system zone of the nonvolatile memory device; and The L2P mapping table also maps a third group of logical addresses among the logical addresses to a third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device, respectively, and the third category of dedicated memory addresses includes the third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device.

22. The memory system of claim 21, wherein: Each volatile memory address in the second category is greater than or equal to the second address boundary and less than or equal to the first address boundary; as well as Each dedicated memory address in the third category is less than the second address boundary.

23. The memory system according to any one of claims 16 to 22, wherein: The memory controller also includes: a volatile memory device interface operably coupled to the volatile memory device; and a nonvolatile memory device interface operably coupled to the nonvolatile memory device.

24. The memory system according to any one of claims 16 to 23, wherein: The volatile memory device includes a dynamic random access memory (DRAM), and the nonvolatile memory device includes a NAND flash memory.

25. The memory system of claim 22, wherein: In response to a read request indicating retrieval of a segment of data associated with a logical address, the L2P search engine is further configured to: Determine an address of an entry in the L2P mapping table based on the logical address; identifying, based on the address of the entry, a physical address stored in the entry of the L2P mapping table; determining, based on the first address boundary and the second address boundary, an address class into which the physical address is classified; as well as Based on the address category, it is instructed to fetch the segment of the data from one of the volatile memory device and the non-volatile memory device.

26. The memory system of claim 25, wherein: In order to determine the address category, the L2P search engine is further configured to: In response to the physical address being greater than the first address boundary, determining that the physical address is classified as a first category of user data addresses, wherein the first category of user data addresses is mapped to the storage area of ​​the user zone of the nonvolatile memory device; In response to the physical address being below the second address boundary, determining that the physical address is classified as a third category of special memory addresses, wherein the third category of special memory addresses is mapped to the storage area of ​​the system area of ​​the nonvolatile memory device; or In response to the physical address being equal to or greater than the second address boundary and equal to or less than the first address boundary, determining that the physical address is classified as the second category of volatile memory addresses, wherein the second category of volatile memory addresses is mapped to the storage block of the volatile memory device.

27. The memory system of claim 26, wherein: In order to instruct to obtain the segment of the data, the L2P search engine is further configured to: In response to the physical address being classified as a dedicated memory address of the third category or a user data address of the first category, instructing to read the segment of the data from the non-volatile memory device using the physical address; or In response to the physical address being classified as a volatile memory address of the second category, an instruction is given to fetch the segment of the data from the volatile memory device using the physical address.

28. A method for operating a memory controller, comprising: Maintaining a logical-to-physical (L2P) mapping table, wherein the L2P mapping table maps logical addresses to physical addresses respectively; as well as The physical addresses mapped by the L2P mapping table are organized into address classes based on at least one address boundary.

29. The method according to claim 28, wherein: The at least one address boundary includes a first address boundary stored in a first register.

30. The method of claim 29, wherein: The address categories include: a first category of user data addresses mapped to a storage area of ​​a user zone of a non-volatile memory device; and a second category of volatile memory addresses mapped to a storage block of a volatile memory device.

31. The method of claim 30, wherein: The L2P mapping table maps a first group of logical addresses among the logical addresses to a first group of physical addresses associated with the storage area of ​​the user area of ​​the non-volatile memory device, respectively, and the first category of user data addresses includes the first group of physical addresses associated with the storage area of ​​the user area of ​​the non-volatile memory device; as well as The L2P mapping table further maps a second group of the logical addresses to identifiers (IDs) of the storage blocks of the volatile memory device, respectively, and the second category of volatile memory addresses includes the IDs of the storage blocks of the volatile memory device.

32. The method according to claim 30 or 31, wherein: Each user data address in the first category is greater than the first address boundary; and Each volatile memory address in the second category is less than the first address boundary.

33. The method according to any one of claims 30 to 32, wherein: The at least one address boundary also includes a second address boundary lower than the first address boundary.

34. The method of claim 33, wherein: The address categories further include: a third category of dedicated memory addresses mapped to a storage area of ​​a system zone of the nonvolatile memory device; and The L2P mapping table also maps a third group of logical addresses among the logical addresses to a third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device, respectively, and the third category of dedicated memory addresses includes the third group of physical addresses associated with the storage area of ​​the system area of ​​the non-volatile memory device.

35. The method of claim 33 or 34, wherein: Each volatile memory address in the second category is greater than or equal to the second address boundary and less than or equal to the first address boundary; as well as Each dedicated memory address in the third category is less than the second address boundary.

36. The method according to any one of claims 30 to 35, wherein: The volatile memory device includes a dynamic random access memory (DRAM), and the nonvolatile memory device includes a NAND flash memory.

37. The method according to any one of claims 34 to 36, further comprising: In response to a read request indicating retrieval of a segment of data associated with a logical address, determining an address of an entry in the L2P mapping table based on the logical address; identifying, based on the address of the entry, a physical address stored in the entry of the L2P mapping table; determining, based on the first address boundary and the second address boundary, an address class into which the physical address is classified; as well as Based on the address category, it is instructed to fetch the segment of the data from one of the volatile memory device and the non-volatile memory device.

38. The method of claim 37, wherein: Determining the address category includes: In response to the physical address being greater than the first address boundary, determining that the physical address is classified as a first category of user data addresses, wherein the first category of user data addresses is mapped to the storage area of ​​the user zone of the nonvolatile memory device; In response to the physical address being below the second address boundary, determining that the physical address is classified as a third category of special memory addresses, wherein the third category of special memory addresses is mapped to the storage area of ​​the system area of ​​the non-volatile memory device; or In response to the physical address being equal to or greater than the second address boundary and equal to or less than the first address boundary, determining that the physical address is classified as the second category of volatile memory addresses, wherein the second category of volatile memory addresses is mapped to the storage block of the volatile memory device.

39. The method of claim 38, wherein: The fragment indicating to obtain the data includes: In response to the physical address being classified as a dedicated memory address of the third category or a user data address of the first category, instructing to read the segment of the data from the non-volatile memory device using the physical address; or In response to the physical address being classified as a volatile memory address of the second category, an instruction is given to fetch the segment of the data from the volatile memory device using the physical address.

40. A non-transitory computer-readable storage medium storing instructions that, when executed by a memory controller of a memory system, cause the memory controller to perform a method comprising: Maintaining a logical-to-physical (L2P) mapping table, wherein the L2P mapping table maps logical addresses to physical addresses respectively; as well as The physical addresses mapped by the L2P mapping table are organized into address classes based on at least one address boundary.

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