Low dropout regulator

Abstract

The invention discloses a low-dropout linear voltage regulator which is totally divided into three parts, the first part is an error amplifier, and it is guaranteed that the output voltage of the low-dropout linear voltage regulator is kept unchanged under different load currents; the second part is a source following current output stage, the output current is divided into two branches, one branch is supplied to the base electrode of an NPN triode, and the other branch is supplied to a first NMOS tube connected with a diode; and the third part is a zero point tracking part, the principle of the zero point tracking part is to obtain a current which is proportional to the current flowing to the base electrode of the NPN triode so as to obtain a zero point, and the frequency of the zero point is increased along with the increase of the load current for frequency compensation. The three parts, a power NPN triode, a partial pressure feedback resistor and a plug-in capacitor form a whole circuit. According to the invention, the driving current can reach the ampere level, the requirement of the whole circuit on the value of the equivalent series resistance of the external capacitor is reduced, and the resistance value range of the equivalent series resistance of the external capacitor is expanded.

Description

Technical Field

[0001] The invention relates to power management technology, and in particular to a low voltage difference linear regulator. Background Art

[0002] Currently, low dropout regulators (LDO) are widely used in various chips. When the current of a chip increases to the ampere level as the chip scale increases and the process node decreases, the power tube of the LDO will be placed outside the chip for cost, process compatibility, and chip heat dissipation considerations to achieve a better overall system implementation effect. At this time, a regulator circuit that drives the external power tube is needed to provide a stable core voltage for the chip.

[0003] There is a low voltage drop linear regulator circuit such as Figure 1 As shown, by reasonably setting the Miller resistor Rc and the capacitor Cc, setting the value of R2 to be much larger than R3, and selecting the appropriate equivalent series resistance (ESR) Resr of the external capacitor CL, this circuit can achieve normal operation of the load current from 0 to ten mA level.

[0004] As mentioned above, the focus is on analyzing how the main poles in this circuit are distributed. Figure 2 for Figure 1 The simplified small signal equivalent diagram of can be obtained based on this small signal diagram and its description.

[0005] Its main pole P1 is placed at Figure 1 The Vout output terminal in. Its size is:

[0006]

[0007] gmn is the equivalent transconductance of the NPN transistor

[0008] Secondly, the pole P2 is placed Figure 1 At the output end of MOS tube PM2. Its size is:

[0009]

[0010] Ro-pass is Figure 1 The equivalent impedance seen at the drain end of MOS tube PM2.

[0011] When the load current is small (uA level), there is basically no current flowing through the NPN transistor. At this time, all the current flows to the load end through the resistor R3. At this time, a zero point Z2 is generated for frequency compensation, and its size is:

[0012]

[0013] The circuit can be stable by properly setting the secondary pole P2 and the zero point Z2.

[0014] When the load current is large (mA level), the NPN transistor starts to work normally, and most of the current is supplied to the load end through the NPN transistor. At this time, the zero point Z2 has been pushed to high frequency and cannot play a compensation effect. It is necessary to generate an additional zero point Z1 for compensation through a suitable equivalent series resistor Resr. Its size is:

[0015]

[0016] The circuit can be stable by properly setting the secondary pole P2 and the additional zero Z1.

[0017] In the existing low-dropout linear regulator circuit, the effective series resistance Resr of the external capacitor CL participates in the overall circuit frequency compensation, so its value range is small and its compatibility is poor; the load current cannot be extended to the ampere level because the main pole is set at the load end. Summary of the invention

[0018] The technical problem to be solved by the present invention is to provide a low voltage difference linear regulator (LDO), which can achieve a driving current of ampere level, reduce the requirements of the overall circuit on the equivalent series resistance value of the external capacitor, and expand the resistance range of the equivalent series resistance of the external capacitor.

[0019] In order to solve the above technical problems, the present invention provides a low voltage difference linear regulator, which includes an error amplifier, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a first capacitor C1, a fifth resistor R5, an NPN transistor Q1, an external capacitor CL, a sixth resistor R6 and a seventh resistor R7;

[0020] The source ends of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the collector of the NPN transistor and one end of the fifth resistor R5 are connected to the working voltage VDD;

[0021] The NPN transistor Q1 has an emitter as the output terminal of the low voltage difference linear regulator, and a base VB connected to the drain terminal of the second PMOS transistor PM2, the drain terminal of the first NMOS transistor NM1, the gate terminal of the first NMOS transistor NM1 and the gate terminal of the second NMOS transistor NM2;

[0022] The external capacitor CL is connected between the emitter of the NPN transistor Q1 and the ground;

[0023] The sixth resistor R6 and the seventh resistor R7 are connected in series between the emitter of the NPN transistor Q1 and the ground;

[0024] The error amplifier has a negative input terminal connected to the series connection point of the sixth resistor R6 and the seventh resistor R7, a positive input terminal connected to the reference voltage Vref, and an output terminal connected to the gate terminal of the sixth PMOS transistor PM6 and one end of the first capacitor C1;

[0025] The other end of the first capacitor C1 is connected to the drain end of the fifth PMOS transistor PM5 and the other end of the fifth resistor R5;

[0026] The sixth PMOS transistor PM6 has a source terminal connected to the drain terminal of the first PMOS transistor PM1, the gate terminal of the first PMOS transistor PM1, the gate terminal of the second PMOS transistor PM2 and the gate terminal of the third PMOS transistor PM3, and a drain terminal connected to the ground;

[0027] The drain terminal of the third PMOS transistor PM3 is connected to the drain terminal of the second NMOS transistor NM2, the drain terminal of the third NMOS transistor NM3, the gate terminal of the third NMOS transistor NM3 and the gate terminal of the fourth NMOS transistor NM4;

[0028] The fourth PMOS transistor PM4 has its gate and drain terminals short-circuited and connected to the gate terminal of the fifth PMOS transistor PM5 and the drain terminal of the fourth NMOS transistor NM4;

[0029] Source terminals of the first NMOS transistor NM1 , the second NMOS transistor NM2 , the third NMOS transistor NM3 , and the fourth NMOS transistor NM4 are grounded.

[0030] Preferably, the drain current I_PM1 of the first PMOS transistor PM1 is obtained by controlling the gate voltage of the sixth PMOS transistor PM6 by the output of the error amplifier, and the drain current I_PM2 of the second PMOS transistor PM2 is obtained by mirroring I_PM1, I_PM1:I_PM2=1:N, N≥1.

[0031] Preferably, the error amplifier, the first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3, the fourth PMOS tube PM4, the fifth PMOS tube PM5, the sixth PMOS tube PM6, the first NMOS tube NM1, the second NMOS tube NM2, the third NMOS tube NM3, the fourth NMOS tube NM4, the first capacitor C1, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 are placed inside a chip, and the NPN transistor and the external capacitor CL are placed outside the chip.

[0032] Preferably, a fourth capacitor C4 is connected in parallel across the sixth resistor R6.

[0033] Preferably, the drain end of the sixth PMOS transistor PM6 is grounded through a current limiter.

[0034] Preferably, the current limiter is a current limiting resistor.

[0035] Preferably, the first capacitor C1 is 10 pF to 100 pF.

[0036] The low-dropout linear regulator (LDO) circuit of the present invention can achieve a driving current of the ampere level, and reduces the requirements of the overall circuit on the equivalent series resistance Resr of the external capacitor, thereby expanding the resistance range of the equivalent series resistance Resr of the external capacitor. The equivalent series resistance Resr of the external capacitor can theoretically be 0-1 ohm. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 It is a circuit diagram of an existing low voltage drop linear regulator;

[0039] Figure 2 yes Figure 1 The simplified small signal equivalent diagram of the low dropout linear regulator shown;

[0040] Figure 3 is a circuit diagram of an embodiment of a low voltage dropout linear regulator of the present invention;

[0041] Figure 4 yes Figure 3 The simplified small signal equivalent diagram of the low dropout linear regulator shown in Figure 1 is shown in Figure 2. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] Embodiment 1

[0044] A low dropout regulator (LDO) such as Figure 3As shown, it includes an error amplifier (ERROR AMPLIFER), a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a first capacitor C1, a fifth resistor R5, an NPN transistor Q1, an external capacitor CL, a sixth resistor R6 and a seventh resistor R7;

[0045] The source ends of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the collector of the NPN transistor Q1 and one end of the fifth resistor R5 are connected to the working voltage VDD;

[0046] The NPN transistor Q1 has an emitter as the output terminal of the low voltage difference linear regulator, and a base VB connected to the drain terminal of the second PMOS transistor PM2, the drain terminal of the first NMOS transistor NM1, the gate terminal of the first NMOS transistor NM1 and the gate terminal of the second NMOS transistor NM2;

[0047] The external capacitor CL is connected between the emitter of the NPN transistor Q1 and the ground;

[0048] The sixth resistor R6 and the seventh resistor R7 are connected in series between the emitter of the NPN transistor Q1 and the ground;

[0049] The error amplifier has a negative input terminal connected to the series connection point of the sixth resistor R6 and the seventh resistor R7, a positive input terminal connected to the reference voltage Vref, and an output terminal connected to the gate terminal of the sixth PMOS transistor PM6 and one end of the first capacitor C1;

[0050] The other end of the first capacitor C1 is connected to the drain end of the fifth PMOS transistor PM5 and the other end of the fifth resistor R5;

[0051] The sixth PMOS transistor PM6 has a source terminal connected to the drain terminal of the first PMOS transistor PM1, the gate terminal of the first PMOS transistor PM1, the gate terminal of the second PMOS transistor PM2 and the gate terminal of the third PMOS transistor PM3, and a drain terminal connected to the ground;

[0052] The drain terminal of the third PMOS transistor PM3 is connected to the drain terminal of the second NMOS transistor NM2, the drain terminal of the third NMOS transistor NM3, the gate terminal of the third NMOS transistor NM3 and the gate terminal of the fourth NMOS transistor NM4;

[0053] The fourth PMOS transistor PM4 has its gate and drain terminals short-circuited and connected to the gate terminal of the fifth PMOS transistor PM5 and the drain terminal of the fourth NMOS transistor NM4;

[0054] Source terminals of the first NMOS transistor NM1 , the second NMOS transistor NM2 , the third NMOS transistor NM3 , and the fourth NMOS transistor NM4 are grounded.

[0055] Preferably, the drain current I_PM1 of the first PMOS transistor PM1 is obtained by controlling the gate voltage of the sixth PMOS transistor PM6 by the output of the error amplifier, and the drain current I_PM2 of the second PMOS transistor PM2 is obtained by mirroring I_PM1, and the ratio is 1:N, N≥1.

[0056] The low dropout regulator (LDO) of the first embodiment is divided into three parts. The first part is an error amplifier (ERROR AMPLIFER), which is used to keep the voltage of the voltage divided feedback of the output voltage VOUT of the low dropout linear regulator under different load currents basically consistent with the reference voltage Vref through its own high gain and loop negative feedback mechanism, thereby ensuring that the output voltage VOUT of the low dropout linear regulator remains unchanged under different load currents. The second part is a source-followed current output stage composed of the sixth PMOS transistor PM6, the first PMOS transistor PM1, and the second PMOS transistor PM2. The output current I_PM2 is divided into two branches, one branch flows to the base of the NPN transistor (IB_NPN), and the other branch flows to the first NMOS transistor NM1 (I_NM1) connected with a diode, I_PM2=IB_NPN+I_NM1; the third part is the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3 and the fourth NMOS transistor NM4, together with the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the first capacitor C1 and the fifth resistor R5 to form a zero-point tracking part. The principle is to obtain a current (IB_NPN) proportional to the base of the NPN transistor on the sixth PMOS transistor PM6, and then obtain a zero point, whose frequency increases with the increase of load current, and is used for frequency compensation. These three parts, together with the power NPN transistor, the voltage divider feedback resistor, and the external capacitor CL constitute the entire circuit.

[0057] Figure 4 To simplify the small signal analysis diagram, the third part, zero point tracking, which has a clear function and is not related to the rest of the diagram, is not included in the diagram. The whole diagram is divided into a green frame and a blue frame. The green frame is Figure 3 The error amplifier and the sixth PMOS transistor PM6 and the first PMOS transistor PM1 are partially simplified, where r1 is the equivalent resistance at the output of the error amplifier, and r2 and c2 are the equivalent resistance and capacitance at net2. The values ​​of c1 and r1 are both relatively large, c1 is at the level of tens of pF, and r1 is at the level of tens of MΩ. The main pole P1 is: P1 = 1 / r1*c1. The blue box part is Figure 3The second PMOS tube PM2, the power NPN transistor and the external capacitor CL are partially simplified, and the overall transfer function is:

[0058]

[0059] Where Rp and Cp are equivalent resistance and capacitance at VB, Re, Ce, and gmn are parameters in the equivalent simplified hybrid Π model of the power NPN transistor. By calculating the transfer function, the secondary pole P2 at the output terminal Vout of the low-dropout linear regulator and the third pole P3 at the base VB of the NPN transistor can be obtained.

[0060] The idea of ​​overall loop compensation is to place the main pole at the output net1 of the error amplifier, so that the main pole will not move to high frequency as the load current increases. The secondary pole and the third pole are at the output VOUT of the low-dropout linear regulator and the base VB of the NPN transistor, respectively. By adding a zero tracking circuit, the zero point follows the movement of the secondary pole. In this way, the influence of the secondary pole can be offset by the additional zero point, and the main pole and the third pole are greatly different. The overall loop can ensure that the load current is stable from the mA level to the A level. After the above design, the bandwidth of the overall loop is not high due to the relatively low frequency of the main pole. The frequency Z1 = 1 / Resr*CL of the zero point generated by the equivalent series resistance (ESR) Resr of the external capacitor CL itself, outside its bandwidth or near the bandwidth, as long as the equivalent series resistance Resr resistance does not reach the level of 1Ω, will not have a negative impact on the overall loop stability.

[0061] As mentioned above, as long as the appropriate external capacitor CL is selected and the parameters of the MOS tube in the circuit are reasonably adjusted, an ampere-level voltage regulator circuit that drives an external NPN transistor can be realized.

[0062] There are many ways to implement the specific circuit that constitutes the zero-point tracking part, which are not limited to the embodiments, as long as the obtained resistance value and the IB_NPN current are correlated.

[0063] The low-dropout linear regulator (LDO) of the present invention can achieve a driving current of the ampere level, and reduces the requirements of the overall circuit on the equivalent series resistance Resr of the external capacitor, and expands the resistance range of the equivalent series resistance Resr of the external capacitor. The equivalent series resistance Resr of the external capacitor can theoretically be from 0 to 1 ohm.

[0064] Embodiment 2

[0065] Based on the low dropout linear regulator (LDO) of the first embodiment, the error amplifier, the first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3, the fourth PMOS tube PM4, the fifth PMOS tube PM5, the sixth PMOS tube PM6, the first NMOS tube NM1, the second NMOS tube NM2, the third NMOS tube NM3, the fourth NMOS tube NM4, the first capacitor C1, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 are placed inside a chip, and the NPN transistor and the external capacitor CL are placed outside the chip.

[0066] Preferably, a fourth capacitor C4 is connected in parallel across the sixth resistor R6.

[0067] Preferably, the drain end of the sixth PMOS transistor PM6 is grounded through a current limiter.

[0068] Preferably, the current limiter is a current limiting resistor.

[0069] Preferably, the first capacitor C1 is 10 pF to 100 pF.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A low voltage dropout linear regulator, characterized in that: The invention comprises an error amplifier, a first PMOS tube (PM1), a second PMOS tube (PM2), a third PMOS tube (PM3), a fourth PMOS tube (PM4), a fifth PMOS tube (PM5), a sixth PMOS tube (PM6), a first NMOS tube (NM1), a second NMOS tube (NM2), a third NMOS tube (NM3), a fourth NMOS tube (NM4), a first capacitor (C1), a fifth resistor (R5), an NPN transistor (Q1), an external capacitor (CL), a sixth resistor (R6) and a seventh resistor (R7); The source ends of the first PMOS tube (PM1), the second PMOS tube (PM2), the third PMOS tube (PM3), the fourth PMOS tube (PM4), and the fifth PMOS tube (PM5), the collector of the NPN transistor, and one end of the fifth resistor (R5) are connected to an operating voltage; The NPN transistor (Q1) has an emitter as the output end of the low voltage difference linear regulator, and a base VB connected to the drain end of the second PMOS transistor (PM2), the drain end of the first NMOS transistor (NM1), the gate end of the first NMOS transistor (NM1) and the gate end of the second NMOS transistor (NM2); The external capacitor (CL) is connected between the emitter of the NPN transistor (Q1) and the ground; The sixth resistor (R6) and the seventh resistor (R7) are connected in series between the emitter of the NPN transistor (Q1) and the ground; The error amplifier has a negative input terminal connected to the series connection point of the sixth resistor (R6) and the seventh resistor (R7), a positive input terminal connected to the reference voltage Vref, and an output terminal connected to the gate terminal of the sixth PMOS transistor (PM6) and one end of the first capacitor (C1); The other end of the first capacitor (C1) is connected to the drain end of the fifth PMOS tube (PM5) and the other end of the fifth resistor (R5); The sixth PMOS tube (PM6) has a source end connected to the drain end of the first PMOS tube (PM1), the gate end of the first PMOS tube (PM1), the gate end of the second PMOS tube (PM2) and the gate end of the third PMOS tube (PM3), and a drain end connected to the ground; The drain end of the third PMOS tube (PM3) is connected to the drain end of the second NMOS tube (NM2), the drain end of the third NMOS tube (NM3), the gate end of the third NMOS tube (NM3) and the gate end of the fourth NMOS tube (NM4); A fourth PMOS tube (PM4), whose gate and drain terminals are short-circuited and connected in parallel to the gate terminal of the fifth PMOS tube (PM5) and the drain terminal of the fourth NMOS tube (NM4); The source ends of the first NMOS transistor (NM1), the second NMOS transistor (NM2), the third NMOS transistor (NM3) and the fourth NMOS transistor (NM4) are grounded.

2. The low voltage dropout linear regulator according to claim 1, characterized in that: The drain current I_PM1 of the first PMOS tube (PM1) is obtained by controlling the gate voltage of the sixth PMOS tube (PM6) through the output of the error amplifier, and the drain current I_PM2 of the second PMOS tube (PM2) is obtained by mirroring I_PM1, where I_PM1:I_PM2=1:N, N≥1.

3. The low voltage dropout linear regulator according to claim 1, characterized in that: An error amplifier, a first PMOS tube (PM1), a second PMOS tube (PM2), a third PMOS tube (PM3), a fourth PMOS tube (PM4), a fifth PMOS tube (PM5), a sixth PMOS tube (PM6), a first NMOS tube (NM1), a second NMOS tube (NM2), a third NMOS tube (NM3), a fourth NMOS tube (NM4), a first capacitor (C1), a fifth resistor (R5), a sixth resistor (R6) and a seventh resistor (R7) are arranged inside a chip, and the NPN transistor and the external capacitor (CL) are arranged outside the chip.

4. The low voltage dropout linear regulator according to claim 1, characterized in that: The fourth capacitor (C4) is connected in parallel across the sixth resistor (R6).

5. The low voltage dropout linear regulator according to claim 1, characterized in that: The drain end of the sixth PMOS tube (PM6) is grounded through a current limiter.

6. The low voltage dropout linear regulator according to claim 5, characterized in that: The current limiter is a current limiting resistor.

7. The low voltage dropout linear regulator according to claim 1, characterized in that: The first capacitor (C1) is 10pF to 100pF.

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