Copper wire bonding process after copper treatment of silicon carbide power device chip

By adopting the copper-wire bonding process on the silicon carbide power device chip, the problem of difficult control of the thickness and uniformity of the coating layer in the preparation of the chip electrode layer is solved, more stable electrical connections and higher damage resistance are achieved, and the reliability and service life of the chip are significantly improved.

CN119694909APending Publication Date: 2025-03-25HEFEI ZHONGHENG MICRO SEMICON CO LTD
0 Cites 4 Cited by

Patent Information

Application Number
CN202411795283.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-09
Publication Date
2025-03-25

AI Technical Summary

Technical Problem

The prior art is difficult to accurately control the thickness and uniformity of the coating layer when preparing the chip electrode layer, resulting in wafer warping or insufficient buffering, affecting chip reliability; insufficient optimization of traditional bonding technology parameters leads to unstable bonding quality and frequent occurrence of dummy welding and desoldering; the stress buffering effect of conventional buffer layers is poor, which limits the chip's damage resistance and overall stability improvement.

Method used

The copper wire bonding process after copperization of silicon carbide power device chips is adopted, including chip pretreatment, electrode layer evaporation, preparation of gradient structure buffer layer, copper wire preparation and hot pressing ultrasonic bonding, etc., to improve bonding quality and stress dispersion effect by precisely controlling the thickness and structural design of the plating layer.

Benefits of technology

The stability and bonding quality of the chip surface electrical connection are improved, which significantly improves the reliability and damage resistance of the chip, extends the service life of the chip, and reduces the risk of product failure caused by chip damage.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The invention discloses a copper wire bonding process for a silicon carbide power device chip after copperization, and relates to the technical field of chip manufacturing, and the copper wire bonding process comprises the following specific steps: step 1, chip pretreatment: preparing the silicon carbide power device chip, placing the chip in a cleaning tank, and cleaning the silicon carbide power device chip; the method has the advantages that the nickel layer, the metal palladium layer and the metal copper layer with the specific thickness and sequence are evaporated on the surface of the chip, the buffer layer with the gradient structure is prepared, the plating uniformity and the appropriate thickness are ensured through the accurately-controlled electrode layer evaporation process, the problems of wafer warping, buffer failure and the like are solved, and the production efficiency is improved. A stable electrical connection basis is provided for the chip, the elasticity modulus of the gradient structure of the buffer layer can be gradually reduced from contact with the electrode layer to contact with the copper wire according to the stress distribution characteristics, the stress dispersion effect is greatly improved, the reliability of the chip in the bonding and subsequent use processes is remarkably improved, the service life of the chip is prolonged, and the production cost is reduced. And the risk of product failure caused by chip damage is reduced.
Need to check novelty before this filing date? Find Prior Art