32APSK parallel demodulation method and system

Abstract

The invention discloses a 32APSK parallel demodulation method and system, and the method comprises the steps: receiving a radio-frequency signal through an antenna, carrying out the frequency conversion processing through a receiving channel, converting the radio-frequency signal into an intermediate-frequency signal, carrying out the digital-to-analog conversion, obtaining an intermediate-frequency digital signal, carrying out the grouping according to a fixed length, and obtaining a data package with a fixed length, mixing the intermediate frequency digital signal in the data packet with two paths of in-phase orthogonal carriers to obtain a mixed signal, and filtering the mixed signal through a low-pass filter to generate an in-phase baseband signal and an orthogonal baseband signal; in-phase baseband signals and orthogonal baseband signals are sequentially subjected to resampling, frequency offset estimation, carrier synchronization, coherent demodulation and judgment to obtain judged signals, and finally equalization processing is carried out to remove inter-symbol interference. The method has the advantages of low data dependence and high degree of parallelism, symbol synchronization and carrier synchronization are realized by using an open loop after I and Q signals are acquired, the degree of parallelism is high, and the method is suitable for a GPU platform and 32 APSK signal demodulation at any rate.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a 32APSK parallel demodulation method and system. Background Art

[0002] Amplitude Phase Shift Keying (APSK) modulation system has high spectrum efficiency and has a lower peak-to-average ratio and a larger dynamic range than the same-order quadrature amplitude modulation (QAM). At the same time, as space payloads continue to increase and communication bandwidth resources become increasingly scarce, increasing the modulation order to improve system spectrum utilization has become a common method. Therefore, 32APSK has been widely used in satellite communications. In recent years, Graphics Processing Unit (GPU) has made great progress in the field of general computing, and its powerful parallel processing capabilities have provided a new solution for the field of signal processing.

[0003] At present, the traditional 32APSK demodulation system is mainly implemented using a DSP-FPGA platform. After the intermediate frequency signal is sent to a high-speed ADC for digital-to-analog conversion, the digital signal is sent to the FPGA chip for digital down-conversion to obtain two zero intermediate frequency in-phase / quadrature (I / Q) baseband signals. The baseband signal is sent to the symbol synchronization module and the carrier synchronization module, and then to the equalization module to complete the entire demodulation process.

[0004] In the traditional demodulation scheme, the symbol synchronization module is implemented using the Gardner loop, and the carrier synchronization module is implemented using the four-phase loose-tail loop. Both modules are feedback loops. This continuous feedback adjustment requires frequent thread synchronization on the one hand, and increases the data dependency within the algorithm on the other hand. The parallelism is poor and is not suitable for the GPU platform. Summary of the invention

[0005] The purpose of this application is to overcome the existing technical defects and provide a 32APSK parallel demodulation method and system. After acquiring the I and Q signals, an open loop is used to realize symbol synchronization and carrier synchronization. The method has high parallelism and is suitable for 32APSK signal demodulation on a GPU platform and at any rate.

[0006] The purpose of this application is achieved through the following technical solutions:

[0007] In a first aspect, the present application proposes a 32APSK parallel demodulation method, the method comprising:

[0008] Receive the radio frequency signal through the antenna and convert the radio frequency signal into an intermediate frequency signal through the receiving channel through frequency conversion processing;

[0009] Performing digital-to-analog conversion on the intermediate frequency signal to obtain an intermediate frequency digital signal, and grouping the intermediate frequency digital signal according to a fixed length to obtain a fixed-length data packet;

[0010] Mixing the intermediate frequency digital signal in the data packet with two in-phase and orthogonal carriers to obtain a mixed signal;

[0011] The mixed signal is filtered by a low-pass filter to generate an in-phase baseband signal and a quadrature baseband signal;

[0012] The in-phase baseband signal and the orthogonal baseband signal are sequentially resampled, frequency offset estimated, code element distribution determined, carrier synchronization, coherently demodulated and judged to obtain a judged signal;

[0013] The judged signal is equalized to remove inter-code interference.

[0014] In a possible implementation, the range of the fixed length L is where f s is the sampling rate of the digital-to-analog conversion, and Δf is the difference between the actual carrier frequency and the estimated carrier frequency.

[0015] In a possible implementation manner, the sampling rate of the resampled signal is rfs, where rfs=rs·M, rs is the signal symbol rate, and M is the oversampling multiple.

[0016] In a possible implementation manner, the frequency offset f obtained by the resampled frequency offset estimation is b is f1 / 16, where f1 is the frequency at which the peak of the 16th power spectrum of the resampled signal is located.

[0017] In a possible implementation manner, the step of determining the symbol distribution includes:

[0018] Set the number of sampling points of the first code element to x, the number of complete code elements to y, the number of sampling points contained in each complete code element to M, the number of sampling points of the last code element to z, and calculate the integral value v corr : Where L is the signal packet length, s(k) is the resampled signal, p is the code element start point, and q is the code element end point;

[0019] The resampled signal and the estimated frequency offset f b The result of multiplying the constructed carriers s(t): s(t) = ((I(t) + j*Q(t))*exp(j·2·pi·f b t)) 8, where I(t) is the in-phase baseband signal and Q(t) is the quadrature baseband signal;

[0020] Traverse the number of sampling points M, and in v corr When the maximum value is obtained, the corresponding number of sampling points x is determined.

[0021] In a possible implementation manner, the carrier synchronization step includes:

[0022] Step S5-1: set the frequency f e The range is set to [-rfs / (8*N), rfs / (8*N)], the step is set to rfs / (4·N·U), and the initial phase The range is set to [0, π], the step is set to π / V, N is the FFT length, U represents the number of equal parts of the frequency interval, and V represents the number of equal parts of the phase interval;

[0023] Step S5-2: construct a search signal r(t):

[0024] Step S5-3, traverse (U+1)·(V+1) cases and calculate the integral value v corr , the maximum value of the integral corresponds to f1 and The estimated result of the initial parameter The corresponding step is

[0025] Step S5-4, determine whether the iterative search condition is met, if not, execute step S5-5, if yes, execute step S5-6;

[0026] Step S5-5: frequency f e The range is set to [f es -f step , f es +f step ], the stepping is set to 2f step / U, change the initial phase The range is set to The stepping is set to Return to step S5-3;

[0027] Step S5-5: Output parameter estimation results

[0028] In a possible implementation manner, a signal obtained by performing coherent demodulation according to the parameter estimation result is: and

[0029]

[0030] In the second aspect, the present application proposes a 32APSK parallel demodulation system, which includes a radio frequency receiving channel, an analog-to-digital conversion module, a data packetization module, an orthogonal down-conversion module, a low-pass filtering module, a resampling module, a symbol synchronization module, a carrier synchronization module, a demodulation module, and an equalization module;

[0031] The RF receiving channel is used to convert the received RF signal into an intermediate frequency signal through frequency conversion processing;

[0032] The analog-to-digital conversion module is used to perform digital-to-analog conversion on the intermediate frequency signal to obtain an intermediate frequency digital signal;

[0033] A data packetization module is used to group the intermediate frequency digital signal into fixed-length packets;

[0034] The orthogonal down-conversion module is used to mix the intermediate frequency digital signal in the data packet with two in-phase orthogonal carriers to obtain a mixed signal;

[0035] A low-pass filtering module, used for filtering the mixed signal through a low-pass filter to generate an in-phase baseband signal and an orthogonal baseband signal;

[0036] A resampling module, used for sequentially resampling an in-phase baseband signal and an orthogonal baseband signal;

[0037] A symbol synchronization module is used to estimate frequency offset and determine symbol distribution;

[0038] A carrier synchronization module, used for carrier synchronization;

[0039] A demodulation module, used for coherent demodulation and decision-making to obtain a signal after decision;

[0040] The equalization module is used to perform equalization processing on the judged signal to remove inter-code interference.

[0041] The above-mentioned main scheme of the present application and its further options can be freely combined to form multiple schemes, all of which are schemes that can be adopted and claimed for protection in the present application; and in the present application, (non-conflicting options) options and other options can also be freely combined. After understanding the scheme of the present application, those skilled in the art can understand that there are multiple combinations based on the prior art and common knowledge, all of which are technical schemes to be protected by the present application, and they are not exhaustively listed here.

[0042] The present application discloses a 32APSK parallel demodulation method and system, firstly, receiving a radio frequency signal through an antenna and converting the radio frequency signal into an intermediate frequency signal through a receiving channel through frequency conversion processing, performing digital-to-analog conversion to obtain an intermediate frequency digital signal, grouping according to a fixed length to obtain a fixed-length data packet, mixing the intermediate frequency digital signal in the data packet with two in-phase orthogonal carriers to obtain a mixed signal, and then filtering the mixed signal through a low-pass filter to generate an in-phase baseband signal and an orthogonal baseband signal; resampling, frequency deviation estimation, carrier synchronization, coherent demodulation and judgment of the in-phase baseband signal and the orthogonal baseband signal in turn to obtain a signal after judgment, and finally performing equalization processing to remove inter-code interference. It has the advantages of low data dependence and high parallelism. After obtaining I and Q signals, open loop is used to realize symbol synchronization and carrier synchronization, with high parallelism, and is suitable for 32APSK signal demodulation on GPU platforms and at any rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 A flow chart of a 32APSK parallel demodulation method proposed in an embodiment of the present application is shown.

[0045] Figure 2 A flow chart from receiving channel to data packetization proposed in an embodiment of the present application is shown.

[0046] Figure 3 A flowchart of the resampling to equalization process proposed in an embodiment of the present application is shown.

[0047] Figure 4 The constellation diagram after low-pass filtering proposed in the embodiment of the present application is shown.

[0048] Figure 5 The constellation diagram after coherent demodulation proposed in the embodiment of the present application is shown.

[0049] Figure 6 The diagram shows the effect after equalization proposed in the embodiment of the present application.

[0050] Figure 7 A bit error performance diagram after 32APSK demodulation is shown in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0052] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0053] In the traditional demodulation scheme, the symbol synchronization module is implemented using the Gardner loop, and the carrier synchronization module is implemented using the four-phase loose-tail loop. Both modules are feedback loops. This continuous feedback adjustment requires frequent thread synchronization on the one hand, and increases the data dependency within the algorithm on the other hand. The parallelism is poor and is not suitable for the GPU platform.

[0054] Therefore, in order to solve the problems of multiple feedback loops, serious data dependence, and inability to parallelize processing in traditional 32APSK demodulation systems and methods, the embodiment of the present application proposes a 32APSK parallel demodulation method and system, which has the advantages of low data dependence and high parallelism. After obtaining the I and Q signals, the loop algorithms such as the Gardner loop and the four-phase loose tail loop in the traditional method are abandoned, and the open loop is used to achieve symbol synchronization and carrier synchronization. The parallelism is high and it is suitable for GPU platforms and 32APSK signal demodulation at any rate. It is described in detail below.

[0055] Please refer to Figure 1 , Figure 1 A schematic flow chart of a 32APSK parallel demodulation method proposed in an embodiment of the present application is shown, and the method comprises the following steps:

[0056] Step S1, receiving a radio frequency signal through an antenna and converting the radio frequency signal into an intermediate frequency signal through a receiving channel through frequency conversion processing.

[0057] After the RF signal is captured by the antenna, it enters the receiving channel, where it is converted into an intermediate frequency (IF) signal through frequency conversion (up-conversion or down-conversion), which simplifies subsequent circuit design, reduces requirements on component performance, and facilitates signal processing.

[0058] Step S2: performing digital-to-analog conversion on the intermediate frequency signal to obtain an intermediate frequency digital signal, and grouping the intermediate frequency digital signal according to a fixed length to obtain a fixed-length data packet.

[0059] The intermediate frequency signal is converted from the analog domain to the digital domain and becomes a digital signal through an analog-to-digital converter. In order to facilitate processing and transmission, the intermediate frequency digital signal will be divided into data packets of fixed length, dividing the continuous digital signal stream into data blocks or data packets of fixed length.

[0060] Figure 2 A flow chart from receiving channel to data packetization proposed in an embodiment of the present application is shown. First, the signal is received by the RF (radio frequency) receiving channel; then these signals are converted into digital streams through IF (intermediate frequency) digital conversion; then at the center of the data stream, the data is input into the "data packetization" link and split into smaller data packets (packetized data).

[0061] The range of fixed length L is where f s is the sampling rate of the digital-to-analog conversion, and Δf is the difference between the actual carrier frequency and the estimated carrier frequency.

[0062] Step S3, mixing the intermediate frequency digital signal in the data packet with two in-phase orthogonal carriers to obtain a mixed signal;

[0063] The conversion from IF to baseband is completed by multiplying the IF digital signal with the locally generated in-phase and quadrature carriers. The two signals generated represent the in-phase component I and the quadrature component Q of the original signal respectively.

[0064] Step S4, filtering the mixed signal through a low-pass filter to generate an in-phase baseband signal and an orthogonal baseband signal;

[0065] The mixed signal passes through a low-pass filter to filter out high-frequency noise and unnecessary components, retaining the baseband signal close to DC, thereby obtaining pure I and Q baseband signals.

[0066] The signal symbol rate rs is obtained by receiving the signal and converting the digital-to-analog signal, and performing orthogonal down-conversion and low-pass filtering on the received digital signal to obtain the constellation diagram after low-pass filtering. Figure 4 The constellation diagram after low-pass filtering proposed in the embodiment of the present application is shown.

[0067] Step S5, resampling the in-phase baseband signal and the quadrature baseband signal in sequence, frequency offset estimation and symbol distribution determination, carrier synchronization, coherent demodulation and decision making are performed to obtain a decided signal.

[0068] Resampling adjusts the sampling rate of the signal according to the needs of demodulation and processing, including upsampling or downsampling, to match the sampling rate requirements of subsequent processing links. Frequency offset estimation and symbol distribution estimate the frequency offset of the received signal relative to the local reference clock by analyzing the signal characteristics, and determine the starting position and distribution of each symbol accordingly to prepare for carrier synchronization. Based on the results of frequency offset estimation, carrier synchronization further accurately calculates the frequency and phase of the carrier to achieve precise alignment of the receiving and transmitting carriers. Using the parameters of frequency offset and carrier recovery, coherent demodulation is performed on the baseband signal, that is, it is converted back to the original data bit stream. This process includes amplitude and phase judgment according to the 32APSK modulation rule.

[0069] Based on step S4, the low-pass filtered signal is resampled to obtain a resampled signal I r (t) and Q r (t), the sampling rate of the resampled signal is rfs, rfs = rs·M, rs is the signal symbol rate, and M is the oversampling multiple (integer).

[0070] Figure 3 The flowchart of the resampling to equalization process proposed in the embodiment of the present application is shown, and the frequency deviation f obtained by the frequency deviation estimation after resampling is b is f1 / 16, where f1 is the frequency at which the peak of the 16th power spectrum of the resampled signal is located.

[0071] First, set the FFT step size to N, and divide the signal into segments of length N for frequency domain analysis. The signal s(k) is resampled to adjust its sampling rate to make it more suitable for FFT analysis or to match the sampling rate of other parts of the system. Resampling can reduce or increase the number of sampling points to meet specific analysis requirements. Calculate the spectrum of the resampled signal s(k), and further perform a 16th power operation on the amplitude value of the spectrum.

[0072] Find the frequency of the peak in the processed spectrum. This peak corresponds to the frequency component with the most concentrated energy in the signal, and in theory it should be close to the actual carrier frequency of the signal. By comparing the peak frequency found with the expected carrier frequency, we can calculate the difference between the two, which is the frequency deviation.

[0073] The steps of determining the code element distribution include:

[0074] Set the number of sampling points of the first code element to x, the number of complete code elements to y, the number of sampling points contained in each complete code element to M, the number of sampling points of the last code element to z, and calculate the integral value v corr : Where L is the signal packet length, s(k) is the resampled signal, p is the code element start point, and q is the code element end point;

[0075] The resampled signal and the estimated frequency offset f b The result of multiplying the constructed carriers s(t): s(t) = ((I(t) + j*Q(t))*exp(j·2·pi·f b t)) 8 , where I(t) is the in-phase baseband signal, Q(t) is the quadrature baseband signal, and pi is π;

[0076] Traverse the number of sampling points M, and in v corr When the maximum value is obtained, the corresponding number of sampling points x is determined.

[0077] The number of sampling points of the first symbol is set to x, which refers to the number of samples in the received signal used to represent the first symbol. The number of complete symbols is y: It refers to the total number of complete symbols in the currently processed data segment, excluding partial symbols. The number of sampling points M contained in each complete symbol is the number of sampling points that a complete symbol should contain. The number of sampling points z of the last symbol is similar to the first symbol, and may not meet M sampling points due to boundary effects.

[0078] L is the signal packet length, which is the total length of the signal segment to be analyzed, including all code elements and possible partial code elements. s(k) is the resampled signal, ensuring that the signal is suitable for further processing. Calculate the integral value v corr The estimated carrier (frequency and phase) in coherent demodulation is then used to multiply the resampled signal.

[0079] Traverse 1, 2, 3, ..., M, and check each possible starting position one by one within the range of each complete codeword length M, and find the most likely codeword boundary through integration or other decision criteria. By traversing and calculating the integral value, find the starting position (x) corresponding to the maximum integral value, which represents the most accurate codeword starting point, and then determine the codeword distribution of the entire sequence.

[0080] In a possible implementation manner, the carrier synchronization step includes:

[0081] Step S5-1: set the frequency f e The range is set to [-rfs / (8*N), rfs / (8*N)], the step is set to rfs / (4·N·U), and the initial phase The range is set to [0, π], the step is set to π / V, N is the FFT length, U represents the number of equal parts of the frequency interval, and V represents the number of equal parts of the phase interval;

[0082] Step S5-2: construct a search signal r(t):

[0083] Step S5-3, traverse (U+1)·(V+1) cases and calculate the integral value v corr , the maximum value of the integral corresponds to f1 and The estimated result of the initial parameter The corresponding step is

[0084] Step S5-4, determine whether the iterative search condition is met, if not, execute step S5-5, if yes, execute step S5-6;

[0085] Step S5-5: frequency f e The range is set to [f es -f step , f es +f step ], the stepping is set to 2f step / U, change the initial phase The range is set to The stepping is set to Return to step S5-3;

[0086] Step S5-5: Output parameter estimation results

[0087] In the process of carrier synchronization, the search space is initialized first, and the frequency f e The range is set to [-rfs / (8*N), rfs / (8*N)], and the step is set to rfs / (4·N·U), where N represents the FFT length, U represents the number of equal parts into which the frequency interval is divided, and V represents the number of equal parts into which the phase interval is divided. In this embodiment, U=16, V=16, which can be customized.

[0088] Initial Phase The range is set to [0, π], and the step is set to π / V. Then the search signal r(t) is constructed. Using the initialized frequency and phase range, a series of possible carrier signals are constructed by traversing different frequency and phase values. Next, all possible frequency and phase combinations are traversed, and the integral value of the received signal multiplied by the constructed carrier signal under each combination is calculated. The frequency f1 and phase with the largest integral value are This is the result of the initial parameter estimation. The corresponding step is

[0089] After that, iterative judgment is performed. If the accuracy of the preliminary estimate is high enough, that is, the preset iteration end condition is reached, the refined search is skipped and the parameter estimation result is directly output. Otherwise, enter a more refined search phase, update the search space, and replace the frequency f of the last parameter estimation result with e The range is set to [fes -f step , f es +f step ], the step size is set to 2·f step / U; The range is set to The stepping is set to Traverse all (U+1)·(V+1) cases again and calculate the integral value according to formula (3). The maximum integral value corresponds to f1 and This is the initial parameter estimation result The corresponding step is The iteration search is terminated until the conditions are met. Finally, the best frequency and phase estimation values ​​obtained after multiple iterations are output as the result of carrier synchronization.

[0090] In coherent demodulation, the best frequency and phase estimates are used to construct a local carrier that matches the received signal. This carrier is strictly aligned with the carrier of the received signal in frequency and phase. The received resampled signal is multiplied by this constructed local carrier. The signal is moved from the carrier to the baseband so that it can directly reflect the amplitude and phase information of the original modulated data.

[0091] The signal obtained by coherent demodulation based on the parameter estimation result is: and

[0092]

[0093] Due to the M-fold oversampling, each symbol period is divided into M equally spaced sampling points. The benefit of oversampling is that it can improve the anti-interference capability and timing accuracy. The M / 2+1th point is selected as the final value of the symbol. Figure 5 The constellation diagram after coherent demodulation proposed in the embodiment of the present application is shown.

[0094] Step S6: perform equalization processing on the judged signal to remove inter-symbol interference.

[0095] The demodulated signal is equalized to reduce or eliminate inter-symbol interference (ISI) and ensure data accuracy. The equalizer compensates for the frequency characteristics of the channel so that the waveform of each symbol at the receiving end is as close to the ideal state as possible.

[0096] The equalization module adopts the conventional Constant Modulus Algorithm (CMA) and the Least Mean Square algorithm (LMS), which will not be described here. Figure 6 The diagram shows the effect after equalization proposed in the embodiment of the present application.

[0097] Figure 7 The bit error performance diagram after 32APSK demodulation of the embodiment of the present application is shown, and the performance is comparable to that of the traditional algorithm using a feedback loop.

[0098] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0099] First, the data dependency is low and the parallelism is high. After acquiring the I and Q signals, the present invention abandons the loop algorithms such as the Gardner loop and the four-phase loose tail loop in the traditional method, and realizes the symbol synchronization and carrier synchronization in an open loop, which has high parallelism and is suitable for the GPU platform.

[0100] Second, it is suitable for 32APSK signal demodulation at any rate.

[0101] A possible implementation of a 32APSK parallel demodulation system is given below, which is used to execute the various execution steps and corresponding technical effects of the 32APSK parallel demodulation method shown in the above embodiments and possible implementations. The system includes a radio frequency receiving channel, an analog-to-digital conversion module, a data packetization module, an orthogonal down-conversion module, a low-pass filtering module, a resampling module, a symbol synchronization module, a carrier synchronization module, a demodulation module, and an equalization module;

[0102] The RF receiving channel is used to convert the received RF signal into an intermediate frequency signal through frequency conversion processing;

[0103] The analog-to-digital conversion module is used to perform digital-to-analog conversion on the intermediate frequency signal to obtain an intermediate frequency digital signal;

[0104] A data packetization module is used to group the intermediate frequency digital signal into fixed-length packets to obtain fixed-length packets;

[0105] The orthogonal down-conversion module is used to mix the intermediate frequency digital signal in the data packet with two in-phase orthogonal carriers to obtain a mixed signal;

[0106] A low-pass filtering module, used for filtering the mixed signal through a low-pass filter to generate an in-phase baseband signal and an orthogonal baseband signal;

[0107] A resampling module, used for sequentially resampling an in-phase baseband signal and an orthogonal baseband signal;

[0108] A symbol synchronization module is used to estimate frequency offset and determine symbol distribution;

[0109] A carrier synchronization module, used for carrier synchronization;

[0110] A demodulation module, used for coherent demodulation and decision-making to obtain a signal after decision;

[0111] The equalization module is used to perform equalization processing on the judged signal to remove inter-code interference.

[0112] The RF receiving channel is responsible for receiving RF signals from space or wired links and converting them into intermediate frequency signals. This reduces the complexity of subsequent processing and filters out unwanted out-of-band interference. The intermediate frequency signals received by the analog-to-digital conversion module (AD) are converted into digital signals so that the computer can process them. The data packetization module divides the continuous digital signals into data packets that are easy to process.

[0113] The orthogonal down-conversion module converts the intermediate frequency digital signal to the baseband and separates the in-phase component (I path) and the orthogonal component (Q path) of the signal, which is completed by multiplying the locally generated orthogonal carrier to achieve the complex representation of the signal. The low-pass filter module (LPF) filters out the multiplied frequency components generated by the down-conversion operation in the I-path and Q-path signals, retains the baseband signal, and ensures the purity of the signal. The resampling module adjusts the sampling rate of the signal according to system requirements, which may be used to match different system clocks, or optimize processing efficiency, and sometimes it is also used to eliminate clock deviations caused by inconsistent processing speeds of different parts.

[0114] The symbol synchronization module estimates and corrects the frequency deviation (frequency offset) between the received signal and the local clock, and determines the exact start time of each symbol. The carrier recovery module estimates and compensates for the carrier frequency offset and phase offset in the received signal by analyzing the I and Q signals, achieving precise synchronization of the carrier and ensuring the accuracy of demodulation. The demodulation module uses the synchronization information obtained previously to convert the baseband signal into the original data stream. For 32APSK, this means identifying 32 different amplitude and phase combinations, corresponding to 32 possible data symbols. The equalization module uses an equalizer to compensate for distortion caused by the channel, such as multipath propagation effects, to further improve signal quality and ensure that the data is decoded correctly.

[0115] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A 32APSK parallel demodulation method, characterized in that: The method comprises: Receive the radio frequency signal through the antenna and convert the radio frequency signal into an intermediate frequency signal through the receiving channel through frequency conversion processing; Performing digital-to-analog conversion on the intermediate frequency signal to obtain an intermediate frequency digital signal, and grouping the intermediate frequency digital signal according to a fixed length to obtain a fixed-length data packet; Mixing the intermediate frequency digital signal in the data packet with two in-phase and orthogonal carriers to obtain a mixed signal; The mixed signal is filtered by a low-pass filter to generate an in-phase baseband signal and a quadrature baseband signal; The in-phase baseband signal and the orthogonal baseband signal are sequentially resampled, frequency offset estimated, code element distribution determined, carrier synchronization, coherently demodulated and judged to obtain a judged signal; The judged signal is equalized to remove inter-code interference.

2. The 32APSK parallel demodulation method according to claim 1, characterized in that: The range of fixed length L is where f s is the sampling rate of the digital-to-analog conversion, and Δf is the difference between the actual carrier frequency and the estimated carrier frequency.

3. The 32APSK parallel demodulation method according to claim 2, characterized in that: The sampling rate of the resampled signal is rfs, rfs=rs·M, rs is the signal symbol rate, and M is the oversampling multiple.

4. The 32APSK parallel demodulation method according to claim 1, characterized in that: The frequency deviation f obtained by resampling the frequency deviation estimation b is f1 / 16, where f1 is the frequency at which the peak of the 16th power spectrum of the resampled signal is located.

5. The 32APSK parallel demodulation method according to claim 4, characterized in that: The steps of determining the code element distribution include: Set the number of sampling points of the first code element to x, the number of complete code elements to y, the number of sampling points contained in each complete code element to M, the number of sampling points of the last code element to z, and calculate the integral value v corr : Where L is the signal packet length, s(k) is the resampled signal, p is the code element start point, and q is the code element end point; The resampled signal and the estimated frequency offset f b The result of multiplying the constructed carriers s(t): s(t) = ((I(t) + j*Q(t))*exp(j·2·pi·f b t)) 8 , where I(t) is the in-phase baseband signal and Q(t) is the quadrature baseband signal; Traverse the number of sampling points M, and in v corr When the maximum value is obtained, the corresponding number of sampling points x is determined.

6. The 32APSK parallel demodulation method according to claim 5, characterized in that: The steps of carrier synchronization include: Step S5-1: set the frequency f e The range is set to [-rfs / (8*N), rfs / (8*N)], the step is set to rfs / (4·N·U), and the initial phase The range is set to [0, π], the step is set to π / V, N is the FFT length, U represents the number of equal parts of the frequency interval, and V represents the number of equal parts of the phase interval; Step S5-2: construct a search signal r(t): Step S5-3, traverse (U+1)·(V+1) cases and calculate the integral value v corr , the maximum value of the integral corresponds to f1 and The estimated result of the initial parameter The corresponding step is Step S5-4, determine whether the iterative search condition is met, if not, execute step S5-5, if yes, execute step S5-6; Step S5-5: frequency f e The range is set to [f es -f step , f es +f step ], the stepping is set to 2f step / U, the initial phase The range is set to The stepping is set to Return to step S5-3; Step S5-5: Output parameter estimation results 7. The 32APSK parallel demodulation method according to claim 1, characterized in that: The signal obtained by coherent demodulation based on the parameter estimation result is: and 8. A 32APSK parallel demodulation system, characterized in that: The system includes a radio frequency receiving channel, an analog-to-digital conversion module, a data packetization module, an orthogonal down-conversion module, a low-pass filtering module, a resampling module, a symbol synchronization module, a carrier synchronization module, a demodulation module and an equalization module; The RF receiving channel is used to convert the received RF signal into an intermediate frequency signal through frequency conversion processing; The analog-to-digital conversion module is used to perform digital-to-analog conversion on the intermediate frequency signal to obtain an intermediate frequency digital signal; A data packetization module is used to group the intermediate frequency digital signal into fixed-length packets to obtain fixed-length packets; The orthogonal down-conversion module is used to mix the intermediate frequency digital signal in the data packet with two in-phase orthogonal carriers to obtain a mixed signal; A low-pass filtering module, used for filtering the mixed signal through a low-pass filter to generate an in-phase baseband signal and an orthogonal baseband signal; A resampling module, used for sequentially resampling an in-phase baseband signal and an orthogonal baseband signal; A symbol synchronization module is used to estimate frequency offset and determine symbol distribution; A carrier synchronization module, used for carrier synchronization; A demodulation module, used for coherent demodulation and decision-making to obtain a signal after decision; The equalization module is used to perform equalization processing on the judged signal to remove inter-code interference.

Images