Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the steps that a substrate is provided, a stacking layer formed by alternately arranging a plurality of first sacrificial layers and a plurality of second sacrificial layers is formed on the substrate, and the second sacrificial layers and the substrate are made of the same material; forming a vertical opening penetrating through the stack layer, extending into the substrate, and forming a cavity in the substrate; forming a protective layer in the concave cavity of the substrate; taking the protection layer as an etching stop layer, and transversely etching a part of the second sacrificial layer in the stack layer along the vertical opening to form a plurality of side cavities which are arranged at intervals in the vertical direction; forming a plurality of lower electrodes on the surface of the second sacrificial layer exposed by the plurality of side cavities; forming a capacitor dielectric layer on the surfaces of the plurality of lower electrodes, wherein the capacitor dielectric layer is also located in the vertical opening and is in contact with the protection layer; an upper electrode is formed on the surface of the capacitor dielectric layer, and the multiple lower electrodes, the capacitor dielectric layer and the upper electrode form a capacitor structure. The embodiment of the invention can improve the performance of the device.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to semiconductor devices and methods for making the same. Background Art

[0002] The development of memory pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technical barriers encountered by existing structures are becoming more and more obvious. Therefore, developing more novel structures based on existing structures is a favorable means to break through existing technical barriers.

[0003] The emergence of three-dimensional memory meets the above needs. However, in the process of manufacturing three-dimensional memory, when etching the stacked layers to form the active layer of the device, or forming a capacitor, especially when etching the stacked layers through a lateral wet etching process, the substrate is easily severely damaged, resulting in device failure. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a method for preparing a semiconductor device is provided, comprising: providing a substrate, and forming a stacked layer of alternatingly arranged multiple first sacrificial layers and multiple second sacrificial layers on the substrate, wherein the second sacrificial layers and the substrate are made of the same material; forming a vertical opening that penetrates the stacked layer, and the vertical opening extends into the substrate to form a cavity in the substrate; forming a protective layer in the cavity of the substrate; using the protective layer as an etching stop layer, and laterally etching part of the second sacrificial layer in the stacked layer along the vertical opening to form a plurality of side cavities arranged at intervals in the vertical direction; forming a plurality of lower electrodes on the surfaces of the second sacrificial layers exposed in the plurality of side cavities; forming a capacitor dielectric layer on the surfaces of the plurality of lower electrodes, the capacitor dielectric layer also being located in the vertical opening and in contact with the protective layer; and forming an upper electrode on the surface of the capacitor dielectric layer, wherein the plurality of lower electrodes, the capacitor dielectric layer and the upper electrode constitute a capacitor structure.

[0005] In some embodiments, the protective layer extends from the substrate toward the stacked layer, and the extension height of the protective layer is less than or equal to the height of the top surface of the second layer among the multiple first sacrificial layers, and greater than or equal to the height of the top surface of the substrate, wherein the first layer among the multiple first sacrificial layers is located on the top surface of the substrate.

[0006] In some embodiments, forming a protective layer in the cavity of the substrate includes: forming a silicon oxide layer on the sidewall of the cavity; forming a silicon germanium layer on the bottom wall of the cavity, wherein the silicon germanium layer fills the cavity and contacts the silicon oxide layer.

[0007] In some embodiments, after forming a plurality of side cavities, the preparation method further includes processing the protective layer, including: oxidizing the surface of the silicon germanium layer to form a silicon germanium oxide layer, the silicon germanium oxide layer being located on the remaining silicon germanium layer; removing germanium atoms in the silicon germanium oxide layer by acidic gas to form a silicon oxide layer having pores; continuing to remove the remaining silicon germanium layer along the pores by acidic gas to form a cavity, the cavity being located below the oxide layer having pores, and exposing the silicon oxide layer located on the sidewalls of the cavity and the substrate on the bottom wall of the cavity.

[0008] In some embodiments, forming a protective layer in the cavity of the substrate includes: forming a silicon oxide layer on the sidewall of the cavity; forming a boron-doped silicon layer on the bottom wall of the cavity, wherein the boron-doped silicon layer fills the cavity and contacts the silicon oxide layer.

[0009] In some embodiments, forming a protective layer in the cavity of the substrate includes: performing a second in-situ water vapor growth process on the surface of the exposed substrate at a pressure of 0-5 Torr and a temperature of 900-1000°C to form a first silicon oxide layer; and / or performing a second in-situ water vapor growth process at a pressure of 10-15 Torr and a temperature of 700-850°C to form a second silicon oxide layer.

[0010] In some embodiments, the preparation method also includes: forming a plurality of active layers arranged in a vertical direction in the stacked layer, the active layer extending in a first horizontal direction, and the active layer being composed of a second sacrificial layer; forming a plurality of word lines arranged in a vertical direction in the stacked layer, the word lines being arranged on the active layer and extending in a second horizontal direction intersecting the first horizontal direction; forming at least one bit line extending in the vertical direction in the stacked layer, the active layer contacting the bit line and the lower electrode of the capacitor structure at both ends of the first horizontal direction, respectively.

[0011] According to a second aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate having a cavity; a protective layer located in the cavity of the substrate; a capacitor located on the substrate, the capacitor comprising: a plurality of lower electrodes arranged at intervals along a vertical direction on the substrate; a capacitor dielectric layer located on the surfaces of the plurality of lower electrodes, and the capacitor dielectric layer and the protective layer are in contact with each other; and an upper electrode located on the surface of the capacitor dielectric layer.

[0012] In some embodiments, the protective layer includes: a silicon oxide layer located on the sidewall of the cavity; a silicon oxide layer with pores, located between the silicon oxide layers on the sidewall of the cavity and contacting the silicon oxide layer on the sidewall of the cavity, and a cavity, located below the silicon oxide layer with pores, and the cavity exposes the silicon oxide layer on the sidewall of the cavity and the substrate of the bottom wall of the cavity; wherein the capacitor dielectric layer conformally covers the surface of the silicon oxide layer with pores and the surface of the silicon oxide on the sidewall of the cavity.

[0013] In some embodiments, the semiconductor device further includes: a plurality of active layers arranged at intervals along the vertical direction, the active layers extending along a first horizontal direction; a plurality of word lines arranged at intervals along the vertical direction, the word lines being disposed on the active layers and extending along a second horizontal direction intersecting the first horizontal direction; and at least one bit line, the bit line extending along the vertical direction, the active layer contacting the bit line and the lower electrode of the capacitor structure at both ends of the first horizontal direction, respectively.

[0014] In an embodiment of the present disclosure, a method for preparing a semiconductor device is provided, wherein a stacked layer of a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately is formed on a substrate, wherein the second sacrificial layers and the substrate are made of the same material, and then the stacked layer is etched and an electrode material is deposited to form a capacitor including a plurality of lower electrodes, a capacitor dielectric layer and an upper electrode. In an embodiment of the present disclosure, a protective layer is provided on the surface of the substrate, so that before etching the stacked layer, especially when the second sacrificial layer made of the same material as the substrate is removed by lateral etching, the substrate is protected. In addition, the embodiments of the present disclosure can also improve the leakage current formed between the substrate and the device, thereby improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figures 1A to 11C A schematic diagram showing the structure of each stage in the semiconductor device manufacturing process of an exemplary embodiment; Figure 12 to Figure 14 A schematic diagram showing the structure of each stage in a semiconductor device manufacturing process according to another exemplary embodiment; Figures 15 to 21 A schematic diagram showing the structure of each stage in a semiconductor device manufacturing process according to another exemplary embodiment; Fig. 22 The diagram is a schematic structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0016] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0017] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0018] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, such that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0019] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0020] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0021] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0022] The present disclosure also provides a method for preparing a semiconductor device, the method comprising providing a substrate, and forming a stacked layer of a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately on the substrate, wherein the second sacrificial layers and the substrate are made of the same material; forming a vertical opening penetrating the stacked layer, and the vertical opening extending into the substrate to form a cavity in the substrate; forming a protective layer in the cavity of the substrate; using the protective layer as an etching stop layer, etching part of the second sacrificial layer in the stacked layer laterally along the vertical opening to form a plurality of side cavities arranged at intervals in the vertical direction; forming a plurality of lower electrodes on the surfaces of the second sacrificial layers exposed in the plurality of side cavities; forming a capacitor dielectric layer on the surfaces of the plurality of lower electrodes, the capacitor dielectric layer also being located in the vertical opening and in contact with the protective layer; forming an upper electrode on the surface of the capacitor dielectric layer, wherein the plurality of lower electrodes, the capacitor dielectric layer and the upper electrode constitute a capacitor structure.

[0023] In the embodiment of the present disclosure, a stacked layer of multiple first sacrificial layers and multiple second sacrificial layers arranged alternately is formed on a substrate, and the second sacrificial layers and the substrate are made of the same material. Afterwards, the stacked layer is etched and the electrode material is deposited to form a capacitor including multiple lower electrodes, a capacitor dielectric layer and an upper electrode. In the embodiment of the present disclosure, by providing a protective layer on the surface of the substrate, the substrate is protected before etching the stacked layer, especially when the second sacrificial layer made of the same material as the substrate is removed by lateral etching. In addition, the embodiment of the present disclosure can also improve the leakage current formed between the substrate and the device, thereby improving the device performance.

[0024] Figures 1A to 11C The structure diagram of each stage in the semiconductor device manufacturing process of an exemplary embodiment is shown. Figure 1A , 2A , and 11A are plan schematic diagrams of each stage in the preparation of a semiconductor device. Figure 1B , 2B , Figures 3 to 10 ,as well as Fig. 11B They are cross-sectional views taken along line AA' at various stages in the preparation of a semiconductor device. Figure 1C and Fig. 11C The following are cross-sectional views taken along the BB' line at each stage in the preparation of the semiconductor device. Figures 1A to 11C The semiconductor structure and the preparation process thereof provided by the embodiments of the present disclosure are described in detail.

[0025] Please refer to Figures 1A to 1C , a substrate 100 is provided, and a stacked layer ST of a plurality of first sacrificial layers 110 and a plurality of second sacrificial layers 120 arranged alternately is formed on the substrate 100. The plurality of first sacrificial layers 110 are arranged on the substrate 100 along a vertical direction Z and are spaced apart from each other, and the first sacrificial layer of the bottom layer (i.e., the first layer) is located on the substrate 100. The plurality of second sacrificial layers 120 are also arranged on the substrate 100 along a vertical direction Z and are spaced apart from each other, and the second sacrificial layer of the bottom layer (i.e., the first layer) is located on the first sacrificial layer 110.

[0026] Please continue to refer to Figures 1A to 1C , a plurality of third sacrificial layers 130 are formed in the stacked layer ST. The plurality of third sacrificial layers 130 extend along the first horizontal direction X, and separate the plurality of first sacrificial layers 110 from each other in the second horizontal direction Y, the first sacrificial layers 110 extend along the first horizontal direction X, and the plurality of second sacrificial layers 120 from each other in the second horizontal direction Y, the second sacrificial layers 120 extend along the first horizontal direction X. The first horizontal direction X and the second horizontal direction Y intersect with each other. In some embodiments, the first horizontal direction X and the second horizontal direction Y are perpendicular to each other, and are both perpendicular to the vertical direction Z.

[0027] The material of the substrate 100 includes a semiconductor material, for example, a single-element semiconductor material (for example, silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), a II-VI compound semiconductor material (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), an organic semiconductor material or other semiconductor materials known in the art.

[0028] The material of the first sacrificial layer 110 is, for example, at least one of silicon oxide, silicon nitride or silicon oxynitride. The second sacrificial layer 120 is the same material as the substrate 100. In some embodiments, the substrate is, for example, a silicon substrate, and the second sacrificial layer 120 is also a silicon layer accordingly. The material of the third sacrificial layer 130 is, for example, polysilicon or a carbon layer. The second sacrificial layer 120 in the stacked layer ST includes a silicon layer of the same material as the substrate 100, which can not only be directly used as the material of the active layer 200 of the semiconductor device, but also has a large etching selectivity ratio with the materials of the first sacrificial layer 110 and the third sacrificial layer 130, which is conducive to the patterning process. In the embodiment of the present disclosure, the semiconductor device in the present disclosure is formed by patterning and pattern filling the first sacrificial layer 110, the second sacrificial layer 120 and the third sacrificial layer 130.

[0029] Please refer to Figure 1B , among the multiple first sacrificial layers 110, the first sacrificial layer 110-1 located in the first layer has a first thickness H1, and the remaining first sacrificial layers 110-2, 110-3 ... 110-N may have substantially the same second thickness H2. Among the multiple second sacrificial layers 120, each second sacrificial layer 120-1, 120-2 ... 120-N may have substantially the same third thickness H3. The first thickness H1 may be greater than the second thickness H2, and the second thickness H2 may be greater than the third thickness H3. The first sacrificial layer 110-1 with the first thickness H1 is a layer directly contacting the substrate 100, which may be used as a dummy layer and has a relatively large thickness, which may improve the damage to the substrate 100 caused by the subsequent lateral etching of the second sacrificial layer 120 and the third sacrificial layer 130. The second sacrificial layer 120 with the third thickness H3 is made of the same material as the substrate 100. After patterning, it may be used as a device layer in a semiconductor device. It has a relatively small thickness and may provide a semiconductor device with a higher stacking density. The first sacrificial layer with the second thickness H2 is used as an isolation layer between device layers. Its thickness is between the first thickness H1 and the third thickness H3. It can provide an ideal isolation effect between device layers and protect the device surface.

[0030] Please refer to FIG. 2A to FIG. 2B , a plurality of initial active layers 200a are formed in the stacked layer ST. The initial active layer 200a is a part of the second sacrificial layer 120, and after patterning, the final active layer 200 (such as FIG. 11A to FIG. 11C As shown). The multiple initial active layers 200a may be arranged in a spaced relationship from each other in the vertical direction Z and the second horizontal direction Y. The multiple initial active layers 200a extend along the first horizontal direction X. The multiple initial active layers 200a are isolated from each other by an isolation structure, and the isolation structure may include at least one of silicon oxide, silicon nitride, silicon oxynitride or polysilicon, for example, Figure 2A and 2BAs shown, the plurality of initial active layers 200 a arranged at intervals in the vertical direction Z are isolated from each other by the first sacrificial layer 110 . The plurality of initial active layers 200 a arranged at intervals in the second horizontal direction Y are isolated from each other by the third sacrificial layer 130 .

[0031] In the embodiment of the present disclosure, by selectively etching the second sacrificial layer 120, an initial active layer 200a can be formed, and further an active layer 200 of the transistor Tr is formed, and the active layer 200 includes a first source / drain region, a channel region, and a second source / drain region arranged in sequence along the first horizontal direction Y. That is, the active layer 200 is composed of the second sacrificial layer 120 in the stacked layer ST, and the material is the same as that of the substrate 100, which is single crystal silicon. In some embodiments of the present disclosure, before performing lateral wet etching of the silicon layer, the exposed silicon substrate can be protected by a protective layer to prevent the substrate from being severely damaged by wet etching, while improving the leakage current between the device and the substrate.

[0032] Please continue to refer to FIG. 2A to FIG. 2B , a plurality of word lines 300 arranged at intervals along the vertical direction Z are formed in the stacked layer ST. The word lines 300 are formed in the first sacrificial layer 110. In some embodiments, the plurality of word lines 300 are arranged at intervals along the vertical direction Z and the first horizontal direction X. The word lines 300 intersect with the active layer 200, extend along the second horizontal direction Y, and are disposed on the corresponding plurality of active layers 200 in the second horizontal direction Y to form the gate electrode of the transistor Tr, and the gate electrode covers the channel region of the active layer 200. A gate dielectric layer is also included between the word lines 300 and the active layer 200. The gate electrode of the transistor in the present disclosure may be a GAA type (Gate all around), a CAA type (Channel all around), a double-gate type DG (double-gate) or a single-gate type SG (single-gate) gate electrode. For example, a double-gate gate electrode is used. In this case, the word line 300 is also a corresponding horizontal double word line. Each word line 300 includes a pair of conductive wires disposed on two opposite surfaces of the active layer 200 in the vertical direction Z.

[0033] The material of the gate dielectric layer can be selected from at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric film having a dielectric constant higher than that of silicon oxide, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO3), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), and zirconium oxide (ZrO).

[0034] The material of word line 300 can be selected from at least one of doped polysilicon, metal, metal nitride or metal carbide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), titanium silicon carbonitride (TiSiCN), tantalum aluminum carbonitride (TaAlCN) and tantalum silicon carbonitride (TaSiCN).

[0035] Please continue to refer to FIG. 2A to FIG. 2B , at least one bit line 400 extending along the vertical direction Z is formed in the stacked layer ST. In some embodiments, a plurality of bit lines 400 are formed. The plurality of bit lines 400 are arranged in a first horizontal direction X and a second horizontal direction Y, and each bit line 300 extends along the vertical direction Z. Figure 2A and Figure 2B As shown, each bit line 300 contacts one end of multiple active layers 200 in the vertical direction Z, such as the first source / drain region of the active layer 200. It is worth noting that the bit line 400 is shared between adjacent memory cells in the first horizontal direction X, and the two are mirror-symmetric with each other about the bit line 400.

[0036] The material of the bit line 300 can be selected from at least one of doped polysilicon, metal, metal nitride or metal carbide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), titanium silicon carbonitride (TiSiCN), tantalum aluminum carbonitride (TaAlCN) and tantalum silicon carbonitride (TaSiCN).

[0037] Please refer to Figure 3 At least one vertical opening 100A is formed in the stacked layer ST. The vertical opening 100A is between adjacent word lines 300 in the first horizontal direction X, providing a deposition space for the subsequent formation of a capacitor 400. Please continue to refer to Figure 3 , forming a vertical opening 100A penetrating the stacked layer ST, and the vertical opening 100A extends into the substrate 100, forming a cavity 100B in the substrate. The substrate cavity 100B includes a bottom wall 101 and two side walls 102 located on both sides of the bottom wall 101. The two side walls 102 are opposite to each other. The vertical opening 100A extends along the second horizontal direction Y, exposing the first sacrificial layer 110, the second sacrificial layer 120, the third sacrificial layer 130 in the stacked layer ST, and a portion of the surface of the substrate 100. The vertical opening 100A disconnects the initial active layer 200a in the first horizontal direction X to form an intermediate active layer 200b.

[0038] Please refer to Figure 4 , a conformally covered first protective material 141 is formed in the vertical opening 100A, and the first protective material covers the surfaces of the first sacrificial layer 110, the second sacrificial layer 120, the third sacrificial layer 130, and the surface of the substrate cavity 100B. Figure 4 , the first protective material 141 located at the bottom wall 101 of the cavity and the top surface of the stacked layer ST is removed, so that the bottom wall 101 of the substrate 100 extending along the second horizontal direction Y is exposed again. The remaining first protective material 141 is located at the sidewall of the vertical opening 100A, covering the side surfaces of the first sacrificial layer 110, the second sacrificial layer 120, the third sacrificial layer 130 and the sidewall 102 of the cavity.

[0039] The first protective material 141 is, for example, a silicon oxide layer formed by an atomic layer deposition (ALD) process, which not only has a relatively ideal density but also has a uniform thickness, and can well cover the material surface, provide a barrier, and protect the substrate surface to facilitate subsequent process steps.

[0040] Please refer to Figure 5 , a second protective material 142 is filled in the cavity 100B of the substrate 100 along the vertical opening 100A. The second protective material 142 covers the bottom wall 101 of the cavity and extends from the substrate 100 toward the stacked layer ST. The extension height of the second protective material 142 is less than or equal to the height of the top surface of the second layer 110-2 in the plurality of first sacrificial layers, and is greater than or equal to the height of the top surface of the substrate 100. In some embodiments, the extension height of the second protective material 142 is less than the height of the top surface of the second layer 110-2 in the plurality of first sacrificial layers. In some embodiments, the extension height of the second protective material 142 is higher than the height of the top surface of the substrate 100. When the extension height H110 of the protective layer 150 is too low, for example, lower than the top surface of the substrate 100, it will be difficult to protect the shoulder of the substrate 100, and the shoulder of the substrate 100 may be easily damaged during lateral wet etching, resulting in device failure. When the extension height H110 of the protection layer 150 is too high, for example, higher than the first sacrificial layer 110-2 of the second layer, it is easy to affect the devices in the storage unit in the second layer, thereby reducing the integration density of the semiconductor device. Figure 5 As shown, in some embodiments, the second protection material 142 extends to the top surface of the first sacrificial layer 110 - 1 of the first layer (ie, the first sacrificial layer 110 - 1 located on the top surface of the substrate 100 and having the first thickness H1 ).

[0041] Please continue to refer to Figure 5In a specific embodiment of the present disclosure, a silicon germanium layer (SiGe) of a single crystal structure is selectively and directionally grown on the substrate surface of the exposed cavity bottom wall 101 along the vertical opening 100A by, for example, a selective epitaxial growth (SEG) process as a second protective material 142. The silicon germanium layer fills the cavity 100B in the substrate 100 and extends to cover the first sacrificial layer 110-1 of a part of the first layer. The silicon germanium layer extends along the second horizontal direction Y. There is a first protective material 141 between the silicon germanium layer and the cavity sidewall 102. In the embodiment of the present disclosure, the silicon germanium layer and the silicon substrate 100 have similar lattices. The silicon germanium layer directionally grown on the cavity bottom wall 101 not only has a simple process and a regular morphology, but also has little effect on other process steps or device performance. When etching, for example, wet etching the second sacrificial layer 102 of the same material as the substrate 100 in the stacked layer, the silicon germanium layer will not be completely consumed, thereby protecting the surface of the substrate 100.

[0042] Of course, in other embodiments, a single crystal silicon layer (Si) can be selectively and directionally grown on the substrate surface of the exposed cavity bottom wall 101 by a selective epitaxial growth (SEG) process. Specifically, single crystal silicon doped with P-type ions, such as single crystal silicon doped with boron (B) ions, can be epitaxially grown to form multi-hole P-type silicon, thereby suppressing the etching rate of the silicon layer by the etching solution during wet etching.

[0043] Please refer to Figure 6 , remove the first protective material 141 exposed by the vertical opening 100A, that is, remove the first protective material 141 not covered by the second protective material 142, so that the first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130 located on the sidewall of the vertical opening 100A are exposed again. The remaining first protective material 141 is located on the sidewall 102 of the cavity, and the second protective material 142 is located on the bottom wall 101 of the cavity. The top surfaces of the two are flush and in contact with each other, forming an exemplary protective layer 140 of the present disclosure.

[0044] Please refer to Figure 7, continue to use the protection layer 140 as an etching stop layer, and etch part of the second sacrificial layer 120 in the stacked layer ST along the vertical opening 100A, forming a plurality of side cavities 100C arranged at intervals in the first horizontal direction X, the second horizontal direction Y, and the vertical direction Z. The remaining plurality of second sacrificial layers 120 form the final plurality of active layers 200, that is, the active layer 200 is formed by the middle active layer 200b. At this time, according to the embodiment of the present disclosure, the plurality of active layers 200 are arranged at intervals in the vertical direction Z, the first horizontal direction X, and the second horizontal direction Y, and are arranged in a three-dimensional array on the substrate 100, so as to form a three-dimensional semiconductor device. The active layer 200 is located between the word lines 300, and one end of the active layer 200 in the first horizontal direction X contacts the bit line 400, and the other end is exposed by the side cavity 100C. After a plurality of lower electrodes 510 of the capacitor structure 500 are subsequently formed in the plurality of side cavities 100C, the active layer 200 contacts the lower electrode 510 at the other end of the first horizontal direction X.

[0045] In the embodiment of the present disclosure, the second sacrificial layer 120 is side-etched by lateral wet etching, and by controlling the type of etching solution, etching rate and other factors during the wet etching process, it can be ensured that the removed second sacrificial layer 120 is relatively complete, and the formed active layer 200 has a regular morphology, which effectively improves the electrical performance of the device. In the embodiment of the present disclosure, the second sacrificial layer 120 and the substrate 100 are made of the same material. Before the lateral wet etching of the second sacrificial layer 120 is performed, the protective layer 140 is formed on the exposed surface of the substrate 100 to protect the surface of the substrate 100 and effectively improve the damage of the substrate 100.

[0046] Please refer to Figure 8 and Fig. 9 , multiple side cavities 100C are connected to the vertical opening 100A to form a comb-shaped opening space, and a lower electrode material 510' is deposited along the comb-shaped opening space. The lower electrode material 510' conformally covers the surfaces of the first sacrificial layer 110, the second sacrificial layer 120, the third sacrificial layer 130, and the protective layer 140. Afterwards, please refer to Fig. 9 , along the vertical opening 100A, the lower electrode material 510' exposed in the vertical opening 100A is removed to form a plurality of lower electrodes 510 spaced apart from each other in the first horizontal direction X, the second horizontal direction Y and the vertical direction Z. The plurality of lower electrodes 510 are respectively located in the plurality of side cavities 100C, that is, in the space enclosed by the active layer 200, the first sacrificial layer 110 and the second sacrificial layer 130, and the lower electrode 510 is in a horizontally oriented U-shaped cylinder, with the opening facing the vertical opening 100A.

[0047] Please refer to Fig.10, a capacitor dielectric layer 520 is formed on the surface of the plurality of lower electrodes exposed in the comb-shaped opening space along the vertical opening 100A, and the capacitor dielectric layer 520 is located on the inner wall and outer wall surface of the U-shaped cylindrical lower electrode 510. Further, as Fig.10 As shown, the first capacitor dielectric layer 520 is a continuous layer, which is also located on the surface exposed by the vertical opening 100A and contacts the protection layer 140 .

[0048] Please refer to FIG. 11A to FIG. 11C , continue along the vertical opening 100A, and form an upper electrode 530 on the surface of the capacitor dielectric layer 520. The upper electrode 530 fills the remaining space of the comb-shaped opening space. The upper electrode 530 can also be called a common electrode. A plurality of lower electrodes 510, a capacitor dielectric layer 520, and an upper electrode 530 form a capacitor structure 500. It is worth noting that, as shown in FIG. 11, the capacitor structures between adjacent storage cells in the first horizontal direction X are formed simultaneously, and the two are mirror-symmetric to each other about the upper electrode 530.

[0049] The material of the lower electrode 510 can be selected from at least one of metal, metal nitride or metal oxide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium oxide (IrO2), titanium oxide (TiO). In some embodiments, the lower electrode 510 is, for example, a titanium nitride layer.

[0050] The material of the capacitor dielectric layer 520 can be selected from at least one of high-k dielectric films having a dielectric constant higher than that of silicon oxide, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO3), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), and zirconium oxide (ZrO). In some embodiments, the capacitor dielectric layer 520 is, for example, a composite layer of hafnium oxide and zirconium oxide.

[0051] The material of the upper electrode 530 can be selected from at least one of doped polysilicon, metal, metal nitride or metal oxide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium oxide (IrO2), titanium oxide (TiO). In some embodiments, the upper electrode includes a composite layer of titanium nitride and polysilicon, and the polysilicon layer and the titanium nitride are in contact with each other. For example, a titanium nitride layer can be conformally deposited on the surface of the capacitor dielectric layer 520, and then a polysilicon layer is deposited in the remaining space of the comb-shaped opening space along the vertical opening 100A to form the upper electrode 530. The upper electrode 530 is an integral layer, and the portion of the first upper electrode 530 located in the vertical opening 100A extends along the second horizontal direction Y.

[0052] Figure 12 to Figure 14 The schematic diagram of the structure of each stage of the method for preparing a semiconductor device in other embodiments is shown. In this embodiment, on the basis of the previous embodiment, after forming multiple side cavities, the protective layer is also processed to form a protective layer 150 of another embodiment. In this embodiment, the protective layer 150 includes a cavity, a silicon oxide layer with pores located above the cavity, and a silicon oxide layer located on the sidewall of the cavity. This embodiment can isolate the device layer, such as the contact between the electrode layer, the gate electrode and the substrate 100 in the capacitor, and improve the leakage current between the two.

[0053] Please refer to Figure 7 , and please refer to Fig.12 , the second sacrificial layer 120 in the stacked layer ST is laterally etched by using the protective layer 140 including the silicon germanium layer 142 and the silicon oxide layer 141 as an etching stop layer, and then a plurality of side cavities 100C are formed, and then the silicon germanium layer 142 is thermally oxidized to form a silicon germanium oxide layer (SiGeOx) 143. In some embodiments, the surface of the silicon germanium layer 142 is thermally oxidized to form a silicon germanium oxide layer 143 by thermal annealing at a high temperature, such as 900°C to 1000°C, in the presence of an oxygen source. The silicon germanium oxide layer 143 is located on the remaining silicon germanium layer 142. The silicon germanium oxide layer 143 is located on the surface of the silicon germanium layer 142, and its thickness is relatively thin, about 1 / 5 to 1 / 3 of the initial silicon germanium layer thickness, for example, 1 / 4. The silicon germanium layer with oxidized surface has more stable properties, and at the interface between the lower silicon germanium layer 142 and the upper silicon germanium oxide layer 143, Ge atoms are enriched and the concentration increases.

[0054] Afterwards, please refer to Fig.13, and then the lower silicon germanium layer 142 is removed to form a cavity 144. In this embodiment, for example, the Ge atoms in the silicon germanium oxide layer 143 are first removed by an acidic gas, such as hydrogen chloride (HCl) gas, to form pores. Afterwards, the HCl gas continues to remove the remaining silicon germanium layer 142 below the silicon germanium oxide layer 143 along the pores to form a cavity 144. The cavity 144 exposes the silicon oxide layer 141 located on the sidewall 100 of the cavity and the substrate 100 on the bottom wall 101 of the cavity. After removing the Ge atoms, the upper silicon germanium oxide layer 143 forms a silicon oxide layer 145 with pores. The silicon oxide layer 141 located on the sidewall of the cavity, the silicon oxide layer 145 with pores, and the cavity 144 form a protective layer 150 of another exemplary embodiment of the present disclosure. The silicon oxide layer 145 with pores is located between the silicon oxide layers 141 on the sidewalls of the cavity and contacts the silicon oxide layer 141 on the sidewalls of the cavity. The cavity 144 is located below the silicon oxide layer 145 having pores, and the cavity 145 exposes the silicon oxide layer 141 on the sidewalls of the cavity and the substrate 100 on the bottom wall of the cavity.

[0055] It is worth noting that in this embodiment, the step of forming the cavity 144 is performed after the second sacrificial layer 120 is laterally etched. This can fully avoid the etching solution flowing into the cavity of the substrate 100 along the pores or the silicon germanium oxide layer 143 being too thin, thereby damaging the protective layer 150 and the substrate 100 and affecting the device performance.

[0056] Afterwards, please refer to Fig.14 A capacitor structure 500 including a plurality of lower electrodes 510, a capacitor dielectric layer 520, and an upper electrode 530 is formed in the comb-shaped opening space along the vertical opening 100A. The capacitor dielectric layer 520 is in contact with the protection layer 150, and conformally covers the surface of the silicon oxide layer 145 having pores and the surface of the silicon oxide 141 of the sidewall of the cavity. In this embodiment, the leakage current between the device and the substrate 100 can be further reduced and improved.

[0057] Figures 15 to 22 The schematic diagrams of the structures of the semiconductor device manufacturing method at various stages in other embodiments are shown. The protective layer 180 of another embodiment is shown, which does not completely fill the groove in the substrate 100, but is located on the bottom wall 101 and two side walls 102 of the concave cavity of the substrate 100, and further located on a part of the top surface of the substrate 100, contacting the first sacrificial layer 110-1 of the first layer. In this embodiment, the protective layer 180 does not extend to the storage unit of the second layer, which provides more space for integration in the vertical direction, and can improve the integration density.

[0058] Please refer back to Figure 3 and Fig.15After forming the vertical opening 100A, a fourth sacrificial layer 160 is formed in the vertical opening 100A to conform to the shape of the cover, and a fifth sacrificial layer 170 is formed on the surface of the fourth sacrificial layer 160 exposed by the vertical opening 100A. Fig.15 , the fifth sacrificial layer 170 located on the bottom wall 101 of the cavity of the substrate 100 and the top surface of the stacked layer ST is removed along the vertical opening 100A, so that the fourth sacrificial layer 160 located on the bottom wall 101 of the cavity is exposed. The remaining fifth sacrificial layer 170 is located on the sidewall of the fourth sacrificial layer 160.

[0059] In this embodiment, the fourth sacrificial layer 160 is, for example, a silicon oxide layer or a silicon nitride layer formed by an atomic layer deposition (ALD) process. The fifth sacrificial layer 170 is, for example, a silicon nitride layer, a carbon layer or a polysilicon layer formed by an atomic layer deposition process. The thickness of the fourth sacrificial layer 160 may be greater than the thickness of the fifth sacrificial layer 170. The fifth sacrificial layer 170 is located on the surface of the fourth sacrificial layer 160, and forms a barrier for the subsequent removal of part of the fourth sacrificial layer 160 to form the protective layer 150.

[0060] Please refer to Fig.16 , the fourth sacrificial layer 160 is etched downward along the vertical opening 100A, for example, by wet etching to remove the fourth sacrificial layer 160 located on the surface of the substrate 100, that is, the bottom wall 101 and the side wall 102. Further, a portion of the first sacrificial layer 110-1 on the top surface of the substrate 100 is further removed to expose the shoulder of the substrate 100 to form a sacrificial space 100D.

[0061] Please refer to Fig.17 , a protective layer 180 is formed in the concave cavity 100B of the substrate. Specifically, in some embodiments, the fifth sacrificial layer 170 is removed, and then, for example, a portion of the substrate is oxidized by an in-situ steam growth (ISSG) process to form a silicon oxide layer. The silicon oxide layer consumes the silicon layer on the surface of the substrate, and the thickness of the silicon oxide layer is relatively thick, greater than or equal to 30nm. The silicon oxide layer is located on the bottom wall 101, the side wall 102 of the substrate, and the top surface of a portion of the substrate 100, contacting the first sacrificial layer 110-1. The fourth sacrificial layer 160 protects the surface of the second sacrificial layer 120 exposed in the vertical opening 100A from oxidation.

[0062] Please continue to refer to Fig.17, the protective layer 180 can be formed by an in-situ water vapor growth process. For example, the first in-situ water vapor growth process can be performed on the surface of the exposed substrate at a pressure of 0-5 Torr and a temperature of 900-1000°C to form a first silicon oxide layer 181. At this time, the first silicon oxide layer 181 effectively reduces oxide layer defects through the temperature, improves the interface reliability of Si-SiO2, and forms a high-end morphology through the pressure, so as to better cover the exposed top surface of the substrate 100.

[0063] Please refer to Fig.18 In other embodiments of the present disclosure, the protective layer 180 can also be formed by multiple in-situ water vapor growth processes, such as two, three, four times, etc. For example, a high-quality and high-uniformity silicon oxide layer is formed by two in-situ water vapor growth processes. The first ISSG process can form a first silicon oxide layer 181 at a pressure of 0-5 Torr and a temperature of 900-1000°C. After that, the second ISSG process is performed again, for example, at a pressure of 10-15 Torr and a temperature of 700-850°C to form a second oxide layer 182. Thus, the first ISSG process reduces oxide layer defects by high temperature, improves the interface reliability of Si-SiO2, and forms a high-end morphology by lower pressure. The second ISSG process reduces the reaction rate by low temperature, and complements the oxide layer formed by the first ISSG process by higher pressure to improve the morphology of the first silicon oxide layer 181. The first silicon oxide layer 181 and the second silicon oxide layer 182 form the protective layer 180 of the exemplary embodiment of the present disclosure.

[0064] Afterwards, please refer to Fig.19 , a protective layer 180 including a third silicon oxide layer 183 may also be formed. For example, the third silicon oxide layer 183 is formed on the surface of the first silicon oxide layer by an atomic layer deposition (ALD) process. The third silicon oxide layer 183 occupies the position of the original fourth sacrificial layer 160. The third silicon oxide layer 183 is in contact with the first sacrificial layer 110-1 of the first layer. The first silicon oxide layer 181, the second silicon oxide layer 182, and the third silicon oxide layer 183 form the protective layer 180 of the exemplary embodiment of the present disclosure.

[0065] Please refer to Fig. 20 The remaining fourth sacrificial layer 160 in the vertical opening 100A is removed, so that the first sacrificial layer 110 , the second sacrificial layer 120 , and the third sacrificial layer 130 on the sidewall of the vertical opening 100A are exposed again. The protective layer 180 covers the surface of the substrate 100 .

[0066] Please refer back to Figure 7 , and please refer to Fig.21, continue to use the protective layer 180 as an etching stop layer, and wet-etch a portion of the second sacrificial layer 120 in the stacked layer ST laterally along the vertical opening 100A to form a plurality of side cavities 100C. The plurality of side cavities 100C are connected to the vertical opening 100A to form a comb-shaped opening space. A capacitor structure 400 including a plurality of lower electrodes 510, a capacitor dielectric layer 520, and an upper electrode 530 is formed in the comb-shaped opening space along the vertical opening 100A. In this embodiment, when the second sacrificial layer 120 is wet-etched laterally, the protective layer 150 of the silicon oxide layer formed by the ISSG process can improve the damage to the substrate and improve the leakage current between the device and the substrate 100.

[0067] Please refer to Fig. 22 The embodiment of the present disclosure also provides an electronic device 1 having a storage function, the electronic device comprising a processor 2 and a storage device 3 electrically connected to the processing device, the storage device 3 comprising the semiconductor device 4 described in the above-mentioned Figures 1 to 21. The electronic device can be a terminal device, such as a personal computer (Personal Computer), (mobile phone, tablet computer (pad), consumer electronics (Consumer electronics), such as smart home appliances, autonomous driving (automotive), smart wearable products (for example, smart watches, smart bracelets), virtual reality (virtualreality, VR) equipment, augmented reality (augmented reality, AR) equipment, and can also be a server (server), data center (data center), etc. The memory device 3 can be, for example, a high-performance, high-bandwidth, high-density non-volatile dual in-line memory module (Non-Volatile Dual In-Line Memory Module, NVDIMM) or storage class memory (Storage Class Memory, SCM). The storage function in the electronic device 1 can be realized by these storage devices 3.

[0068] In some embodiments, the processor 2 and the memory 3 can be two independent chips to form an independent memory. In other embodiments, the memory 3 and the processor 2 can also be integrated into the same chip to form an embedded memory. Fig.21 The described semiconductor device 4 can solve the same technical problem and achieve the same expected effect.

[0069] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, and forming a stacked layer of a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately on the substrate, wherein the second sacrificial layers and the substrate are made of the same material; forming a vertical opening penetrating the stacked layers, wherein the vertical opening extends into the substrate to form a cavity in the substrate; forming a protective layer in the cavity of the substrate; Using the protective layer as an etching stop layer, a portion of the second sacrificial layer in the stacked layer is laterally etched along the vertical opening to form a plurality of side cavities spaced apart in the vertical direction; forming a plurality of lower electrodes respectively on the surfaces of the second sacrificial layer exposed in the plurality of side cavities; forming a capacitor dielectric layer on the surfaces of the plurality of lower electrodes, wherein the capacitor dielectric layer is also located in the vertical opening and in contact with the protective layer; An upper electrode is formed on the surface of the capacitor dielectric layer, wherein the plurality of lower electrodes, the capacitor dielectric layer and the upper electrode form a capacitor structure.

2. The preparation method according to claim 1, characterized in that: The protective layer extends from the substrate toward the stacked layer, and the extension height of the protective layer is less than or equal to the height of the top surface of the second layer among the multiple first sacrificial layers, and greater than or equal to the height of the top surface of the substrate, wherein the first layer among the multiple first sacrificial layers is located on the top surface of the substrate.

3. The preparation method according to claim 1 or 2, characterized in that: Forming a protective layer in the cavity of the substrate includes: forming a silicon oxide layer on the sidewall of the cavity; A silicon germanium layer is formed on the bottom wall of the cavity. The silicon germanium layer fills the cavity and is in contact with the silicon oxide layer.

4. The preparation method according to claim 3, characterized in that: After forming the plurality of side cavities, the preparation method further comprises treating the protective layer, including: Oxidizing the surface of the silicon germanium layer to form a silicon germanium oxide layer, wherein the silicon germanium oxide layer is located on the remaining silicon germanium layer; removing germanium atoms in the silicon germanium oxide layer by acidic gas to form a silicon oxide layer having pores; The remaining silicon germanium layer is continuously removed along the pores by the acidic gas to form a cavity, wherein the cavity is located below the silicon oxide layer having the pores and the silicon oxide layer located on the sidewalls of the cavity and the substrate on the bottom wall of the cavity are exposed.

5. The preparation method according to claim 1 or 2, characterized in that: Forming a protective layer in the cavity of the substrate includes: forming a silicon oxide layer on the sidewall of the cavity; A boron-doped silicon layer is formed on the bottom wall of the cavity. The boron-doped silicon layer fills the cavity and is in contact with the silicon oxide layer.

6. The preparation method according to claim 1, characterized in that: Forming a protective layer in the cavity of the substrate includes: Performing a first in-situ water vapor growth process on the exposed surface of the substrate at a pressure of 0 to 5 Torr and a temperature of 900 to 1000° C. to form a first silicon oxide layer; and / or, A second in-situ water vapor growth process is performed at a pressure of 10 to 15 Torr and a temperature of 700 to 850° C. to form a second silicon oxide layer.

7. The preparation method according to claim 1, characterized in that: The preparation method further comprises: forming a plurality of active layers arranged at intervals along the vertical direction in the stacked layers, wherein the active layers extend along a first horizontal direction and are formed by the second sacrificial layer; forming a plurality of word lines arranged at intervals along the vertical direction in the stacked layer, wherein the word lines are disposed on the active layer and extend along a second horizontal direction intersecting the first horizontal direction; At least one bit line extending along the vertical direction is formed in the stacked layer, and two ends of the active layer in the first horizontal direction respectively contact the bit line and the lower electrode of the capacitor structure.

8. A semiconductor device, characterized in that: include: a substrate having a cavity; A protective layer located in the cavity of the substrate; A capacitor is located on the substrate, and the capacitor comprises: A plurality of lower electrodes are arranged on the substrate at intervals along the vertical direction; A capacitor dielectric layer is located on the surface of the plurality of lower electrodes, and the capacitor dielectric layer and the protective layer are in contact with each other; The upper electrode is located on the surface of the capacitor dielectric layer.

9. The semiconductor device according to claim 8, characterized in that The protective layer comprises: a silicon oxide layer located on a sidewall of the cavity; a silicon oxide layer having pores, located between the silicon oxide layers on the sidewalls of the cavity and contacting the silicon oxide layer on the sidewalls of the cavity, and A cavity, located below the silicon oxide layer having pores, wherein the cavity exposes the silicon oxide layer on the sidewall of the cavity and the substrate on the bottom wall of the cavity; The capacitor dielectric layer conformally covers the surface of the silicon oxide layer having pores and the surface of the silicon oxide on the side wall of the cavity.

10. The semiconductor device according to claim 8 or 9, characterized in that: The semiconductor device further comprises: A plurality of active layers are arranged at intervals along the vertical direction, and the active layers extend along a first horizontal direction; A plurality of word lines are arranged at intervals along the vertical direction, the word lines are arranged on the active layer and extend along a second horizontal direction intersecting the first horizontal direction; At least one bit line extends along the vertical direction, and two ends of the active layer in the first horizontal direction respectively contact the bit line and the lower electrode of the capacitor structure.

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