A SiC jfet device with improved avalanche capability and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductors, in particular to a SiC JFET device with improved avalanche capability and a manufacturing method thereof. The source region and the gate region are simultaneously arranged in a groove, and the depth of the second-type doped region of the source region is different from that of the second-type doped region of the gate region, wherein the junction depth of the second-type doped region of the source region is deeper than that of the second-type doped region of the gate region, so that the maximum electric field is at the junction edge of the second-type doped region of the source region in the off state, thereby making the avalanche current enter the source electrode through the ohmic contact of the source region without passing through the gate electrode, and the reliability of the avalanche is ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC JFET device with improved avalanche capability and a manufacturing method thereof. Background Art

[0002] Wide-bandgap semiconductor materials like SiC and GaN offer approximately three times the bandgap width, ten times the critical breakdown electric field strength, and higher electron mobility compared to silicon. Consequently, SiC and GaN devices offer advantages over Si devices, including higher voltage withstand, operating frequency, efficiency, and temperature tolerance. Power electronics systems based on wide-bandgap SiC and GaN devices can not only reduce switching losses by more than half, but also achieve smaller equipment, lighter weight, and overall cost advantages, representing the future of next-generation power electronics systems.

[0003] Compared to the low channel mobility and gate reliability issues caused by the high MOS interface state of SiC MOSFET, SiC junction field effect transistor (JFET) does not have a MOS gate structure, so the device is relatively simple and mature. Conventional SiC junction field effect transistor (JFET) is a trench structure, such as Figure 1 As shown. The gate is at the bottom of the trench, and the P+ region at the bottom of the trench is used to deplete the conductive channel, thereby achieving the shutdown of the device. However, in conventional structures, since the P+ region is only electrically connected to the gate, when an avalanche breakdown occurs in the device, the avalanche current directly enters the gate through the P+ region. The gate will pass a very large avalanche current, which will cause great pressure on the gate drive circuit and can easily burn the gate drive circuit directly. Therefore, in ordinary JFET devices, including conventional planar JFET devices and trench JFET devices, the avalanche current passes through the gate, which will damage the gate drive control chip, and the avalanche capability is very weak. The invention of a junction field effect transistor device with high avalanche capability is of great significance to power electronic systems that use junction field effect transistor devices. Summary of the Invention

[0004] In view of this, an object of the present invention is to provide a SiC JFET device with improved avalanche capability and a manufacturing method thereof, so as to solve the problem of weak avalanche capability of conventional planar JFET devices and trench JFET devices.

[0005] Based on the above objectives, the present invention provides a SiC JFET device with improved avalanche capability, comprising a drain, an N+ layer of a first doping type, an N+ buffer layer, an N-drift layer, an N-channel layer, a P+ region of a second doping type, a gate, and a source, arranged sequentially from bottom to top. A trench structure is provided on the front of the device, and mesas are formed on the upper portions of both sides of the trench. A dielectric layer is provided in the middle of the bottom of the trench, isolating the bottom sides and sidewalls of the trench into two regions, one of which is a P+ region of the second doping type connected to the source, i.e., the P+ region of the second doping type in the source region, and the other is a P+ region of the second doping type connected to the gate, i.e., the P+ region of the second doping type in the gate region.

[0006] On both sides of the bottom of the trench, the depths of the second doping type P+ region of the source region and the second doping type P+ region of the gate region are different, wherein the junction depth of the second doping type P+ region of the source region is deeper than the junction depth of the second doping type P+ region of the gate region, so that in the off state, the maximum electric field is at the junction edge of the second doping type P+ region of the source region.

[0007] Preferably, the width of the dielectric layer in the middle of the trench is greater than the interval between the two second doping type P+ regions at the bottom of the trench, that is, the dielectric layer covers both the second doping type P+ region of the source region and the second doping type P+ region of the gate region.

[0008] Preferably, the top of the mesa is an ohmic contact of the source region, and the ohmic contact of the source region at the top of the mesa is electrically connected to the ohmic contact of the source region at one side of the bottom of the trench.

[0009] Preferably, there is a certain distance between the two sides of the bottom of the trench and the second doping type P+ region of the source region and the second doping type P+ region of the gate region, so that under the maximum specified gate-source voltage, there is no penetration between the two second doping type P+ regions.

[0010] Preferably, a heavily doped first type doped layer is provided on the top of the mesa, overlapping with the dielectric layer on the sidewall of the gate region, that is, the bottom of the heavily doped first type doped layer on the top of the mesa is lower than the highest point of the sidewall dielectric layer, ensuring that there is no short circuit between the gate and the source.

[0011] The present invention also provides a method for manufacturing a SiC JFET device with improved avalanche capability, comprising the following steps:

[0012] epitaxially growing a highly doped first-type buffer layer and a low doped first-type drift layer on a highly doped first-type SiC substrate, wherein the concentration and thickness of the drift layer are determined according to a designed breakdown voltage of the device;

[0013] A highly doped first type doped region is formed by implanting a film on the surface of the active region, a dielectric mask is formed on the surface, and the SiC surface is etched by a plasma method to form a SiC trench;

[0014] An ion implantation mask is formed on one side of the trench, and ions of a second type of dopant are implanted on the other side, where the second type of dopant ions are implanted into the bottom and sidewalls of the trench respectively;

[0015] All masks are removed, and the wafer is cleaned by RCA. A carbon film protective layer is applied on the wafer surface, followed by high-temperature annealing to activate the implanted ions and repair the lattice loss caused by the implantation. Sacrificial oxidation is then performed and the thin SiC layer on the surface is removed.

[0016] Thermal oxidation is performed to form a thin surface oxide layer, and a dielectric layer is formed by deposition and etching in the middle of the bottom of the trench;

[0017] Deposit a second dielectric layer, anisotropically etch the second dielectric layer on the mesa and the bottom of the trench, and slightly overetch the SiC to ensure that there is no dielectric on the subsequent ohmic contact areas of the source and gate regions;

[0018] Depositing metal and performing a metal silicide process to form source ohmic contacts on the mesa and in the trench and gate ohmic contacts in the trench. The source ohmic contacts on the mesa and in the trench are electrically connected in subsequent metal processes and connected to the source clamp metal, and the gate ohmic contacts are electrically connected to the gate clamp metal;

[0019] The dielectric is deposited and etched back to cover the grooves and expose the ohmic contact on the table. The source and gate block metals are deposited and etched for electrical connection with external circuits in chip applications. The third dielectric layer is then deposited and etched to form a passivation layer, and a polyimide protective layer is further applied.

[0020] The back of the wafer is thinned to remove most of the substrate and retain only part of the supporting layer to further reduce the resistance of the substrate. Metal is deposited and laser annealed to form an ohmic contact. A thick block metal is then made on the back of the wafer for electrical connection to the external circuit.

[0021] Preferably, the junction depth of the second type doped ions in the source region is greater than the junction depth of the second type doped ions in the gate region, which is achieved by etching deeper trenches in the source region implantation area or by implanting ions in the source region with higher energy.

[0022] Preferably, the width of the intermediate dielectric layer is greater than the spacing between the source region and the second doping type layer of the gate region, that is, one side of the dielectric layer covers the second doping type layer of the gate region, and the other side covers the second doping type layer of the source region.

[0023] Preferably, the heavily doped first type doped layer on the top of the mesa overlaps with the dielectric layer on the sidewall of the gate region to a certain extent, that is, the bottom of the heavily doped first type doped layer on the top of the mesa is lower than the highest point of the sidewall dielectric layer.

[0024] Beneficial effects of the present invention: The SiC JFET device with improved avalanche capability and the manufacturing method thereof provided by the present invention have different depths of the second doping type P+ region of the source region and the second doping type P+ region of the gate region, wherein the junction depth of the second doping type P+ region of the source region is deeper than the junction depth of the second doping type P+ region of the gate region. Therefore, in the off state, the maximum electric field is located at the junction edge of the second doping type P+ region of the source region, so that the avalanche current enters the source electrode through the ohmic contact of the source region without passing through the gate, thereby ensuring the reliability of the avalanche.

[0025] By ensuring that the bottom of the heavily doped first-type doped layer on the top of the mesa is lower than the highest point of the sidewall dielectric layer, a short circuit between the gate and the source can be effectively avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only for the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 Schematic diagram of a conventional trench structure of a SiC junction field effect transistor (JFET) in the prior art;

[0028] Figure 2 Schematic diagram of the structure of a SiC JFET device with improved avalanche capability according to the present invention

[0029] Figure 3 Schematic diagram of another SiC JFET device structure with improved avalanche capability according to the present invention

[0030] Figure 4 Schematic diagram of sequentially producing a buffer layer and an epitaxial layer structure on a substrate in Example 1 of the present invention

[0031] Figure 5 Schematic diagram after trench etching in Example 1 of the present invention

[0032] Figure 6 Schematic diagram of completing the first and second doping type ion doping in Example 1 of the present invention

[0033] Figure 7 Schematic diagram of completing the trench sidewall protection dielectric layer in embodiment 1 of the present invention

[0034] Figure 8 Schematic diagram of completing ohmic contact between source and gate regions and trench dielectric filling in embodiment 1 of the present invention

[0035] Figure 9Schematic diagram of the structure after chip manufacturing is completed in Example 1 of the present invention

[0036] Figure 10 Schematic diagram after trench etching in Example 2 of the present invention

[0037] Figure 11 Schematic diagram of completing the first and second doping type ion doping in embodiment 2 of the present invention

[0038] Figure 12 A schematic diagram of the structure of the chip after manufacturing is completed in Example 2 of the present invention. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to specific embodiments.

[0040] It should be noted that, unless otherwise defined, the technical or scientific terms used in the present invention should have the usual meanings understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0041] The embodiments of this specification provide a SiC JFET device with improved avalanche capability, the device structure is as follows Figure 2 and Figure 3 As shown, from bottom to top, they are the drain, the first-doped N+ layer, the N+ buffer layer, the N-drift layer, the N-channel layer, the second-doped P+ region, the gate, and the source. The front of the device features a trench structure. The bottom, sides, and sidewalls of the trench are filled with the second-doped P+ regions, connecting to the source and gate. A dielectric layer is located in the center of the trench bottom, isolating the source and gate regions on either side of the trench.

[0042] Furthermore, the doping depths of the second-doping type P+ regions of the source region and the gate region on both sides of the bottom of the trench are different, wherein the junction depth of the second-doping type P+ region connected to the source region is deeper than the junction depth of the second-doping type P+ region connected to the gate region, so that in the off state, the maximum electric field is at the junction edge of the second-doping type P+ region connected to the source region.

[0043] Furthermore, the doping depth of the source region at the bottom of the trench is deeper than the doping junction depth of the gate region. One method is to use higher ion implantation energy when doping the source region, so that after ion implantation and doping of the source region and the gate region at the bottom of the trench, the junction depth of the source region is deeper.

[0044] Furthermore, the doping depth of the source region at the bottom of the trench is deeper than the doping junction depth of the gate region. One method is to make the trench depth of the source region deeper so that after ion implantation and doping of the source region and the gate region at the bottom of the trench, the junction depth of the source region is deeper.

[0045] Furthermore, the width of the isolation dielectric in the middle of the trench is greater than the spacing between the source region and the second doping type P+ region of the gate region at the bottom of the trench, that is, the isolation dielectric simultaneously covers part of the second doping type P+ region of the source region and the second doping type P+ region of the gate region, ensuring that the ohmic contacts at the bottom are all within the second doping type P+ region.

[0046] Furthermore, the top of the mesa is also an ohmic contact of the source region, and the ohmic contact of the source region at the top of the mesa is electrically connected to the ohmic contact of the source region at one side of the bottom of the trench.

[0047] Furthermore, the ohmic contact of the gate region and the second type doped region at the bottom side of the trench are isolated from the source region, that is, they are not electrically connected. The gate ohmic contact region is isolated from the source region at the top by the dielectric in the trench.

[0048] Furthermore, a certain spacing is maintained between the second-doped P+ regions on both sides of the trench bottom, connecting to the source and gate regions, respectively. This requires that no punch-through occurs between these two doped regions at the maximum specified gate-source voltage, ensuring that the gate-source breakdown voltage meets product design requirements.

[0049] Furthermore, there is a heavily doped first-type doped layer of a certain thickness on the top of the mesa, which overlaps with the dielectric layer on the sidewall of the gate region to a certain extent, that is, the bottom of the heavily doped first-type doped layer on the top of the mesa is lower than the highest point of the sidewall dielectric layer, which can effectively avoid short circuit between the gate and the source.

[0050] Furthermore, the junction depth of the second doping type doped region in the source region at the bottom of the trench is greater than the junction depth of the second doping type P+ region in the gate region. This is achieved by the ion implantation energy in the source region being greater than the energy implanted in the gate region. The depths of the bottom of the source and gate region trenches may be the same or different.

[0051] Furthermore, the junction depth of the second doping type doped region in the source region at the bottom of the trench is greater than the junction depth of the second doping type P+ region in the gate region. This is achieved by making the trench depth in the source region greater than the trench depth in the gate region. The ion implantation energy at the bottom of the source and gate region trenches can be the same or different.

[0052] The first type and the second type described in the present invention can be interchanged. Specific embodiment 1:

[0053] A SiC JFET device with improved avalanche capability and a method for manufacturing the same, comprising:

[0054] A highly doped first doping type buffer layer 101 and a low doped first type drift layer 102 are epitaxially grown on a highly doped first doping type SiC substrate 100. Figure 4 The concentration and thickness of the drift layer are determined by the breakdown voltage of the device design.

[0055] Furthermore, a highly doped first-type doped region 103 is formed by implantation on the surface of the active area. First-type dopant ions are then implanted on the surface to increase the doping concentration of the channel region 102a, thereby reducing the resistance of the channel. A dielectric layer is deposited and etched on the surface to form a SiC etch mask. The dielectric mask can be one or more layers of SiO2, SiN, polysilicon, etc. The thickness of the dielectric mask is required to be sufficient to block subsequent ion implantation after etching the SiC trench.

[0056] The SiC surface is etched by plasma method to form SiC groove 20, such as Figure 5 The trench depth can generally be about 0.5 microns to 3 microns, and the trench spacing can generally be about 0.5 microns to 3 microns. This can effectively form channel depletion pinch-off under gate control without increasing channel resistance by making the trench too deep.

[0057] Next, a dielectric layer is deposited in the trench to fill the gate region. The dielectric layer in the left gate region of the trench is removed by etching, leaving the dielectric layer in the right trench as an ion implantation mask. Ions are implanted at the bottom and sidewalls of the trench to form a second-doped P+ region 104. The second-type ion implantation in the gate region is completed. The ion implantation concentration at the bottom surface is relatively high, for example, greater than 1E18 cm⁻³, to facilitate ohmic contact formation.

[0058] Next, the mask is removed. A dielectric layer is deposited again within the trench to fill the trench. The dielectric layer in the source region on the right side of the trench is etched away, leaving the dielectric layer on the left side of the trench as an ion implantation mask. Ions are implanted at the bottom and sidewalls of the trench to form a second-type doping type P+ region 105. This completes the second type of ion implantation in the source region. A higher ion implantation concentration at the bottom surface, such as greater than 1E18 cm⁻³, facilitates ohmic contact formation.

[0059] The effect is the same whether the left or right side of the trench is selected as the gate region or source region.

[0060] The junction depth of the second type of doped ions in the source region is greater than the junction depth of the second type of doped ions in the gate region. This can be achieved by injecting higher energy ions into the source region. In Example 2 of the present invention, this is achieved by making the trench depth in the source region deeper than that in the gate region. In this way, as shown in the figure, the maximum electric field will appear between A or B in the source region, and breakdown will first occur at point A or B. The avalanche current enters the source through the ohmic contact in the source region without passing through the gate, thereby ensuring the reliability of the avalanche.

[0061] Next, all masks are removed and the wafer is cleaned using RCA. A carbon film protective layer is applied to the wafer surface, followed by high-temperature annealing to activate the implanted ions and repair lattice loss caused by implantation. Sacrificial oxidation is then performed to remove the thin SiC layer on the surface, improving the quality of the SiC surface.

[0062] Further, thermal oxidation is performed to form a thin surface oxide layer. Preferably, annealing is performed in a NO or N2O atmosphere after thermal oxidation to improve the quality of the dielectric layer. The dielectric layer is deposited and etched, and the dielectric layer 200 is retained in the middle of the bottom of the trench, such as Figure 6 As shown, the dielectric layer can be SiO2 or SiN, or a multi-layer composite. Preferably, the height of the dielectric layer is close to the height of the mesa, which facilitates subsequent trench filling and planarization processes. Furthermore, the width of the intermediate dielectric layer 200 plus the subsequent sidewall dielectrics 201a and 201b is greater than the spacing between the source and gate regions of the second doping type layer. That is, one side of the dielectric layer overlies the gate region's second doping type layer 104, and the other side overlies the source region's second doping type layer 105.

[0063] Further, a second dielectric layer is deposited, and the second dielectric layer on the terrace and the bottom of the trench is removed by anisotropic etching, leaving the second dielectric layer 201a in the gate region of the trench sidewall and the second dielectric layer 201b in the source region, as shown in FIG. Figure 7 As shown. The height of the second dielectric layers 201a and 201b is higher than the bottom of the first doping type layer 103. The SiC is slightly overetched to ensure that no dielectric material is present on the subsequent ohmic contact areas of the source and gate regions. The second dielectric layer can be SiO2, etc. Metal is deposited and a metal silicide process is performed to form the source ohmic contact 301 on the mesa, the source ohmic contact 302 in the trench, and the gate ohmic contact 303 in the trench. The source ohmic contacts on the mesa and in the trench are electrically connected in the subsequent metal processing.

[0064] Deposit dielectric and etch back, so that dielectric 202 covers the trench and exposes the ohmic contact on the mesa, as shown in FIG. Figure 8The pressure metal 401 of the deposited and etched source and gate is used for electrical connection with external circuit in chip application, and a third dielectric layer is deposited and etched to form passivation. The pressure metal can be Al, AlCu, AlSiCu or NiAu, TiNiAg, etc. The passivation dielectric is preferably SiO2, SiN, SiON or several layers of composite. A polyimide protective layer is then formed.

[0065] Further, the wafer back is thinned to remove most of the substrate and only keep part of the support layer, further reducing the resistance of the substrate. A metal is deposited and laser annealing is performed to form an ohmic contact. A thick pressure metal 402 is then formed on the wafer back for electrical connection with external circuit. The back metal can be NiPbAu or TiNiAg, etc. as shown in Figure 9 .

[0066] The first doping type ion can be N+, P+, etc. and the second doping type ion can be Al+, B+, etc. Specific embodiment 2:

[0067] A SiC JFET device with improved avalanche capability and its manufacturing method, other manufacturing methods are similar to embodiment 1, and the difference from embodiment 1 is that the trench 20 is etched twice, so that the source region trench 20a is deeper than the left side 20b, as shown in Figure 10 . In this way, even if the same energy ion implantation is used in the source region and the gate region in the trench, the doping region of the source region will still be deeper than the gate region, as shown in Figure 11 . Ensuring that the maximum electric field is still at the edge A or B of the P+ region of the second doping type in the source region, ensuring the avalanche capability. The final device structure diagram is shown in Figure 12 .

[0068] It should be understood by those skilled in the art that the above discussion of any embodiment is only exemplary and is not intended to limit the scope of the present application to these examples; under the idea of the present application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of the present application as described above. In order to be brief, they are not provided in detail. Any omissions, modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A SiC JFET device with improved avalanche capability, characterized in that: The device comprises a drain, an N+ layer of a first doping type, an N+ buffer layer, an N-drift layer, an N-channel layer, a P+ region of a second doping type, a gate, and a source, which are arranged in sequence from bottom to top. The front of the device is provided with a trench structure, and mesas are formed on the upper parts of both sides of the trench. A dielectric layer is provided in the middle of the bottom of the trench to isolate the P+ region of the second doping type on both sides and the sidewall of the trench into two regions, one of which is the P+ region of the second doping type connected to the source, and the other is the P+ region of the second doping type connected to the gate. On both sides of the bottom of the trench, the depths of the second doping type P+ region of the source region and the second doping type P+ region of the gate region are different, wherein the junction depth of the second doping type P+ region of the source region is deeper than the junction depth of the second doping type P+ region of the gate region, so that in the off state, the maximum electric field is at the junction edge of the second doping type P+ region of the source region.

2. The SiC JFET device with improved avalanche capability according to claim 1, wherein: The width of the dielectric layer in the middle of the trench is greater than the interval between the two second doping type P+ regions at the bottom of the trench, so that the dielectric layer covers both the second doping type P+ region of the source region and the second doping type P+ region of the gate region.

3. The SiC JFET device with improved avalanche capability according to claim 1, wherein: The top of the mesa is the ohmic contact of the source region, and the ohmic contact of the source region at the top of the mesa is electrically connected with the ohmic contact of the source region at one side of the bottom of the trench.

4. The SiC JFET device with improved avalanche capability according to claim 1, wherein: There is a certain distance between the two sides of the bottom of the trench and the second doping type P+ region of the source region and the second doping type P+ region of the gate region, so that under the maximum specified gate-source voltage, there is no penetration between the two second doping type P+ regions.

5. The SiC JFET device with improved avalanche capability according to claim 1, wherein: A heavily doped first type doping layer is provided on the top of the mesa, overlapping with the dielectric layer on the sidewall of the gate region, so that the bottom of the heavily doped first type doping layer on the top of the mesa is lower than the highest point of the sidewall dielectric layer.

6. A method for manufacturing a SiC JFET device with improved avalanche capability, characterized in that: The following steps are involved: epitaxially growing a highly doped first-type buffer layer and a low doped first-type drift layer on a highly doped first-type SiC substrate, wherein the concentration and thickness of the drift layer are determined according to a designed breakdown voltage of the device; A highly doped first type doped region is formed by implanting a film on the surface of the active region, a dielectric mask is formed on the surface, and the SiC surface is etched by a plasma method to form a SiC trench; A filling dielectric layer is deposited in the trench, and the dielectric layer in the gate region on the left side of the trench is removed by etching. The dielectric layer on the right side of the trench is retained as an ion implantation mask, and ions of the second type of doping are implanted on the other side. The second type of doping ions are implanted at the bottom and sidewalls of the trench to form a P+ region of the second doping type. The mask is removed, and a filling dielectric layer is deposited again in the trench. The dielectric layer in the source region on the right side of the trench is removed by etching, while the dielectric layer on the left side of the trench is retained as an ion implantation mask. Ions are implanted at the bottom and sidewalls of the trench to form another second type doped region. All masks are removed, and the wafer is RCA cleaned. A carbon film protective layer is applied to the wafer surface, followed by high-temperature annealing to activate the implanted ions and repair the lattice loss caused by the implantation. Sacrificial oxidation is then performed to remove the thin SiC layer on the surface. Thermal oxidation is performed to form a thin surface oxide layer, and a dielectric layer is formed by deposition and etching in the middle of the bottom of the trench; Deposit a second dielectric layer, anisotropically etch the second dielectric layer on the mesa and the bottom of the trench, and slightly overetch the SiC to ensure that there is no dielectric on the subsequent ohmic contact areas of the source and gate regions; Depositing metal and performing a metal silicide process to form source ohmic contacts on the mesa and in the trench and gate ohmic contacts in the trench. The source ohmic contacts on the mesa and in the trench are electrically connected in subsequent metal processes and connected to the source clamp metal, and the gate ohmic contacts are electrically connected to the gate clamp metal; Deposit dielectric and etch back to cover the trench and expose the ohmic contact on the mesa. Deposit and etch the source and gate metal blocks for electrical connection with external circuits in chip applications. Deposit and etch the third dielectric layer to form a passivation layer, and then cover with a polyimide protective layer. The back of the wafer is thinned to remove most of the substrate and retain only part of the supporting layer to reduce the resistance of the substrate. Metal is deposited and laser annealed to form an ohmic contact. A thick block metal is then set on the back of the wafer for electrical connection to the external circuit.

7. The method for manufacturing a SiC JFET device with improved avalanche capability according to claim 6, wherein: The junction depth of the second type doped ions in the source region is greater than that of the second type doped ions in the gate region, which is achieved by etching deeper trenches in the source region implantation area or by implanting ions in the source region with higher energy.

8. The method for manufacturing a SiC JFET device with improved avalanche capability according to claim 6, wherein: The width of the intermediate dielectric layer is greater than the spacing between the source region and the second doping type layer of the gate region, so that one side of the dielectric layer covers the second doping type layer of the gate region and the other side covers the second doping type layer of the source region.

9. The method for manufacturing a SiC JFET device with improved avalanche capability according to claim 6, wherein: The heavily doped first type doped layer on the top of the mesa overlaps with the dielectric layer on the sidewall of the gate region to a certain extent, so that the bottom of the heavily doped first type doped layer on the top of the mesa is lower than the highest point of the sidewall dielectric layer, ensuring that there is no short circuit between the gate and the source.

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