Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors, in the semiconductor device, at least two first grids and at least two first active regions are arranged in a crossed manner, a second active region is positioned between the adjacent first active regions, and a second grid is positioned on the second active region; when at least four transistors are formed on the semiconductor device, a fifth transistor is formed on the second active region and the second grid electrode. According to the arrangement, the number of the transistors is increased while the structure of the semiconductor device is not changed, the integration level of the semiconductor device is increased, and the performance of the semiconductor device is further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] With the birth of Moore's Law, the number of transistors in semiconductor devices doubles every year. As time goes by, the process node has reached 2nm or even 0.3nm, all in order to increase the number of transistors and improve the operating speed of chips.

[0003] When the growth reaches a certain level, it is no longer possible to increase the number of transistors without changing the structure, but structural changes will make the process very complicated.

[0004] Based on this, how to further increase the number of transistors in a semiconductor device through arrangement design has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] Based on this, it is necessary to provide a semiconductor device and a method for preparing the same in order to increase the number of transistors in the semiconductor device and the integration of the semiconductor device.

[0006] In order to achieve the above object, on one hand, the present invention provides a semiconductor device, the semiconductor device comprising a substrate and a gate layer located on the substrate,

[0007] The substrate comprises:

[0008] At least two first active regions extending along the first direction and arranged along the second direction;

[0009] a second active region, located between adjacent first active regions in the second direction, the first direction and the second direction being parallel to the substrate, and the first direction and the second direction intersecting;

[0010] The gate layer comprises:

[0011] at least two first gates extending along the second direction and arranged along the first direction, and at least two of the first gates are arranged to cross at least two of the first active regions, and adjacent first gates are located on both sides of the second active regions in the first direction;

[0012] The second gate is located on the second active region.

[0013] In one embodiment, the first active region includes a first channel region, and the second active region includes a second channel region; the first channel region and the second channel region have the same conductivity type.

[0014] In one embodiment, the first active region further includes a first doped region, the first doped region and the first channel region are alternately arranged along the first direction, the first doped region and the second channel region have opposite conductivity types, and the second channel region is connected to the first doped regions of two adjacent first active regions in the second direction.

[0015] In one embodiment, the second gate is connected to the first gate in the first direction.

[0016] In one embodiment, the first active region includes a first channel region, and the second active region includes a second channel region; the first channel region has a first conductivity type, the second channel region has a second conductivity type, and the conductivity types of the first channel region and the second channel region are different.

[0017] In one embodiment, the first active region also includes a second doped region, the second doped region and the first channel region are arranged alternately along the first direction, the second doped region includes a first sub-region, a second sub-region and a third sub-region arranged in sequence along the first direction, the first sub-region and the third sub-region have the second conductivity type, the second sub-region has the first conductivity type, and the second channel region is connected to the second sub-regions of two adjacent first active regions at least in the second direction.

[0018] In one embodiment, the second gate is spaced apart from the first gate in the first direction.

[0019] In one embodiment, the second active region further includes a third doped region, the third doped region is located on both sides of the second channel region in the second direction, and the third doped region has the first conductivity type; the second gate is spaced apart from the first active region in the second direction.

[0020] In one embodiment, the first active region further includes a first doped region, the first doped region and the first channel region are alternately arranged along the first direction, the first doped region has a second conductivity type, and the third doped region is connected to the first doped region.

[0021] In one embodiment, the second gate is connected to the first gate in the first direction.

[0022] On the other hand, the present application also provides a method for preparing a semiconductor device, comprising:

[0023] providing a substrate;

[0024] Doping the substrate to form an active region, wherein the active region includes a first active region and a second active region, the number of the first active regions is at least two, the first active regions extend along a first direction and are arranged along a second direction, the second active regions are located between adjacent first active regions in the second direction, the first direction and the second direction are parallel to the substrate, and the first direction and the second direction intersect;

[0025] A gate layer is formed on the substrate, the gate layer includes a first gate and a second gate, the number of the first gates is at least two, the first gates extend along the second direction and are arranged along the first direction, at least two of the first gates are cross-arranged with at least two of the first active regions, and adjacent first gates are located on both sides of the second active region in the first direction, and the second gate is located on the second active region.

[0026] Compared with the prior art, the above technical solution has the following unexpected technical effects:

[0027] In the semiconductor device, it includes a substrate and a gate layer located on the substrate, wherein the substrate includes at least two first active regions extending along a first direction and arranged along a second direction; the second active region is located between adjacent first active regions in the second direction, the first direction and the second direction are parallel to the substrate, and the first direction intersects with the second direction; the gate layer includes at least two first gates extending along the second direction and arranged along the first direction, and the at least two first gates are cross-arranged with the at least two first active regions, and the adjacent first gates are located on both sides of the second active region in the first direction; the second gate is located on the second active region.

[0028] Since at least two first gates and at least two first active regions in the semiconductor device are arranged crosswise, and the second active region is located between adjacent first active regions, and the second gate is located on the second active region, when the semiconductor device forms at least four transistors, a fifth transistor is formed at the second active region and the second gate. This arrangement increases the number of transistors without changing the structure of the semiconductor device, increases the integration of the semiconductor device, and further improves the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0031] Figure 2 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;

[0032] Figure 3 One of the structural schematic diagrams of another semiconductor device provided in an embodiment of the present application;

[0033] Figure 4 A schematic diagram of the structure of a first active region and a second active region provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of the structure of a gate layer provided in an embodiment of the present application;

[0035] Figure 6 A second structural schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0036] Figure 7 A third structural schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0037] Figure 8 A fourth structural schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0038] Fig. 9 A fifth structural schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0039] Fig.10 A sixth structural schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0040] Fig.11 A schematic diagram of a process for preparing a semiconductor device provided in an embodiment of the present application;

[0041] Fig.12 A schematic diagram of the structure after an active area is formed in the preparation process of a semiconductor device provided in an embodiment of the present application;

[0042] Fig.13 A schematic diagram of the structure after an isolation structure is formed in the preparation process of a semiconductor device provided in an embodiment of the present application;

[0043] Fig.14 A schematic diagram of the structure after a well region is formed in the preparation process of a semiconductor device provided in an embodiment of the present application;

[0044] Fig.15 A schematic diagram of the structure after a gate layer is formed in the preparation process of the semiconductor device provided in an embodiment of the present application;

[0045] Fig.16 A schematic diagram of the structure after a source or drain is formed in the preparation process of the semiconductor device provided in an embodiment of the present application;

[0046] Fig.17 A schematic diagram of the structure after metal silicide is formed in the preparation process of the semiconductor device provided in an embodiment of the present application;

[0047] Fig.18 A schematic diagram of the structure after a contact structure is formed during the preparation process of the semiconductor device provided in an embodiment of the present application.

[0048] Explanation of the accompanying drawings: 01-substrate; 02-gate layer; 03-first active region; 04-second active region; 05-first gate; 06-second gate; 07-first channel region; 08-second channel region; 09-first doped region; 10-second doped region; 11-first sub-region; 12-second sub-region; 13-third sub-region; 14-third doped region; 15-isolation structure; 16-deep N-well; 17-P-well, 18-doped region; 19-metal silicide; 20-contact structure. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0052] refer to Figure 1 , Figure 1 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application; the semiconductor device comprises a substrate 01 and a gate layer 02 located on the substrate 01.

[0053] Substrate 01 includes:

[0054] At least two first active regions 03 extend along the first direction M and are arranged along the second direction N.

[0055] The second active region 04 is located between adjacent first active regions 03 in the second direction N. The first direction M and the second direction N are parallel to the substrate 01 , and the first direction M and the second direction N intersect.

[0056] The gate layer 02 includes:

[0057] At least two first gates 05 extend along the second direction N and are arranged along the first direction M. The at least two first gates 05 are intersecting with at least two first active regions 03 , and adjacent first gates 05 are located on both sides of the second active region 04 in the first direction M.

[0058] The second gate 06 is located on the second active region 04 .

[0059] Specifically, in this embodiment, the first direction M and the second direction N are parallel to the plane where the substrate 01 is located, and the first direction M intersects with the second direction N. In one embodiment, the first direction M and the second direction N are perpendicular to each other. A transistor is formed at the intersection of the first active region 03 and the first gate 05. At least two first active regions 03 and at least two first gates 05 are arranged crosswise, and at least four intersection regions can be formed, that is, at least four transistors are formed.

[0060] The second active region 04 is located between adjacent first active regions 03 in the second direction N. It should be noted that the second active region 04 may be connected to the first active region 03 or may not be connected to the first active region 03, and there is no specific limitation. The second gate 06 is located on the second active region 04. The second gate 06 may completely cover the second active region 04 or may partially cover the second active region 04, and there is no specific limitation. For a clearer display, Figure 1 These are examples only.

[0061] In the case where the arrangement of the first active area 03 and the first gate 05 remains unchanged, a transistor can be formed at the intersection of the second active area 04 and the second gate 06, so that a new transistor is added to the arrangement of the existing semiconductor device. Since the new transistor is located between the existing four transistors, no more layout is required, thereby improving the integration of the semiconductor device. Furthermore, in the case where the structure of the semiconductor device remains unchanged, the number of transistors is increased by 25%, thereby improving the performance of the semiconductor device.

[0062] Optional, reference Figure 1 In another embodiment of the present application, the first active region 03 includes a first channel region 07 , and the second active region 04 includes a second channel region 08 ; the first channel region 07 and the second channel region 08 have the same conductivity type.

[0063] Specifically, the overlapping area of ​​the first active area 03 and the first gate 05 has a first channel area 07, and the extension direction of the first channel area 07 is a first direction M. The overlapping area of ​​the second active area 04 and the second gate 06 has a second channel area 08, and the extension direction of the second channel area 08 is a second direction N, that is, the conductive directions of the first channel area 07 and the second channel area 08 are different.

[0064] It should be noted that the first channel region 07 and the second channel region 08 have the same conductivity type, both are N-type conductivity type or both are P-type conductivity type, that is, the at least five transistors formed are the same transistors. The second channel region 08 and the first channel region 07 are arranged in an extending direction that intersects, which can increase the integration of the semiconductor device.

[0065] Optional, reference Figure 2 , Figure 2 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application; in another embodiment of the present application, the first active region 03 further includes a first doped region 09, the first doped region 09 and the first channel region 07 are alternately arranged along the first direction M, the first doped region 09 and the second channel region 08 have opposite conductivity types, and the second channel region 08 is connected to the first doped regions 09 of two adjacent first active regions 03 in the second direction N. It should be noted that the first doped region 09 serves as a source or drain of the transistor.

[0066] Specifically, two first active regions 03 and two first gates 05 are used as an example for description. The first doped regions 09 and the first channel regions 07 are arranged alternately along the first direction M, that is, in the embodiment of the present application, in the first direction M, the first doped region 09 between the transistor corresponding to the first channel region 07 in the i-th row and the transistor corresponding to the first channel region 07 in the i+1-th row is shared, where i≥1, and i is a positive integer.

[0067] In this embodiment, the second channel region 08 is connected to the first doping regions 09 of two adjacent first active regions 03 in the second direction N. That is, Figure 2As shown, the second channel region 08 uses the first doping region 09 as the doping region of the transistor formed here. In the second direction N, the transistor corresponding to the second channel region 08 in the i-th column and the transistor corresponding to the second channel region 08 in the i+1-th column share the first doping region 09, wherein when at least five transistors share part of the doping region, the conductivity type of the first doping region 09 is opposite to that of the second channel region 08, and the conductivity type of the first doping region 09 is opposite to that of the first channel region 07, that is, the conductivity type of the first channel region 07 is the same as that of the second channel region 08, and at this time at least five transistors of the same type can be formed, and the types of transistors include N-type transistors or P-type transistors. When the doping region is shared, the integration of the semiconductor device can be further increased.

[0068] Optional, reference Figure 3 , Figure 3 One of the structural schematic diagrams of another semiconductor device provided in the embodiment of the present application; Figure 4 , Figure 4 A schematic diagram of the structure of a first active region and a second active region provided in an embodiment of the present application; Figure 5 , Figure 5 A schematic diagram of the structure of a gate layer provided in an embodiment of the present application; in another embodiment of the present application, the second gate 06 is connected to the first gate 05 in the first direction M.

[0069] Specifically, two first active regions 03 and two first gates 05 are used as an example for description. When the second gate 06 is connected to the first gate 05 in the first direction M, Figure 4 As shown, the structures of the first active region 03 and the second active region 04 on the substrate 01 may be in the shape of an I, and as shown in FIG. Figure 5 As shown, the structure of the gate layer 02 can also be an "I" shape. In this case, the active region and the gate layer 02 are rotated and stacked to form a structure as shown in FIG. Figure 3 In the structure shown, the second active region 04 is completely covered by the second gate 06, and the doping region of the transistor formed at the first channel region 07 and the second channel region 08 is shared. When the doping region is shared, the integration of the semiconductor device can be further increased.

[0070] It should be noted that in the above embodiment, when the doped region is shared, only the second active region 04 and the second gate 06 need to be formed to form a new transistor in the arrangement region of the four transistors, thereby increasing the number of transistors by 25% and improving the performance of the semiconductor device. In addition, such a configuration further improves the integration of the semiconductor device.

[0071] Optional, reference Figure 1In another embodiment of the present application, the first active region 03 includes a first channel region 07, and the second active region 04 includes a second channel region 08; the first channel region 07 has a first conductivity type, and the second channel region 08 has a second conductivity type, and the conductivity types of the first channel region 07 and the second channel region 08 are different.

[0072] Specifically, the overlapped region of the first active region 03 and the first gate 05 has a first channel region 07 extending in a first direction M. The overlapped region of the second active region 04 and the second gate 06 has a second channel region 08 extending in a second direction N.

[0073] It should be noted that the first channel region 07 has a first conductivity type, the second channel region 08 has a second conductivity type, and the first conductivity type is different from the second conductivity type. The transistor formed at the intersection of the first gate 05 and the first active region 03 and the transistor formed at the intersection of the second gate 06 and the second active region 04 are of different types. When an N-type transistor is formed in the first channel region 07, a P-type transistor is formed in the second channel region 08; or when a P-type transistor is formed in the first channel region 07, an N-type transistor is formed in the second channel region 08. At this time, since the extension directions of the channel regions are not in the same direction when different types of transistors are arranged, the integration of semiconductor devices having two different types of transistors can be greatly improved.

[0074] Optional, reference Figure 6 , Figure 6 The second structural schematic diagram of another semiconductor device provided for an embodiment of the present application; in another embodiment of the present application, the first active region 03 also includes a second doped region 10, the second doped region 10 and the first channel region 07 are alternately arranged along the first direction M, the second doped region 10 includes a first sub-region 11, a second sub-region 12 and a third sub-region 13 arranged in sequence along the first direction M, the first sub-region 11 and the third sub-region 13 have the second conductivity type, the second sub-region 12 has the first conductivity type, and the second channel region 08 is connected to the second sub-regions 12 of two adjacent first active regions 03 at least in the second direction N.

[0075] Specifically, when the first channel region 07 has the first conductivity type and the second channel region 08 has the second conductivity type, the first active region 03 further includes a second doping region 10, and the second doping region 10 and the first channel region 07 are arranged alternately along the first direction M. The second doping region 10 includes a first sub-region 11, a second sub-region 12, and a third sub-region 13 arranged in sequence along the first direction M, wherein in the first direction M, the first sub-region 11 is used as the doping region of the transistor corresponding to the first channel region 07 in the i-th row, wherein i≥1, and i is a positive integer. The third sub-region 13 is used as the doping region of the transistor in the i+1-th row, and since the first channel region 07 has the first conductivity type, the first sub-region 11 and the third sub-region 13 both have the second conductivity type. The second sub-region 12 is used as the doping region of the transistor corresponding to the second channel region 08 in the i-th column, and since the second channel region 08 has the second conductivity type, the second sub-region 12 has the first conductivity type. It should be noted that the second channel region 08 is connected to the second sub-regions 12 of two adjacent first active regions 03 at least in the second direction N, so that a new transistor can be formed.

[0076] In this embodiment, since the conductivity types of the first channel region 07 and the second channel region 08 are different, the conductivity types of the doping regions on both sides of the different channel regions also need to be different, and the types of transistors formed are naturally different. When an N-type transistor is formed at the first channel region 07, a P-type transistor is formed at the second channel region 08, or when a P-type transistor is formed at the first channel region 07, an N-type transistor is formed at the second channel region 08. At this time, the second doping region 10 is provided with a first sub-region 11, a second sub-region 12, and a third sub-region 13, which can ensure that the first channel region 07 and the second channel region 08 are between the doping regions corresponding thereto. Since the channel regions are not in the same direction when different types of transistors are arranged, the integration of semiconductor devices having two different types of transistors can be greatly improved.

[0077] Optional, reference Figure 6 In another embodiment of the present application, the second gate 06 and the first gate 05 are spaced apart in the first direction M.

[0078] Specifically, when the first channel region 07 has the first conductivity type and the second channel region 08 has the second conductivity type, the second gate 06 and the first gate 05 can be spaced apart in the first direction M. Such a setting can reduce the area of ​​the gate layer 02, reduce the use of the gate layer 02 material, and further reduce the manufacturing cost.

[0079] Optional, reference Figure 7 , Figure 7A third structural schematic diagram of another semiconductor device provided for an embodiment of the present application; in another embodiment of the present application, the second active region 04 also includes a third doped region 14, the third doped region 14 is located on both sides of the second channel region 08 in the second direction N, and the third doped region 14 has a first conductivity type; the second gate 06 is spaced apart from the first active region 03 in the second direction N.

[0080] Specifically, in the present embodiment, in the second direction N and on one side of the second active region 04, the third doped region 14 is located on both sides of the second channel region 08. Since the second channel region 08 has the second conductivity type, the third doped region 14 has the first conductivity type to form a transistor. It should be noted that the second gate 06 is arranged at intervals from the first active region 03 in the second direction N, that is, the second active region 04 is not connected to the first active region 03. At this time, since the first channel region 07 extends in the first direction M and the second channel region 08 extends in the second direction N, the transistor formed at the first channel region 07 of the first active region 03 and the transistor formed at the second channel region 08 of the second active region 04 are of different types. In the present embodiment, by arranging transistors of different types, that is, setting the extension direction of the channel region in the intersecting direction, the occupied area of ​​the layout can be reduced and the integration of the semiconductor device can be increased.

[0081] Optional, reference Figure 8 , Figure 8 A fourth structural schematic diagram of another semiconductor device provided in an embodiment of the present application; the first active region 03 also includes a first doping region 09, the first doping region 09 and the first channel region 07 are alternately arranged along the first direction M, the first doping region 09 has a second conductivity type, and the third doping region 14 is connected to the first doping region 09.

[0082] Specifically, in this embodiment, in the first direction M, the first active region 03 includes first doped regions 09 on both sides of the first channel region 07. The conductivity type of the first doped region 09 is opposite to that of the first channel region 07, that is, the first channel region 07 has the first conductivity type, and the first doped region 09 has the second conductivity type. At this time, the third doped region 14 can be connected to the first doped region 09, but the doping types of the first doped region 09 and the third doped region 14 are different, that is, the type of transistor formed in the first active region 03 is different from the type of transistor formed in the second active region 04. The first doped regions 09 and the first channel regions 07 are alternately arranged along the first direction M, that is, two adjacent first channel regions 07 can share one first doped region 09 in the first direction M. At this time, since the first doped region 09 is partially shared, the area of ​​the semiconductor device can be further reduced and the integration of the semiconductor device can be increased.

[0083] Optional, reference Fig. 9 , Fig. 9 A fifth structural diagram of another semiconductor device provided in an embodiment of the present application; in another embodiment of the present application, the second gate 06 is connected to the first gate 05 in the first direction M.

[0084] Specifically, when the first channel region 07 has the first conductivity type and the second channel region 08 has the second conductivity type, the second gate 06 can be connected to the first gate 05 in the first direction M. At this time, the gate layer 02 is prepared in an "I" shape. This arrangement can make the preparation of the gate layer 02 easier.

[0085] It should be noted that no matter whether the second gate 06 and the first gate 05 are spaced apart in the first direction M or the second gate 06 and the first gate 05 are connected in the first direction M, a transistor different from that in the first channel region 07 can be formed in the second channel region 08, thereby increasing the number of transistors and further improving the integration of the semiconductor device.

[0086] In addition, based on the above structure that the first channel region 07 has the first conductivity type and the second channel region 08 has the second conductivity type, the present application also provides a stress introduction method, which is described below.

[0087] With the development of integrated circuits, the process node is below 45nm. In order to improve the performance of NMOS and PMOS devices, some new processes will be used to improve the mobility of carriers, such as SMT (stress memory technology), SPT, SiGe epitaxy, SIC epitaxy, ultraviolet irradiation and other methods. For semiconductor devices with both NMOS and PMOS structures, since the working carriers of NMOS are electrons and the working carriers of PMOS are holes, the two devices prefer different stresses. Therefore, when stress is introduced into NMOS or PMOS, different stress layers or different epitaxial processes are required for stress introduction. The stress required for NMOS and PMOS to increase performance is shown in Table 1 below:

[0088] Table 1

[0089]

[0090] When the semiconductor device in the present application is used, an NMOS is formed in the first channel region 07 and a PMOS is formed in the second channel region 08 as an example for explanation. Fig.10 , Fig.10The sixth structural schematic diagram of another semiconductor device provided for the embodiment of the present application; the extension direction of the first channel region 07 is L1, and the width direction of the first channel region 07 is W1. The extension direction of the second channel region 08 is L2, and the width direction of the second channel region 08 is W2. Among them, the stress required for the extension direction L of the second channel region 08 is compressive stress y. Since the stress required for the width direction W1 of the first channel region 07 is tensile stress x, providing tensile stress x to the width direction W1 of the first channel region 07 can achieve the compressive stress y required for the extension direction L2 of the second channel region 08. The stress required for the extension direction L1 of the first channel region 07 is the same as the stress required for the width direction W2 of the second channel region 08. Therefore, in this embodiment, NMOS and PMOS can use the same stress layer for stress introduction. Similarly, forming PMOS at the first channel region 07 and forming NMOS at the second channel region 08 can also achieve stress introduction in the same stress layer. The stress introduction method realizes the stress introduction of two different types of transistors by using only one stress layer, thereby reducing the process preparation cost.

[0091] Based on the above embodiments, the present application also provides a method for preparing a semiconductor device, referring to Fig.11 , Fig.11 A schematic diagram of a method for preparing a semiconductor device provided in an embodiment of the present application; Figure 12-Figure 18 , Figure 12-Figure 18 A schematic diagram of a portion of the structure obtained in the method for preparing a semiconductor device provided in an embodiment of the present application; comprising the following steps:

[0092] Step S101: providing a substrate 01.

[0093] Step S102: doping the substrate 01 to form an active area AA.

[0094] Among them, the active area AA includes a first active area 03 and a second active area 04, the number of the first active areas 03 is at least two, the first active areas 03 extend along the first direction M and are arranged along the second direction N, the second active areas 04 are located between adjacent first active areas 03 in the second direction N, the first direction M and the second direction N are parallel to the substrate 01, and the first direction M and the second direction N intersect.

[0095] In this step, if Fig.12 As shown, a substrate 01 is provided, an active area AA is formed on the substrate 01, and doping is performed in the area where the first active area 03 and the second active area 04 are required to be set to define the active area AA. In this step, the first active area 03 and the second active area 04 can be of the type in the above embodiment, and no specific limitation is made here.

[0096] Then the isolation trench etching is performed, such as Fig.13As shown, an isolation material is filled in the isolation trench to form an isolation structure 15, and a grinding process is performed to planarize the surface. The grinding method may be chemical mechanical polishing (CMP).

[0097] Afterwards, if Fig.14 As shown, a well region is implanted in the formed active area AA. In this embodiment, an ion implantation method can be used to first form a deep N well 16 and then form a P well 17. It should be noted that the formation position of the well region is based on the type of transistor to be formed and is not specifically limited here. It is set according to the arrangement of specific transistors.

[0098] Step S103 : forming a gate layer 02 on the substrate 01 .

[0099] Among them, the gate layer 02 includes a first gate 05 and a second gate 06, the number of the first gates 05 is at least two, the first gates 05 extend along the second direction N and are arranged along the first direction M, and at least two first gates 05 are cross-arranged with at least two first active areas 03, and adjacent first gates 05 are located on both sides of the second active area 04 in the first direction M, and the second gate 06 is located on the second active area 04.

[0100] In this step, if Fig.15 As shown, a gate layer 02 is formed on one side of the substrate 01. It should be noted that before forming the gate layer 02, a gate oxide layer covering the substrate 01 is first formed, and then a gate material layer of a certain thickness is deposited on one side of the gate oxide layer, and then photolithography is used to perform exposure, development, and etching to obtain the gate oxide layer. Fig.15 The gate layer 02 may be of the type in the above-mentioned embodiment, and no specific limitation is made here. The first gate 05 and the second gate 06 may be connected or not connected. Fig.15 The first gate 05 and the second gate 06 are not connected for illustration only.

[0101] After forming the gate layer 02, a certain thickness of oxide layer and silicon nitride layer are grown on the gate layer 02 and the substrate 01 side in sequence, and the oxide layer and silicon nitride layer are photolithographically processed to form the first sidewall around the gate layer 02. Then, ion implantation of the non-locally diffused drain (NLDD) and the doped region is performed. The implanted ions are activated by annealing process.

[0102] Then, a certain thickness of oxide layer and silicon nitride layer are grown on the gate layer 02, the substrate 01 and one side of the first sidewall in sequence, and the oxide layer and silicon nitride layer are photolithographically processed to form a second sidewall on both sides of the first sidewall. Then, N+ ion implantation or P+ ion implantation is performed in the doping region 18 to form a source or drain, forming a Fig.16 The structure shown. It should be noted that, depending on the different devices formed, the conductivity type of the source and drain formed will be different accordingly. For example, to form an NMOS device, the source and drain are formed by N+ ion implantation; to form a PMOS device, the source and drain are formed by P+ ion implantation. The source and drain can be formed according to specific needs, and then annealed at a certain temperature to activate the ions. It should be noted that the first side wall and the second side wall are not marked in the figure, and the area covered by the first side wall and the second side wall will not be implanted with ions.

[0103] Then, the SMT process is continued to be used to form a stress layer covering the gate layer 02, the substrate 01, the first side wall and the second side wall. It should be noted that the NMOS device needs a stress layer with tensile stress, and the PMOS device needs to deposit a stress layer with compressive stress. This process needs to be determined according to the arrangement of the design, and there is no specific limitation on this. For example, when an NMOS device and a PMOS device are formed in a semiconductor device, and the channel regions of the NMOS device and the PMOS device are cross-arranged, the same type of stress layer can be used for covering, and there is no specific limitation on this. Afterwards, an annealing process is used to conduct the stress to the channel region to improve the performance of the transistor, and then the stress layer is removed.

[0104] Afterwards, a self-aligned layer is formed in the area where the contact structure 20 needs to be formed to reduce the resistance of the device, including sequentially depositing an oxide layer and a silicon nitride layer covering the gate layer 02, the substrate 01, the first side wall and the second side wall, and then etching the oxide layer and the silicon nitride layer using an etching process to expose the source and drain on the surface of the gate layer 02 and the substrate 01.

[0105] like Fig.17 As shown, metal silicide 19 is then formed on the surface of the gate layer 02 and the source and drain on the substrate 01. It should be noted that Fig.17 For the sake of clarity, the metal silicide 19 actually covers the gate layer 02, the source and the drain.

[0106] The formation of metal silicide 19 includes: first SiCoNi pre-cleaning the oxide layer on the surface of substrate 01 by about 60 angstroms to ensure that the subsequently deposited metal can directly contact the clean silicon surface, and then depositing NiPt alloy by about 120 angstroms for the subsequent formation of metal silicide. In order to protect the NiPt alloy from oxidation, a 50 angstrom thick TIN layer is deposited thereon as a covering layer, and then a first rapid thermal annealing is performed at a temperature of 290°C for a duration of 30 seconds. This step will cause the NiPt alloy to react with silicon to form a high-resistance metal silicide Ni2PtSi, and then a second rapid thermal annealing is performed to form a low-resistance NiPtSi2. After completing the two rapid thermal anneals, the nickel in the area where NiPtSi2 is not formed is removed to form the above Fig.17 structure.

[0107] After that, 330 angstroms of amorphous silicon nitride is deposited, which acts as a hard mask to protect the underlying material during subsequent pattern transfer and etching processes.

[0108] Then, 2100 angstroms of oxide is deposited as an insulating layer, and 1900 angstroms of amorphous carbon (aC) is deposited as an anti-reflective coating (ARC), followed by 320 angstroms of silicon and 50 angstroms of silicon dioxide as a composite anti-reflective coating. Then, 200 angstroms of bottom anti-reflective coating (BARC) is deposited.

[0109] Then, 1000 angstroms of photoresist (PR) is applied to develop and expose the contact structure. The photoresist is used as a mask to form a contact hole for setting the contact structure 20 by dry or wet etching technology. This process may include multiple etching steps, each optimized for a specific material layer to ensure accurate size and shape. The position of the contact structure on the gate layer 02 can be set to one or more, which needs to be adjusted according to the actual application.

[0110] After the contact hole is formed, a titanium film is deposited. This film acts as an adhesion layer and barrier layer to enhance the adhesion of subsequent deposited materials and prevent metals such as tungsten from diffusing into silicon dioxide or other dielectric materials. Then a titanium nitride film is deposited. This film also acts as an adhesion layer and barrier layer to further enhance the adhesion and diffusion barrier capabilities of the metal layer. TiN also has good conductivity, which helps improve the performance of electrical connections.

[0111] A layer of tungsten is deposited in the contact hole using a physical vapor deposition (PVD) or chemical vapor deposition (CVD) method. After the tungsten layer is deposited, chemical mechanical polishing is performed to flatten the surface to form a Fig.18The structure shown in FIG. Then, the subsequent processes can be continued.

[0112] When the preparation method is used to prepare semiconductor devices, when the formed transistors are of the same type, the source or drain between different transistors can be shared. For example, an "I"-type active area and an "I"-type gate layer are set, and the "I"-type active area and the "I"-type gate layer are rotated and cross-set, so that a fifth transistor is formed between the four transistors. At this time, the source and the drain are shared, and the arrangement area remains unchanged while the number of transistors is increased by 25%, thereby improving the performance of the semiconductor.

[0113] In addition, when the types of transistors formed are different, the channel regions of the NMOS device and the PMOS device can be cross-set according to the difference in stress required by different types of transistors, which reduces the area of ​​the semiconductor device while allowing the same stress layer to introduce stress to the NMOS device and the PMOS device at the same time, reducing the preparation cost.

[0114] In addition, this design can also be applied to the FinFET process, with more obvious improvement effects.

[0115] In the description of this specification, the description with reference to the terms "some embodiments", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0116] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises a substrate and a gate layer located on the substrate. The substrate comprises: At least two first active regions extending along the first direction and arranged along the second direction; a second active region, located between adjacent first active regions in the second direction, the first direction and the second direction being parallel to the substrate, and the first direction and the second direction intersecting; The gate layer comprises: at least two first gates extending along the second direction and arranged along the first direction, and at least two of the first gates are arranged to cross at least two of the first active regions, and adjacent first gates are located on both sides of the second active regions in the first direction; The second gate is located on the second active region.

2. The semiconductor device according to claim 1, wherein: The first active region includes a first channel region, and the second active region includes a second channel region; the first channel region and the second channel region have the same conductivity type.

3. The semiconductor device according to claim 2, characterized in that The first active region also includes a first doped region, which is alternately arranged with the first channel region along the first direction, the first doped region and the second channel region have opposite conductivity types, and the second channel region is connected to the first doped regions of two adjacent first active regions in the second direction.

4. The semiconductor device according to claim 2, characterized in that The second gate is connected to the first gate in the first direction.

5. The semiconductor device according to claim 1, wherein: The first active region includes a first channel region, and the second active region includes a second channel region; the first channel region has a first conductivity type, and the second channel region has a second conductivity type, and the conductivity types of the first channel region and the second channel region are different.

6. The semiconductor device according to claim 5, characterized in that The first active region also includes a second doped region, and the second doped region and the first channel region are arranged alternately along the first direction. The second doped region includes a first sub-region, a second sub-region and a third sub-region arranged in sequence along the first direction. The first sub-region and the third sub-region have the second conductivity type, and the second sub-region has the first conductivity type. The second channel region is connected to the second sub-regions of two adjacent first active regions at least in the second direction.

7. The semiconductor device according to claim 5, characterized in that The second gate is spaced apart from the first gate in the first direction.

8. The semiconductor device according to claim 5, characterized in that The second active region further includes a third doped region, the third doped region is located at both sides of the second channel region in the second direction, and the third doped region has the first conductivity type; the second gate is spaced apart from the first active region in the second direction.

9. The semiconductor device according to claim 8, characterized in that The first active region further includes a first doped region, the first doped region and the first channel region are alternately arranged along the first direction, the first doped region has a second conductivity type, and the third doped region is connected to the first doped region.

10. The semiconductor device according to claim 8, characterized in that The second gate is connected to the first gate in the first direction.

11. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; Doping the substrate to form an active region, wherein the active region includes a first active region and a second active region, the number of the first active regions is at least two, the first active regions extend along a first direction and are arranged along a second direction, the second active regions are located between adjacent first active regions in the second direction, the first direction and the second direction are parallel to the substrate, and the first direction and the second direction intersect; A gate layer is formed on the substrate, the gate layer includes a first gate and a second gate, the number of the first gates is at least two, the first gates extend along the second direction and are arranged along the first direction, at least two of the first gates are cross-arranged with at least two of the first active regions, and adjacent first gates are located on both sides of the second active region in the first direction, and the second gate is located on the second active region.

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