Memory fault prediction method and device, chip, equipment and storage medium

Abstract

The invention discloses a memory fault prediction method and device, a chip, equipment and a storage medium, and belongs to the technical field of computers. The method comprises the steps that error position distribution of an error correction unit associated with a memory is obtained, the memory comprises at least one memory particle, the error correction unit comprises a plurality of data bits obtained from a plurality of storage units of the memory through continuous multiple burst reading, and each data bit corresponds to one storage unit in the memory; the error position distribution is used for indicating the position of an error data bit in a plurality of data bits, and the error position distribution causes the occurrence of CE in the memory; a memory fault model is obtained, the memory fault model comprises at least one reference position distribution, and the reference position distribution is associated with the UCE of the memory; according to the similarity between the error position distribution and the at least one reference position distribution, a prediction result is output, and the prediction result is used for indicating the probability that the UCE occurs in the memory. The method is beneficial to improving the timeliness of memory fault prediction.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory failure prediction method and device, chip, equipment and storage medium. Background Art

[0002] With the development of Internet technology, the memory capacity of servers is getting larger and larger. Memory failure is one of the main causes of server failure. In order to support the normal operation of the server, it is necessary to predict memory failure before it occurs.

[0003] In the related art, memory fault prediction can adopt the following method: according to multiple correctable error (CE) information of the memory of the device under test within a set time period, determine the memory fault characteristics of the device under test at multiple memory granularities, wherein the memory granularity includes the whole machine memory granularity, memory bar granularity, physical array granularity and memory particle granularity; according to the resource static information of the device under test and the memory fault characteristics at various memory granularities, predict the probability of uncorrectable error (UCE) of the device under test.

[0004] Since this method needs to collect multiple CE information within a set time period first, the CE information collection process is relatively long, resulting in poor timeliness of the memory fault prediction method. Summary of the invention

[0005] The present application provides a memory fault prediction method and apparatus, chip, device and storage medium, which are conducive to improving the timeliness of memory fault prediction.

[0006] In the first aspect, the present application provides a method for predicting memory faults. The method includes: obtaining the error position distribution of the error correction unit associated with the memory, the memory includes at least one memory particle, each of the memory particles includes a plurality of storage units arranged in an array, the error correction unit includes a plurality of data bits obtained from the plurality of storage units of the at least one memory particle through multiple consecutive burst reads, and the plurality of data bits respectively correspond to one storage unit among the plurality of storage units of the at least one memory particle. That is, each of the data bits corresponds to one storage unit, and different data bits correspond to different storage units. The error position distribution is used to indicate the position of the error data bit among the plurality of data bits, and the error position distribution causes the memory to have a correctable error CE; obtaining a memory fault model, the memory fault model includes at least one reference position distribution, and the reference position distribution is associated with the uncorrectable error UCE of the memory; outputting a prediction result according to the similarity between the error position distribution and at least one reference position distribution, and the prediction result is used to indicate the probability of the memory having UCE.

[0007] In the present application, since the reference position distribution is associated with UCE, the similarity between the error position distribution when CE occurs in the memory and at least one of the reference position distributions is associated with the probability of UCE occurring in the memory, and can reflect the probability of UCE occurring in the memory. The higher the similarity between the error position distribution and the reference position distribution, the higher the possibility of UCE occurring in the memory; conversely, the lower the similarity between the error position distribution of the error correction unit and the reference position distribution, the lower the possibility of UCE occurring in the memory. Therefore, the probability of UCE occurring in the memory can be predicted based on the similarity between the error position distribution when CE occurs in the memory and at least one of the reference position distributions. On the one hand, when CE occurs in the memory, the memory fault can be predicted based on the error position distribution of the error correction unit corresponding to CE, without waiting to collect a large amount of CE information, so the timeliness of memory fault prediction is high. On the other hand, predicting memory faults based on the error position distribution of the error correction unit, that is, based on the mechanism of UCE generation, is conducive to improving the accuracy of memory fault prediction. This prediction method can be used in combination with other fault prediction methods in the relevant technology to further improve the accuracy of memory fault prediction.

[0008] Optionally, the association of the reference position distribution with the UCE of the memory means that: the reference position distribution is the error position distribution when the UCE occurs in the memory, or the reference position distribution is the error position distribution corresponding to the CE that has appeared in the memory within a set time before the UCE occurs. If a CE has appeared within a set time before the UCE occurs in the memory, it means that the CE may subsequently evolve into a UCE, so the error position distribution corresponding to the CE can be used as the reference position distribution.

[0009] Optionally, outputting the prediction result according to the similarity between the error position distribution and at least one of the reference position distributions may adopt any one of the following two methods:

[0010] The first method is to calculate the similarity between the error position distribution and each reference position distribution respectively; and output the prediction result according to the calculated similarity. For example, the highest similarity among the calculated similarities can be determined first, and then the prediction result can be output according to the highest similarity. For another example, the probability of the occurrence of UCE corresponding to each reference position distribution can be determined for each calculated similarity; then the determined probabilities are fused to obtain the fusion result, and finally the prediction result is output according to the fusion result.

[0011] In the first manner, the error position distribution is compared with each reference position distribution to obtain the similarity between the error position distribution and each reference position distribution, which is beneficial to improving the accuracy of the fault prediction result.

[0012] The second method is to calculate the similarity between the error position distribution and each reference position distribution in the memory fault model in sequence; when the calculated similarity is higher than the similarity threshold, stop calculating the similarity and output the prediction result based on the similarity higher than the similarity threshold.

[0013] In the second method, it may not be necessary to calculate the similarities corresponding to all reference position distributions to obtain the prediction result, which is beneficial to improving the fault prediction efficiency.

[0014] Optionally, the error position distribution of the error correction unit is represented by a plurality of first elements, the plurality of first elements correspond one-to-one to the plurality of data bits, and each of the first elements is used to indicate whether a corresponding data bit is an error data bit. The reference position distribution is represented by a plurality of second elements, the plurality of first elements correspond one-to-one to the plurality of second elements. Calculating the similarity between the error position distribution and any of the reference position distributions in the memory fault model comprises: counting the number of first elements in the error position distribution that are different from the corresponding second element to obtain the similarity; or counting the number of first elements in the error position distribution that are the same as the corresponding second element to obtain the similarity.

[0015] Optionally, the method of calculating the similarity between the error position distribution and a reference position distribution may adopt any one of the following two methods.

[0016] In the first mode, the error position distribution is represented by a first binary sequence, the first binary sequence includes a plurality of first data bits, and each of the first data bits is a first element. The reference position distribution is represented by a second binary sequence, the second binary sequence includes a plurality of second data bits, and each of the second data bits is a second element. The Hamming distance between the first binary sequence and the second binary sequence is used as the similarity between the error position distribution and the reference position distribution.

[0017] The first method is used to calculate the similarity, and the calculation method is simple, which is conducive to simplifying the process of memory fault prediction and improving the efficiency of memory fault prediction.

[0018] The second way is that the error position distribution is represented by a first graphic, the first graphic includes a plurality of first units arranged in an array, the plurality of first units correspond one-to-one to the plurality of data bits, and each of the first units is used to indicate whether a corresponding data bit is an error data bit. The reference position distribution is represented by a second graphic, the second graphic includes a plurality of second units arranged in an array. The plurality of second units correspond one-to-one to the plurality of first units. The overlap between the first graphic and the second graphic is determined, and the overlap is used as the similarity between the error position distribution and the reference position distribution. Among them, the overlap is proportional to the number of first fault units in the first graphic that are in the same position as the second fault unit in the second graphic. The first fault unit is a first unit indicating that the corresponding data bit is an error data bit, and the second fault unit is a second unit indicating that the corresponding data bit is an error data bit.

[0019] The first graph and the second graph are used to represent the error position distribution and the reference position distribution respectively, so as to facilitate the determination of the position relationship between the data bits in an error correction unit, for example, the positions in the same burst or the same data queue (DQ).

[0020] In the second manner, the calculation methods of the overlap degree can be divided into two categories. The first category is to calculate the overlap degree based on the number of first faulty units in the first graph that have the same position as the second faulty unit in the second graph; the second category is to calculate the overlap degree based on the number of first faulty units in the first graph that have the same position as the second faulty unit in the second graph and the number of first non-faulty units in the first graph that have the same position as the second non-faulty unit.

[0021] The two types of overlap calculation methods correspond to two different calculation methods, so there are at least four overlap calculation methods as follows:

[0022] The first method is to determine the overlap degree according to the number of first faulty units in the first graph having the same position as the second faulty units in the second graph and the number of second faulty units in the second graph.

[0023] For example, the coincidence degree may be determined as the ratio of the number of first faulty cells in the first graph having the same position as the second faulty cells in the second graph to the number of second faulty cells in the second graph. The calculation logic is simple and easy to implement.

[0024] The second method is to determine the degree of overlap based on the number of first faulty units in the first graph that have the same position as the second faulty unit in the second graph, the relative positions of the first non-faulty units in the first graph that have the same position as the second faulty unit in the second graph and the first faulty unit in the second graph, and the number of second faulty units in the second graph.

[0025] Exemplarily, the number of first faulty units in the first graph that have the same position as the second faulty units in the second graph is first determined; then, based on the relative positions of the first non-faulty units in the first graph that have the same position as the second faulty units in the second graph and the first faulty units in the second graph, the number of first faulty units in the first graph that have the same position as the second faulty units in the second graph is adjusted to obtain an adjusted number; then, the ratio of the adjusted number to the number of second faulty units in the second graph is determined as the overlap degree.

[0026] According to the relative positions of the first non-faulty units in the first graph that are at the same position as the second faulty units in the second graph and the first faulty units in the second graph, the number of the first faulty units in the first graph that are at the same position as the second faulty units in the second graph is adjusted, so that the finally calculated overlap degree can better reflect the similarity between the error position distribution and the reference position distribution, making the result of memory fault prediction more accurate.

[0027] The third type is to determine the degree of overlap based on the number of overlapping units in the first graph and the second graph, and the number of first units in the first graph, wherein the overlapping units include a first faulty unit in the first graph that has the same position as the second faulty unit in the second graph and a first non-faulty unit in the first graph that has the same position as the second non-faulty unit.

[0028] Exemplarily, the ratio of the number of overlapping units to the number of second faulty units in the second graph may be determined as the overlap degree.

[0029] Fourth, the degree of overlap is determined based on the number of overlapping units in the first graph and the second graph, the relative position of the first non-faulty unit in the first graph that is the same position as the second faulty unit in the second graph and the first faulty unit in the second graph, and the number of first units in the first graph.

[0030] Exemplarily, the number of overlapping units is first determined; then, based on the relative positions of the first non-faulty unit in the first graph that is the same as the second faulty unit in the second graph and the first faulty unit in the second graph, the number of overlapping units is adjusted to obtain an adjusted number; then, the ratio of the adjusted number to the number of second faulty units in the second graph is determined as the overlap degree.

[0031] In the second and fourth methods, first, from the first graph, a first non-faulty unit is determined, which has the same position as the second faulty unit in the second graph and the data bit corresponding to the first faulty unit belongs to the same data queue and / or the same burst; an adjustment value is determined according to the determined first non-faulty unit and the set value; and the corresponding quantity is adjusted using the adjustment value, for example, the corresponding quantity is added to the adjustment value to obtain the adjusted quantity. The set value is used to indicate the probability of the determined first non-faulty unit being faulty. The adjustment value is equal to the sum of the set values ​​corresponding to the determined first non-faulty units.

[0032] When a data bit corresponding to a first unit is erroneous, the non-erroneous data bits located in the same DQ and / or burst are more likely to be erroneous. Therefore, once the data bit that is about to be erroneous is erroneous, the corresponding first unit will overlap with the second faulty unit in the second figure. Therefore, a value (i.e., the aforementioned set value) can be set for the first non-faulty storage unit corresponding to this type of data bit to indicate the possibility of its error, and the number of overlapping units can be adjusted according to the set value.

[0033] In some examples, the prediction result may be the aforementioned similarity. In other examples, the prediction result may be a risk level, which is used to indicate the probability of UCE occurring in the memory. The higher the risk level, the greater the probability of UCE occurring in the memory; conversely, the lower the risk level, the smaller the probability of UCE occurring in the memory.

[0034] When the similarity is represented by the Hamming distance, the risk level corresponding to the distance interval to which the Hamming distance belongs can be output according to the distance interval to which the Hamming distance belongs and the correspondence between the distance interval and the risk level. The correspondence includes N distance intervals and N risk levels, and different distance intervals correspond to different risk levels, where N is an integer and N is greater than 1.

[0035] The larger the Hamming distance, the lower the similarity between the error position distribution and the reference position distribution, and the smaller the possibility of UCE. Conversely, the smaller the Hamming distance, the higher the similarity between the error position distribution and the reference position distribution, and the greater the possibility of UCE.

[0036] When the similarity is expressed by overlap, the risk level corresponding to the overlap interval to which the overlap belongs can be output based on the overlap interval to which the overlap belongs and the correspondence between the overlap interval and the risk level. The correspondence includes M overlap intervals and M risk levels, and different overlap intervals correspond to different risk levels, where M is an integer and M is greater than 1.

[0037] The greater the overlap, the higher the similarity between the error position distribution and the reference position distribution, and the greater the possibility of UCE. Conversely, the smaller the overlap, the lower the similarity between the error position distribution and the reference position distribution, and the smaller the possibility of UCE.

[0038] Optionally, the number of risk levels can be set according to actual needs, for example, it can be divided into three risk levels: high, medium and low.

[0039] In a second possible implementation, the memory fault model is a neural network model. The neural network model is trained using first-class samples and second-class samples, wherein the first-class samples are error position distributions of error correction units corresponding to memory with only CE when CE occurs, and the second-class samples are error position distributions of error correction units corresponding to memory with UCE when CE occurs before UCE occurs. The error position distribution is processed using the neural network model to obtain the prediction result.

[0040] The neural network model is used to predict memory failures, without the need to obtain the error location distribution when UCE occurs in the memory in advance, and has a wide range of applications.

[0041] In the second possible implementation, the prediction result may be a probability value of UCE occurring in the memory or a risk level indicating the probability value of UCE occurring in the memory.

[0042] In a second aspect, the present application provides a memory failure prediction device. The memory failure prediction device has the function of implementing the method described in the first aspect or any optional method of the first aspect. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

[0043] In a third aspect, an electronic device is provided. The electronic device includes a processor and a memory. The memory is used to store software programs and modules. The processor implements the method in the first aspect or any possible implementation of the first aspect by running or executing the software program and / or module stored in the memory.

[0044] Optionally, the number of the processors is one or more, and the number of the memories is one or more.

[0045] Optionally, the memory may be integrated with the processor, or the memory may be provided separately from the processor.

[0046] In the specific implementation process, the memory can be a non-transitory memory, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or can be set on different chips. This application does not limit the type of memory and the setting method of the memory and the processor.

[0047] In a fourth aspect, a computer program product is provided, wherein the computer program product comprises computer program code, and when the computer program code is executed by a computer, the computer executes the method in the first aspect or any possible implementation of the first aspect.

[0048] In a fifth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store program codes executed by a processor, wherein the program codes include instructions for implementing a method in any possible implementation of the first aspect above.

[0049] In a sixth aspect, the present application provides a chip including a logic circuit and a power supply circuit, wherein the logic circuit is used to execute a method in any possible implementation of the first aspect, and the power supply circuit is used to supply power to the logic circuit.

[0050] In a seventh aspect, the present application provides another chip. The other chip includes an input interface, an output interface, a processor and a memory. The input interface, the output interface, the processor and the memory are connected through an internal connection path. The processor is used to execute the code in the memory, and when the code is executed, the processor is used to execute the method in any possible implementation of the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a schematic diagram of the hardware structure of a server provided in an embodiment of the present application;

[0052] Figure 2 It is a flowchart of a memory failure prediction method provided in an embodiment of the present application;

[0053] Figure 3 is a schematic diagram of an error correction unit provided in an embodiment of the present application;

[0054] Figure 4 It is a flowchart of another memory failure prediction method provided by an embodiment of the present application;

[0055] Figure 5It is a graphical comparison chart of the error position distribution and the reference position distribution;

[0056] Figure 6 It is a flowchart of another memory failure prediction method provided by an embodiment of the present application;

[0057] Figure 7 It is a block diagram of a memory failure prediction device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0059] Figure 1 Schematic diagram of the hardware structure of a server provided in an embodiment of the present application. Figure 1 As shown, the server 10 includes at least a processor 110, a memory 120, a basic input output system (BIOS) 130, and a baseboard management controller (BMC) 140. The processor 110 and the memory 120 are connected via a bus 150. The BMC 140 and the processor 110 are connected to the BIOS 130, respectively.

[0060] The processor 110 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), or one or more integrated circuits. Optionally, the number of processors 110 may be one or more. When the processor 110 is a CPU, the CPU may have one or more CPU cores.

[0061] The memory 120 can be used to temporarily store computer executable program codes and data. The memory 120 has the characteristics of fast data read and write speed, and can be used as a temporary data storage space for running applications. The memory 120 can use one or more of the following types of memory: dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR SDRAM) (DDR for short), low power DDR (LPDDR), high bandwidth memory (HBM), phase change memory, resistive random access memory (RRAM or ReRAM), magneto-resistive random access memory (MRAM), ferroelectric random access memory (FeRAM), nano random access memory (NRAM) or static random access memory (SRAM), etc. In practical applications, the server 10 may include one or more memories 120. When the server 10 is configured with multiple memories 120 , the multiple memories 120 may be memories of the same type or memories of different types.

[0062] In some examples, the processor 110 includes a memory controller 1101. The memory controller 1101 is used to manage the memory 120 and communicate with the processor 110. In the server 10, the processor 110 and the memory 120 exchange data through the memory controller 1101. For example, when the memory controller 1101 receives a data write request sent by the processor 110, the data in the data write request is saved in the memory 120. For another example, when the memory controller 1101 receives a data read request sent by the processor 110, the memory controller 1101 reads data from the memory 120 according to the memory address carried in the data read request, and returns the read data to the processor 110.

[0063] The memory controller 1101 can detect whether an error occurs in the memory 120. After the memory controller 1101 detects that an error occurs in the memory 120, it reports the error to the BIOS 130, and the BIOS 130 reports the error to the BMC 140 for processing. After processing, the BMC 140 feeds back the processing result to the BIOS 130, and the BIOS 130 issues a command to trigger the processor 110 to perform the corresponding operation, and the BIOS 130 accesses the memory 120 through the memory controller 1101.

[0064] BMC140 is also called an out-of-band controller. The BMC140 stores the program code of the solution of the present application, and by executing the program code, the memory failure prediction method provided by the embodiment of the present application can be implemented. In some examples, BMC140 can be an independent chip.

[0065] In a possible implementation, the chip may include a processor and a memory, and the processor is used to call and run the program code stored in the memory from the memory, so that an electronic device equipped with the chip executes the memory failure prediction method provided in the embodiment of the present application.

[0066] In another possible implementation, the chip includes a logic circuit and a power supply circuit, the logic circuit is used to implement the memory failure prediction method provided in the embodiment of the present application, and the power supply circuit is electrically connected to the logic circuit to power the logic circuit. Exemplarily, the logic circuit can be implemented by a digital signal processor (digital signal processing, DSP), an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD), a discrete gate or transistor logic device, a discrete hardware component, etc. The PLD can be a complex programmable logical device (complex programmable logical device, CPLD), a field programmable gate array (field-programmable gate array, FPGA), a generic array logic (generic array logic, GAL), a data processing unit (data processing unit, DPU), a system on chip (system on chip, SoC) or any combination thereof.

[0067] The bus 150 may include a path for transmitting information between various components of the server 10 (eg, the processor 110 and the memory 120 ).

[0068] It should be noted that Figure 1The memory controller 1101 is disposed in the processor 110 . In other possible implementations, the memory controller 1101 may also be a device external to the processor 110 , and connected to the processor 110 via a bus.

[0069] It should also be noted that Figure 1 The structure shown does not constitute a specific limitation on the server. In other embodiments of the present application, the server may include more or fewer components than shown in the figure, such as the server may also include an external memory (such as a hard disk), or the server may also combine certain components, or split certain components, or use different component arrangements.

[0070] The embodiment of the present application does not limit the architecture of the server. For example, the server 10 may be an X86 architecture server or a non-X86 architecture server. The embodiment of the present application does not limit the form of the server. For example, it may be a blade server, a high-density server, a rack server, or a high-performance server.

[0071] The physical granularity of memory from large to small is: memory bar (also known as dual inline memory module (DIMM), memory rank, memory chip (also known as memory device), storage array (bank), row or column (column) and storage unit (cell).

[0072] Each memory bank has at least one memory column, and each memory column may include multiple memory chips. When a memory bank has multiple memory columns, each memory column contains the same number of memory chips. The number of memory chips in each memory column varies according to the data bit width of the memory chip, and the product of the data bit width and the number of memory chips is the memory bit width. Each memory chip can be divided into multiple storage arrays, and when the memory chip stores data, the data is written into the storage array in bits. In addition, multiple storage arrays can be divided into a storage array group (bankgroup). The storage array includes multiple storage cells arranged in a two-dimensional matrix. In the storage array, a storage cell can be located by rows and columns, and each storage cell is used to store one bit of data. The smallest unit of memory failure is the storage cell on the storage array.

[0073] During the operation of the server 10, the memory 120 may fail. For example, for DRAM, its storage unit is usually composed of a transistor and a capacitor, and the amount of charge carried on the capacitor determines whether the storage unit is 1 or 0. Due to the influence of the external environment or the hardware defects of the transistor, the memory may fail.

[0074] After a memory failure occurs, an error correction algorithm (such as error checking and correcting (ECC)) is used to correct the error. If the error is corrected, it is called CE. If the error exceeds the error correction capability of the error correction algorithm, the error cannot be corrected and is called UCE. UCE can cause problems such as device downtime. Therefore, it is necessary to predict the possibility of UCE before it occurs, that is, to predict memory failures, in order to reduce the occurrence of device downtime and minimize the losses caused by memory failures.

[0075] Figure 2 is a flow chart of a memory fault prediction method provided by an embodiment of the present application. The method can be Figure 1 The BMC in the Figure 2 As shown, the method comprises the following steps:

[0076] 201, obtaining error position distribution of an error correction unit associated with a memory.

[0077] The memory includes at least one memory chip. That is, the memory here may refer to one memory chip, or a memory bar including a plurality of memory chips. Each memory chip includes a plurality of storage units arranged in an array.

[0078] An error correction unit refers to the minimum error correction unit required by the error correction algorithm used by the memory. A memory-associated error correction unit refers to an error correction unit composed of data burst-read from some storage units of the memory. Each error correction unit includes multiple data bits obtained from multiple storage units of each memory particle of the memory through multiple consecutive burst reads. These multiple data bits correspond to a storage unit in the memory, respectively. That is, each data bit corresponds to a storage unit, and different data bits correspond to different storage units. Here, a data bit is a bit of data read from the corresponding storage unit.

[0079] Each error correction unit includes multiple bursts, each burst includes multiple data bits, and the multiple data bits correspond one-to-one to multiple data channels of the memory. Exemplarily, the number of bursts in the error correction unit can be equal to half of the burst length. A burst refers to a method of continuous data transmission between adjacent storage cells in the same row, and the number of cycles of continuous transmission is the burst length.

[0080] For example, Figure 3 As shown, it is assumed that a memory bank includes a memory column, and the memory column includes 18 memory chips, of which 16 memory chips (chips 0-15) are used to store valid data, 1 memory chip is used to store parity check data, and 1 memory chip is used to store cyclic redundancy check (CRC) data.

[0081] For a memory access, the memory will generate multiple bursts in batches (that is, a memory access will generate multiple burst reads, each burst read corresponds to a burst), and each burst generally includes multiple data bits (for example Figure 3 The number of bits of data contained in each burst is equal to the sum of the number of DQs of all memory particles in the memory. Here, each DQ is a data transmission channel of a memory particle, and each data transmission channel corresponds to a data transmission pin of a memory particle. Different bit positions in each burst correspond to different DQs, and the same bit positions of different bursts share a DQ. Figure 3 In the example, the data corresponding to each burst includes 64 bits of valid data (i.e., D0-D63), 4 bits of parity data (i.e., P0-P3), and 4 bits of CRC data (i.e., C0-C3). If the burst length is 8, the data corresponding to 4 bursts form an error correction unit, and each error correction unit includes 288 bits of data. For example, the data corresponding to Burst0-4 form an error correction unit, and the data corresponding to Burst4-7 form an error correction unit. Here, valid data refers to data other than check data.

[0082] The error position distribution is used to indicate the position of the error data bit among all the data bits of the error correction unit, and the error position distribution causes CE to occur in the memory.

[0083] Due to the IO characteristics of DRAM, data bits related to a burst or a DQ are prone to errors together. When the positions of the erroneous data bits in multiple data bits corresponding to the same memory particle of an error correction unit are distributed in multiple bursts and / or multiple DQ errors, UCE may occur in the memory particle.

[0084] When a data bit corresponding to a memory cell in an error correction unit is wrong, the BIOS will report fault information to the BMC. The fault information includes the fault location, fault time, and error location distribution. The fault location refers to the physical address where the memory fault occurs. For example, the physical address is used to indicate the bank, row and / or column, memory chip, memory column, and memory bar where the storage unit corresponding to the error data bit is located. The failure time refers to the time when the memory fault occurs. When implemented, the error location distribution may only include the locations of all data bits corresponding to a memory cell where the error data bit is located in an error correction unit, and the other data bits of the error correction unit are considered to be error-free. Therefore, the error location distribution can describe the location of the error data bits of each data bit of an error correction unit.

[0085] During implementation, the error location distribution may be represented by a portion of the value of a register used to record memory error information.

[0086] For example, Figure 3 In FIG. 1 , the first box from top to bottom represents error correction unit 0, and the second box represents error correction unit 1. If memory cell 0 has an error in error correction unit 0, the error position distribution is used to indicate the position of the error data bit of memory cell 0 among the 16 data bits in error correction unit 0.

[0087] 202 , obtaining a memory fault model, where the memory fault model includes at least one reference position distribution, and the at least one reference position distribution is associated with a UCE of the memory.

[0088] In a first possible implementation manner, the association between the reference position distribution and the UCE of the memory means that the reference position distribution is an error position distribution that may cause the UCE to occur in the memory.

[0089] Each reference position distribution can be determined by a fault injection test. For example, test data is written into the memory in units of error correction units, and in the process of writing the test data, a fault injection tool is used to tamper with the specific position of the test data written into the memory, so as to achieve an error in the specific position of the memory data. If UCE occurs in the memory after a certain test data is written, the corresponding error position distribution is determined as the reference position distribution. During implementation, all error position combinations can be traversed to obtain all possible reference position distributions, that is, a memory fault model is obtained.

[0090] In a second possible implementation, the reference position distribution is associated with the UCE of the memory, which refers to the error position distribution corresponding to the CE associated with the UCE. The CE associated with the UCE means that after the error position distribution corresponding to the CE appears, the memory will have UCE, or the probability of the memory having UCE is high.

[0091] In the second possible implementation, the reference position distribution can be obtained by training a neural network model. For example, the error position distribution of CE that occurs in a memory with UCE within a set time period before the occurrence of UCE is used as a positive sample, and the error position distribution of CE that occurs in a memory with only CE as a negative sample is used to train the initial neural network model to obtain a memory fault model. The memory fault model can characterize at least one reference position distribution.

[0092] Alternatively, the error position distribution of CE that occurs in the memory where UCE occurs within a set time period before UCE occurs is obtained by statistically analyzing the error position distribution. For example, the error position distribution of CE that occurs in the memory where UCE occurs within a set time period before UCE occurs can be sorted in order of the number of times from most to least, and the first X error position distributions are used as reference position distributions, where X is a positive integer and a set value.

[0093] 203 , output a prediction result according to the similarity between the error position distribution and at least one reference position distribution, where the prediction result is used to indicate the probability of UCE occurring in the memory.

[0094] In a second possible implementation, the memory fault model is a neural network model, and the error position distribution of the error correction unit is used as the input of the memory fault model. The output of the memory fault model is used to indicate the probability of UCE occurring in the memory.

[0095] The method can be executed each time a CE is detected in the memory, or can be executed when the number of CEs in the memory reaches a threshold number, or can be executed periodically. When the method is executed periodically, the length of the cycle can be set according to actual needs, and can be in seconds, minutes, hours, etc., which is not limited in the embodiments of the present application.

[0096] In the embodiment of the present application, since the reference position distribution is associated with UCE, the similarity between the error position distribution when CE occurs in the memory and at least one of the reference position distributions is associated with the probability of UCE occurring in the memory, and can reflect the probability of UCE occurring in the memory. The higher the similarity between the error position distribution and the reference position distribution, the higher the possibility of UCE occurring in the memory; conversely, the lower the similarity between the error position distribution and the reference position distribution, the lower the possibility of UCE occurring in the memory. Therefore, the probability of UCE occurring in the memory can be predicted based on the similarity between the error position distribution when CE occurs in the memory and at least one of the reference position distributions. On the one hand, when CE occurs in the memory, the memory fault can be predicted based on the error position distribution of the error correction unit corresponding to CE, without waiting for the collection of a large amount of CE information, so the timeliness of memory fault prediction is high. On the other hand, starting from the similarity between the error position distribution of the error correction unit and the reference position distribution, that is, starting from the mechanism of UCE generation, predicting the memory fault is conducive to improving the accuracy of memory fault prediction. This prediction method can be used in combination with other fault prediction methods in the relevant technology to further improve the accuracy of memory fault prediction.

[0097] Combine the following Figure 4 The above-mentioned first possible implementation method is described in detail.

[0098] Figure 4FIG. 1 is a flow chart of a method for predicting memory failure provided by an embodiment of the present application. Figure 4 As shown, the method includes:

[0099] 401, obtain the error position distribution of the error correction unit associated with the memory.

[0100] For related content, please refer to 301 and detailed description is omitted here.

[0101] In a possible implementation manner, the error position distribution is represented by a plurality of first elements, and the plurality of first elements correspond to a plurality of data bits one by one. Each first element is used to indicate whether a corresponding data bit is an error data bit.

[0102] In some examples, the error position distribution is represented by a first binary sequence. The first binary sequence includes a plurality of first data bits, each of which is used to indicate whether a data bit in the error correction unit is erroneous, that is, each first data bit is a first element.

[0103] The number of first data bits in the first binary sequence is equal to the number of data bits in an error correction unit, or the number of first data bits in the first binary sequence is equal to the number of data bits corresponding to the same memory particle in an error correction unit. In order to facilitate the calculation of similarity, the following mainly uses the example that the number of first data bits in the first binary sequence is equal to the number of data bits corresponding to the same memory particle in an error correction unit.

[0104] Each first data bit uniquely corresponds to a data bit in the error correction unit, and is used to indicate whether the corresponding data bit is erroneous. Optionally, when the first data bit is a first value, it indicates that the corresponding data bit is erroneous, and when the first data bit is a second value, it indicates that the corresponding data bit is not erroneous. In some examples, the first value is 0 and the second value is 1. In other examples, the first value is 1 and the second value is 0.

[0105] In other examples, the error position distribution is represented by a first graph, which includes a plurality of first units arranged in an array, each first unit being used to indicate whether a data bit in an error correction unit is erroneous, that is, each first unit is a first element. The number of first units in the first graph is equal to the number of data bits contained in an error correction unit, or the number of first units in the first graph is equal to the number of data bits corresponding to the same memory chip in an error correction unit. In order to facilitate the calculation of similarity, the following mainly uses the example that the number of first units in the first graph is equal to the number of data bits corresponding to an error correction unit and the same memory chip as an example.

[0106] The row of the first graphic represents a burst, and the column of the first graphic represents a DQ. In the first graphic, a data bit can be indexed by a row and a column. The first graphic is a binary graphic, and each first unit can be composed of one or more pixels. When each first unit is composed of multiple pixels, it can be square or circular, etc. When the first unit is the third value, it means that the corresponding data bit is wrong, and when the first unit is the fourth value, it means that the data of the corresponding data bit is not wrong. Here, the third value and the fourth value can be pixel values ​​(such as grayscale values). In some examples, the third value is 0 and the fourth value is 255. In other examples, the third value is 255 and the fourth value is 0.

[0107] 402 , obtaining a memory fault model, where the memory fault model includes at least one reference position distribution.

[0108] Each reference position distribution is an error position distribution that may cause UCE in the memory.

[0109] 403, respectively calculate the similarity between the error position distribution and each reference position distribution.

[0110] Each reference position distribution includes a plurality of second elements, each second element is used to indicate whether a data bit is erroneous. The plurality of first elements and the plurality of second elements correspond one to one, and the corresponding first elements and second elements are related to the same data bit.

[0111] When the error position distribution is represented by the first binary sequence, the reference position distribution is represented by the second binary sequence, and the second binary sequence includes multiple second data bits, each second data bit is used to indicate whether a data bit is erroneous, that is, each second data bit is a second element. Similar to the first binary sequence, when the second data bit is the first value, it indicates that the corresponding data bit is erroneous, and when the second data bit is the second value, it indicates that the corresponding data bit is not erroneous. The i-th second data bit in the second binary sequence and the i-th first data bit in the first binary sequence correspond to the same data bit of an error correction unit. Here, i is an integer.

[0112] When the error position distribution is represented by a first binary sequence and the reference position distribution is represented by a second binary sequence, step 402 includes: calculating the Hamming distance between the first binary sequence and the second binary sequence. The Hamming distance is the similarity between the error position distribution and the reference position distribution. This calculation method is simple, which is conducive to simplifying the process of memory fault prediction and improving the efficiency of memory fault prediction.

[0113] The first binary sequence and the second binary sequence are compared bit by bit, and the number of first data bits that are at the same data bit position as the second data bit but have different values ​​is determined as the Hamming distance between the first binary sequence and the second binary sequence.

[0114] For example, the error position distribution is 0x2270, and the corresponding first binary sequence is 0b 0010 0 0 10 01110000; the reference position distribution is 0x2670, and the corresponding second binary sequence is 0b 0010 0110 0111 0000. The underline indicates the first data bit that is in the same data bit position as the second data bit but has a different value. There is a total of 1 first data bit that meets this condition. Therefore, the Hamming distance between the first binary sequence and the second binary sequence is 1.

[0115] For another example, the error position distribution is 0x0070, and the corresponding first binary sequence is 0b 00 0 0 0 00 0 01110000; the reference position distribution is 0x2670, and the corresponding second binary sequence is 0b 0010 0110 0111 0000. The underline indicates the first data bit that is in the same data bit position as the second data bit but has a different value. There are 3 first data bits that meet this condition. Therefore, the Hamming distance between the first binary sequence and the second binary sequence is 3.

[0116] For another example, the error position distribution is 0x0884, and the corresponding first binary sequence is 0b 00 0 0 100 0 1000 0 1 00; the reference position distribution is 0x2670, and the corresponding second binary sequence is 0b 0010 0110 0111 0000. The underline represents the first data bit that is in the same data bit position as the second data bit but has a different value. There are 8 first data bits that meet this condition. Therefore, the Hamming distance between the first binary sequence and the second binary sequence is 8.

[0117] In these examples, the error location distribution is part of the value of the register that records the memory error information.

[0118] It can be seen that the larger the Hamming distance is, the lower the similarity between the error position distribution and the reference position distribution is; conversely, the smaller the Hamming distance is, the higher the similarity between the error position distribution and the reference position distribution is.

[0119] The Hamming distance is used as the similarity, that is, the number of first elements different from the corresponding second elements in the error position distribution is counted, and the number obtained by counting is used as the similarity. In other embodiments, the number of first elements identical to the corresponding second elements in the error position distribution can also be used as the similarity. In this case, the larger the number obtained by counting, the higher the similarity; the smaller the number obtained by counting, the lower the similarity.

[0120] If the number of first elements in the error position distribution that are identical to the corresponding second element is used as the similarity, the similarity can be obtained by adding the difference between the length of the first binary sequence and the Hamming distance and the number of data bits of other corresponding memory particles in the error correction unit; or, the difference between the length of the first binary sequence and the Hamming distance is used as the similarity.

[0121] In other embodiments, an array may be used to represent the error position distribution and the reference position distribution, where each number in the array representing the error position distribution is a first element, and each number in the array representing the reference position distribution is a second element.

[0122] When the error position distribution is represented by the first graph, the reference position distribution is represented by the second graph, and the second graph includes a plurality of second units arranged in an array, each second unit is used to indicate whether a data bit in an error correction unit is erroneous, that is, each second unit is a second element. Similar to the first graph, the second graph is also a binary graph. When the second unit is the third value, it indicates that the corresponding data bit is erroneous, and when the second unit is the fourth value, it indicates that the corresponding data bit is not erroneous.

[0123] When the error position distribution is represented by a first graph and the reference position distribution is represented by a second graph, step 402 includes: taking the overlap between the first graph and the second graph as the similarity.

[0124] The first graph includes a first faulty unit and a first non-faulty unit. The first faulty unit is a first unit indicating that a data bit is erroneous, and the first non-faulty unit is a first unit indicating that a data bit is not erroneous, that is, the first non-faulty unit is a first unit other than the first faulty unit.

[0125] The second graph includes a second faulty unit and a second non-faulty unit. The second faulty unit is a second unit indicating that the data bit is erroneous, and the second non-faulty unit is a second unit indicating that the data bit is not erroneous, that is, the second non-faulty unit is a second unit other than the second faulty unit.

[0126] In the embodiment of the present application, the overlap degree is proportional to the number of first faulty units in the first graph having the same position as the second faulty units in the second graph.

[0127] In a possible implementation, the overlap between the first graph and the second graph is calculated based on the number of first faulty units in the first graph that are in the same position as the second faulty units in the second graph. For example, the first faulty units in the plurality of first units and the second faulty units in the plurality of second units may be determined respectively; then, the overlap is determined based on the number of first faulty units in the same position as the second faulty unit and the number of second faulty units.

[0128] In some examples, the ratio of the number of first faulty cells at the same position as the second faulty cell to the number of the second faulty cells may be determined as the coincidence degree.

[0129] In other examples, based on the position of the first non-faulty unit and the position of the first faulty unit at the same position as the second faulty unit, the number of first faulty units at the same position as the second faulty unit is adjusted to obtain an adjusted number; then the ratio of the adjusted number to the number of the second faulty units is determined as the degree of overlap.

[0130] Optionally, based on the first non-faulty cell that is at the same position as the second faulty cell and belongs to the same DQ and / or the same burst as the first faulty cell, the number of the first faulty cell that is at the same position as the second faulty cell is adjusted. This is because in an error correction unit, if a data bit is erroneous, the adjacent data bits that are at the same DQ and / or the same burst as the data bit are more likely to be erroneous.

[0131] The following describes a method for adjusting the number of first faulty units at the same position as the second faulty unit.

[0132] In some examples, in an error correction unit, if a data bit is erroneous, the adjacent data bits in the same DQ as the data bit are more likely to be erroneous, therefore, the number of first units in the first unit other than the first faulty unit that are in the same position as the second faulty unit and belong to the same DQ as the first faulty unit is adjusted to a set value; then the number of first faulty units in the same position as the second faulty unit is added to the sum of all set values ​​to obtain the adjusted number. The set value is greater than 0 and less than or equal to 0.5. For example, the set value may be 0.1 or 0.2 or 0.3, etc. Adjusting the number of the fifth unit according to the number of data bits that are not currently erroneous but are more likely to be erroneous is conducive to making the calculated coincidence more accurate.

[0133] In other examples, in an error correction unit, if a data bit is wrong, the data of the adjacent data bits in the same burst as the data bit is more likely to be wrong, therefore, in the first unit other than the first faulty unit, the number of first units that are in the same position as the second faulty unit and belong to the same burst as the first faulty unit is adjusted to a set value; then the number of first faulty units in the same position as the second faulty unit is added to the sum of all set values ​​to obtain the adjusted number. The set value is greater than 0 and less than or equal to 0.5. For example, the set value may be 0.1 or 0.2 or 0.3, etc.

[0134] In some other examples, the number of first cells in the first cell other than the first fault cell that have the same position as the second fault cell and belong to the same DQ as the first fault cell is adjusted to a set value, and the number of first cells in the first cell other than the first fault cell that have the same position as the second fault cell and belong to the same burst as the first fault cell is adjusted to a set value; then the number of first fault cells in the same position as the second fault cell is added to the sum of all the set values ​​to obtain the adjusted number. The set value is greater than 0 and less than or equal to 0.5. For example, the set value may be 0.1 or 0.2 or 0.3, etc.

[0135] Combine the following Figure 5 The first and second calculation methods of the overlap degree are illustrated with examples. Figure 5 In each of the first and second figures, the black rectangles represent the corresponding erroneous data bits, and the white rectangles represent the non-erroneous data bits. That is, in the first figure, each rectangle represents a first unit, and the black rectangle represents the first faulty unit; in the second figure, each rectangle represents a second unit, and the black rectangle represents the second faulty unit. There are 6 second faulty units in the second figure.

[0136] The first method for calculating the coincidence degree is to use the ratio of the number of first faulty units having the same position as the second faulty unit to the number of second faulty units as the coincidence degree.

[0137] In the first first figure, the number of first fault units is 5, and the positions of all first fault units are the same as the positions of the second fault units in the second figure. Therefore, the number of first fault units with the same position as the second fault unit is 5, and the overlap is equal to 0.83. In the second first figure, the number of first fault units is 3, and the positions of all first fault units are the same as the positions of the second fault units in the second figure. Therefore, the number of first fault units with the same position as the second fault unit is 3, and the overlap is equal to 0.5. In the third first figure, the number of first fault units is 4, and the positions of all first fault units are different from the positions of the second fault units in the second figure. Therefore, the number of the fifth unit is 0, and the overlap is equal to 0.

[0138] The second method for calculating the coincidence degree is as follows: based on the first non-faulty unit that is at the same position as the second faulty unit and belongs to the same DQ as the first faulty unit, the number of the first faulty units at the same position as the second faulty unit is adjusted, and the ratio of the adjusted number to the number of the second faulty units is used as the coincidence degree.

[0139] In the first first figure, the number of first faulty units is 5, and the positions of all first faulty units are the same as the positions of the second faulty units in the second figure. Therefore, the number of first faulty units with the same positions as the second faulty units is 5. Among all first non-faulty units (i.e., in the white rectangle), the first non-faulty unit corresponding to DQ1 and burst1 is adjacent to the first faulty unit corresponding to DQ1 and burst2, and the second unit corresponding to DQ1 and burst1 is the second faulty unit. Therefore, the first unit corresponding to DQ1 and burst1 corresponds to the set value. Assuming the set value is 0.3, the adjusted number is 5.3, and the overlap is 0.88.

[0140] In the second first figure, the number of first faulty cells with the same position as the second faulty cell is 3. Among all the first non-faulty cells (i.e., in the white rectangle), the first non-faulty cell corresponding to DQ1, burst1 is adjacent to the first faulty cell corresponding to DQ1, burst2, and the second cell corresponding to DQ1, burst1 is the second faulty cell, and the first non-faulty cell corresponding to DQ2, burst1 is adjacent to the first faulty cell corresponding to DQ2, burst2, and the second cell corresponding to DQ2, burst1 is the second faulty cell. Therefore, the first cell corresponding to DQ1, burst1 and the first cell corresponding to DQ2, burst1 correspond to the set value. Assuming the set value is 0.3, the adjusted number is 3.6, and the overlap is 0.6.

[0141] In the third first figure, the number of first faulty cells in the same position as the second faulty cell is 0. Among all first non-faulty cells (i.e., in the white rectangle), the first non-faulty cell corresponding to DQ1, burst2 is adjacent to the first faulty cell corresponding to DQ1, burst3, and the second cell corresponding to DQ1, burst2 is the second faulty cell, the first non-faulty cell corresponding to DQ2, burst2 is adjacent to the first faulty cell corresponding to DQ2, burst3, and the second cell corresponding to DQ2, burst2 is the second faulty cell. Therefore, the first cell corresponding to DQ1, burst2 and the first cell corresponding to DQ2, burst2 correspond to the set value. Assuming the set value is 0.3, the adjusted number is 0.6, and the overlap is 0.1.

[0142] In another possible implementation, the overlap degree of the first graph and the second graph is calculated based on the number of first faulty units in the first graph that have the same position as the second faulty unit in the second graph and the number of first non-faulty units in the first graph that have the same position as the second non-faulty unit in the second graph. That is, it is calculated based on the number of overlapping units in the first graph and the second graph, and the overlapping units include the first faulty unit in the same position as the second faulty unit and the first non-faulty unit in the same position as the second non-faulty unit.

[0143] For example, the number of first faulty units at the same position as the second faulty unit and the number of first non-faulty units at the same position as the second non-faulty unit can be determined, that is, the number of overlapping units can be determined; and the overlap degree can be determined based on the number of overlapping units and the number of first units.

[0144] In some examples, the ratio of the number of overlapping units to the number of first units can be determined as the overlap degree. In other examples, the number of overlapping units is first adjusted based on the position of the first non-faulty unit and the position of the first faulty unit at the same position as the second faulty unit to obtain the adjusted number of overlapping units; then, the ratio of the adjusted number of overlapping units to the number of first units is determined as the overlap degree.

[0145] The method for adjusting the number of overlapping units refers to the aforementioned method for adjusting the number of first fault units at the same position as the second fault unit, and a detailed description is omitted here.

[0146] Combine the following Figure 5 The third and fourth calculation methods of the overlap degree are illustrated with examples. Figure 5In each first figure and second figure, a black rectangle indicates that the corresponding data bit is wrong, and a white rectangle indicates that the corresponding data bit is not wrong. That is, in the first figure, each rectangle represents a first unit, a black rectangle represents a first faulty unit, and a white rectangle represents a first non-faulty unit; in the second figure, each rectangle represents a second unit, a black rectangle represents a second faulty unit, and a white rectangle represents a second non-faulty unit. The first figure includes 16 first units.

[0147] The third method for calculating the overlap is to determine the overlap as the ratio of the sum of the number of first faulty units having the same position as the second faulty unit and the number of first non-faulty units having the same position as the second non-faulty unit to the number of first units.

[0148] In the first first figure, the number of overlapping units is 15, and the overlap degree is 0.94. In the second first figure, the number of overlapping units is 13, and the overlap degree is 0.81. In the third first figure, the number of overlapping units is 6, and the overlap degree is 0.38.

[0149] The fourth method for calculating the overlap degree is to use the ratio of the number of adjusted overlap units to the number of first units as the overlap degree.

[0150] In the first first figure, the number of overlapping cells is 15. Among all the first non-faulty cells (i.e., in the white rectangle), the first non-faulty cell corresponding to DQ1 and burst1 is adjacent to the first faulty cell corresponding to DQ1 and burst2, and the second cell corresponding to DQ1 and burst1 is the second faulty cell. Therefore, the first cell corresponding to DQ1 and burst1 corresponds to the set value. Assuming the set value is 0.3, the number of overlapping cells after adjustment is 15.3, and the overlap degree is 0.96.

[0151] In the second first figure, the number of overlapping cells is 13. Among all the first non-faulty cells (i.e., in the white rectangle), the first non-faulty cell corresponding to DQ1, burst1 is adjacent to the first faulty cell corresponding to DQ1, burst2, and the second cell corresponding to DQ1, burst1 is the second faulty cell, the first non-faulty cell corresponding to DQ2, burst1 is adjacent to the first faulty cell corresponding to DQ2, burst2, and the second cell corresponding to DQ2, burst1 is the second faulty cell, therefore, the first cell corresponding to DQ1, burst1 and the first cell corresponding to DQ2, burst1 correspond to the set value. Assuming the set value is 0.3, the number of overlapping cells after adjustment is 13.6, and the overlap degree is 0.85.

[0152] In the third first figure, the number of first faulty cells in the same position as the second faulty cell is 6. Among all first non-faulty cells (i.e., in the white rectangle), the first non-faulty cell corresponding to DQ1 and burst2 is adjacent to the first faulty cell corresponding to DQ1 and burst3, and the second cell corresponding to DQ1 and burst2 is the second faulty cell, the first non-faulty cell corresponding to DQ2 and burst2 is adjacent to the first faulty cell corresponding to DQ2 and burst3, and the second cell corresponding to DQ2 and burst2 is the second faulty cell, therefore, the first cell corresponding to DQ1 and burst2 and the first cell corresponding to DQ2 and burst2 correspond to the set value. Assuming the set value is 0.3, the number of overlapped cells after adjustment is 6.6, and the overlap degree is 0.41.

[0153] It can be seen that the greater the overlap, the higher the similarity between the error position distribution and the reference feature distribution; conversely, the smaller the overlap, the lower the similarity between the error position distribution and the reference position distribution.

[0154] 404. Output prediction results according to the calculated similarities.

[0155] The prediction result is used to indicate the probability of UCE occurring in the memory.

[0156] In one embodiment, the prediction result includes the highest similarity among all calculated similarities. In another embodiment, the prediction result includes the risk level corresponding to the highest similarity among all calculated similarities.

[0157] For example, when the similarity is represented by the Hamming distance, the highest similarity is the minimum Hamming distance. Step 403 includes: according to the distance interval to which the Hamming distance belongs and the correspondence between the distance interval and the risk level, outputting the risk level corresponding to the distance interval to which the minimum Hamming distance belongs, the correspondence includes N distance intervals and N risk levels, different distance intervals correspond to different risk levels, where N is an integer and N is greater than 1.

[0158] For example, N is equal to 3, that is, the risk level is divided into three risk levels: high, medium and low. Distance interval 1 corresponds to a high risk level, distance interval 2 corresponds to a medium risk level, and distance interval 3 corresponds to a low risk level.

[0159] The embodiment of the present application does not limit the division method of the distance interval, and can be adjusted according to actual needs. For example, distance interval 1 can be [1, a1), distance interval 2 can be [a1, a2), and distance interval 3 can be [a2, a3]. For example, a1 is equal to 3, a2 is equal to 10, and a3 is equal to the number of data bits contained in the error correction unit.

[0160] For another example, when the similarity is expressed by overlap, the highest similarity is the maximum overlap. Step 403 includes: according to the overlap interval to which the maximum overlap belongs and the correspondence between the overlap interval and the risk level, outputting the risk level corresponding to the overlap interval to which the maximum overlap belongs, the correspondence includes M overlap intervals and M risk levels, different overlap intervals correspond to different risk levels, wherein M is an integer and M is greater than 1.

[0161] For example, M is equal to 3, that is, the risk level is divided into three risk levels: high, medium and low. The overlap interval 1 corresponds to the low risk level, the overlap interval 2 corresponds to the medium risk level, and the overlap interval 3 corresponds to the high risk level.

[0162] The embodiment of the present application does not limit the division method of the overlap interval, and can be adjusted according to actual needs. For example, the overlap interval 1 can be [0, b1), the overlap interval 2 can be [b1, b2), and the overlap interval 3 can be [b2, 1]. For example, b1 is equal to 0.4, and b2 is equal to 0.8.

[0163] It should be noted that when the memory fault model includes multiple reference position distributions, it is necessary to determine the probability of UCE occurrence corresponding to each reference position distribution, and obtain the prediction result according to the probability corresponding to each reference position distribution.

[0164] In one possible implementation, the prediction result may indicate the maximum probability among the probabilities corresponding to all reference position distributions. In another possible implementation, the probabilities corresponding to the reference position distributions may be fused to obtain a fusion result, and the prediction result is used to indicate the fusion result.

[0165] For example, the fusion result can be calculated using the following formula (1):

[0166] p=1-(1-p1)*(1-p2)……*(1-px) (1),

[0167] Among them, p represents the fusion result, p1 represents the probability corresponding to the first reference position distribution, px represents the probability corresponding to the xth reference position distribution, and x represents the number of all reference position distributions.

[0168] Through steps 403 and 404, it can be achieved that, according to the similarity between the error position distribution and at least one reference position distribution, a prediction result is output, and the prediction result is used to indicate the probability of UCE occurring in the memory.

[0169] Alternatively, in other embodiments, steps 403 and 404 may be replaced by: calculating the similarity between the error position distribution and each reference position distribution in sequence; when the calculated similarity is higher than the similarity threshold, stop calculating the similarity between the error position distribution and the remaining reference position distributions, and output the prediction result according to the similarity higher than the similarity threshold. For example, assuming that the memory fault model includes Y reference position distributions, first calculate the similarity between the error position distribution and the jth reference position distribution. If the similarity is higher than the similarity threshold, stop calculating, and output the prediction result according to the similarity; if the similarity is lower than or equal to the similarity threshold, calculate the similarity between the error position distribution and the j+1th reference position distribution until a similarity higher than the similarity threshold is calculated or until the similarities corresponding to all reference position distributions are calculated. If the similarities corresponding to all reference position distributions are calculated, the prediction result may be output according to the highest similarity among the calculated similarities. Wherein, j is a positive integer, and j is less than or equal to Y.

[0170] If the similarity is higher than the similarity threshold, it means that the probability of UCE in the memory is very high. At this time, there is no need to continue calculating the similarity corresponding to other reference position distributions to obtain the prediction result. Therefore, in the fault prediction process, it may not be necessary to calculate the similarity corresponding to all reference position distributions to obtain the prediction result, which is conducive to improving the efficiency of fault prediction.

[0171] Combine the following Figure 6 The above-mentioned first possible implementation method is described in detail. Figure 6 FIG. 1 is a flow chart of a method for predicting memory failure provided by an embodiment of the present application. Figure 6 As shown, the method includes:

[0172] 601, obtaining error position distribution of an error correction unit associated with a memory.

[0173] 602, obtaining a neural network model.

[0174] The neural network model is trained using the first and second types of samples. The first type of samples are the error position distribution of the error correction unit corresponding to the memory where only CE appears when CE appears, and the second type of samples are the error position distribution of the error correction unit corresponding to the memory where UCE appears when CE appears before UCE appears.

[0175] 603, using a neural network model to process the error position distribution to obtain a prediction result.

[0176] In the embodiments of the present application, the neural network model includes but is not limited to a convolutional neural network (CNN) model, a recurrent neural network (RNN) model, or a long short-term memory network (LSTM) model.

[0177] Optionally, before executing step 601, the method further includes training the neural network model. The training process may be: for a memory in which only CE occurs, the error position distribution corresponding to the CE that has occurred in a first time period is obtained as a first type of sample (negative sample); for a memory in which UCE occurs, the error position distribution corresponding to the CE that has occurred in a second time period before the UCE occurs is obtained as a second type of sample (positive sample); the neural network model is trained using the first type of samples and the second type of samples as training sets, and the trained neural network model is the memory fault model.

[0178] In this embodiment, the error position distribution, the first type of samples and the second type of samples are all represented by graphs. For the contents of the graphs, reference may be made to the first graph and the second graph in the aforementioned embodiment, and detailed descriptions are omitted here.

[0179] Exemplarily, the length of the first time period may be 24 hours. The length of the second time period may also be 24 hours. Optionally, a first label, such as 0, may be added to the first type of sample, indicating that the actual probability of the occurrence of UCE corresponding to the first type of sample is 0, and a second label, such as 1, may be added to the second type of sample, indicating that the actual probability of the occurrence of UCE corresponding to the second type of sample is 1.

[0180] Taking the CNN model as an example, the neural network model includes a convolutional layer, a downsampling layer (also called a pooling layer), a fully connected layer, and an output layer connected in sequence. The convolutional layer is used to extract features from the input graph and input the extracted features into the downsampling layer; the downsampling layer is used to reduce the feature dimension to reduce the complexity of calculation; the fully connected layer is used to obtain the predicted probability based on the output of the downsampling layer; and the output layer is used to output the predicted probability.

[0181] The output of the neural network model may be a predicted probability of UCE occurring in the memory. The loss function of the neural network model may be determined based on the error between the predicted probability output by the neural network model and the actual probability of UCE occurring in the memory. The error between the predicted probability output by the neural network model and the actual probability of UCE occurring in the memory may be represented by the mean square error or cross entropy between the predicted probability and the actual probability.

[0182] In this way, after the training is completed, the neural network model can characterize at least one reference position distribution. The reference position distribution is the error position distribution corresponding to the CE associated with the UCE. Here, the CE associated with the UCE means that if the memory has the error position distribution corresponding to the CE, the memory may have the UCE.

[0183] In one embodiment, the prediction result is the output of the neural network model, that is, the output of the neural network model is output as the prediction result.

[0184] In another embodiment, the prediction result is a risk level corresponding to the probability value, and step 603 includes: outputting the risk level corresponding to the probability interval to which the probability value belongs according to the probability interval to which the probability value belongs and the correspondence between the probability interval and the risk level.

[0185] For example, the risk level is still divided into three risk levels: high, medium and low. Probability interval 1 corresponds to the low risk level, probability interval 2 corresponds to the medium risk level, and probability interval 3 corresponds to the high risk level.

[0186] The embodiment of the present application does not limit the division method of the probability interval, and can be adjusted according to actual needs. For example, probability interval 1 can be [0, c1), probability interval 2 can be [c1, c2), and probability interval 3 can be [c2, 1]. For example, c1 is equal to 0.4, and c2 is equal to 0.8.

[0187] In the embodiment of the present application, the method of outputting the prediction result includes one or more of the following methods: outputting the prediction result on a display device; or outputting the prediction result through a voice device; or recording the prediction result in an alarm log. In this way, the staff can promptly learn the prediction result of the memory failure, and when the probability of UCE in the memory is high, relevant protection measures can be taken in time, such as data migration or redundancy processing of the memory (such as copying the data in the memory to the redundant memory) and replacing the memory, etc., to reduce the loss caused by downtime.

[0188] Optionally, the method may further include: automatically executing some protection measures, such as memory chip isolation, etc., according to the prediction result and based on a set memory protection strategy.

[0189] The following is an illustrative description of the memory failure prediction method provided in the embodiment of the present application with reference to specific examples.

[0190] Example 1

[0191] It is known that the reference position distribution is 0x2670, 4 CEs appear in the memory, and the error position distribution corresponding to each CE is 0x0010, 0x0030, 0x0020, and 0x0010 respectively; after calculation, the Hamming distances between the first binary sequence corresponding to each CE and the second binary sequence corresponding to the reference position distribution are 5, 4, 5, and 5 respectively; a1=3, a2=10, therefore, the error position distribution corresponding to these 4 CEs leads to the risk levels of UCE in the memory as medium, medium, medium, and medium respectively.

[0192] Example 2

[0193] It is known that the reference position distribution is 0x2670, 4 CEs appear in the memory, and the error position distribution corresponding to each CE is 0x2400, 0x2500, 0x2510, and 0x2610 respectively; after calculation, the Hamming distances between the first binary sequence corresponding to each CE and the second binary sequence corresponding to the reference position distribution are 4, 5, 4, and 2 respectively; a1=3, a2=10, therefore, the error position distribution corresponding to these 4 CEs leads to the risk levels of UCE in the memory as medium, medium, medium, and high respectively.

[0194] Example 3

[0195] It is known that the reference position distribution is 0x2670, 4 CEs appear in the memory, and the error position distribution corresponding to each CE is 0x700F, 0x500F, 0x700E, and 0x500D respectively; after calculation, the Hamming distances between the first binary sequences corresponding to the 4 CEs and the second binary sequence corresponding to the reference position distribution are 11, 12, 10, and 11 respectively; a1=3, a2=10, therefore, the error position distribution corresponding to these 4 CEs leads to the risk levels of UCE in the memory as low, low, low, and low respectively.

[0196] Example 4

[0197] It is known that the reference position distribution is 0x2670, and 4 CEs appear in the memory. The error position distribution corresponding to each CE is 0x2401, 0x2410, 0x2630, and 0x2500 respectively. After visualization, it is calculated that the overlap between the first graph corresponding to the 4 CEs and the second graph corresponding to the reference position distribution is 69%, 81%, 94%, and 69% respectively. b1=40%, b2=80%. Therefore, the error position distribution corresponding to these 4 CEs causes the UCE risk levels in the memory to be medium, high, high, and medium respectively.

[0198] Example 5

[0199] For the case where there is no known reference position distribution, the data set has a total of 19763 error position distributions of the memory when only CE occurs, and 4255 error position distributions of the memory when UCE occurs; the memory fault model is obtained by training the CNN model, and the error position distributions corresponding to CE 0x700F, 0x0030, 0x2630, and 0x2500 are input for testing, respectively, and the probabilities of UCE occurring in the memory are 0.12, 0.35, 0.92, and 0.73, respectively; c1=0.4, c2=0.8, therefore, the error position distributions corresponding to these CEs lead to the risk levels of UCE occurring in the memory, respectively, low, low, high, and medium.

[0200] Figure 7 1 is a schematic diagram of the structure of a memory failure prediction device provided by the present application. The prediction device can be implemented as part or all of a computer device by software, hardware, or a combination of both. Figure 7 As shown, the device 700 includes: a first acquisition unit 701, a second acquisition unit 702 and a prediction unit 703. The first acquisition unit 701 is used to acquire the error position distribution of the error correction unit associated with the memory, the memory includes at least one memory particle, each memory particle includes a plurality of storage units arranged in an array, the error correction unit includes a plurality of data bits obtained from a plurality of storage units of at least one memory particle through continuous burst reading, the plurality of data bits respectively correspond to a storage unit of the memory, the error position distribution is used to indicate the position of the error data bit in the plurality of data bits, and the error position distribution causes the memory to have a correctable error CE; the second acquisition unit 702 is used to acquire the memory fault model, the memory fault model includes at least one reference position distribution, the reference position distribution is associated with the uncorrectable error UCE of the memory; the prediction unit 703 is used to output a prediction result according to the similarity between the error position distribution and at least one reference position distribution, the prediction result is used to indicate the probability of the memory having UCE.

[0201] In a possible implementation, the prediction unit 703 includes: a calculation subunit 7031 and an output subunit 7032. In some examples, the calculation subunit 7031 is used to calculate the similarity between the error position distribution and each reference position distribution respectively; the output subunit 7032 is used to output the prediction result according to the calculated similarity. In other examples, the calculation subunit 7031 is used to calculate the similarity between the error position distribution and each reference position distribution in sequence; the output subunit 7032 is used to output the prediction result according to the similarity higher than the similarity threshold when the calculated similarity is higher than the similarity threshold.

[0202] Optionally, the error position distribution is represented by a plurality of first elements, the plurality of first elements correspond one-to-one to a plurality of data bits, and each first element is used to indicate whether a corresponding data bit is an error data bit; the reference position distribution is represented by a plurality of second elements, each second element is used to indicate whether a data bit is error, and the plurality of first elements correspond one-to-one to the plurality of second elements. Calculating the similarity between the error position distribution and any reference position distribution in the memory fault model includes: counting the number of first elements in the error position distribution that are different from the corresponding second elements to obtain the similarity; or counting the number of first elements in the error position distribution that are the same as the corresponding second elements to obtain the similarity.

[0203] In some examples, the error position distribution is represented by a first binary sequence, the first binary sequence includes a plurality of first data bits, and one first data bit is a first element. The reference position distribution is represented by a second binary sequence, the second binary sequence includes a plurality of second data bits, and one second data bit is a second element. The calculation subunit 7031 is used to calculate the Hamming distance between the first binary sequence and the second binary sequence.

[0204] Optionally, the output subunit 7032 is used to determine the risk level to which the possibility of UCE occurring in the memory belongs based on the distance interval to which the Hamming distance belongs and the correspondence between the distance interval and the risk level, wherein the correspondence includes N distance intervals and N risk levels, and different distance intervals correspond to different risk levels, where N is an integer and N is greater than 1.

[0205] In other examples, the error position distribution is represented by a first graph, the first graph includes a plurality of first units arranged in an array, the plurality of first units correspond one-to-one to a plurality of data bits, and each first unit is used to indicate whether a corresponding data bit is an error data bit. The reference position distribution is represented by a second graph, the second graph includes a plurality of second units arranged in an array, the plurality of second units correspond one-to-one to a plurality of first units. The calculation subunit 7031 is used to use the overlap between the first graph and the second graph as the similarity, the overlap is proportional to the number of first faulty units in the first graph that are in the same position as the second faulty unit in the second graph, the first faulty unit is a first unit indicating that the corresponding data bit is an error data bit, and the second faulty unit is a second unit indicating that the corresponding data bit is an error data bit.

[0206] Optionally, the calculation subunit 7031 is used to determine the degree of overlap based on the number of first fault units in the first graph that have the same position as the second fault unit in the second graph, and the number of second fault units in the second graph; or, determine the degree of overlap based on the number of first fault units in the first graph that have the same position as the second fault unit in the second graph, the relative positions of the first non-fault units in the first graph that have the same position as the second fault unit in the second graph and the first fault units in the second graph, and the number of second fault units in the second graph; or, determine the degree of overlap based on the number of overlapping units in the first graph and the number of first units in the first graph, the overlapping units including the first fault unit in the first graph that has the same position as the second fault unit in the second graph and the first non-fault unit in the first graph that has the same position as the second non-fault unit; or, determine the degree of overlap based on the number of overlapping units in the first graph and the second graph, the relative positions of the first non-fault units in the first graph that have the same position as the second fault unit in the second graph and the first fault units in the second graph, and the number of first units in the first graph.

[0207] Optionally, the output subunit 7032 is used to determine the risk level to which the possibility of UCE occurring in the memory belongs based on the overlap interval to which the overlap belongs and the correspondence between the overlap interval and the risk level, wherein the correspondence includes M overlap intervals and M risk levels, and different overlap intervals correspond to different risk levels, wherein M is an integer and is greater than 1.

[0208] In another possible implementation, the memory fault model is a neural network model, which is trained using first-category samples and second-category samples, the first-category samples being the error position distribution of the error correction unit corresponding to a memory in which only CE occurs when CE occurs, and the second-category samples being the error position distribution of the error correction unit corresponding to a memory in which UCE occurs when CE occurs before UCE occurs; the prediction unit 703 is used to process the error position distribution of the error correction unit using the neural network model to obtain a prediction result.

[0209] It should be noted that: when the memory fault prediction device provided in the above embodiment performs memory fault prediction, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the memory fault prediction device provided in the above embodiment and the memory fault prediction method embodiment belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0210] The division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0211] If the integrated module is implemented in the form of hardware, it can be implemented through a chip, a CPU, an ASIC, or a PLD).

[0212] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a terminal device (which can be a personal computer, mobile phone, or communication device, etc.) or a processor (processor) to execute all or part of the steps of the method of each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0213] The descriptions of the processes corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process, please refer to the relevant descriptions of other processes.

[0214] In an embodiment of the present application, a computer-readable storage medium is also provided, which stores computer instructions. When the computer instructions stored in the computer-readable storage medium are executed by a computer device, the computer device executes the memory failure prediction method provided above.

[0215] In an embodiment of the present application, a computer program product including instructions is also provided. When the computer program product is executed on a computer device, the computer device executes the memory failure prediction method provided above.

[0216] In an embodiment of the present application, a chip is further provided. The chip includes a processor and a power supply circuit. The power supply circuit is used to supply power to the processor. The processor is used to execute Figure 2 or Figure 4 or Figure 6 The memory failure prediction method is shown.

[0217] In some examples, the chip further includes a memory, in which computer instructions are stored, and the processor is used to execute the computer instructions stored in the memory to implement Figure 2 or Figure 4 or Figure 6 The memory failure prediction method is shown.

[0218] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meaning understood by persons of ordinary skill in the field to which this application belongs. The words "first", "second", "third" and similar terms used in the patent application specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not indicate a quantitative limitation, but rather indicate the existence of at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. The multiple involved in the embodiments of this application refers to two or more. A and / or B means that there are three situations: A; B; and A and B.

[0219] The above is only an embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A memory failure prediction method, characterized in that: include: Obtaining an error position distribution of an error correction unit associated with a memory, wherein the memory includes at least one memory cell, each of the memory cells includes a plurality of storage cells arranged in an array, the error correction unit includes a plurality of data bits obtained from a plurality of storage cells of the at least one memory cell by continuous burst reading, the plurality of data bits respectively corresponding to one storage cell among the plurality of storage cells of the at least one memory cell, the error position distribution is used to indicate a position of an error data bit in the plurality of data bits, and the error position distribution causes a correctable error CE to occur in the memory; Acquire a memory fault model, wherein the memory fault model includes at least one reference position distribution, and the reference position distribution is associated with an uncorrectable error (UCE) of the memory; According to the similarity between the error position distribution and at least one of the reference position distributions, a prediction result is output, where the prediction result is used to indicate the probability of UCE occurring in the memory.

2. The method according to claim 1, characterized in that: Outputting a prediction result according to the similarity between the error position distribution and at least one reference position distribution includes: respectively calculating the similarity between the error position distribution and each of the reference position distributions; outputting the prediction result according to the calculated similarity; or, Outputting a prediction result according to the similarity between the error position distribution and at least one reference position distribution includes: Calculating the similarity between the error position distribution and each reference position distribution in sequence; When the calculated similarity is higher than the similarity threshold, a prediction result is output according to the similarity higher than the similarity threshold.

3. The method according to claim 2, characterized in that The error position distribution is represented by a plurality of first elements, the plurality of first elements correspond to the plurality of data bits one by one, and each of the first elements is used to indicate whether a corresponding data bit is an error data bit; The reference position distribution is represented by a plurality of second elements, and the plurality of first elements correspond to the plurality of second elements in a one-to-one manner; Calculating the similarity between the error position distribution and any reference position distribution in the memory fault model includes: Counting the number of first elements in the error position distribution that are different from the corresponding second element to obtain the similarity; or, The number of first elements in the error position distribution that are identical to the corresponding second element is counted to obtain the similarity.

4. The method according to claim 3, characterized in that The error position distribution is represented by a first binary sequence, wherein the first binary sequence includes a plurality of first data bits, and one first data bit is one first element; The reference position distribution is represented by a second binary sequence, the second binary sequence includes a plurality of second data bits, and one second data bit is one second element; The counting of the number of first elements in the error position distribution that are different from the corresponding second element to obtain the similarity includes: A Hamming distance between the first binary sequence and the second binary sequence is calculated.

5. The method according to claim 2, characterized in that: The error position distribution is represented by a first graph, the first graph includes a plurality of first units arranged in an array, the plurality of first units correspond to the plurality of data bits one by one, and each of the first units is used to indicate whether a corresponding data bit is an error data bit; The reference position distribution is represented by a second graphic, wherein the second graphic includes a plurality of second units arranged in an array, and the plurality of second units correspond one-to-one to the plurality of first units; Calculating the similarity between the error position distribution and any reference position distribution in the memory fault model includes: The degree of overlap between the first graph and the second graph is taken as the similarity, and the degree of overlap is proportional to the number of first fault units in the first graph that have the same position as the second fault unit in the second graph, the first fault unit is a first unit indicating that the corresponding data bit is an erroneous data bit, and the second fault unit is a second unit indicating that the corresponding data bit is an erroneous data bit.

6. The method according to claim 5, characterized in that The taking the overlap degree between the first graphic and the second graphic as the similarity includes: determining the overlap degree according to the number of first faulty units in the first graph having the same position as the second faulty units in the second graph and the number of second faulty units in the second graph; or, Determine the overlap degree according to the number of first faulty units in the first graph having the same position as the second faulty unit in the second graph, the relative positions of the first non-faulty units in the first graph having the same position as the second faulty unit in the second graph and the first faulty unit in the second graph, and the number of second faulty units in the second graph; or, Determine the overlap degree according to the number of overlapped units in the first graph and the second graph and the number of first units in the first graph, wherein the overlapped units include the first faulty unit in the first graph having the same position as the second faulty unit in the second graph and the first non-faulty unit in the first graph having the same position as the second non-faulty unit in the second graph; or, The overlap degree is determined based on the number of overlapping units in the first graph and the second graph, the relative position of the first non-faulty unit in the first graph that is the same position as the second faulty unit in the second graph and the first faulty unit in the second graph, and the number of first units in the first graph.

7. The method according to claim 1, characterized in that The memory fault model is a neural network model, and the neural network model is trained by using the first type of samples and the second type of samples, wherein the first type of samples is the error position distribution of the error correction unit corresponding to the memory where only CE occurs when CE occurs, and the second type of samples is the error position distribution of the error correction unit corresponding to the memory where UCE occurs when CE occurs before UCE occurs; Outputting a prediction result according to the similarity between the error position distribution and at least one reference position distribution includes: The neural network model is used to process the error position distribution to obtain the prediction result.

8. A memory failure prediction device, characterized in that: include: A first acquisition unit is used to acquire an error position distribution of an error correction unit associated with a memory, wherein the memory includes at least one memory cell, each of the memory cells includes a plurality of storage cells arranged in an array, the error correction unit includes a plurality of data bits obtained from a plurality of storage cells of the at least one memory cell by continuous burst reading, the plurality of data bits respectively corresponding to one storage cell among the plurality of storage cells of the at least one memory cell, the error position distribution is used to indicate a position of an error data bit among the plurality of data bits, and the error position distribution causes a correctable error CE to occur in the memory; A second acquisition unit, configured to acquire a memory fault model, wherein the memory fault model includes at least one reference position distribution, and the reference position distribution is associated with an uncorrectable error UCE of the memory; The prediction unit is used to output a prediction result according to the similarity between the error position distribution and at least one reference position distribution, wherein the prediction result is used to indicate the probability of an uncorrectable error UCE occurring in the memory.

9. A chip, characterized in that: The chip comprises a logic circuit and a power supply circuit, the logic circuit is used to execute the method according to any one of claims 1 to 8, and the power supply circuit is used to supply power to the logic circuit.

10. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory is used to store a software program, and the processor runs or executes the software program stored in the memory so that the electronic device implements the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store program codes executed by a processor, wherein the program codes include instructions for implementing the method according to any one of claims 1 to 7.

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