Switching circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of integrated circuits, and discloses a switching circuit comprising a charging and discharging module which comprises an energy storage unit and a load unit, the first end of the energy storage unit is connected with an input signal, and the second end of the energy storage unit is connected with the first end of the load unit; the discharge module is connected in parallel with the energy storage unit, and the discharge module can absorb electric energy flowing to the energy storage element from a parasitic capacitor in the switching circuit in a conducting state; the reverse current detection module is connected with the second end of the energy storage unit and is used for detecting reverse current flowing to the energy storage unit from the load unit and outputting a first signal according to the state of the reverse current; and the logic module is connected with the output ends of the charging and discharging module and the reverse current detection module and the input end of the discharge module, and is used for performing logic operation on the at least one control signal and the first signal and controlling the on-off of the discharge module based on the result of the logic operation. According to the switching circuit, the ringing phenomenon of the switching circuit can be avoided.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a switching circuit, a chip and an electronic device. Background Art

[0002] A switching circuit is a power supply that maintains a stable output voltage or current by controlling the ratio of the time when the switch is turned on and off. A switching circuit is generally composed of a pulse width modulation (PWM) control circuit, an energy storage element (such as an inductor), and a switch. The input of a switching circuit is generally an AC power source (such as a mains), and the output end is generally a device that requires a DC power source, such as a personal computer. The switching circuit converts the voltage and current between the two.

[0003] At present, when an electronic device using a switching circuit is in a standby or dormant state, the load current of the switching circuit is reduced, and the electronic device will control the switching circuit to enter a discontinuous conduction mode (DCM) and reduce the switching frequency of the switching circuit. When the switching circuit enters the DCM mode, during the controlled shutdown period of the main switch of the switching circuit, the electric energy of the inductor may resonate with the parasitic capacitance of the main switch after the release is completed. This phenomenon can be called the ringing phenomenon. The inductor and capacitor oscillations generated by the ringing phenomenon make the electromagnetic interference problem of the switching circuit serious, and easily cause damage to the components of the switching circuit. Summary of the invention

[0004] Embodiments of the present application provide a switch circuit, a chip, and an electronic device.

[0005] In a first aspect, an embodiment of the present application provides a switching circuit, comprising: a charging and discharging module, comprising an energy storage unit and a load unit, wherein a first end of the energy storage unit is connected to an input signal of the switching circuit, and a second end of the energy storage unit is connected to a first end of the load unit, and the charging and discharging module can switch between a charging cycle and a discharging cycle under the control of at least one control signal; a discharge module, connected in parallel with the energy storage unit, and the discharge module can absorb the electric energy flowing from the parasitic capacitance in the switching circuit to the energy storage element in a conducting state; a reverse current detection module, connected to the second end of the energy storage unit, for detecting a reverse current flowing from the load unit to the energy storage unit, and outputting a first signal according to the state of the reverse current; a logic module, connected to the output end of the charging and discharging module, the reverse current detection module and the input end of the discharge module, for performing a logic operation on at least one control signal and the first signal, and controlling the on and off of the discharge module based on the result of the logic operation.

[0006] Exemplarily, in some embodiments of the present application, the energy storage unit may be, for example, an inductor. During the charging cycle, the charge and discharge module may charge the energy storage unit through an input signal. During the discharging cycle, the energy storage unit may discharge the load unit. After the energy storage unit is discharged, the parasitic capacitance in the device connected to the energy storage unit in the switching circuit may resonate with the energy storage unit, resulting in a ringing phenomenon. Therefore, after the energy storage unit is discharged, the electric energy flowing to the energy storage unit may be absorbed by the discharge module. For example, when the reverse current detection circuit detects the reverse current flowing from the load unit to the energy storage unit, it can be determined that the energy storage unit has been discharged, and the logic operation module can control the discharge module to open according to the operation result, thereby preventing the electric energy in the parasitic capacitance in other devices in the switching circuit from flowing to the inductor, so as to avoid the ringing phenomenon of the switching circuit.

[0007] In a possible implementation of the first aspect above, the charging and discharging module further includes a first switch and a second switch; the first end of the first switch is connected to the second end of the energy storage unit, the second end of the first switch is grounded, and the first switch is used to control the on-off state of the energy storage circuit of the energy storage unit; the first end of the second switch is connected to the second end of the energy storage unit, and the second end of the second switch is connected to the load unit; and at least one control signal includes a first control signal and a second control signal, and the first control signal and the second control signal are respectively used to control the on-off state of the first switch and the second switch.

[0008] In some embodiments, the first switch may be, for example, the first switch S1 mentioned below, the first control signal may be, for example, the PWM signal mentioned below, and the second switch may be, for example, the switch S2 mentioned below. Figure 4B In the embodiment, the corresponding switch S2), the second control signal is, for example, the VG signal hereinafter. In the charging cycle, the first control signal controls the first switch to be turned on, and the second control signal controls the second switch to be turned off, so that the charging and discharging module charges the energy storage unit. In the discharging cycle, the first signal controls the first switch to be turned off, and the second control signal controls the second switch to be turned on, so that the energy storage unit discharges to the load module. In the discharging cycle, if the energy storage unit is discharged, the second control signal can also control the second switch to be turned off to prevent the load module from inputting reverse current to the energy storage unit.

[0009] The state of the above-mentioned second control signal is determined according to the state of the first signal and the state of the first control signal; when the first control signal controls the first switch to be turned on, the second control signal controls the second switch to be turned off; when the first control signal controls the first switch to be turned off, and the state of the first signal corresponds to the absence of reverse current, the second control signal controls the second switch to be turned on; when the first control signal controls the first switch to be turned off, and the state of the first signal corresponds to the presence of reverse current, the second control signal controls the second switch to be turned off.

[0010] Exemplarily, in some embodiments, the first switch may be, for example, a field effect transistor (FET), the source of the first switch is grounded, the gate is connected to the PWM signal, and the drain is connected to the second end of the energy storage module. For example, the first switch is an N-type metal-oxide semiconductor (MOS) field effect transistor (NMOS for short), the gate of the first switch is connected to a high level (the VGS between the gate and the source of the first switch is a high level) to turn on, and is connected to a low level (the VGS between the gate and the source of the first switch is a low level) to turn off. The second switch is a P-type MOS tube (PMOS for short), the gate of the second switch is connected to a high level (the VGS between the gate and the source of the second switch is a high level) to turn off, and is connected to a low level (the VGS between the gate and the source of the second switch is a low level) to turn on. Therefore, when the first control signal is at a high level, the first switch is turned on, the second end of the energy storage unit is grounded, and the energy storage unit is charged by the input signal, the input signal may also be, for example, the input signal VDD hereinafter, and the second control signal is at a high level, controlling the second switch to turn off, so as to prevent the energy storage unit from outputting electrical energy to the load unit. When the first control signal is at a low level, the first switch is turned off, and the second control signal is at a low level, controlling the second switch to be turned on, the energy storage unit starts to discharge, and outputs an output signal to the load module. The output signal may also be, for example, the output voltage Vout mentioned below.

[0011] When the reverse current detection module detects a reverse current, the first signal outputted is a high level; when the reverse current detection module does not detect a reverse current, the first signal outputted is a low level; when the first control signal is a high level, the first switch is turned on, and when the first control signal is a low level, the first switch is turned off; when the second control signal is a high level, the second switch is turned off, and when the second signal is a low level, the second switch is turned on;

[0012] When the first control signal is at a high level, the second control signal is at a high level, and the first signal is at a low level, the logic module controls the discharge module to be turned off;

[0013] When the first control signal is at a low level, the second control signal is at a low level, and the first signal is at a low level, the logic module controls the discharge module to be turned off;

[0014] When the first control signal is at a low level, the second control signal is at a low level, and the first signal is at a high level, the logic module controls the discharge module to be turned off;

[0015] When the first control signal is at a low level, the second control signal is at a high level, and the first signal is at a low level, the logic module controls the discharge module to be turned on.

[0016] Exemplarily, in some embodiments of the present application, the first signal may be, for example, the Vz signal mentioned below. When the reverse current detection module detects a reverse current, a first signal may be issued. The logic module may perform a logic operation based on the first control signal, the second control signal, and the first signal to control the on and off of the discharge module. For example, the logic module may control the discharge module to be turned off during the process of charging the energy storage unit and discharging the energy storage unit. In the process from the end of the discharge of the energy storage unit to the next charging, the discharge module is controlled to be turned on to avoid the ringing phenomenon between the electric energy of the parasitic capacitance of other devices in the switching circuit and the energy storage unit after the discharge of the energy storage unit.

[0017] In a possible implementation of the first aspect, the logic module includes a logic control unit, a switch control unit, and a first field effect transistor;

[0018] The input end of the logic control unit is connected to the charge and discharge module and the reverse current detection module, and is used to obtain the input signal, the first control signal, the second control signal and the first signal of the switch circuit; the output end of the logic control unit is connected to the gate of the first field effect tube; the second end of the energy storage unit is the first node; the input end of the switch control unit is connected to the charge and discharge module, and is used to obtain the input signal and the first node signal of the first node part; the output end of the switch control unit is connected to the drain of the first field effect tube and the discharge circuit; the source of the first field effect tube is grounded.

[0019] In a possible implementation of the first aspect above, the logic control unit includes a first D flip-flop and a second D flip-flop; the input end of the first D flip-flop is connected to the first end of the energy storage unit, the clock end of the first D flip-flop is connected to the output end of the reverse current detection circuit, the reset end of the first D flip-flop is connected to the NOT gate and receives the first control signal, the output end of the first D flip-flop is connected to the reset end of the second D flip-flop, and outputs the first logic signal; the input end of the second D flip-flop is connected to the first end of the energy storage unit, the clock end of the second D flip-flop inputs the second control signal, the output end of the second D flip-flop is connected to the gate of the first field effect transistor and outputs the second logic signal.

[0020] In a possible implementation of the first aspect, the switch control unit includes a second field effect transistor, a third field effect transistor and a fourth field effect transistor; the drain of the second field effect transistor is connected to the first end of the energy storage unit, the source of the second field effect transistor is connected to the source of the third field effect transistor and the source of the fourth field effect transistor, and the gate of the second field effect transistor is connected to the first node; the drain of the third field effect transistor is the output end of the switch control unit, and the drain of the third field effect transistor is connected to the control end of the discharge module and the drain of the first field effect transistor, and the gate of the third field effect transistor is connected to the NOT gate and linked to the first control signal; the drain of the fourth field effect transistor is connected to the first node, and the gate of the fourth field effect transistor is connected to the first end of the energy storage unit.

[0021] In a possible implementation of the first aspect above, the discharge circuit includes a fifth field effect transistor, a sixth field effect transistor and a clamping diode; the drain of the fifth field effect transistor is connected to the first end of the energy storage unit, the source of the fifth field effect transistor is connected to the source of the sixth field effect transistor and the output end of the clamping diode, the gate of the fifth field effect transistor is connected to the gate of the sixth field effect transistor, the input end of the clamping diode, the output end of the switch control unit, and the drain of the first field effect transistor; the drain of the sixth field effect transistor is connected to the first node.

[0022] In a possible implementation of the first aspect above, the switching unit includes a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor; the drain of the seventh field effect transistor is connected to the first end of the energy storage unit, the gate of the seventh field effect transistor is connected to the first node and the gate of the eighth field effect transistor, and the source of the seventh field effect transistor is connected to the source of the eighth field effect transistor; the drain of the eighth field effect transistor is connected to the drain of the first field effect transistor and the drain of the ninth field effect transistor; the source of the ninth field effect transistor is connected to the source of the tenth field effect transistor, the gate of the ninth field effect transistor is connected to the gate of the tenth field effect transistor and the first end of the energy storage unit; and the drain of the tenth field effect transistor is connected to the first node.

[0023] In a possible implementation of the first aspect above, the charging and discharging module also includes a driving module, wherein a first output end of the driving module is connected to a control end of the first switch, and is used to output a first control signal to the first switch; a second output end of the driving module is connected to a control end of the second switch, and is used to output a second control signal to the second switch; and an input end of the driving module is connected to an output end of the reverse current detection circuit.

[0024] In some embodiments of the present application, the driving module can output a first control signal to the first switch to control the on and off of the first switch, and output a second control signal to the second switch to control the on and off of the second switch. It can be understood that during the charging process, the driving module can control the first switch to be turned on and the second switch to be turned off. During the discharge process, the driving module can drive the first switch to be turned off and control the second switch to be turned on. In addition, at the end of the discharge, when the driving module determines that there is a reverse current based on the first signal output by the reverse current detection module, the driving module can control the second switch to be turned off to avoid the reverse current from affecting the switching circuit.

[0025] In a second aspect, an embodiment of the present application provides a chip, which includes a switching circuit provided by the above-mentioned first aspect and various possible implementations of the first aspect.

[0026] In a third aspect, an embodiment of the present application provides an electronic device, including a switching circuit provided by the above-mentioned first aspect and various possible implementations of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A switching circuit of a switching DC boost type is shown;

[0028] Figure 2 A switch circuit connected to a magnetic bead is shown;

[0029] Figure 3 A circuit diagram showing a switch circuit controlling ringing through a ringing suppression resistor;

[0030] Figure 4A According to some embodiments of the present application, a schematic diagram of a switch circuit is shown;

[0031] Figure 4B According to some embodiments of the present application, a structural schematic diagram of a switch circuit is shown;

[0032] Figure 5 According to some embodiments of the present application, a partial circuit diagram of a switch circuit is shown;

[0033] Figure 6 According to some embodiments of the present application, a control signal waveform diagram of a switch circuit is shown;

[0034] Figure 7 According to some embodiments of the present application, a circuit diagram of another switch control unit is shown. DETAILED DESCRIPTION

[0035] Illustrative embodiments of the present application include, but are not limited to, switching circuits and electronic devices.

[0036] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0037] For example, Figure 1 A switching circuit of a DC boost type is shown.

[0038] like Figure 1 As shown, the switch circuit may include an inductor L1 , a first switch S1 , a freewheeling diode D1 , a first capacitor Cout and a load module Rload.

[0039] The switch circuit is connected to the input signal VDD.

[0040] The first switch S1 is connected to a PWM signal, and the PWM signal controls the first switch S1 to be turned on and off. When the PWM signal controls the first switch S1 to be turned on, the first end of the inductor L1 is connected to the input signal VDD, and the second end is grounded, thereby starting to charge. When the PWM signal controls the first switch S1 to be turned off, the inductor L1 starts to discharge, so that the switch circuit outputs an output voltage Vout, thereby supplying power to the load Rload.

[0041] A first end of the freewheeling diode D1 is connected to the second end of the inductor L1 , and a second end of the freewheeling diode D1 is connected to the load Rload, so as to prevent the current of the load Rload from flowing back into the inductor L1 .

[0042] When the current of the load Rload is relatively small or there is no current, for example, when the electronic device enters standby or sleep mode, the switch circuit generally reduces the operating frequency and enters the discontinuous conduction mode DCM mode. In DCM mode, the smaller the current of the load Rload is, the lower the operating frequency is. At this time, serious inductor (Inductor, L) and capacitor (Capacity, C) oscillation may occur at the connection point SW between the inductor L1 and the main switch S1, resulting in ringing phenomenon, which in turn causes serious electromagnetic interference (EMI) problems.

[0043] In order to solve the above problem, in some embodiments, a magnetic bead is usually connected to the switch circuit to suppress the ringing phenomenon.

[0044] For example, Figure 2 A switch circuit connected to a magnetic bead is shown.

[0045] like Figure 2 As shown, Figure 1 The difference from the embodiment is that in this embodiment, a magnetic bead L2 is connected in series between the input end of the switch circuit and the inductor L1. The magnetic bead L2 is a high-frequency filter device, which is mainly used in the field of electromagnetic compatibility to solve some electromagnetic interference problems. For high-frequency signals, the magnetic bead L2 presents a very high impedance when applied to the line; and for low-frequency signals, the magnetic bead L2 presents a very low impedance. Therefore, when ringing occurs in the switch circuit, the magnetic bead L2 can behave as a resistor and absorb the ringing energy to a large extent.

[0046] However, adding magnetic beads L2 to the switch circuit will increase system costs. Since magnetic beads L2 are large in size and cannot be installed on the chip of the switch circuit, adding magnetic beads L2 will increase the number of peripheral devices and cause the switch to be larger in size. And when the parameters of magnetic beads L2 are not set properly, it may cause abnormalities such as howling of system devices, that is, oscillations that fall into the audio range of 20Hz-20kHz.

[0047] In some other embodiments, the ringing phenomenon of the switching circuit is suppressed by connecting a ringing suppression resistor in parallel to the inductance of the switching circuit.

[0048] For example, Figure 3 A circuit diagram showing a switch circuit controlling ringing through a ringing suppression resistor.

[0049] like Figure 3 As shown, Figure 1 The difference between the embodiments is that the switch circuit has a discharge module 301 for releasing ringing energy and a detection control module 302 for detecting whether a ringing phenomenon occurs in the switch circuit connected in parallel at both ends of the inductor L1.

[0050] The discharge module 301 includes a first switch S2 and a ringing suppression resistor Ring connected in parallel with the inductor L1. The first switch S2 and the ringing suppression resistor Ring are connected in series.

[0051] When the detection control module 302 detects that the switch circuit has a ringing phenomenon, it controls the first switch S2 to close, so that the inductor L1 and the ringing suppression resistor Ring form a path, and the ringing suppression resistor Ring absorbs the ringing energy to avoid the ringing phenomenon.

[0052] However, in the above circuit, the detection control module 302 controls the on and off of the switch S2 through the input signal VDD and the voltage of the SW node. When the voltage difference between the input signal VDD and the SW node is large, for example, the voltage difference between the two is greater than 10V, if the first switch S1 uses a MOSFET tube, the gate voltage changes in a large range, which can easily damage the components of the first switch S1. Therefore, the detection control module 302 that controls the closing of the first switch S1 needs to perform a complex level conversion operation, which makes the switch circuit have more components and consumes more power.

[0053] In order to solve the above problems, the present application proposes a switching circuit, including a charging and discharging module, a discharge module, a reverse current detection module and a logic module. The charging and discharging module includes an energy storage unit and a load unit, and the charging module can switch between a charging cycle and a discharging cycle based on at least one control signal. The reverse current detection module can measure the reverse current flowing from the load unit to the energy storage unit, and output a first signal according to the state of the reverse current. The logic module can control the conduction and shutdown of the discharge module according to at least one control signal and the first signal. The discharge module is connected to the energy storage unit, and before the energy storage unit is discharged and charged, the discharge circuit can absorb the electric energy flowing from the parasitic capacitance in the switching circuit to the energy storage element.

[0054] Through the present application, during the charging and discharging process of the energy storage unit, the logic module can control the discharge module to be in a closed state through at least one control signal and the first signal, so as not to affect the normal operation of the switch circuit. When the energy storage unit has released the electric energy but has not yet been charged for the next time, the logic module can control the discharge module to turn on, thereby absorbing the electric energy flowing to the energy storage unit in the switch circuit, and avoiding the ringing phenomenon in the switch circuit. Therefore, the embodiment of the present application does not need to detect whether the switch circuit has a ringing phenomenon, and does not need to perform complex circuit conversion operations, thereby reducing the components of the switch circuit and reducing the power consumption of the switch circuit.

[0055] The switch circuit in this application is described in detail below.

[0056] For example, Figure 4A According to some embodiments of the present application, a schematic diagram of a switch circuit is shown.

[0057] like Figure 4A As shown, the switch circuit includes:

[0058] The charging and discharging module includes an energy storage unit and a load unit. The charging and discharging module can switch between a charging cycle and a discharging cycle under the control of at least one control signal; in the charging cycle, the power supply of the switching circuit can charge the energy storage unit, and in the discharging cycle, the energy storage unit can supply power to the load unit.

[0059] The discharge module is connected to the energy storage unit. When the discharge module is in the on state, it can absorb the electric energy flowing from the parasitic capacitance in the switch circuit to the energy storage element.

[0060] The reverse current detection module is used to detect the reverse current flowing from the load unit to the energy storage unit, and output a first signal according to the state of the reverse current.

[0061] The logic module is used to perform a logic operation on at least one control signal and the first signal, and control the on and off of the discharge module based on the result of the logic operation.

[0062] In some embodiments of the present application, during the charging and discharging process of the energy storage unit of the charging and discharging module, the logic module can control the discharge module to shut down according to the control signal in the charging and discharging module and the first signal sent by the reverse current detection module to ensure the normal operation of the energy storage unit. After the energy storage unit is discharged and before the next charging. The reverse current detection module can detect the reverse current flowing from the load unit to the energy storage unit and change the state of the first signal. The logic module performs logical operations according to the state of the control signal of the charging and discharging module during the discharge cycle and the state of the first signal, and controls the discharge circuit to be turned on, so as to absorb the electric energy flowing from the parasitic capacitors in other devices in the switching circuit to the energy storage unit through the discharge circuit, thereby avoiding resonance between the energy storage unit and the parasitic capacitor, and avoiding the occurrence of ringing phenomenon.

[0063] The switch circuit in the embodiment of the present application is introduced below by taking a boost switch circuit as an example. In the boost switch circuit, the output voltage of the switch circuit is greater than the input voltage.

[0064] For example, Figure 4B According to an embodiment of the present application, a structural schematic diagram of a switch circuit is shown.

[0065] like Figure 4B As shown, the energy storage unit may be, for example, an inductor L1 , and the load unit may include, for example, an output capacitor Cout and a load resistor Rload.

[0066] like Figure 4B As shown, the charge and discharge module of the switch circuit further includes a first switch S1, a second switch S2, and a driving module 404, wherein the first switch S1 and the second switch S2 are, for example, field effect transistors.

[0067] The first switch S1 is used to control the on-off state of the energy storage circuit of the energy storage unit, and the second switch S2 is used to control the on-off state of the connection circuit between the energy storage unit and the load unit.

[0068] A first end of the inductor L1 is connected to the input signal VDD, and a second end of the inductor L1 is connected to the drain of the first switch and the drain of the second switch.

[0069] The gate of the first switch is connected to the driving module 404, and the driving module 404 inputs a PWM signal (as a first control signal) to the gate of the first switch. The source of the first switch is grounded, and the PWM signal is used to control the on and off of the first switch S1. The portion between the second end of the inductor L1 and the first end of the first switch S1 is called a first node, and the first node has a first node signal SW.

[0070] The gate of the second switch is connected to the driving module 404, and the driving module 404 inputs a VG signal (as a second control signal) to the gate of the second switch. The source of the second switch is connected to the load unit, and the VG signal is used to control the on and off of the second switch.

[0071] The discharge module 401 is connected in parallel with the resistor L1, and the discharge module 401 includes a third switch S3 and a ringing-off resistor Ring. The first end of the third switch S3 is connected to the first end of the inductor L1, and the second end of the switch S3 is connected to the first end of the ringing-off resistor Ring. The second end of the ringing-off resistor Ring is connected to the second end of the inductor L1.

[0072] The reverse current detection module 403 can be connected to the first node, for example, to detect the reverse current flowing from the load unit to the energy storage unit. The reverse current detection module 403 is connected to the driving module 404 and inputs a Vz signal (as a first signal) to the driving module 404.

[0073] The logic module 402 may receive at least one control signal (for example, including a first control signal and a second control signal), an input signal VDD, a first signal Vz, a first control signal PWM, a second control signal VG, a first node signal SW, and a preference PWM_N opposite to the first control signal PWM. The logic module 402 may, for example, be connected to the discharge module 401, so as to control the on and off of the third switch S3 of the discharge module 401 based on the logic operation result.

[0074] like Figure 4B As shown, in some embodiments, the state of the second control signal VG is determined according to the state of the first signal Vz and the state of the first control signal PWM. For example, when the inductor L1 is charged, the driving module 404 controls the first switch S1 to turn on through the PWM signal, and controls the second switch S2 to turn off through the VG signal. Thus, the first end of the inductor L1 receives the input signal VDD, and the second end is grounded to form a loop, and the input signal VDD charges the inductor L1.

[0075] When the inductor L1 is discharged, the driving module 404 controls the first switch S1 to be turned off through the PWM signal, and controls the second switch S2 to be turned on through the VG signal. As a result, the second end of the inductor L1 is connected to the load unit, thereby providing electrical energy to the load unit. During the period when the inductor L1 provides electrical energy to the load unit, the current flows from the inductor L1 to the load unit, so the reverse current detection module 403 will not detect the reverse current. The Vz signal output by the reverse current detection module 403 to the driving module 404 will not indicate that the VG signal output by the driving module 404 controls the second switch S2 to be turned off.

[0076] When the inductor L1 finishes discharging, the first switch S1 is still in the off state. Since the inductor L1 has released all the electric energy, the voltage of the load unit is high (for example, the voltage generated by the input capacitor Cout is high), and a reverse current will flow from the load unit to the energy storage unit in the switch circuit. After the reverse current detection module 403 detects the reverse current, the Vz signal output to the driving module 404 indicates that the VG signal output by the driving module 404 controls the second switch S2 to be turned off.

[0077] like Figure 4B As shown, the first switch S1 can be, for example, an NMOS transistor. The source of the first switch S1 is grounded, so the gate of the first switch S1 enters the on state when a high level is input, and enters the off state when a low level is input.

[0078] The second switch S2 may be a PMOS tube, for example, the drain of the second switch S2 is connected to the second end of the inductor L1, and the source is a load unit. The switch S2 may be turned on when the gate receives a low level and turned off when the gate receives a high level.

[0079] When the reverse current detection module 403 does not detect the reverse current flowing from the load unit to the inductor L1 , the Vz signal output to the driving module 404 is at a low level. When the reverse current is detected, the Vz signal output to the driving module 404 is at a high level.

[0080] It can be understood that when the PWM signal is at a high level, the first switch S1 is controlled to be turned on, and the second end of the inductor L1 is grounded. In addition, the VG signal output by the driving module 404 is also at a high level, and the second switch S2 is controlled to be turned off. The reverse current detection module 403 does not detect the reverse current, and the output Vz signal is at a low level. At this time, the input signal VDD charges the inductor L1, and the first node signal SW at the first node is 0 voltage. In addition, the logic module 402 controls the third switch S3 of the discharge module 401 to be turned off based on the PWM signal, the PWM_N signal, the Vz signal, and the VG signal, and the discharge module 401 does not work.

[0081] When the PWM signal is at a low level and the inductor L1 is in the discharge stage, the first switch S1 is controlled to be turned off, the VG signal output by the driving module 404 is at a low level, the second switch S2 is controlled to be turned on, and the inductor L1 releases the stored electric energy to charge the load unit. At this time, the SW node voltage at SW is the output signal Vout. In addition, during the discharge process of the inductor L1, the reverse current detection module still does not detect the reverse current, and the Vz signal is at a low level. The logic module 402 controls the third switch S3 of the discharge module 401 to be turned off based on the PWM signal, the PWM_N signal, the Vz signal, and the VG signal, and the discharge module 401 does not work.

[0082] When the PWM signal is at a low level and the discharge of the inductor L1 is completed, the first switch S1 is controlled to be turned off, the VG signal output by the driving module 404 is at a low level, and the second switch S2 is controlled to be turned on. After the inductor L1 releases the electric energy, the output voltage Vout of the load unit is high, and there may be a reverse current flowing from the load unit to the inductor L1 in the switch circuit. At this time, the reverse current detection module 403 detects the reverse current, and the output Vz signal rises to a high level. At this time, the SW node voltage at SW is the output signal Vout. The logic module 402 controls the third switch S3 of the discharge module 401 to be turned off based on the PWM signal, the PWM_N signal, the Vz signal and the VG signal, and the discharge module 401 does not work.

[0083] When the PWM signal is at a low level and the discharge of the inductor L1 is completed, the first switch S1 is controlled to be turned off, and the driving module 404 receives the high-level Vz signal and controls the VG signal to be raised to a high level, thereby controlling the second switch S2 to be turned off. The logic module 402 controls the third switch S3 of the discharge module 401 to be turned on based on the PWM signal, the PWM_N signal, the Vz signal and the VG signal. The discharge module 401 is connected in parallel with the inductor L1 to absorb the electric energy flowing to the inductor L1. At this time, the SW node voltage at SW is the output signal Vout.

[0084] The following is an introduction to the logic modules in the embodiments of the present application.

[0085] For example, Figure 5 According to an embodiment of the present application, a partial circuit diagram of a switch circuit is shown.

[0086] like Figure 5 As shown, the logic module 402 includes a logic control unit, a switch control unit and a first field effect transistor.

[0087] The input end of the logic control unit is connected to the input signal VDD, the first signal Vz, the first control signal PWM and the second control signal VDD. The output end of the logic control unit is connected to the gate of the first field effect transistor MN1.

[0088] The input end of the switch control unit includes an input signal VDD, a first node signal SW and a PWM_N signal opposite to the first control signal. The output end of the switch control unit is connected to the drain of the first field effect transistor MN1 and the discharge module 401 .

[0089] The source of the first field effect transistor MN1 is grounded.

[0090] Exemplarily, in some embodiments of the present application, the first field effect transistor MN1 is, for example, an NMOS transistor, that is, the first field effect transistor MN1 is turned on when the VGS is at a high level, and since the source of the first field effect transistor MN1 is grounded, the gate of the first field effect transistor MN1 is turned on when the high level is connected. In some embodiments of the present application, the voltage of the part where the drain of the first field effect transistor MN1 is connected to the switch control unit is the VP_gate signal, and the VP_gate signal (as the third control signal) is used to control the on and off of the discharge module 401. It can be understood that when the first field effect transistor MN1 is turned on, the VP_gate signal is 0 (the first field effect transistor is turned on, the drain and the source are connected to the ground). Therefore, when the VP_gate signal output by the switch control unit is a high level and the first field effect transistor MN1 is turned off, the discharge module 401 can receive a high level VP_gate signal.

[0091] In some embodiments, the logic control unit includes a first D flip-flop and a second D flip-flop;

[0092] An input signal is input to an input terminal of the first D flip-flop, a first signal is input to a clock terminal of the first D flip-flop, a first control signal is input to a reset terminal of the first D flip-flop, an output terminal of the first D flip-flop is connected to a reset terminal of the second D flip-flop, and a first logic signal is output;

[0093] The input terminal of the second D flip-flop inputs an input signal, the clock terminal of the second D flip-flop inputs a second control signal, the reset terminal of the second D flip-flop is connected to the NOT gate and receives the first logic signal, and the output terminal of the second D flip-flop is connected to the gate of the first field effect transistor and outputs the second logic signal.

[0094] Exemplarily, the first D flip-flop and the second D flip-flop are both D flip-flops triggered along the rising edge. In an embodiment of the present application, the D flip-flop includes an input terminal D, an output terminal Q, a clock terminal CLK, and a reset terminal R (or a reset terminal R_N). The D flip-flop can store a signal input by the input terminal D, and when the signal of the clock terminal CLK is on the rising edge (for example, rising from a low level to a high level), the signal output by the output terminal Q of the D flip-flop is the signal input by the current input terminal D. At other times, the signal output by the output terminal Q of the D flip-flop remains unchanged (for example, the input signal of the input terminal D changes, and the output signal of the output terminal D remains unchanged). The reset terminal R of the D flip-flop is triggered when the reset terminal R of the D flip-flop is connected to a low level, and the output terminal Q of the D flip-flop outputs a low level. In some embodiments, the reset terminal R of the D flip-flop can also be connected to an inverter. For example, the reset terminal R_N of the first D flip-flop, when R_N receives a high level, the first D flip-flop is reset, and the output terminal Q1 of the first D flip-flop outputs a low level.

[0095] like Figure 5 As shown, the input terminal D of the first D flip-flop is connected to the input signal VDD, the clock terminal CLK inputs the first signal Vz, the reset terminal R_N inputs the first control signal PWM, the output terminal Q is connected to the reset terminal R of the second D flip-flop, and outputs the first logic signal q1.

[0096] The input terminal D of the second D flip-flop is connected to the input signal VDD, the clock terminal CLK inputs the second control signal VG, the reset terminal R is connected to the NOT gate and receives the first logic signal q1, the output terminal Q1 is connected to the gate of the first field effect transistor MN1 and outputs the second logic signal q2.

[0097] Continue to refer to Figure 5 In some embodiments, the switch control unit includes a second field effect transistor MP1, a third field effect transistor MP2, and a fourth field effect transistor MP3.

[0098] The drain of the second field effect transistor MP1 receives the input signal, the source of the second field effect transistor MP1 is connected to the source of the third field effect transistor MP2 and the source of the fourth field effect transistor MP3, and the gate of the second field effect transistor MP1 is connected to the first node signal.

[0099] The drain of the third field effect transistor MP2 is the output end of the switch control unit, and the drain of the third field effect transistor MP2 is connected to the control end of the discharge module 401 and the drain of the first field effect transistor NM1, and the gate of the third field effect transistor MP2 is connected to the NOT gate and linked to the first control signal PWM, that is, the PWM_M signal; the drain of the fourth field effect transistor MP3 is connected to the first node signal SW, and the gate of the fourth field effect transistor MP3 receives the input signal.

[0100] In some embodiments of the present application, the second field effect transistor MP1, the third field effect transistor MP2, and the fourth field effect transistor MP3 can be, for example, PMOS transistors. That is, the second field effect transistor MP1, the third field effect transistor MP2, and the fourth field effect transistor MP3 are turned on when the gate is connected to a low level so that VGS is at a low level; and are turned off when the gate is connected to a high level so that VGS is at a high level. In addition, there is a parasitic diode inside the second field effect transistor MP1, the third field effect transistor MP2, and the fourth field effect transistor MP3, and the parasitic diode points from the drain to the source. That is to say, the second field effect transistor MP1, the third field effect transistor MP2, and the fourth field effect transistor MP3 can be turned on when the drain voltage is at a high level and the source voltage is at a low level.

[0101] Continue to refer to Figure 5 In some embodiments, the discharge circuit 401 includes a fifth field effect transistor MP4, a sixth field effect transistor MP5, and a clamping diode ZD1.

[0102] The drain of the fifth field effect transistor MP4 is connected to the input signal VDD, the source of the fifth field effect transistor MP4 is connected to the source of the sixth field effect transistor MP5 and the output end of the clamping diode ZD1, and the gate of the fifth field effect transistor MP4 is connected to the gate of the sixth field effect transistor MP5, the input end of the clamping diode ZD1, the output end of the switch control unit, and the drain of the first field effect transistor MN1.

[0103] The drain of the sixth field effect transistor is connected to the first node MP5.

[0104] Exemplarily, in some embodiments of the present application, the fifth field effect transistor MP4 and the sixth field effect transistor MP5 can be used as the third switch S3. The ringing resistor Ring can be, for example, a resistor inside the fifth field effect transistor MP4 and the sixth field effect transistor MP5. The clamping diode ZD1 is used to control the voltage difference between the source and the gate of the fifth field effect transistor MP4 and the sixth field effect transistor MP5. For example, the control voltage difference will not exceed 5V to avoid damage to the fifth field effect transistor MP4 and the sixth field effect transistor MP5 due to excessive voltage difference between the source and the gate. In addition, when the gate voltage of the fifth field effect transistor MP4 (or the sixth field effect transistor MP5) is higher than the source voltage, the clamping diode can balance the voltage between the gate and the source. When the gate voltage of the fifth field effect transistor MP4 (or the sixth field effect transistor MP5) is lower than the source voltage, the clamping diode ZD1 can maintain the voltage difference between the gate and the source.

[0105] In some embodiments of the present application, the fifth field effect transistor MP4 and the sixth field effect transistor MP5 can be, for example, PMOS transistors. That is, the fifth field effect transistor MP4 and the sixth field effect transistor MP5 are turned on when VGS is at a low level; and are turned off when the gate is connected to a high level so that VGS is at a high level. In addition, there is a parasitic diode inside the fifth field effect transistor MP4 and the sixth field effect transistor MP5, and the parasitic diode points from the drain to the source. That is, the fifth field effect transistor MP4 and the sixth field effect transistor MP5 can be turned on when the drain voltage is at a high level and the source voltage is at a low level.

[0106] The following describes a process in which a logic module controls the discharge module to be turned on and off in an embodiment of the present application.

[0107] For example, Figure 6 According to an embodiment of the present application, a control signal waveform diagram of a switch circuit is shown.

[0108] like Figure 6 As shown, the waveform diagram includes a first control signal PWM, a second control signal VG, an inductor current IL of the inductor L1, a first signal Vz, a third control signal VP_gate signal, and a SW signal.

[0109] The first control signal PWM has a charging cycle and a discharging cycle. For example, a cycle in which the PWM signal outputs a high level is a charging cycle, and a cycle in which the PWM signal outputs a low level is a discharging cycle.

[0110] In the charging cycle, the second control signal VG is at a high level, thereby controlling the second switch S2 to be turned off to charge the inductor L1. In the discharging cycle, during the discharge of the inductor L1, the second control signal VG is at a low level, controlling the second switch S2 to be turned on, so that the inductor L1 is discharged. After the discharge of the inductor L1 is completed, the reverse current detection module 403 detects the reverse current, and the second control signal VG rises to a high level, controlling the second switch S2 to be turned off.

[0111] For example, the inductor L1 can be charged during a charging period of the first control signal PWM to increase the inductor current IL, and can release electrical energy during a discharging period of the first control signal PWM to reduce the inductor current IL.

[0112] The first signal Vz is a signal sent when the reverse current detection module 403 detects the presence of reverse current in the switch circuit. For example, after the inductor current IL is fully released, the output voltage Vout may be greater than the input signal VDD to generate a reverse current, and the Vz signal generated by the reverse current detection module 403 outputs a high level. When the reverse current detection module 403 does not detect a reverse current, the output first signal Vz is a low level.

[0113] The third control signal VP_gate is a control signal of the third switch S3, and is used to control the on and off of the third switch S3. In the charging cycle, the VP_gate signal output by the switch control unit is equal to the input signal VDD. In the discharge cycle, during the discharge process of the inductor L1, the VP_gate signal output by the switch unit is equal to the output signal Vout. After the discharge of the inductor L1 is completed, the VP_gate signal is 0 because the first field effect transistor MN1 is turned on.

[0114] The first node signal SW is the connection node between the second end of the inductor L1 and the first switch. When the switch circuit generates a ringing phenomenon, the first node signal SW will oscillate. In an embodiment of the present application, during the charging cycle, the first node signal SW is 0 (the first switch is turned on and the first node is grounded). During the discharge cycle, the first node signal SW is equal to the output signal Vout. At the end of the discharge, since the discharge module 401 is turned on, the electric energy flowing from other devices to the inductor L1 can be absorbed, and the discharge module 401 short-circuits the inductor L1. At this time, the first node signal SW is equal to the input signal VDD.

[0115] Next, combine Figure 4B-Figure 6 The following is a flow chart showing the implementation of the ringing suppression module 430 for suppressing the ringing phenomenon.

[0116] Reference Figure 4B-Figure 6In the charging cycle, the PWM signal outputs a high level, the first switch S1 is turned on, the VG signal is a high level, and the second switch S2 is turned off. At this time, the second end of the inductor L1 is grounded, the current flowing through the inductor L1 increases, the inductor L1 starts to store energy, the inductor current IL rises, and the first node is grounded, and the SW signal is 0 (low level). Since the second switch S2 is turned off, there is no reverse current in the switch circuit, so the Vz signal is a low level.

[0117] The drain of the second FET MP1 is connected to the input signal VDD, the gate is connected to the SW signal 0, and the source has no signal input. Since the input signal VDD connected to the drain of MP1 is high level, the second FET MP1 can be turned on through the internal parasitic diode, so that the source outputs the signal VDD.

[0118] The source of the fourth field effect transistor MP3 is connected to the VDD signal, the gate is also connected to the VDD signal, the gate-source voltage difference (VGS) of the fourth field effect transistor MP3 is 0, and therefore the fourth field effect transistor MP3 enters the off state.

[0119] The gate of the third field effect tube MP2 is connected to the PWM_N signal, and the PWM_N signal is low when the PWM signal outputs a high level. The source of the third field effect tube MP2 is connected to the VDD signal, so the VGS of the third field effect tube MP2 is low, and the third field effect tube MP2 enters the on state.

[0120] The PWM signal input to the reset terminal R_N of the first D flip-flop is at a high level, so the first D flip-flop is in a reset state (since the reset terminal R_N of the first D flip-flop is connected to a NOT gate, the high level input to the reset terminal R_N of the first D flip-flop is converted to a low level, triggering a reset), the first D flip-flop is reset, and the q1 signal output from the output terminal Q is at a low level. The q1 signal input to the reset terminal R of the second D flip-flop is at a low level, so the second D flip-flop is in a reset state, and the q2 signal output at the output terminal Q1 is at a low level.

[0121] At this time, the second field effect transistor MP1 and the third field effect transistor MP2 are turned on, the fourth field effect transistor MP3 is turned off, and the switch control unit outputs the VDD signal (the drain of the third field effect transistor MP2 outputs the VDD signal). The gate of the switch MN1 is connected to the q2 signal at a low level, and the voltage connected to the source is 0, so the VGS of the switch MN1 is at a low level, and the switch MN1 enters the off state, and VP_gate = VDD at this time.

[0122] The VP_gate connected to the gates of the fifth field effect transistor MP4 and the sixth field effect transistor MP5 is at a high level. Due to the effect of the clamping diode ZD1, the source signal of the fifth field effect transistor MP4 and the sixth field effect transistor MP5 is also VP_gate, that is, the source and the gate are the same, and VGS is 0. Therefore, the fifth field effect transistor MP4 and the sixth field effect transistor MP5 are in the off state, and the discharge module 401 does not work.

[0123] Continue to refer to Figure 4B-Figure 6 In the discharge cycle, the PWM signal input is low level, the first switch S1 is in the off state, the VG signal is low level, the second switch S2 is turned on, the inductor L1 discharges to the load unit, and the output signal Vout increases. At this time, the SW signal is equal to the output signal Vout (the second switch S2 is turned on, and the first node is connected to the load unit).

[0124] The SW node voltage input to the gate of the second field effect transistor MP1 is equal to the output signal Vout, and the drain input has the input signal VDD. At this time, the source signal of the second field effect transistor MP1 is first considered to be low level, so the source signal of the fourth field effect transistor MP3 is also low level, and the gate of the fourth field effect transistor is connected to the input signal VDD, so the VGS of the fourth field effect transistor MP3 is high level, and the fourth field effect transistor MP3 cannot be turned on through the gate. However, the SW signal input to the drain of the fourth field effect transistor MP3 is equal to the output signal Vout. In the boost switch circuit, the Vout signal is greater than VDD, so. The fourth field effect transistor MP3 can be turned on through the internal parasitic diode. In other words, the source output of the fourth field effect transistor MP3 has a SW signal. At this time, the source of the second field effect transistor MP1 receives the SW signal, the gate is also a SW signal, and the drain receives the VDD signal. The VDD signal is less than the SW signal, so the second field effect transistor MP1 is turned off.

[0125] At this time, the PWM signal outputs a low level, the PWM_N signal connected to the gate of the third field effect transistor MP2 is a high level, and the source is connected to the output voltage Vout is a high level. The size of the PWM signal can be set so that the PWM_N signal is smaller than the output voltage Vout, so that the VGS of the third field effect transistor MP2 is a low level, and the third field effect transistor MP2 is in a conducting state.

[0126] The PWM signal input to the reset terminal R_N of the first D flip-flop is at a low level, so the first D flip-flop is in a normal working state. Since the input signal Vz of the clock terminal CLK of the first D flip-flop always remains at a low level, the q1 signal output from the output terminal D of the first D flip-flop remains at a low level. The q1 signal connected to the reset terminal R of the second D flip-flop is at a low level. Therefore, the second D flip-flop is in a reset state, and the q2 signal output from the output terminal Q1 of the second D flip-flop is still at a low level.

[0127] Since the second field effect transistor MP1 is turned off, and the third field effect transistor MP2 and the fourth field effect transistor MP3 are turned on, the switch control unit outputs a SW signal, that is, the output signal Vout. At this time, the q2 signal connected to the gate of the first field effect transistor MN1 is at a low level, and the source voltage is 0, so the VGS of the first field effect transistor MN1 is at a low level, and the switch MN1 is turned off, so that the VP_gate signal is equal to the output signal Vout.

[0128] The gate input VP_gate voltage of the fifth field effect transistor MP4 and the sixth field effect transistor MP5 is at a high level. Due to the same reason as the above charging process, the fifth field effect transistor MP4 and the sixth field effect transistor MP5 are turned off, and the discharge module 401 does not work.

[0129] Continue to refer to Figure 4B-Figure 6 In the discharge cycle, when the inductor L1 finishes discharging, the output signal Vout is greater than the input signal VDD, so the reverse current detection module 403 detects the reverse current, and the output Vz signal rises to a high level. In addition, the drive module 404 outputs a VG signal that also rises to a high level to control the second switch S2 to enter the off state, the PWM signal is at a low level, and the first switch S1 continues to be in the off state.

[0130] At this time, the PWM signal input to the reset terminal R_N of the first D flip-flop is at a low level, and the first D flip-flop is in a normal working state. The signal VDD at the input terminal D of the first D flip-flop is at a high level, and the signal Vz at the clock terminal CLK rises to a high level, so the q1 signal outputted by the output terminal Q of the first D flip-flop is the same as the input signal VDD at the input terminal D, both of which are at a high level. The q1 signal connected to the reset terminal R of the second D flip-flop is at a high level, so the second D flip-flop is not reset and is in a normal working state. After receiving the high-level Vz signal, the output VG signal of the driving module 404 rises from a low level to a high level, and controls the second switch S2 to turn off. At this time, the second D flip-flop is triggered at the rising edge of the VG signal at the clock terminal CLK, and the q2 signal outputted by the output terminal Q1 is the same as the input signal VDD at the input terminal D, which is at a high level.

[0131] At this time, the source voltage of the first field effect transistor MN1 is 0, and the q2 signal connected to the gate is high level. Therefore, the VGS of the first field effect transistor MN1 is high level and is in the on state, VP_gate=0.

[0132] At this time, the gates of the fifth field effect transistor MP4 and the sixth field effect transistor MP5 are connected to a low level. First, the source of the fifth field effect transistor MP4 is considered to be at a low level. Since the drain of the fifth field effect transistor MP4 is the input signal VDD, the source signal is at a low level, and the parasitic diode inside the fifth field effect transistor MP4 points from the drain to the source, therefore, the fifth field effect transistor MP4 is turned on. The source output VDD signal of the fifth field effect transistor MP4 is a high level. Due to the effect of the clamping diode ZD1, the gates of the fifth field effect transistor MP4 and the sixth field effect transistor MP5 are still connected to a low level. Therefore, the source of the sixth field effect transistor MP5 is at a high level, the gate is at a low level, and VGS is less than 0. Thus, the sixth field effect transistor MP5 enters the on state. At this time, the fifth field effect transistor MP4 and the sixth field effect transistor MP5 are both in the on state, and the discharge module 401 is started, thereby short-circuiting the inductor L1 to avoid the current generated at the inductor L1 and the ringing phenomenon. At this time, the voltage at the node SW is stable as the input signal VDD, and no ringing phenomenon will occur.

[0133] Through the logic module 402 and the discharge module 401 in the embodiment of the present application, the ringing energy of the switching circuit can be released when the switching circuit enters the DCM mode to avoid the ringing phenomenon of the switching circuit. In addition, the logic module 402 in the present application only needs to control the discharge module 401 to release the ringing energy of the switching circuit through multiple switching tubes, and there is no need for complex level conversion, thereby reducing the power consumption of the switching circuit.

[0134] In other embodiments, the switch tube of the switch control unit may also include other forms.

[0135] Exemplarily, the switch unit includes a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, and a tenth field effect transistor.

[0136] The drain of the seventh field effect tube is connected to the input signal, the gate of the seventh field effect tube is connected to the first node signal and the gate of the eighth field effect tube, and the source of the seventh field effect tube is connected to the source of the eighth field effect tube.

[0137] The drain of the eighth field effect transistor is connected to the drain of the first field effect transistor and the drain of the ninth field effect transistor.

[0138] The source of the ninth field effect tube is connected to the source of the tenth field effect tube, the gate of the ninth field effect tube is connected to the gate of the first field effect tube and outputs the input signal.

[0139] The drain of the tenth field effect transistor inputs the first node signal.

[0140] For example, Figure 7 According to an embodiment of the present application, a circuit diagram of another switch control unit is shown.

[0141] and Figure 5 Compared with the switch control unit in the embodiment, the embodiment of the present application does not need to prevent the second field effect tube MP1 and the fourth field effect tube MP3 from being turned on by the back-to-back structure of the third field effect tube MP2. In this embodiment, the position of the second field effect tube MP1 is set with a field effect tube MP1A (as an example of the seventh field effect tube) and a field effect tube MP1B (as an example of the eighth field effect tube). The field effect tube MP1A and the field effect tube MP1B are connected to the common gate and the common source, and the gate is connected to the SW signal. The drain of the field effect tube MP1A is connected to the input signal VDD, and the drain of the field effect tube MP1B is the output end of the switch control unit. The position of the fourth field effect tube is set with a field effect tube MP3A and a field effect tube MP3B, which can also prevent the VDD signal from being connected to the SW signal. The field effect tube MP3A (as an example of the ninth field effect tube) and the field effect tube MP3B (as an example of the tenth field effect tube) are connected to the common gate and the common source, and the gate is connected to the input signal VDD. The drain of the FET MP3B is connected to the SW signal, the drain of the FET MP3A is the output of the switch control unit and is connected to the drain of the FET MP1B. The FETs MP1A, MP1B, MP3A and MP3B can be, for example, P-channel MOSFETs.

[0142] For example, during the charging cycle of the inductor L1, the SW signal is 0, the field effect transistor MP1A is turned on through the internal parasitic diode, the source of the field effect transistor MP1B is connected to the input signal VDD, and the VGS of the field effect transistor MP1B is low, so the field effect transistor MP1A and the field effect transistor MP1B are both in the on state. At this time, the gate voltage of MP3A is the input signal VDD, and the source signal is 0, so the field effect transistor MP3A enters the off state. At this time, the voltage output by the switch control unit is the input signal VDD, which is Figure 5 In the charging cycle of the embodiment, the output of the switch control unit is the same.

[0143] In the discharge cycle, when the inductor L1 is discharged, the SW signal is the output signal Vout, and the output signal Vout is greater than the input signal VDD. At this time, the source voltage of the field effect transistor MP1A and the field effect transistor MP1B is low level, and the gate voltage is high level, so the field effect transistor MP1A and the field effect transistor MP1B are both in the off state. At this time, since the drain signal VDD of the field effect transistor MP1A is higher than the source signal, the field effect transistor MP1A can be turned on through the internal parasitic diode, but the field effect transistor MP1B still cannot be turned on. Therefore, the field effect transistor MP1A enters the on state, and the field effect transistor MP1B enters the off state.

[0144] The drain of the field effect transistor MP3B is connected to the SW signal, that is, the output signal Vout, the gate is connected to the input signal VDD, and the source signal is 0. Therefore, the VGS of the field effect transistor MP3B is high, and the field effect transistor MP3B is in the off state. However, since the output signal Vout of the drain of the field effect transistor MP3B is high, and the source is low. Therefore, the field effect transistor MP3B can be turned on through the internal parasitic diode. At this time, the source of the field effect transistor MP3A is connected to the output signal Vout, and the gate is connected to the input signal VDD. Therefore, the VGS of the field effect transistor MP3A is low, and the field effect transistor MP3A is turned on. At this time, the output end of the switch control unit outputs the output voltage Vout, which is Figure 5 In the embodiment, when the inductor L1 is discharged, the signals outputted from the output terminals of the switch units are the same.

[0145] In the discharge cycle, when the inductor L1 is discharged, the output terminal of the switch control unit will be grounded regardless of any input signal. Figure 5 The same as the embodiment.

[0146] It can be understood that the control submodule in the above embodiment can also include more switching tubes or fewer switching tubes, or other types of switching tubes, which are used to control the discharge module 401 to start when the inductor L1 finishes discharging, and control the discharge module 401 to shut down when the inductor L1 is charging and discharging.

[0147] The embodiment of the present application also provides a chip. The chip includes the switch circuit and other functional circuits provided in the above embodiment of the present application. The switch circuit can avoid the ringing phenomenon.

[0148] An embodiment of the present application further provides an electronic device, comprising the switch circuit provided by any one of the above embodiments, or the chip provided by the above embodiments.

[0149] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0150] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0151] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0152] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A switching circuit, characterized in that: include: A charge and discharge module, comprising an energy storage unit and a load unit, wherein a first end of the energy storage unit is connected to an input signal of the switch circuit, a second end of the energy storage unit is connected to a first end of the load unit, and the charge and discharge module can switch between a charge cycle and a discharge cycle under the control of at least one control signal; A discharge module is connected in parallel with the energy storage unit, and the discharge module can absorb the electric energy flowing from the parasitic capacitance in the switch circuit to the energy storage element in a conducting state; a reverse current detection module, connected to the second end of the energy storage unit, for detecting a reverse current flowing from the load unit to the energy storage unit, and outputting a first signal according to a state of the reverse current; A logic module is connected to the charge and discharge module, the output end of the reverse current detection module and the input end of the discharge module, and is used to perform a logic operation on the at least one control signal and the first signal, and control the on and off of the discharge module based on the result of the logic operation.

2. The switch circuit according to claim 1, characterized in that: The charging and discharging module also includes a first switch and a second switch; A first end of the first switch is connected to a second end of the energy storage unit, a second end of the first switch is grounded, and the first switch is used to control the on / off state of the energy storage circuit of the energy storage unit; The first end of the second switch is connected to the second end of the energy storage unit, and the second end of the second switch is connected to the load unit; The at least one control signal includes a first control signal and a second control signal, and the first control signal and the second control signal are used to control the on and off of the first switch and the second switch respectively.

3. The switch circuit according to claim 2, characterized in that: The logic module includes a logic control unit, a switch control unit and a first field effect transistor; The input end of the logic control unit is connected to the charge and discharge module and the reverse current detection module, and is used to obtain the input signal of the switch circuit, the first control signal, the second control signal and the first signal; The output end of the logic control unit is connected to the gate of the first field effect transistor; The second end of the energy storage unit is a first node; The input end of the switch control unit is connected to the charge and discharge module to obtain the input signal and the first node signal of the first node part, and the output end of the switch control unit is connected to the drain of the first field effect transistor and the discharge circuit; The source of the first field effect transistor is grounded.

4. The switch circuit according to claim 3, characterized in that: The logic control unit includes a first D flip-flop and a second D flip-flop; The input end of the first D flip-flop is connected to the first end of the energy storage unit, the clock end of the first D flip-flop is connected to the output end of the reverse current detection circuit, the reset end of the first D flip-flop is connected to the NOT gate and receives the first control signal, the output end of the first D flip-flop is connected to the reset end of the second D flip-flop, and outputs a first logic signal; The input end of the second D flip-flop is connected to the first end of the energy storage unit, the clock end of the second D flip-flop inputs the second control signal, and the output end of the second D flip-flop is connected to the gate of the first field effect transistor and outputs a second logic signal.

5. The switch circuit according to claim 3, characterized in that: The switch control unit includes a second field effect transistor, a third field effect transistor and a fourth field effect transistor; The drain of the second field effect transistor is connected to the first end of the energy storage unit, the source of the second field effect transistor is connected to the source of the third field effect transistor and the source of the fourth field effect transistor, and the gate of the second field effect transistor is connected to the first node; The drain of the third field effect tube is the output end of the switch control unit, and the drain of the third field effect tube is connected to the control end of the discharge module and the drain of the first field effect tube, and the gate of the third field effect tube is connected to the NOT gate and linked to the first control signal; The drain of the fourth field effect transistor is connected to the first node, and the gate of the fourth field effect transistor is connected to the first end of the energy storage unit.

6. The switch circuit according to claim 3, characterized in that: The discharge circuit includes a fifth field effect transistor, a sixth field effect transistor and a clamping diode; The drain of the fifth field effect transistor is connected to the first end of the energy storage unit, the source of the fifth field effect transistor is connected to the source of the sixth field effect transistor and the output end of the clamping diode, and the gate of the fifth field effect transistor is connected to the gate of the sixth field effect transistor, the input end of the clamping diode, the output end of the switch control unit, and the drain of the first field effect transistor; The drain of the sixth field effect transistor is connected to the first node.

7. The switch circuit according to claim 3, characterized in that: The switch unit includes a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor; The drain of the seventh field effect tube is connected to the first end of the energy storage unit, the gate of the seventh field effect tube is connected to the first node and the gate of the eighth field effect tube, and the source of the seventh field effect tube is connected to the source of the eighth field effect tube; The drain of the eighth field effect transistor is connected to the drain of the first field effect transistor and the drain of the ninth field effect transistor; The source of the ninth field effect tube is connected to the source of the tenth field effect tube, and the gate of the ninth field effect tube is connected to the gate of the tenth field effect tube and the first end of the energy storage unit; The drain of the tenth field effect transistor is connected to the first node.

8. The switch circuit according to claim 2, characterized in that: The charging and discharging module further includes a driving module, wherein a first output terminal of the driving module is connected to a control terminal of the first switch, and is used to output the first control signal to the first switch; The second output terminal of the driving module is connected to the control terminal of the second switch, and is used to output the second control signal to the second switch; The input end of the driving module is connected to the output end of the reverse current detection circuit.

9. A chip, characterized in that: The chip comprises the switching circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: A switch circuit comprising any one of claims 1 to 8.

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