Output driver

Abstract

An output driver includes a pull-up transistor having a first current path coupled between a supply voltage and an output node; a pull-down transistor having a second current path coupled between the output node and a reference ground; the gate driving circuit is used for driving the control end of the pull-up transistor according to the first control signal and driving the control end of the pull-down transistor according to the second control signal; the logic control circuit is used for generating a first control signal and a second control signal according to an input signal and an enable control signal; and the current source circuit is used for respectively providing pull-down or pull-up current related to the power supply voltage to the control end of the pull-up transistor or the pull-down transistor when the output signal at the output node is in a rising edge or falling edge process, so as to counteract the influence of the power supply voltage on the transmission time of the output signal. Therefore, stable transmission time can be maintained in a wide power supply voltage range.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly to an output driver. Background Art

[0002] In the application of high-speed analog-to-digital converters (ADCs), as the conversion rate continues to increase, the performance requirements for output drivers are also getting higher and higher. The output driver needs to provide enough current to meet the needs of high-speed data transmission, which results in a large amount of changing current in a short period of time, resulting in significant switching noise on the power line. In addition, in application scenarios with large capacitive loads, the inductive effects of the package and circuit board can cause voltage rebound (i.e., supply bounce) on the power line. These noises will not only cause delays and oscillations in data transmission, but may also cause crosstalk between adjacent signal lines, and in severe cases may even affect the normal operation and performance of the internal circuits of the chip.

[0003] In order to solve the above problems, controlling the slew rate of the output driver has become an effective technical means. By adjusting the slew rate of the output driver, the current change rate can be reduced, thereby reducing the generation of noise. Currently, there are many methods to control the slew rate of the output driver, among which the capacitor feedback structure is favored due to its high area efficiency.

[0004] like Figure 1 As shown, the output driver 100 of the prior art includes a pull-up transistor M1 connected between the power supply voltage VDD_IO and the output node N0, a pull-down transistor M2 connected between the output node N0 and the ground terminal, and transistors M3 to M6. Among them, the transistor M5 and the transistor M3 are connected in series between the power supply voltage VDD_IO and the ground terminal, and the middle node between the two is connected to the gate of the pull-up transistor M1. The transistors M3 and M5 are used to provide a pull-up drive signal VGP to the pull-up transistor M1 according to the input signal Din, and then the load capacitor CL at the output pad PAD connected to the output node N0 is charged through the pull-up transistor M1. The transistors M4 and M6 are connected in series between the power supply voltage VDD_IO and the ground terminal, and the middle node between the two is connected to the gate of the pull-down transistor M2. The transistors M4 and M6 are used to provide a pull-down drive signal VGN to the pull-down transistor M2 according to the input signal Din, and then the load capacitor CL at the output pad PAD is discharged through the pull-down transistor M2.

[0005] The output driver 100 of the prior art introduces capacitor feedback from the output pad PAD to the gates of the pull-up transistor M1 and the pull-down transistor M2, and then controls the gate voltages of the pull-up transistor M1 and the pull-down transistor M2 to match the output current and the load. In this structure, the transistor M3 and the transistor M4 act as a constant current source, and the feedback capacitors CFP and CFN are used to keep the gate voltage VGP of the pull-up transistor M1 and the gate voltage VGN of the pull-down transistor M2 at a relatively stable value during the rising edge or falling edge of the output pad PAD, so that the transmission time of the output driver mainly depends on the power supply voltage, the feedback capacitor and the current source, and has little to do with the size of the output load within a large range.

[0006] However, the transmission time of this traditional capacitor feedback structure is directly related to the power supply voltage VDD_IO, which limits its application in a wider power supply voltage range, causing the transmission time to vary greatly under different power supply voltages, thereby limiting the performance stability of the circuit under different power supply voltages and load conditions. Summary of the invention

[0007] In view of this, an object of the present invention is to provide an output driver capable of maintaining a stable transmission time under a wider power supply voltage range to adapt to various application scenarios.

[0008] According to one aspect of the present invention, there is provided an output driver, comprising: a pull-up transistor having a first current path, the first current path being coupled between a power supply voltage and an output node; a pull-down transistor having a second current path, the second current path being coupled between the output node and a reference ground; a gate drive circuit, for generating a pull-up drive signal according to a first control signal to drive a control terminal of the pull-up transistor, and for generating a pull-down drive signal according to a second control signal to drive the control terminal of the pull-down transistor; a feedback capacitor, coupled between the gate drive circuit and the output node, for maintaining the stability of the pull-up drive signal or the pull-down drive signal; and a current source circuit, for providing a pull-down current related to the power supply voltage to the control terminal of the pull-up transistor when the output signal at the output node is at a rising edge, or providing a pull-up current related to the power supply voltage to the control terminal of the pull-down transistor when the output signal is at a falling edge, so as to reduce the influence of the power supply voltage on the transmission time of the output signal.

[0009] Optionally, both the pull-up current and the pull-down current are proportional to the power supply voltage.

[0010] Optionally, the gate drive circuit includes: a first submodule, used to generate the pull-up drive signal according to the first control signal and its inverted signal; and a second submodule, used to generate the pull-down drive signal according to the second control signal and its inverted signal, wherein the feedback capacitor is coupled between the first reference node between the first submodule and the second submodule and the output node.

[0011] Optionally, the first submodule includes: a first transistor coupled between the power supply voltage and a second reference node, and the inverted signal of the first control signal is used to drive the control end of the first transistor; and a second transistor coupled between the second reference node and the first reference node, and the first control signal is used to drive the control end of the second transistor, wherein the second reference node is connected to the control end of the pull-up transistor to provide the pull-up drive signal thereto, and the second submodule includes: a third transistor coupled between the first reference node and a third reference node, and the second control signal is used to drive the control end of the third transistor; and a fourth transistor coupled between the third reference node and a reference ground, and the inverted signal of the second control signal is used to drive the control end of the fourth transistor, wherein the third reference node is connected to the control end of the pull-down transistor to provide the pull-down drive signal thereto.

[0012] Optionally, it also includes: a logic control circuit, used to generate the first control signal and the second control signal according to an input signal and an enable control signal, wherein the logic control circuit is used to output the first control signal as a valid signal when the input signal and the enable control signal are both valid signals, and to output the second control signal as a valid signal when the input signal is an invalid signal and the enable control signal is a valid signal.

[0013] Optionally, the logic control circuit includes: a NAND gate, a first input terminal for receiving the enable control signal, a second input terminal for receiving the input signal, and an output terminal for outputting the first control signal; a first inverter, an input terminal connected to the output terminal of the NAND gate, and an output terminal for outputting an inverted signal of the first control signal; a NOR gate, a first input terminal for receiving the input signal, a second input terminal for receiving the inverted signal of the enable control signal, and an output terminal for outputting the second control signal; a second inverter, an input terminal connected to the output terminal of the NOR gate, and an output terminal for outputting an inverted signal of the second control signal.

[0014] Optionally, the current source circuit includes: a first current source circuit connected to the control end of the pull-up transistor, and used to provide a pull-down current to the control end of the pull-up transistor during the rising edge of the output signal; and a second current source circuit connected to the control end of the pull-down transistor, and used to provide a pull-up current to the control end of the pull-down transistor during the falling edge of the output signal.

[0015] Optionally, the first current source circuit includes: a first switch, a first end of which is connected to the power supply voltage; a first resistor, a first end of which is connected to the second end of the first switch; a fifth transistor, a first end of which is connected to the second end of the first resistor, and a second end of which is connected to a reference ground; a sixth transistor, a first end of which is connected to the control end of the pull-up transistor, and the control end is connected to the first end of the fifth transistor; a second resistor, a first end of which is connected to the control end of the fifth transistor and the second end of the sixth transistor; a second switch, a first end of which is connected to the second end of the second resistor, and a second end of which is connected to the reference ground; a third resistor, a first end of which is connected to the control end of the pull-up transistor; a third switch, a first end of which is connected to the second end of the third resistor, and a second end of which is connected to the reference ground; a fourth switch, a first end of which is connected to the control end of the fifth transistor, and a second end of which is connected to the reference ground; and a fifth switch, a first end of which is connected to the control end of the sixth transistor, and a second end of which is connected to the reference ground. The second current source circuit includes: a seventh transistor, a first end of which is connected to the power supply voltage; a fourth resistor, a first end of which is connected to the second end of the seventh transistor; a sixth switch, a first end of which is connected to the second end of the fourth resistor, and a second end of which is connected to the reference ground; a seventh switch, a first end of which is connected to the power supply voltage; a fifth resistor, a first end of which is connected to the second end of the seventh switch; an eighth transistor, a first end of which is connected to the second end of the fifth resistor and the control end of the seventh transistor, the control end of which is connected to the second end of the seventh transistor, and the second end of which is connected to the control end of the pull-down transistor; an eighth switch, a first end of which is connected to the power supply voltage; a sixth resistor, a first end of which is connected to the second end of the eighth switch, and a second end of which is connected to the control end of the pull-down transistor; a ninth switch, a first end of which is connected to the power supply voltage, and a second end of which is connected to the control end of the seventh transistor; and a tenth switch, a first end of which is connected to the power supply voltage, and a second end of which is connected to the control end of the eighth transistor.

[0016] Optionally, the turning on and off of the first switch to the fifth switch is controlled by the first control signal, and the turning on and off of the sixth switch to the tenth switch is controlled by the second control signal, wherein when the first control signal is a valid signal, the first switch to the third switch is turned on, and the fourth switch and the fifth switch are turned off; when the first control signal is an invalid signal, the first switch to the third switch is turned off, and the fourth switch and the fifth switch are turned on; when the second control signal is a valid signal, the sixth switch to the eighth switch is turned on, and the ninth switch and the tenth switch are turned off; when the second control signal is an invalid signal, the sixth switch to the eighth switch is turned on, and the ninth switch and the tenth switch are turned off.

[0017] Optionally, the pull-down transistor, the first transistor and the second transistor are N-channel field effect transistors, and the pull-up transistor, the third transistor and the fourth transistor are P-channel field effect transistors.

[0018] Optionally, the fifth transistor and the sixth transistor are N-channel field effect transistors, and the seventh transistor and the eighth transistor are P-channel field effect transistors.

[0019] In summary, the embodiment of the present invention provides a slew rate controlled output driver based on capacitor feedback and a wide power supply voltage operating range. By using a current source circuit to provide a pull-down or pull-up current related to the power supply voltage to the driving transistor, the correlation between the output driver transmission time and the power supply voltage and the output impedance is reduced, so that the output conversion time is relatively stable under a relatively wide power supply voltage and capacitive load, and then the output driver can maintain a stable output conversion time under different power supply voltage and load conditions, thereby enhancing the circuit's adaptability to environmental changes and improving the robustness of the circuit. The output driver of the embodiment of the present invention can maintain a stable transmission time under a wide power supply voltage range and different load capacitance conditions, has strong adaptability, and is suitable for a variety of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0021] Figure 1 FIG. 1 is a circuit diagram of an output driver according to the prior art.

[0022] Figure 2 FIG. 4 is a schematic diagram showing the structure of an output driver according to an embodiment of the present invention.

[0023] Figure 3 A circuit schematic diagram of a driving circuit and a gate driving circuit according to an embodiment of the present invention is shown.

[0024] Figure 4 A circuit diagram of a logic control circuit according to an embodiment of the present invention is shown.

[0025] Figure 5 FIG. 4 is a circuit diagram of a first current source circuit according to an embodiment of the present invention.

[0026] Figure 6 FIG. 4 is a circuit diagram showing a second current source circuit according to an embodiment of the present invention.

[0027] Figure 7 A waveform comparison diagram showing the transmission delay of the output driver according to the embodiment of the present invention and the output driver according to the prior art is shown. DETAILED DESCRIPTION

[0028] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0029] Many specific details of the present invention are described below, such as component structures, materials, dimensions, processing techniques and technologies, in order to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0030] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuit, a programmable circuit, a state machine circuit and / or an element that can store instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0031] In the present application, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal and a control terminal. When the MOSFET is in the on state, current flows from the first terminal to the second terminal. The first current terminal, the second current terminal and the control terminal of a P-channel MOSFET are the source, the drain and the gate, respectively, and the first current terminal, the second current terminal and the control terminal of an N-channel MOSFET are the drain, the source and the gate, respectively.

[0032] Figure 2FIG. 2 shows a schematic diagram of the structure of an output driver according to an embodiment of the present invention. Figure 2 The output driver 200 includes a driving circuit 210 , a gate driving circuit 220 , a current source circuit and a logic control circuit 240 .

[0033] Among them, the output pad PAD is connected to the output node of the driving circuit 210 through the output line, the capacitive load CL is connected between the output pad PAD and the reference ground GND, and the driving circuit 210 is used to pull up or pull down the output pad PAD according to the control signal to provide it with an output signal Dout.

[0034] Further, Figure 3 FIG. 2 is a schematic diagram of a driving circuit 210 according to an embodiment of the present invention. Figure 3 The driving circuit 210 may include a pull-up transistor M1 (e.g., a P-channel MOSFET) and a pull-down transistor M2 (e.g., an N-channel MOSFET), the pull-up transistor M1 being connected between the power supply voltage VDD_IO and the output node N0, the pull-down transistor M2 being connected between the output node N0 and the reference ground GND, and the output node N0 being connected to the output pad PAD. The pull-up transistor M1 and the pull-down transistor M2 have a current path therethrough (in the case of a field effect transistor such as a MOSFET, the current path is between the source and the drain of the MOSFET), thereby providing a current path from the supply power VDD_IO and the reference ground GND to the output node N0 between the transistors M1 and M2.

[0035] For example, Figure 3 As shown, the source of the pull-up transistor M1 is connected to the power supply voltage VDD_IO, the drain of the pull-up transistor M1 is connected to the output node N0, the drain of the pull-down transistor M2 is connected to the output node N0, and the source of the pull-down transistor M2 is connected to the reference ground GND.

[0036] For example, the power supply voltage VDD_IO is provided as an IO power supply voltage (Input / Output Power Supply), and the IO power supply voltage refers to a voltage level used when the chip interacts with external devices for data, which is directly related to the performance and stability of the chip.

[0037] The gate drive circuit 220 is used to generate a pull-up drive signal VGP and a pull-down drive signal VGN to respectively control the pull-up operation and the pull-down operation of the drive circuit 210. Further, the gate drive circuit 220 is used to apply the pull-up drive signal VGP and the pull-down drive signal VGN to the control terminals (gates in the case of field effect transistors such as MOSFETs) of the pull-up transistor M1 and the pull-down transistor M2 to control the on and off of the pull-up transistor M1 and the pull-down transistor M2.

[0038] Further, the gate driving circuit 220 is used to generate the pull-up driving signal VGP and the pull-down driving signal VGN according to the first control signal CTRL1 and the second control signal CTRL2 from the logic control circuit 240. For example, the gate driving circuit 220 can generate the pull-up driving signal VGP according to the first control signal CTRL1, and the gate driving circuit 220 can generate the pull-down driving signal VGN according to the second control signal CTRL2.

[0039] Furthermore, the output driver 200 of the embodiment of the present invention also includes a feedback capacitor CF, which is connected between the gate drive circuit 220 and the output node N0. The feedback capacitor CF is used to drive the gate drive circuit 220 according to the voltage feedback at the output node N0, so that the pull-up drive signal VGP and the pull-down drive signal VGN are at a relatively stable value during the rising or falling edge of the voltage at the output pad PAD, so that the output current matches the load.

[0040] Further, Figure 3 FIG. 2 is a circuit diagram of a gate driving circuit 220 according to an embodiment of the present invention. Figure 3 As shown, the gate driving circuit 220 may include two submodules 221 and 222. The submodule 221 is used to generate the pull-up driving signal VGP according to the first control signal CTRL1 and its inverted signal CTRL1B, and the submodule 222 is used to generate the pull-down driving signal VGN according to the second control signal CTRL2 and its inverted signal CTRL2B.

[0041] Further, the submodule 221 includes P-channel MOSFET transistors M5 and M3, the transistors M5 and M3 are connected in series between the power supply voltage VDD_IO and the node A3, the intermediate node A1 of the transistors M5 and M3 is connected to the control end of the pull-up transistor M1, the control end of the transistor M3 is connected to the first control signal CTRL1, and the control end of the transistor M5 is connected to the inverted signal CTRL1B of the first control signal. The transistors M3 and M5 are used to control the logic state of the pull-up drive signal VGP according to the first control signal CTRL1. For example, the first control signal CTRL1 and its inverted signal CTRL1B are, for example, binary "0" (or logic low signal) and "1" (or logic high signal). When the first control signal CTRL1 is a valid signal (for example, "0" or logic low signal), the inverted signal CTRL1B of the first control signal is "1" or logic high signal, the transistor M3 is turned on and the transistor M5 is turned off, and the pull-up drive signal VGP is pulled low through the pull-down current IBP, so that the pull-up transistor M1 is turned on and the output node N0 is pulled up. When the first control signal CTRL1 is an invalid signal (for example, "1" or logic high signal), the inverted signal CTRL1B of the first control signal is "0" or logic low signal, the transistor M5 is turned on and the transistor M3 is turned off, and the pull-up drive signal VGP is pulled high to a logic high signal through the transistor M5, so that the pull-up transistor M1 is turned off.

[0042] Further, the submodule 222 includes N-channel MOSFET transistors M4 and M6, which are connected in series between the node A3 and the reference ground GND, the intermediate node A2 of the transistors M4 and M6 is connected to the control end of the pull-down transistor M2, the control end of the transistor M4 is connected to the second control signal CTRL2, and the control end of the transistor M6 is connected to the inverted signal CTRL2B of the second control signal. The transistors M4 and M6 are used to control the logic state of the pull-down drive signal VGN according to the second control signal CTRL2. For example, the second control signal CTRL2 and its inverted signal CTRL2B are, for example, binary "0" (or logic low signal) and "1" (or logic high signal). When the second control signal CTRL2 is a valid signal (for example, "1" or logic high signal), the inverted signal CTRL2B of the second control signal is "0" or logic low signal, the transistor M4 is turned on and the transistor M6 is turned off, the pull-down drive signal VGN is pulled high by the pull-up current IBN, so that the pull-down transistor M2 is turned on, and the output node N0 is pulled down. When the second control signal CTRL2 is an invalid signal (for example, "0" or logic low signal), the inverted signal CTRL2B of the second control signal is "1" or logic high signal, the transistor M6 is turned on and the transistor M4 is turned off, the pull-down drive signal VGN is pulled down to a logic low signal by the transistor M6, so that the pull-down transistor M2 is turned off.

[0043] Furthermore, the feedback capacitor CF is coupled between the node A3 and the output node N0, and drives the drain terminals of the transistors M3 and M4 according to the voltage feedback at the output node N0, so that the pull-up drive signal VGP and the pull-down drive signal VGN are at a relatively stable value during the rising or falling edge of the voltage at the output pad PAD, so that the output current matches the load.

[0044] Continue to refer Figure 2 , the logic control circuit 240 is used to generate the first control signal CTRL1 and the second control signal CTRL2 according to the input signal Din and the enable control signal EN. For example, the input signal Din and the enable control signal EN are, for example, binary "0" (or logic low signal) and "1" (or logic high signal). When the input signal Din and the enable control signal EN are both valid signals (for example, "1" or logic high signal), the first control signal CTRL1 is a valid signal (for example, "0" or logic low signal); when the input signal Din is an invalid signal (for example, "0" or logic low signal) and the enable control signal EN is a valid signal (for example, "1" or logic high signal), the second control signal CTRL2 is a valid signal (for example, "1" or logic high signal).

[0045] Further, Figure 4FIG. 2 is a circuit diagram showing a logic control circuit 240 according to an embodiment of the present invention. Figure 4 As shown, the logic control circuit 240 includes a NAND gate NAND1, a NOR gate NOR1, an inverter INV1 and an inverter INV2. Among them, one input end of the NAND gate NAND1 is used to receive the enable control signal EN, the other input end of the NAND gate NAND1 is used to receive the input signal Din, and the NAND gate NAND1 is used to perform a NAND calculation on the input signal Din and the enable control signal EN to provide the first control signal CTRL1 at the output end of the NAND gate NAND1. The input of the inverter INV1 is connected to the output end of the NAND gate NAND1, and its output is used to provide the inverted signal CTRL1B of the first control signal. One input end of the NOR gate NOR1 is used to receive the inverted signal ENB of the enable control signal, the other input end of the NOR gate is used to receive the input signal Din, and the NOR gate NOR1 is used to perform a NOR calculation on the input signal Din and the signal ENB to provide the second control signal CTRL2 at the output end of the NOR gate NOR1. An input of the inverter INV2 is connected to an output terminal of the NOR gate NOR1 , and an output of the inverter INV2 is used to provide an inverted signal CTRL2B of the second control signal.

[0046] It should be noted that the circuit structure of the logic control circuit 240 in the above embodiment is only exemplary, and the present invention does not limit this. Those skilled in the art may also choose to implement the logic control circuit 240 through other logic or analog circuits.

[0047] Continue to refer Figure 2 and Figure 3 The current source circuit is used to be connected to the reference nodes A1 and A2 in the gate driving circuit 220 (or the gate terminals of the pull-up transistor M1 and the pull-down transistor M2), and is used to provide the gate driving circuit 220 with a pull-down current IBP or a pull-up current IBN related to the power supply voltage VDD_IO during the rising edge or falling edge of the output pad PAD, so as to offset the influence of the power supply voltage VDD_IO on the transmission time of the output signal Dout, and obtain a constant transmission time in the output driver 200.

[0048] Further, the current source circuit includes a first current source circuit 231 and a second current source circuit 232. The first current source circuit 231 is connected to the reference node A1 in the gate drive circuit 220 or the gate terminal of the pull-up transistor M1, and is used to provide the gate drive circuit 220 with a pull-down current IBP related to the power supply voltage VDD_IO during the rising edge of the output pad PAD or the output node N0, thereby controlling the transmission time of the output signal Dout from a logic low signal to a logic high signal. The second current source circuit 232 is connected to the reference node A2 in the gate drive circuit 220 or the gate terminal of the pull-down transistor M2, and is used to provide the gate drive circuit 220 with a pull-up current IBN related to the power supply voltage VDD_IO during the falling edge of the output pad PAD or the output node, thereby controlling the transmission time of the output signal Dout from a logic high signal to a logic low signal. Therefore, in this embodiment, by setting the first current source circuit 231 and the second current source circuit 232, the rising edge transmission time or the falling edge transmission time of the output driver is ultimately only related to the feedback capacitor CF and the internal resistance of the current source circuit, and is independent of the power supply voltage VDD_IO and the output impedance, so that a constant transmission time can be obtained within a wide power supply voltage range.

[0049] Figure 5 FIG. 4 is a circuit diagram of a first current source circuit according to an embodiment of the present invention. For the convenience of explanation, Figure 5 Only the pull-up transistor M1, the transistor M3, the transistor M5 and the feedback capacitor CF are shown, and the pull-down transistor M2 and the transistors M4 and M6 are not shown. Figure 5 As shown, the first current source circuit 231 includes resistors R1 to R3, transistors M7, transistor M8, and switches S1 to S5. Among them, transistors M7 and M8 are, for example, N-channel MOSFETs, a first end of switch S5 is connected to the power supply voltage VDD_IO, a second end of switch S5 is connected to the first end of resistor R3, a second end of resistor R3 is connected to the gate of transistor M8 and the drain of transistor M7, a gate of transistor M7 is connected to the source of transistor M8 and the first end of resistor R1, and a source of transistor M7 is connected to the reference ground GND. The drain of transistor M8 is connected to the reference node A1 and the gate of the pull-up transistor M1, a second end of resistor R1 is connected to one end of switch S1, and the other end of switch S1 is connected to the reference ground GND. The first end of resistor R2 is connected to the reference node A1 and the gate of the pull-up transistor M1, a second end of resistor R2 is connected to one end of switch S2, and the other end of switch S2 is connected to the ground GND. The switch S3 is connected between the gate of the transistor M8 and the reference ground GND, and the switch S4 is connected between the gate of the transistor M7 and the reference ground GND.

[0050] Furthermore, the on and off of the switches S1 to S5 in the first current source circuit 231 are controlled by the first control signal CTRL1. In a preferred embodiment, the logic control circuit 240 may further include a switch control unit 241, which is used to control the on and off of the switches S1 to S5 according to the first control signal CTRL1.

[0051] Further, when the enable control signal EN is a logic high signal, and during the rising edge of the input signal Din changing from a logic low signal to a logic high signal, the first control signal CTRL1 is a logic low signal, the transistor M3 is turned on, and the transistor M5 is turned off. At this time, the gate terminal voltage VGP of the pull-up transistor M1 starts to drop from the power supply voltage VDD_IO, and the discharge current is equal to the pull-down current IBP provided by the first current source circuit 231. When the gate terminal voltage VGP drops to VDD_IO-VTP1 (VTP1 is the threshold voltage of the pull-up transistor M1), the pull-up transistor M1 is turned on and the voltage of the output pad PAD rises. At the same time, due to the effect of the feedback capacitor CF, a compensation current Icp flowing through the feedback capacitor CF is generated, and the current magnitude is:

[0052] (1)

[0053] Among them, C F is the capacitance value of the compensation capacitor CF, V PAD is the voltage at the output pad PAD. When the compensation current Icp is equal to the pull-down current IBP, the gate voltage VGP of the pull-up transistor M1 is stabilized near a certain value, so that the output current of the output driver remains stable, and the voltage rise rate of the output pad PAD is stable. When the gate voltage VGP of the pull-up transistor M1 is pulled down to the ground potential, the rising process of the voltage of the output pad PAD ends. It can be seen that the slew rate SR+ of the rising edge of the output signal Dout can be calculated by the following formula:

[0054] (2)

[0055] Generally, the rising edge transmission time of the output driver is defined as the time for the output signal Dout to rise from 10% to 90%. Therefore, the rising edge transmission time of the output driver 200 can be obtained as:

[0056] (3)

[0057] According to formula (3), it can be concluded that, without considering the gate terminal parasitic capacitance of the output driver transistor, the rising edge transmission time of the output driver 200 is related to the pull-down current IBP, the size of the feedback capacitor CF and the power supply voltage VDD_IO. Furthermore, the embodiment of the present invention can reduce the correlation between the transmission time and the power supply voltage VDD_IO by introducing a correlation coefficient with the power supply voltage VDD_IO into the pull-down current IBP, thereby obtaining a constant transmission time within a wide power supply voltage range.

[0058] Further, when the enable control signal EN is a logic high signal, and the input signal Din changes from a logic low signal to a logic high signal, the first control signal CTRL1 is a logic low signal, the switches S1, S2, and S5 are turned on, the switches S3 and S4 are turned off, and the current flows from the power supply voltage VDD_IO through the resistor R3 so that the operating voltage of the transistors M7 and M8 is established, so that the current flowing through the resistor R1 can be obtained as:

[0059] (4)

[0060] Among them, V GS7 is the gate-source voltage of transistor M7. In addition, when the pull-up transistor M1 is turned on, the voltage of the pull-up drive signal VGP is stabilized at VDD_IO-|V GS1 |, where V GS1 is the gate-source voltage of the pull-up transistor M1, so the current flowing through the resistor R2 can be obtained as:

[0061] (5)

[0062] Since the pull-down current IBP is equal to the sum of the current flowing through the resistor R1 and the current flowing through the resistor R2, the pull-down current IBP can be obtained as:

[0063] (6)

[0064] According to formula (6), by adjusting the resistance values ​​of resistors R1 and R2, the second term in formula (6) can be made equal to zero, and then:

[0065] (7)

[0066] In another embodiment, the resistors R1 and R2 may be set as variable resistors. Further, substituting the obtained pull-down current IBP into formula (3), it can be obtained:

[0067] (8)

[0068] It can be concluded that in this embodiment, the pull-down current IBP related to the power supply voltage VDD_IO is generated by the first current source circuit 231, so that the rising edge transmission time of the output driver is only related to the feedback capacitor CF and the internal resistance R2 of the current source circuit, and is independent of the power supply voltage VDD_IO and the output impedance, thereby controlling the transmission time of the output driver and obtaining a constant transmission time within a wide power supply voltage range.

[0069] Figure 6 FIG. 4 is a circuit diagram of a second current source circuit according to an embodiment of the present invention. Similarly, for the convenience of explanation, Figure 6 Only the pull-down transistor M2, the transistor M4, the transistor M6 and the feedback capacitor CF are shown, and the pull-up transistor M1 and the transistors M3 and M5 are not shown. Figure 6 As shown, the second current source circuit 232 includes resistors R4 to R6, transistors M9, transistors M10, and switches S6 to S10. Among them, transistors M9 and M10 are, for example, P-channel MOSFETs, the source of transistor M9 is connected to the power supply voltage VDD_IO, the drain of transistor M9 is connected to the first end of resistor R4, the second end of resistor R4 is connected to the first end of switch S6, and the second end of switch S6 is connected to the reference ground GND. The first end of switch S7 is connected to the power supply voltage VDD_IO, the second end of switch S7 is connected to the first end of resistor R5, the second end of resistor R5 is connected to the gate of transistor M9 and the source of transistor M10, the gate of transistor M10 is connected to the drain of transistor M9, and the drain of transistor M10 is connected to the reference node A2 and the gate of pull-down transistor M2. The first end of switch S8 is connected to the power supply voltage VDD_IO, the second end of switch S8 is connected to the first end of resistor R6, and the second end of resistor R6 is connected to the reference node A2 and the gate of pull-down transistor M2. The switch S9 is connected between the power supply voltage VDD_IO and the gate of the transistor M10 , and the switch S10 is connected between the power supply voltage VDD_IO and the gate of the transistor M9 .

[0070] Furthermore, the on and off of switches S6 to S10 in the second current source circuit 232 are controlled by the second control signal CTRL2. In a preferred embodiment, the logic control circuit 240 may further include a switch control unit 242, which is used to control the switching of switches S6 to S10 according to the second control signal CTRL2.

[0071] Further, when the enable control signal EN is a logic high signal, and during the falling edge of the input signal Din changing from a logic high signal to a logic low signal, the second control signal CTRL2 is a logic high signal, the transistor M4 is turned on, and the transistor M6 is turned off. At this time, the gate terminal voltage VGN of the pull-down transistor M2 starts to rise from the reference ground GND, and the charging current is equal to the pull-up current IBN provided by the second current source circuit 232. When the gate terminal voltage VGN rises to VTP2 (VTP2 is the threshold voltage of the pull-down transistor M2), the pull-down transistor M2 is turned on and the voltage of the output pad PAD drops. At the same time, due to the effect of the feedback capacitor CF, a compensation current Icp flowing through the feedback capacitor CF is generated, and the current magnitude can be calculated according to formula (1). When the compensation current Icp is equal to the pull-up current IBN, the gate terminal voltage VGN of the pull-down transistor M2 is stabilized near a certain value, so that the output current of the output driver remains stable, and the voltage drop rate of the output pad PAD is stable, and finally the slew rate SR- of the falling edge of the output signal Dout can be obtained as follows:

[0072] (9)

[0073] Similarly, the falling edge transmission time of the output driver is generally defined as the time for the output signal Dout to fall from 90% to 10%. Therefore, the falling edge transmission time of the output driver can be obtained as:

[0074] (10)

[0075] According to formula (10), it can be concluded that, without considering the gate terminal parasitic capacitance of the output driver transistor, the falling edge transmission time of the output driver 200 is related to the pull-up current IBN, the size of the feedback capacitor CF and the power supply voltage VDD_IO. Furthermore, the embodiment of the present invention can reduce the correlation between the transmission time and the power supply voltage VDD_IO by introducing a correlation coefficient with the power supply voltage VDD_IO into the pull-up current IBN, thereby obtaining a constant transmission time within a wide power supply voltage range.

[0076] Further, when the enable control signal EN is a logic high signal and the input signal Din changes from a logic high signal to a logic low signal, the second control signal CTRL2 is a logic high signal, switches S6, S7 and S8 are turned on, switches S9 and S10 are turned off, and the current flows from the power supply voltage VDD_IO through the resistor R4 so that the operating voltage of the transistors M9 and M10 is established, so that the current flowing through the resistor R5 can be obtained as:

[0077] (11)

[0078] Where V GS9is the gate-source voltage of transistor M9. In addition, when the pull-down transistor M2 is just turned on and the output is still at the falling edge, the gate voltage VGN of the pull-down transistor M2 is stabilized at VGS2, so the current flowing through the resistor R6 can be obtained as:

[0079] (12)

[0080] Since the pull-up current IBN is equal to the sum of the current flowing through the resistor R5 and the current flowing through the resistor R6, the pull-up current IBN can be obtained as:

[0081] (13)

[0082] According to formula (13), by adjusting the resistance values ​​of resistors R5 and R6, the second term in formula (13) can be made equal to zero, and then:

[0083] (14)

[0084] In another embodiment, the resistors R5 and R6 may be set as variable resistors. Further, substituting the obtained pull-up current IBN into formula (10), it can be obtained:

[0085] (15)

[0086] It can be concluded that in this embodiment, the pull-up current IBN related to the power supply voltage VDD_IO is generated by the second current source circuit 232, so that the falling edge transmission time of the output driver is only related to the feedback capacitor CF and the internal resistance R5 of the current source circuit, and has nothing to do with the power supply voltage VDD_IO and the output impedance, thereby controlling the falling edge transmission time of the output driver and obtaining a constant transmission time within a wide power supply voltage range.

[0087] Figure 7 The following is a waveform comparison diagram showing the rising edge transmission time of the output driver of the embodiment of the present invention and the output driver of the prior art. Figure 7 In FIG. 1 , the horizontal axis represents the power supply voltage VDD_IO, and the vertical axis represents the transmission time of the output driver, wherein curve 1 represents the transmission time curve of the output driver 200 of the embodiment of the present invention, and curve 2 represents the transmission time curve of the output driver of the prior art. Figure 7 As shown, when the power supply voltage VDD_IO is in the range of 2.4V to 5.5V, the transmission time of the output driver in the prior art is positively correlated with the power supply voltage VDD_IO, while the transmission time of the output driver in the embodiment of the present invention can remain relatively constant.

[0088] In summary, the embodiment of the present invention provides a slew rate controlled output driver based on capacitor feedback and a wide power supply voltage operating range. By using a current source circuit to provide a pull-down or pull-up current related to the power supply voltage to the driving transistor, the correlation between the output driver transmission time and the power supply voltage and the output impedance is reduced, so that the output conversion time is relatively stable under a relatively wide power supply voltage and capacitive load, and then the output driver can maintain a stable output conversion time under different power supply voltage and load conditions, thereby enhancing the circuit's adaptability to environmental changes and improving the robustness of the circuit. The output driver of the embodiment of the present invention can maintain a stable transmission time under a wide power supply voltage range and different load capacitance conditions, has strong adaptability, and is suitable for a variety of application scenarios.

[0089] It should be noted that although the device is described herein as a certain N-channel or P-channel device, or a certain N-type or P-type doped region, it will be understood by those skilled in the art that complementary devices can also be realized according to the present invention. It will be understood by those skilled in the art that the conductivity type refers to the mechanism by which the conduction occurs, such as conduction by holes or electrons, and therefore the conductivity type does not refer to the doping concentration but to the doping type, such as P-type or N-type.

[0090] It will be understood by those skilled in the art that the words "during", "when" and "when ..." used in this article in connection with the operation of the circuit are not strict terms indicating an action that occurs immediately when the start-up action begins, but that there may be some small but reasonable one or more delays between it and the reaction action initiated by the start-up action, such as various transmission delays, etc. The words "approximately" or "substantially" used in this article mean that the element value has a parameter that is expected to be close to the declared value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be strictly the declared value. It has been properly determined in the art that a deviation of at least ten percent (10%) (for semiconductor doping concentrations, at least twenty percent (20%)) is a reasonable deviation from the accurate ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive logic or negative logic is used. For example, "logic high" and "logic low" are used to describe the logic level of a signal. A signal with a "logic high" is different from a signal with a "logic low". For example, when a signal having a first voltage corresponds to a "logic high level", a signal having a second voltage may correspond to a "logic low level". According to an embodiment, the "logic high level" may be set to a higher voltage than the "logic low level". In addition, according to an embodiment, the logic level of the signal may be set to other logic levels or opposite logic levels. For example, according to an embodiment, a signal having a logic high level may be set to have a logic low level, and according to an embodiment, a signal having a logic low level may be set to have a logic high level.

[0091] In addition, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0092] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An output driver, comprising: a pull-up transistor having a first current path coupled between a supply voltage and an output node; a pull-down transistor having a second current path coupled between the output node and a reference ground; a gate driving circuit, configured to generate a pull-up driving signal according to a first control signal to drive the control end of the pull-up transistor, and to generate a pull-down driving signal according to a second control signal to drive the control end of the pull-down transistor; A feedback capacitor, coupled between the gate drive circuit and the output node, for maintaining stability of the pull-up drive signal or the pull-down drive signal; as well as A current source circuit is used to provide a pull-down current related to the power supply voltage to the control terminal of the pull-up transistor when the output signal at the output node is at a rising edge, or to provide a pull-up current related to the power supply voltage to the control terminal of the pull-down transistor when the output signal is at a falling edge, so as to reduce the influence of the power supply voltage on the transmission time of the output signal.

2. The output driver according to claim 1, wherein: The pull-up current and the pull-down current are both proportional to the power supply voltage.

3. The output driver according to claim 1, wherein: The gate drive circuit comprises: A first submodule, configured to generate the pull-up driving signal according to the first control signal and its inverted signal; and The second submodule is configured to generate the pull-down driving signal according to the second control signal and its inverted signal. The feedback capacitor is coupled between a first reference node between the first submodule and the second submodule and the output node.

4. The output driver according to claim 3, wherein: The first submodule includes: A first transistor is coupled between the power supply voltage and a second reference node, and the inverted signal of the first control signal is used to drive a control terminal of the first transistor; and a second transistor coupled between the second reference node and the first reference node, wherein the first control signal is used to drive a control terminal of the second transistor, The second reference node is connected to the control terminal of the pull-up transistor to provide the pull-up driving signal thereto. The second submodule includes: a third transistor coupled between the first reference node and a third reference node, wherein the second control signal is used to drive a control terminal of the third transistor; and a fourth transistor coupled between the third reference node and a reference ground, wherein the inverted signal of the second control signal is used to drive a control terminal of the fourth transistor, The third reference node is connected to the control terminal of the pull-down transistor to provide the pull-down driving signal thereto.

5. The output driver according to claim 1, wherein: Also includes: a logic control circuit, configured to generate the first control signal and the second control signal according to an input signal and an enable control signal, The logic control circuit is used to output the first control signal as a valid signal when the input signal and the enable control signal are both valid signals, and to output the second control signal as a valid signal when the input signal is an invalid signal and the enable control signal is a valid signal.

6. The output driver according to claim 5, wherein: The logic control circuit comprises: A NAND gate, wherein the first input terminal is used to receive the enable control signal, the second input terminal is used to receive the input signal, and the output terminal is used to output the first control signal; A first inverter, whose input end is connected to the output end of the NAND gate, and whose output end is used to output an inverted signal of the first control signal; A NOR gate, wherein the first input terminal is used to receive the input signal, the second input terminal is used to receive the inverted signal of the enable control signal, and the output terminal is used to output the second control signal; The second inverter has an input end connected to the output end of the NOR gate, and an output end used to output an inverted signal of the second control signal.

7. The output driver according to claim 1, wherein: The current source circuit comprises: a first current source circuit connected to the control terminal of the pull-up transistor, and configured to provide a pull-down current to the control terminal of the pull-up transistor during a rising edge of the output signal; and The second current source circuit is connected to the control end of the pull-down transistor and is used to provide a pull-up current to the control end of the pull-down transistor during the falling edge of the output signal.

8. The output driver according to claim 7, wherein: The first current source circuit comprises: a first switch having a first end connected to the power supply voltage; a first resistor, a first end of which is connected to the second end of the first switch; a fifth transistor, a first terminal of which is connected to the second terminal of the first resistor, and a second terminal of which is connected to a reference ground; a sixth transistor, a first terminal of which is connected to the control terminal of the pull-up transistor, and a control terminal of which is connected to the first terminal of the fifth transistor; a second resistor, a first end of which is connected to the control end of the fifth transistor and the second end of the sixth transistor; a second switch, a first end of which is connected to the second end of the second resistor, and a second end of which is connected to the reference ground; a third resistor, a first end of which is connected to the control end of the pull-up transistor; a third switch, a first end of which is connected to the second end of the third resistor, and a second end of which is connected to the reference ground; a fourth switch, a first terminal of which is connected to the control terminal of the fifth transistor, and a second terminal of which is connected to the reference ground; and a fifth switch, a first end of which is connected to the control end of the sixth transistor, and a second end of which is connected to the reference ground, The second current source circuit comprises: a seventh transistor, a first terminal of which is connected to the power supply voltage; a fourth resistor, a first end of which is connected to the second end of the seventh transistor; a sixth switch, a first end of which is connected to the second end of the fourth resistor, and a second end of which is connected to the reference ground; a seventh switch, a first end of which is connected to the power supply voltage; a fifth resistor, a first end of which is connected to the second end of the seventh switch; an eighth transistor, a first end of which is connected to the second end of the fifth resistor and the control end of the seventh transistor, a control end of which is connected to the second end of the seventh transistor, and a second end of which is connected to the control end of the pull-down transistor; an eighth switch, a first end of which is connected to the power supply voltage; a sixth resistor, a first end of which is connected to the second end of the eighth switch, and a second end of which is connected to the control end of the pull-down transistor; a ninth switch, a first terminal of which is connected to the power supply voltage, and a second terminal of which is connected to the control terminal of the seventh transistor; and A tenth switch has a first end connected to the power supply voltage and a second end connected to the control end of the eighth transistor.

9. The output driver according to claim 8, wherein: The on and off of the first to fifth switches are controlled by the first control signal, and the on and off of the sixth to tenth switches are controlled by the second control signal. Wherein, when the first control signal is a valid signal, the first switch to the third switch are turned on, and the fourth switch and the fifth switch are turned off; when the first control signal is an invalid signal, the first switch to the third switch are turned off, and the fourth switch and the fifth switch are turned on. When the second control signal is a valid signal, the sixth switch to the eighth switch are turned on, and the ninth switch and the tenth switch are turned off; when the second control signal is an invalid signal, the sixth switch to the eighth switch are turned off, and the ninth switch and the tenth switch are turned on.

10. The output driver according to claim 4, wherein: The pull-down transistor, the first transistor and the second transistor are N-channel field effect transistors, The pull-up transistor, the third transistor, and the fourth transistor are P-channel field effect transistors.

11. The output driver according to claim 8, wherein: The fifth transistor and the sixth transistor are N-channel field effect transistors, The seventh transistor and the eighth transistor are P-channel field effect transistors.

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