Processors, chips and computer equipment

Abstract

The embodiment of the present application provides a processor, a chip and a computer device, wherein the processor includes an arbitration module and a plurality of instruction fetch modules, wherein the plurality of instruction fetch modules respectively have respective instruction pre-fetch cache queues; the arbitration module is used to allocate an instruction fetch module to a process included in the processing flow of the message to be processed in response to the completion of reception of the message to be processed, and to send an instruction fetch message to the instruction fetch module; the instruction fetch message carries the instruction storage address of the process assigned to the instruction fetch module; each instruction fetch module extracts the corresponding instruction from the memory according to the instruction storage address in the instruction fetch message received by itself, and stores the extracted instruction in its own instruction pre-fetch cache queue. By applying the embodiment of the present application, the processing efficiency of the instruction pipeline can be significantly improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to processors, chips and computer equipment. Background Art

[0002] In the pipeline design of the CPU (Central Processing Unit), instruction fetching is an important link that affects the performance of the entire pipeline. In general-purpose processors, the instruction fetch module is generally a register cache queue with a certain depth. The instruction fetch module will fetch instructions from the memory according to the instruction address and put them into the register cache queue to complete the instruction fetching so that the decoding module can fetch instructions from the register cache queue for subsequent processing.

[0003] In practical applications, the performance of the pipeline is easily affected by factors such as dependencies between previous and next stages, complex calculations, fence instructions, memory access back pressure, and jump instructions. Among them, jump instructions are used more frequently and have a greater impact on pipeline performance. In the case of branch instructions, instruction fetching is not necessarily linear, and the address used by the next instruction needs to be calculated by the pipeline. Therefore, the pipeline will pause for several clock cycles, resulting in insufficient overall processing efficiency of the pipeline. Summary of the invention

[0004] The purpose of this application is to provide a processor, a chip and a computer device to improve the processing efficiency of the instruction pipeline. The specific technical solution is as follows:

[0005] In a first aspect, the present application provides a processor, comprising an arbitration module and a plurality of instruction fetch modules, wherein the plurality of instruction fetch modules respectively have respective instruction prefetch cache queues;

[0006] The arbitration module is used for allocating an instruction fetch module to a process included in the processing flow of the message to be processed in response to the completion of receiving the message to be processed, and sending an instruction fetch message to the instruction fetch module; the instruction fetch message carries the instruction storage address of the process allocated to the instruction fetch module;

[0007] Each of the instruction fetch modules fetches corresponding instructions from the memory according to the instruction storage address in the instruction fetch message received by itself, and stores the fetched instructions into its own instruction prefetch cache queue.

[0008] Optionally, the instruction fetch module is further configured to, in the process of fetching instructions from the memory, if a preset wait type instruction is obtained, suspend instruction fetching for the current process and set its own working state to idle; the execution of the preset wait type instruction depends on the return of the first execution result of other instructions;

[0009] The arbitration module is specifically used to allocate an idle instruction fetch module to the process in the message to be processed, and send an instruction fetch message to the idle instruction fetch module.

[0010] Optionally, each of the processes corresponds to a respective first program counter, and the first program counter is used to record a storage address of an unexecuted instruction in the corresponding process;

[0011] The arbitration module is further used to allocate an instruction fetch module to the aborted process from idle instruction fetch modules in response to the return of the first execution result to which the aborted process depends; obtain the instruction storage address of the unexecuted instructions of the aborted process from the first program counter, generate a first instruction fetch message according to the instruction storage address of the unexecuted instructions, and send the first instruction fetch message to the instruction fetch module.

[0012] Optionally, a to-be-executed process queue is maintained in the processor, and the to-be-executed process queue caches the process ID and status of each process waiting for instruction fetch; wherein the initial status of each process is a ready status;

[0013] The arbitration module is specifically used to allocate an idle instruction fetch module to a process in a ready state according to the to-be-executed process queue;

[0014] The instruction fetch module is further used to switch the first process back to the queue of processes to be executed after terminating instruction fetching for the first process; wherein the first process enters a waiting state after being switched back to the queue of processes to be executed by the instruction fetch module, and the first process is updated to a ready state after detecting the return of a first execution result on which it depends.

[0015] Optionally, the preset wait type instructions include: instructions in a process that depend on the execution results of other processes.

[0016] Optionally, the instruction fetch module is further used to suspend the instruction fetching process of the current process when a branch instruction is obtained; and continue to execute the instruction fetching process of the current process in response to the second execution result of the branch instruction being returned.

[0017] Optionally, the multiple instruction fetch modules each have their own second program counter, the count value of the second program counter represents the instruction storage address of the current instruction to be fetched; the instruction fetch message carries the instruction storage address of the first instruction of the process assigned to the instruction fetch module; the instruction fetch module fetches instructions according to the count value of its own second program counter;

[0018] The second program counter is used to update its own count value to the instruction storage address carried in the instruction fetch message after receiving the instruction fetch message sent by the arbitration module, and increase the preset value on its own count value after the instruction fetch module completes the extraction of the current instruction.

[0019] Optionally, the processor also includes a pipeline module;

[0020] The pipeline module is used to poll and read instructions in the multiple instruction fetch modules, and perform subsequent pipeline processing on the read instructions.

[0021] In a second aspect, the present application provides a chip comprising any of the processors described above.

[0022] In a third aspect, the present application provides a computer device comprising any chip of the foregoing items.

[0023] Beneficial effects of this application:

[0024] The processor, chip and computer device provided by the present application are provided with an arbitration module and multiple instruction fetch modules in the processor according to the actual characteristics that message processes can be processed in parallel. The arbitration module allocates an instruction fetch module to the process included in the processing flow of the message to be processed, and sends an instruction fetch message to the instruction fetch module, and the instruction fetch message carries the instruction storage address of the corresponding process. Each instruction fetch module can extract the corresponding instruction from the memory according to the instruction storage address in the instruction fetch message received by itself, and store the extracted instruction in its own instruction pre-fetch cache queue.

[0025] It can be seen that each instruction fetch module has its own instruction fetch logic and instruction pre-fetch cache queue, and can fetch instructions for different message processes in parallel. When the instruction fetch process of an instruction fetch module is suspended due to factors such as branch instructions and barrier instructions, other instruction fetch modules can still fetch instructions according to their own instruction fetch logic. In other words, it can ensure that the instruction pipeline in the processor can fetch instructions uninterruptedly, realize uninterrupted instruction pipeline processing, avoid pipeline stagnation caused by factors such as branch instructions and barrier instructions, and improve the efficiency of the pipeline.

[0026] Furthermore, since each instruction fetch module has an instruction pre-fetch cache queue, it can tolerate a larger memory access delay. When multiple processors are integrated in a chip and the memory space used to store instructions in multiple processors is the same, the instruction fetch module in each processor can also more effectively absorb the delay increased by multi-processor access conflicts.

[0027] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0029] Figure 1 It is a schematic diagram of a five-stage pipeline in the related art;

[0030] Figure 2 A schematic diagram of an instruction pre-fetch cache queue in an instruction fetch module in the related art;

[0031] Figure 3 A schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0032] Figure 4 A schematic diagram of the message processing stage provided in an embodiment of the present application;

[0033] Figure 5 Another structural schematic diagram of a processor provided in an embodiment of the present application;

[0034] Figure 6 A schematic diagram of the process of performing instruction pipeline processing by the processor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0036] In large chip designs, CPUs are often integrated into the chip as IP (intellectual property core). However, general-purpose CPUs often cannot meet the functional and performance requirements of the chip. Therefore, when the CPU is embedded as a small IP into a larger application chip (such as a network processing chip), it is generally necessary to adapt the chip's functions to appropriately modify the integrated CPU's behavior logic. For example, in a network processing chip, the message processing function often has a customized part.

[0037] The processor's processing of messages is usually implemented based on instruction pipeline technology. The instruction pipeline breaks down the processing process of an instruction into multiple sub-processes, each of which is completed by a dedicated circuit, so that these sub-processes can be executed in parallel, thereby improving the efficiency of the processor in executing instructions.

[0038] Take the common five-stage pipeline of instructions as an example to illustrate. Figure 1 The figure is a schematic diagram of a five-stage pipeline. The horizontal axis is time, showing seven clock cycles from T to 7T, and the vertical axis is the instructions targeted by the pipeline, showing three instructions: instruction n, instruction n+1, and instruction n+2. Figure 1 It can be seen that in the five-stage pipeline, the processing of an instruction includes five stages: instruction fetch, decoding, execution, memory access, and write back. In the instruction fetch stage, the processor extracts the next instruction to be executed from storage spaces such as ILM (Instruction Local Memory), icache (instruction cache), or memory; in the decoding stage, the processor decodes the extracted instruction to determine the type of operation to be performed and the registers or operands involved; in the execution stage, the processor executes the decoded instruction according to the instruction content; in the memory access stage, if the instruction being processed needs to access the memory, this stage is used to access the memory; in the write back stage, the execution result of the instruction will be written back to the register file or other storage location.

[0039] In an ideal situation, Figure 1 Each of the five stages requires a clock cycle T to complete. Moreover, after the specialized circuit responsible for each stage completes the processing of the current instruction, it can process the next instruction, so that the processor can execute a new instruction every clock cycle. In the absence of conflicts, the five-stage pipeline in the hardware can process five instructions at the same time in one clock cycle.

[0040] In the instruction pipeline, instruction fetching is in the first stage of the pipeline, so the performance of instruction fetching is related to the performance of the pipeline, which is also related to the execution efficiency of the processor. In general-purpose processors, the instruction fetch module is generally a register cache queue with a depth of n (also often called an instruction prefetch cache queue), which can cache N instructions, and the depth N is designed to ensure that the delay of accessing the storage space can be absorbed.

[0041] Take the instruction fetch module to fetch instructions from the ILM as an example. Specifically, ILM is a local memory used to store commonly used instructions, and the instruction fetch speed for ILM is the fastest. Assuming that the latency of accessing ILM data is 2 clock cycles, then N can be set to 3, that is, Figure 2 As shown, the register cache queue includes three registers, register 0, register 1 and register 2, each of which can cache a 32-bit instruction. The number of instructions that the instruction fetch module can pre-fetch is 3. There will be three pointers to maintain the data in the three registers, namely:

[0042] issue_prt: updated after the instruction fetch module initiates an instruction fetch request to the ILM, which can be understood as the tail pointer of the cache queue.

[0043] response_prt: The location pointer where the ILM data is returned after the instruction fetch request is initiated.

[0044] retire_prt: Updated after the pipeline decode module takes the instruction, indicating that the current instruction cache is retired. It can be understood as the first pointer of the cache queue.

[0045] After initialization, the three pointers mentioned above all point to register 0. After the instruction fetch module initiates the first instruction fetch request to the ILM, the issue_prt pointer is updated to point to register 1. After the instruction data is returned from the ILM and the returned instruction data is stored in register 0 based on the current response_prt pointer, the response_prt pointer is updated to point to register 1. After the pipeline decoder module takes instruction data from register 0 based on the current retire_prt pointer, the retire_prt pointer is updated to point to register 1. After the instruction fetch module initiates the second instruction fetch request to the ILM, the issue_prt pointer is updated to point to register 2. After the instruction data is returned from the ILM and the returned instruction data is stored in register 1 based on the current response_prt pointer, the response_prt pointer is updated to point to register 2. After the pipeline decoder module takes instruction data from register 1 based on the current retire_prt pointer, the retire_prt pointer is updated to point to register 2. After the instruction fetch module initiates the third instruction fetch request to the ILM, the issue_prt pointer is updated to point to register 0; after the instruction data is returned from the ILM and stored in register 2 based on the current response_prt pointer, the response_prt pointer is updated to point to register 0; after the pipeline decoding module takes the instruction data from register 2 based on the current retire_prt pointer, the retire_prt pointer is updated to point to register 0, and the subsequent process is similar.

[0046] In practical applications, the performance of the pipeline is easily affected by factors such as dependencies between previous and next stages, complex calculations, fence instructions, memory access back pressure, and jump instructions. Take jump instructions as an example. In the case of jump instructions, instruction fetching is not necessarily linear, and the address used by the next instruction needs to be calculated by the pipeline. Therefore, for the instruction fetch module described in the above example, when the instruction fetch module extracts the jump instruction, the instruction fetch module may not be able to fetch instructions in the following few clock cycles, so that the next-level decoding module, execution module, etc. cannot obtain instructions from the instruction fetch module, causing the pipeline to pause for several clock cycles, resulting in insufficient overall processing efficiency of the pipeline.

[0047] In view of this, the present application improves the execution logic of the processor in instruction fetching and provides a processor. Exemplarily, the processor may be the CPU mentioned above.

[0048] Figure 3 is a schematic diagram of a processor provided in an embodiment of the present application, see Figure 3The processor includes an arbitration module and a plurality of instruction fetch modules, and the plurality of instruction fetch modules respectively have respective instruction pre-fetch cache queues.

[0049] The instruction pre-fetch storage queue of each instruction fetch module is in the form of: Figure 2 In practical applications, the number of instruction fetch modules and the depth of the instruction pre-fetch cache queue in each instruction fetch module can be set in combination with actual needs, and the embodiments of the present application are not limited thereto.

[0050] In the embodiment of the present application, in order to improve the message processing efficiency, each instruction fetch module can fetch instructions for different instructions in a parallel working manner.

[0051] To ensure that the instruction fetching logics of each instruction fetching module are independent of each other, in the embodiment of the present application, instruction fetching is specifically implemented in cooperation between the arbitration module and the instruction fetching module, and the specific execution logic is as follows:

[0052] The arbitration module is used to allocate an instruction fetch module to the process in the message to be processed in response to the completion of receiving the message to be processed, and send an instruction fetch message to the instruction fetch module; the instruction fetch message carries the instruction storage address of the process allocated to the instruction fetch module.

[0053] Each instruction fetch module fetches corresponding instructions from the memory according to the instruction storage address in the instruction fetch message received by itself, and stores the fetched instructions into its own instruction prefetch cache queue.

[0054] In actual application scenarios, the entire processing flow of a message can be divided into multiple stages according to time. These multiple stages are serially related, and one or more processes need to be executed in each stage. Each process can be specifically understood as a process, which contains its own program code and the activities being executed (such as the count value of the program counter and the content in the processor register). Each process has its own independent address space and resources.

[0055] Generally speaking, the processes within a stage can be run in parallel. Figure 4 For example, the processing flow of a message includes five stages from stage 1 to stage 5 in time. Each stage includes one or more processes to be executed, and there are nine processes from process 1 to process 9. Among them, process 1 and process 2 in stage 1 can be parallelized, process 3, process 4 and process 5 in stage 2 can be parallelized, and process 7 and process 8 in stage 4 are the same.

[0056] Generally speaking, a processor needs to process multiple such messages at the same time, and the processing of different messages is independent, that is, at the same time, the number of processes that can be processed in parallel in the processor is relatively large. Based on this feature in the actual application scenario, in the message processing device provided in the embodiment of the present application, for the message to be processed, the entire processing flow of the message is specifically divided into different processes, and the different processes of the message are respectively assigned to different instruction fetching modules for instruction fetching, so as to realize parallel processing between processes.

[0057] Specifically, after the message enters the processor, the relevant data content of each process in the message processing flow will be loaded into the processor's memory, and these data contents include the address of the storage space where the instructions required to process the corresponding process are located. Therefore, after the processor completes the reception of the message to be processed, the arbitration module can obtain the instruction storage address corresponding to each process of the message in the memory, and guide the instruction fetching module to fetch the instruction for the corresponding process through the obtained instruction storage address.

[0058] As described above, there may be several messages to be processed in the processor at the same time, and each message includes several processes, that is, the number of processes that need to be processed in the processor is large. The embodiment of the present application does not strictly limit the specific allocation logic of the arbitration module to allocate each process of the message to a specific instruction fetch module, and each process can be allocated to an instruction fetch module to achieve parallel processing of different processes.

[0059] As an example, the arbitration module can poll to determine the idle status of each instruction fetch module, and according to the idle status of each instruction fetch module, the queued processes are sequentially assigned to the idle instruction fetch modules. In the embodiment of the present application, an instruction fetch module is called idle, which specifically means that the instruction fetch module has not been assigned to a process, or has completed the instruction fetch processing for the latest assigned process.

[0060] Exemplarily, in order to facilitate the arbitration module to assign each process of the message to each instruction fetch module, each instruction fetch module can maintain its own working state. For example, the initial working state of the instruction fetch module can be set to idle. After the arbitration module assigns a process to a certain instruction fetch module, the instruction fetch module will update its own working state to working, and perform instruction fetch processing for the process. After completing the instruction fetch processing for the process, it will update its own working state to idle. Therefore, for the process to be processed, the arbitration module can poll to determine the working state of each instruction fetch module, find an idle instruction fetch module, and assign an idle instruction fetch module to the process to be processed.

[0061] After determining to assign a process to a specific instruction fetch module, the arbitration module can send an instruction fetch message to the specific instruction fetch module, and carry the instruction storage address corresponding to the process in the instruction fetch message. After receiving the instruction fetch message sent by the arbitration module, the instruction fetch module can extract the instruction at the instruction storage address indicated by the instruction fetch message, and store the extracted instruction into its own instruction prefetch cache queue to implement instruction fetch. In actual applications, the data in the instruction prefetch cache queue of each instruction fetch module can be maintained through the aforementioned issue_prt, response_prt and retire_prt three pointers, and the pointers of different instruction prefetch cache queues are independent of each other. The specific update logic of each pointer can refer to the description in the previous text, which will not be repeated here.

[0062] The following is a specific example. Assume that the message processing device includes four instruction fetching modules, namely instruction fetching module 1 to instruction fetching module 4, and the four instruction fetching modules are all in an idle state. If there are two messages to be processed, message 1 and message 2, and the processing stage diagrams of message 1 and message 2 are both as shown in FIG. Figure 4As shown. The arbitration module can assign process1 of message 1 to instruction fetch module 1 for processing, and send the instruction storage address corresponding to process1 of message 1 to instruction fetch module 1; assign process2 of message 1 to instruction fetch module 2 for processing, and send the instruction storage address corresponding to process2 of message 1 to instruction fetch module 2; assign process1 of message 2 to instruction fetch module 3 for processing, and send the instruction storage address corresponding to process1 of message 2 to instruction fetch module 3; and assign process2 of message 2 to instruction fetch module 2 for processing, and send the instruction storage address corresponding to process2 of message 2 to instruction fetch module 4. The four instruction fetch modules will fetch instructions according to the instruction storage addresses they receive, thereby realizing parallel instruction fetch processing for a total of four processes, namely, process1 and process2 of message 1, and process1 and process2 of message 2.

[0063] The processor provided in the embodiment of the present application is provided with an arbitration module and a plurality of instruction fetch modules according to the actual characteristics that message processes can be processed in parallel. The arbitration module allocates an instruction fetch module to the process included in the processing flow of the message to be processed, and sends an instruction fetch message to the instruction fetch module, and carries the instruction storage address of the corresponding process through the instruction fetch message. Each instruction fetch module can extract the corresponding instruction from the memory according to the instruction storage address in the instruction fetch message received by itself, and store the extracted instruction in its own instruction pre-fetch cache queue.

[0064] It can be seen that each instruction fetch module has its own instruction fetch logic and instruction pre-fetch cache queue, and can fetch instructions for different message processes in parallel. When the instruction fetch process of an instruction fetch module is suspended due to factors such as branch instructions and barrier instructions, other instruction fetch modules can still fetch instructions according to their own instruction fetch logic. In other words, it can ensure that the instruction pipeline in the processor can fetch instructions uninterruptedly, realize uninterrupted instruction pipeline processing, avoid pipeline stagnation caused by factors such as branch instructions and barrier instructions, and improve the efficiency of the pipeline.

[0065] Furthermore, since each instruction fetch module has an instruction pre-fetch cache queue, it can tolerate a larger memory access delay. When multiple processors are integrated in a chip and the memory space used to store instructions in multiple processors is the same, the instruction fetch module in each processor can also more effectively absorb the delay increased by multi-processor access conflicts.

[0066] In one embodiment of the present application, Figure 5As shown, the processor also includes a pipeline module; the pipeline module is used to poll and read instructions in multiple instruction fetch modules, and perform subsequent pipeline processing on the read instructions.

[0067] Specifically, when the entire instruction processing process is split based on the instruction pipeline technology, instruction fetching is only the first stage of the pipeline. After completing the instruction fetching, a series of subsequent pipeline processing is required for the extracted instructions to complete the entire processing process. The pipeline module is used to implement this subsequent series of pipeline processing, which may include multiple sub-modules. Taking the processor using a five-stage pipeline as an example, the pipeline module specifically includes a decoding module, an execution module, a memory access module, and a write-back module.

[0068] In the embodiment of the present application, since there are multiple parallel instruction fetch modules, and the pipeline module can usually only read one instruction in one clock cycle, the pipeline module can read instructions from each instruction fetch module in a polling manner. Specifically, the pipeline module can query the empty and full status of the instruction prefetch cache queue in each instruction fetch module in a certain order. If the prefetch cache queue in the queried instruction fetch module is not empty, an instruction is read from the prefetch cache queue for subsequent pipeline processing.

[0069] In one embodiment of the present application, in order to ensure that each instruction fetch module can perform instruction fetch processing continuously, each instruction fetch module may have its own program counter (PC). The count value of the program counter in each instruction fetch module represents the instruction storage address of the current instruction to be fetched. During the instruction fetch process, the instruction fetch module specifically fetches the instruction at the instruction storage address indicated by the count value of its own program counter.

[0070] In actual application scenarios, the processing of a single process usually involves the extraction of a large number of instructions. Therefore, the instruction storage address corresponding to a single process is not just one, but includes the storage address of each instruction involved in the process. For example, if process 1 of message 1 involves 100 instructions, and these 100 instructions are stored in 100 storage units with index numbers from 0 to 99, then the instruction fetching module 1 needs to fetch a total of 100 instructions from the 100 storage units with index numbers from 0 to 99 to implement the instruction fetching for process 1. Among them, each storage unit can be specifically understood as a specific storage space in the memory for storing instructions.

[0071] In order to enable the instruction fetch module to continuously fetch instructions corresponding to each assigned process, in the embodiment of the present application, the program counter of each instruction fetch module has a self-increment function. That is to say, after the instruction fetch module fetches an instruction, the count value of the program counter in the instruction fetch module will automatically add a preset value to prepare for the instruction fetch module to fetch the next instruction. The preset value is related to the length of the instruction. For example, if the length of the instruction is 1 storage unit, the preset value is 1. After the instruction fetch module extracts the instruction stored in a certain storage unit according to the count value of the program counter, the count value of the program counter is automatically +1, that is, it will point to the next storage unit after the certain storage unit, so that the instruction fetch module can fetch instructions from the next storage unit next time.

[0072] In an embodiment of the present application, after allocating a process to a specific instruction fetch module, the arbitration module will specifically generate an instruction fetch message carrying the instruction storage address of the first instruction corresponding to the process, and send the generated instruction fetch message to the program counter of the specific instruction fetch module. After receiving the instruction fetch message sent by the arbitration module, the program counter will update its own count value to the storage address carried in the received instruction fetch message, so that the instruction fetch module to which the program counter belongs can extract the first instruction corresponding to the corresponding process based on the updated count value. After the instruction fetch module completes the instruction fetch of the current instruction, the program counter in the instruction fetch module will increase the preset value on its own count value based on the self-increment function, so that the instruction fetch module can perform the next instruction fetch according to the updated count value of the program counter.

[0073] This is explained with reference to a specific example. Assume that the arbitration module assigns process 1 of message 1 to instruction fetch module 1 for processing. Process 1 of message 1 involves a total of 100 instructions, and these 100 instructions are stored in 100 storage units with index numbers from 0 to 99. Then the arbitration module will generate an instruction fetch message containing index number 0, and send the instruction fetch message to program counter 1 of instruction fetch module 1. After receiving the instruction fetch message, the program counter of instruction fetch module 1 will update its own count value to 0, so that instruction fetch module 1 can extract the instruction in the storage unit with index number 0 according to the count value. After instruction fetch module 1 completes the extraction of the instruction in the storage unit with index number 0, the program counter of instruction fetch module 1 adds 1 to its own count value, and the count value is updated to 1, so that instruction fetch module 1 will extract the instruction in the storage unit with index number 1 according to the count value next time. Based on the same principle, after instruction fetch module 1 completes the extraction of the quality in the storage unit with index number 1, the program counter of instruction fetch module 1 adds 1 to its own count value, and the count value is updated to 2. Similarly, instruction fetch module 1 can extract instructions in the storage units with index numbers from 2 to 99 and complete the instruction fetch of process 1 for message 1.

[0074] After the instruction fetch module completes the fetching of the last instruction corresponding to the assigned process, it can update its own working state to idle so that the arbitration module can assign other processes to itself for instruction fetching.

[0075] Specifically, in an actual message pipeline, the last instruction corresponding to a process is generally a custom state control instruction. The execution result of the last instruction fed back by the pipeline module to the instruction fetch module is used to indicate that the instruction fetch module can switch its own working state to the idle state. In an example, after the instruction fetch module extracts the last instruction corresponding to the process, if the subsequent decoding module identifies the currently processed instruction as the last instruction of the process during the instruction parsing process, it can return a control signal to the instruction fetch module that extracted the instruction, indicating that it has completed the instruction fetch for the current process. After receiving the control signal, the instruction fetch module can update its own working state to idle.

[0076] In actual application scenarios, the storage addresses of various instructions corresponding to a process are not always continuous. Specifically, some instructions can be used to change the instruction fetching logic of the processor, and give the instruction storage address of the next instruction to be fetched through their own execution results. This embodiment of the application refers to such instructions as branch instructions.

[0077] When the instruction fetch module extracts a branch instruction, the instruction fetch module cannot extract the next instruction at the next continuous storage address based on the self-increment function of the program counter, but needs to wait for the execution result of the branch instruction to be returned, and then extract the next instruction according to the instruction storage address indicated by the execution result after the execution result of the branch instruction is returned.

[0078] In some related technologies, a branch prediction function is provided to avoid pipeline stalls caused by waiting for the execution result of a branch instruction to be returned. The branch prediction function can predict the instruction storage address of the next instruction before the execution result of the branch instruction is actually returned, and the instruction fetch module fetches the instruction according to the predicted instruction storage address. However, the accuracy of the branch prediction function is limited. If the prediction result is wrong, it will bring further adverse effects to the subsequent pipeline processing. Moreover, the BTB (Branch Target Buffer) and BHT (Branch History Table) that need to be maintained for branch prediction will occupy a large amount of resources, which is not conducive to improving processor performance.

[0079] As mentioned above, in an embodiment of the present application, since there are multiple instruction fetching modules, parallel instruction fetching can be performed. Therefore, even if the instruction fetching process of an instruction fetching module stops due to a branch instruction, the remaining instruction fetching modules can also execute normal instruction fetching logic, thereby ensuring that the pipeline module can read instructions from each instruction fetching module uninterruptedly, and the entire pipeline will not stop. Therefore, in an embodiment of the present application, the branch prediction function can be omitted, and the instruction fetching module is also used to suspend the instruction fetching process of the current process when a branch instruction is obtained. In other words, when the instruction fetching module obtains a branch instruction, the instruction fetching module can directly stop its own instruction fetching process, wait for the execution result of the branch instruction to be returned, and then continue to execute the instruction fetching process of the current process in response to the execution result of the branch instruction being returned.

[0080] In actual applications, instructions generally carry their own OPCode (Operation Code), which is used to characterize the type of operation corresponding to the instruction (such as a branch operation). Thus, in one example, after fetching the instruction, the instruction fetch module can parse the OPCode (Operation Code) of the extracted instruction to determine whether it has fetched a branch instruction. If the instruction fetch module determines that it has fetched a branch instruction based on the OPCode of the instruction, the instruction fetch module can stop its own instruction fetch process after the pipeline module fetches the branch instruction, and wait for the execution result of the branch instruction to be returned.

[0081] After the pipeline module takes the branch instruction from an instruction fetch module, it will perform subsequent decoding, execution and other processing on the branch instruction, and return the execution result of the branch instruction to the instruction fetch module, so that the instruction fetch module can continue to extract the next jump instruction based on the execution result of the branch instruction.

[0082] In one example, when the pipeline module extracts an instruction from an instruction fetch module, it can also obtain the instruction fetch module ID of the instruction fetch module. Therefore, after the pipeline module extracts a branch instruction from the instruction fetch module and subsequently obtains the execution result of the branch instruction, the execution result of the branch instruction is returned to an instruction fetch module indicated by the instruction fetch module ID according to the instruction fetch module ID recorded for the branch instruction. Therefore, the instruction fetch module can obtain the instruction storage address of the next instruction to be fetched by itself according to the execution result of the branch module, and continue its own instruction extraction process. In a specific implementation, a special branch result return interface can be set between the pipeline module and each instruction fetch module, so that the pipeline module returns the execution result of the branch instruction to the corresponding instruction fetch module through the return interface.

[0083] For example, suppose that the instruction fetch module 2 extracts the nth instruction corresponding to process 2 of message 1 from the storage unit with index number 120 during the instruction fetch processing for process 2 of message 1, and identifies it as a branch instruction by parsing the OPCode of the nth instruction. Then the instruction fetch module 2 will wait for the execution result of the branch instruction to be returned, and will not extract the instruction in the storage unit with index number 121 according to the self-increment logic of the program counter. In addition, when the pipeline module extracts the nth instruction corresponding to process 2 of message 1 from the instruction fetch module 2, it will also obtain the instruction fetch module id of the instruction fetch module 2, so that if the pipeline module subsequently obtains that the storage address of the next instruction indicated by the nth instruction corresponding to process 2 of message 1 is 150, the pipeline module can return the storage address of the next instruction indicated by the nth instruction to the instruction fetch module 2 according to the instruction fetch module id recorded for the instruction, so that the instruction fetch module 2 extracts the n+1th instruction corresponding to process 2 of message 1 from the storage unit with index number 150.

[0084] Combined with the description in the previous text, it can be seen that after the arbitration module assigns a process to a specific instruction fetch module for instruction fetching, and sends the instruction storage address of the first instruction corresponding to the process to the specific instruction fetch module. In the process of the specific instruction fetch module fetching instructions for each instruction corresponding to the process, if the instruction fetch module extracts a branch instruction, the next instruction can be extracted according to the instruction storage address indicated by the execution result of the branch instruction. If the instruction extracted by the instruction fetch module is not a branch instruction, the next instruction can be extracted at the next instruction storage address in sequence according to the self-increment logic of the program counter. In short, as long as the instruction fetch module obtains the instruction storage address of the first instruction corresponding to a process, it can then autonomously complete the extraction of each instruction corresponding to the process.

[0085] In the embodiment of the present application, since there are multiple instruction fetching modules that can perform instruction fetching in parallel, even if the operation of one instruction fetching module is stalled due to the execution of a branch instruction, the remaining instruction fetching modules can still perform normal instruction fetching, thereby ensuring that the pipeline module can read instructions from each instruction fetching module uninterruptedly, and the entire pipeline will not stop, and the processing efficiency of the pipeline can be effectively guaranteed. Therefore, the branch prediction function can be omitted, and the instruction fetching module directly suspends its own instruction fetching process when executing a branch instruction, and then continues to fetch instructions after the execution result of the branch instruction is returned. The strategy for dealing with branch logic is simpler, and there is no need to occupy a large amount of resources due to maintaining the BTB and BHT.

[0086] Similarly, when applying the above-mentioned processor provided by the embodiment of the present application, when a fence instruction of an instruction fetched by an instruction fetch module causes the instruction fetch process of the instruction fetch module to be suspended due to the barrier mechanism of the fence instruction, the remaining instruction fetch modules can still perform normal instruction fetching, thereby ensuring that the pipeline module can continuously read instructions from each instruction fetch module, and the entire pipeline will not stop, and the processing efficiency of the pipeline can be effectively guaranteed.

[0087] In one embodiment of the present application, the instruction fetch module is also used to terminate the instruction fetching for the current process and set its own working state to idle when a preset wait type instruction is obtained during the process of fetching instructions from the memory; the execution of the preset wait type instruction depends on the return of the first execution result of other instructions.

[0088] In actual application scenarios, some instructions may have data dependencies. For example, if the execution of instruction a requires the execution result of instruction b, the instruction pipeline needs to wait for the execution of instruction b to be completed before it can process instruction a. For example, if the processing stage diagram of message 3 is as follows Figure 3 As shown, it can be seen that process6 of message 3 and process3 to process5 of message 3 have a sequential relationship in terms of timing, that is, the execution of process6 requires the execution results of process3 to process5, so the instruction pipeline needs to process process6 after completing the execution of process3 to process5. Another example, if instruction c is used to instruct the processor to look up a table to obtain a certain data result, and instruction d is used to instruct the processor to perform further calculations based on the data result obtained by looking up the table, then the execution of instruction d requires the execution result of instruction c, so the instruction pipeline needs to wait for the execution of instruction c to be completed before processing instruction d.

[0089] For example, if the arbitration module assigns process5 of message 3 to instruction fetch module 1 for instruction fetch processing, and assigns process6 of message 3 to instruction fetch module 2 for instruction fetch processing, and when instruction fetch module 2 performs instruction fetch processing on process6, process5 has not yet been executed. Even if instruction fetch module 2 performs instruction fetch processing on process6 and passes the extracted instructions to the pipeline module, the pipeline module cannot perform subsequent processing on the acquired instructions, so the pipeline processing of process6 will be stagnant, and it needs to wait for the execution result of process5 to be returned before it can continue to run.

[0090] It should be understood that such as the above-mentioned waiting for other processes to complete processing, or waiting for the table lookup results to be obtained, usually requires more clock cycles. If the instruction fetch module suspends its own instruction fetch process to wait for the corresponding processing process to end, the processing efficiency of the instruction pipeline will be significantly reduced. Therefore, in the embodiment of the present application, in order to avoid the long-term occupation of the instruction fetch module by instructions that cannot be executed, a type of instruction that needs to rely on the execution results of other instructions to be executed and the execution results of the other instructions require more clock cycles to be obtained can be defined as a waiting type instruction in advance during the code development stage, so that when the instruction fetch module extracts this type of waiting type instruction, it will stop extracting instructions for the current process and set its own working state to idle.

[0091] After the instruction fetch module that has extracted the preset wait type instruction sets its own working state to idle, the arbitration module can recognize that the instruction fetch module is idle and allocate other processes to be processed to the instruction fetch module for instruction fetch processing.

[0092] In one example, the preset wait type instructions may include: instructions in a process that depend on the execution results of other processes.

[0093] For example, if the message stage of message 3 satisfies Figure 4 , the execution of the instructions in process6 of message 3 depends on the execution results of the instructions in processes3 to process5 of message 3, and the instructions in process6 of message 3 can be defined as waiting type instructions. However, it is worth noting that although process6 of message 3 and processes3 to process5 of message 3 have a timing dependency, in actual applications, process6 of message 3 may not actually use the execution results of processes3 to process5 until it has been executed to a certain progress, that is, a part of the instructions corresponding to process6 of message 3 may be processed smoothly. In view of this situation, only the instructions in process6 of message 3 that actually need to use the execution results of processes3 to process5 of message 3 can be defined as waiting type instructions. For example, if process6 of message 3 corresponds to a total of 100 instructions, then before process3 to process5 of message 3 are executed, the first 50 instructions of the 100 instructions may be executed correctly, and the last 50 instructions require the execution results of process3 to process5 and must wait until the execution results of process3 to process5 are returned before they can be executed. The 51st instruction corresponding to process6 of message 3 can be defined as a waiting type instruction.

[0094] Of course, in actual applications, the instructions that can be defined as wait-type instructions are not limited to the instructions specified in the above examples, and can be selected according to actual conditions.

[0095] In an example, the OPCode of the instruction can be used to identify whether the current instruction is a preset waiting type instruction. Therefore, when the instruction fetch module obtains the instruction, it can identify whether it has extracted a waiting type instruction by parsing the OPCode of the instruction. When it is determined that it has extracted a waiting type instruction, it will terminate the instruction fetch process for the current process and update its own working state to idle.

[0096] Take the case where the arbitration module assigns process6 of message 3 to instruction fetch module 1 for instruction fetch processing, process6 of message 3 depends on the execution results of process3 to process5 of message 3, and the 51st instruction corresponding to process6 of message 3 is defined as a waiting type instruction. After completing the sequential fetching of the first 50 instructions corresponding to process6 of message 3, when further fetching the 51st instruction corresponding to process6 of message 3, instruction fetch module 1 will identify the instruction as a preset waiting type instruction, thereby terminating the instruction fetching process for process6 of message 3 and setting its own working state to idle.

[0097] In the embodiment of the present application, during the process of executing instruction fetching for the assigned process by the instruction fetching module, when the instruction fetching module obtains the preset waiting type instruction, the instruction fetching module will stop the instruction fetching for the current process and set its own working state to idle. Based on this design, the idle instruction fetching module can wait for the arbitration module to assign other processes to itself, and execute instruction fetching for the newly assigned process. The process that cannot be executed will not occupy the instruction fetching module for a long time, so that the pipeline efficiency can be effectively improved.

[0098] In one embodiment of the present application, each process of the message corresponds to its own program counter, and the program counter is used to record the storage address of the unexecuted instruction in the corresponding process. It should be noted that the program counters of each instruction fetch module mentioned above and the program counters corresponding to each process of the message described here are specifically different program counters, and each counts independently.

[0099] Specifically, after the relevant data of each process of the message is loaded into the memory of the processor, the processor will maintain a program counter for each process, and use the program counter to record the storage address of the unexecuted instructions corresponding to each process. As mentioned above, each process may involve the processing of a large number of instructions, so this program counter is generally used to record the instruction storage address of the next instruction to be executed in the corresponding process.

[0100] For example, it is assumed that process6 of message 3 corresponds to 100 instructions, and these 100 instructions are respectively stored in 100 storage units with index numbers from 500 to 599. Before the arbitration module assigns process6 of message 3 to a specific instruction fetch module for instruction fetch processing, the count value of the program counter corresponding to process6 of message 3 is 500. After the arbitration module assigns process6 of message 3 to instruction fetch module 1 for instruction fetch processing and the instruction pipeline completes the pipeline processing of the first instruction corresponding to process, the count value of the program counter corresponding to process6 of message 3 is updated to 501, and so on.

[0101] It can be understood that if an instruction fetch module terminates instruction fetching for a process after executing instruction fetching for a period of time, the storage address of the next instruction to be executed corresponding to the process will also be recorded in the program counter corresponding to the process. Continuing with the example in the previous paragraph. If the instruction fetch module 1 identifies the 51st instruction as a preset waiting type instruction after fetching the 51st instruction corresponding to process6 of message 3, and terminates instruction fetching for process6 of message 3. After the instruction fetch module 1 terminates instruction fetching for process6 of message 3, the count value of the program counter corresponding to process6 of message 3 is the instruction storage address of the 51st instruction corresponding to process6 of message 3, which is specifically 550.

[0102] In the embodiment of the present application, in order to enable the instruction pipeline to subsequently perform pipeline processing on the instructions corresponding to the aborted process, the arbitration module is also used to respond to the return of the first execution result that the aborted process depends on, allocate an instruction fetch module to the aborted process from an idle instruction fetch module, obtain the instruction storage address of the unexecuted instructions of the aborted process from the program counter corresponding to the aborted process, generate a first instruction fetch message according to the instruction storage address of the unexecuted instruction, and send the first instruction fetch message to the instruction fetch module allocated to the aborted process.

[0103] In actual applications, the suspended process caches the storage address of the specific information it needs to wait for, and this specific information can be modified by other processes. The suspended process needs to wait for these specific information to be modified to a specific state value by other processes before it can continue to execute. Therefore, in one example, the suspended process can periodically detect (for example, detect at each clock cycle) whether these specific information matches the state value it is waiting for. If so, it indicates that the execution result that the suspended process depends on has been returned, so that the suspended process can request the arbitration module to allocate an instruction fetch module to itself again.

[0104] After the arbitration module learns that the execution result that the aborted process depends on has been returned, it can reassign the instruction fetch module to the aborted process so that the process can be processed next. After assigning the instruction fetch module to the previously aborted process, the arbitration module can read the program counter corresponding to the aborted process to determine the instruction storage address of the next instruction to be executed corresponding to the aborted process, and then send an instruction fetch message to the instruction fetch module assigned to the aborted process, and carry the storage address in the instruction fetch message, so that the instruction pipeline can continue to process the process from the place where it was last aborted.

[0105] Exemplarily, in the case where the execution of process6 of message 3 depends on the execution results of process3 to process5 of message 3, if instruction fetch module 1 terminates the instruction fetching for process6 of message 3 after fetching the 51st instruction corresponding to process6 of message 3, then as described above, the count value of the program counter corresponding to process6 of message 3 will stay at the instruction storage address of the 51st instruction corresponding to process6 of message 3, specifically 550. Then, if process6 of subsequent message 3 detects that the execution result it is waiting for has returned and requests the arbitration module to allocate an instruction fetch module for itself, the arbitration module will allocate an instruction fetch module for process6 of message 3 again from the idle instruction fetch modules. Assuming that the arbitration module allocates process6 of message 3 to instruction fetch module 2, the arbitration module will read the count value 550 of the program counter corresponding to process6 of message 3, and send an instruction fetch message to instruction fetch module 2, and carry the instruction storage address 550 in the instruction fetch message. After receiving the instruction fetch message, instruction fetch module 2 can extract the 51st instruction corresponding to process6 of message 3 from the storage unit with index number 550 according to the instruction fetch message, so that the instruction pipeline can continue to process process6 of message 3.

[0106] Based on the same principle, when the arbitration module allocates an instruction fetch module to a process for the first time, the arbitration module can also obtain the instruction storage address of the first instruction corresponding to the process by reading the count value in the program counter corresponding to the process, and generate a corresponding instruction fetch message based on the instruction storage address.

[0107] In one embodiment of the present application, a to-be-executed process queue is maintained in the processor, and the to-be-executed process queue caches processes waiting for instruction fetching.

[0108] In the embodiment of the present application, the process queue to be executed can be specifically understood as the cache space occupied by each process to be executed in the processor. Specifically, there may be a large number of processes to be processed in the processor, while the number of instruction fetch modules is limited. Therefore, the processes waiting for instruction fetch can be cached through the process queue to be executed, so that the arbitration module can subsequently assign these processes to the idle instruction fetch modules for processing, and in the embodiment of the present application, the initial state of each process cached in the process queue to be executed is the ready state. Exemplarily, if there are two messages, message 1 and message 2, to be processed, and the two messages have 9 processes respectively, and there are 4 idle instruction fetch modules in the message device, then the arbitration module can only assign 4 of the 18 processes to the instruction fetch modules, and the other 14 processes are cached in the process queue to be executed in the ready state.

[0109] In the embodiment of the present application, when the arbitration module allocates an instruction fetch module to a process waiting for instruction fetch, it specifically allocates an idle instruction fetch module to a process in a ready state in a process queue to be executed. Exemplarily, when the arbitration module allocates an instruction fetch module to a process waiting for instruction fetch, it can first find a process in a ready state in the process queue to be executed, read the program counter corresponding to the process, obtain the instruction storage address of the unexecuted instruction corresponding to the process, generate an instruction fetch message based on the instruction storage address, and send it to the instruction fetch module determined for the process.

[0110] In addition, as mentioned above, for a process that is terminated by the instruction fetch module, the arbitration module needs to re-assign the instruction fetch module to the terminated process after the execution result that the instruction in the terminated process depends on is returned. Therefore, in the embodiment of the present application, in order to facilitate the arbitration module to re-assign the instruction fetch module to the terminated process, the instruction fetch module is also used to switch the first process back to the queue of processes to be executed after the instruction fetch for the first process is terminated. In the embodiment of the present application, after a process is terminated by the instruction fetch module and switched back to the queue of processes to be executed, the state of the process is specifically a waiting state.

[0111] As mentioned above, the aborted process caches the storage address of the specific information it needs to wait for, and the aborted process needs to wait for these specific information to be modified to a specific state value by other processes. Therefore, in the embodiment of the present application, when a process is terminated by the instruction fetch module, the process can subsequently periodically detect whether these specific information matches the state value it is waiting for. When it is detected that these specific information matches the state value it is waiting for, the process determines that the execution result it is waiting for has been returned. At this time, the process can update its own state to the ready state so that the arbitration module can allocate the instruction fetch module to itself again.

[0112] Exemplarily, in the case where the execution of process6 of message 3 depends on the execution results of process3 to process5 of message 3, if instruction fetch module 1 extracts the 51st instruction corresponding to process6 of message 3 and identifies that the 51st instruction is a preset waiting type instruction, then the instruction fetch module can switch process6 of message 3 to the to-be-executed process queue and record its state as a waiting state. If process6 of subsequent message 3 detects that the execution results of process3 to process5 on which it depends are returned, process6 of message 3 updates its own state to a ready state, so that the arbitration module can allocate an instruction fetch module to process6 of message 3 again.

[0113] Therefore, in the process of the arbitration module allocating an instruction fetch module to the process waiting for instruction fetch in the queue of processes to be executed, before the execution results of process3 to process5 of message 3 are returned, since the state of process6 of message 3 is in the waiting state, the arbitration module will not allocate an instruction fetch module to process6 of message 3 again during this period. Before the execution results of process3 to process5 of message 3 are returned, since the state of process6 of message 3 has been updated to the ready state, the arbitration module can allocate an instruction fetch module to process6 of message 3 again.

[0114] It can be seen that when the state of a process waiting for instruction fetch is in the waiting state, it indicates that the execution result that further pipeline processing of the process depends on has not yet been returned, and it is not suitable to pipeline process the process through the instruction pipeline at present. Therefore, it can also be considered that the conditions for pipeline processing of the process are not yet mature. Correspondingly, if the state of a process waiting for instruction fetch is in the ready state, it can be considered that the conditions for pipeline processing of the process are mature.

[0115] Therefore, in the embodiment of the present application, each process to be executed is cached through the process to be executed, and the status of the process to be executed is maintained, so that the arbitration module can judge whether the conditions for pipeline processing are mature for each process according to whether the status of each process in the queue of processes to be executed is a waiting state or a ready state, and then assign an instruction fetch module to the process with a judgment result of yes (i.e., a process in a ready state). This can avoid the situation where the arbitration module assigns a process to a specific instruction fetch module for processing, but the instruction pipeline cannot perform pipeline processing on the process, which helps to ensure the processing efficiency of the instruction pipeline.

[0116] For ease of understanding, the following Figure 6 The process of performing instruction pipeline processing on the processor provided in the embodiment of the present application is exemplified.

[0117] Figure 6 There are four instruction fetch modules in total, from instruction fetch module 1 to instruction fetch module 4. The instruction fetch logic and instruction pre-fetch cache of the four instruction fetch modules are independent of each other, and each can process a message process in parallel. Since there are usually multiple processes waiting to be processed in the processor, the number is much greater than the number of instruction fetch modules, so only four processes can be considered as the executing process at the same time (for example Figure 61_process1, message 1_process2, message 2_process1, and message 2_process2 are shown in FIG. 1 . Four instruction fetching modules fetch instructions for the four processes respectively, and the other processes are processes waiting to be executed (for example, Figure 6 The arbitration module will allocate an instruction fetch module to the process n, process n+1 and process m in the queue. After an instruction fetch module is idle, the arbitration module will allocate the process waiting to be executed to the idle instruction fetch module for execution. The process ID and status of the process waiting to be executed will be recorded in the queue of processes to be executed.

[0118] When an instruction fetch module extracts a branch instruction, the instruction fetch module will suspend its own instruction fetch process and continue to fetch instructions after the execution result of the branch instruction is returned. When one instruction fetch module is suspended, the remaining three instruction fetch modules can continue to run, that is, it can ensure that the instruction fetch module sends instruction fetch requests to the memory without interruption. After the memory receives the instruction fetch request sent by the instruction fetch module, it will read the instruction data in the corresponding instruction storage address and return it to the corresponding instruction fetch module, so as to ensure that the instruction prefetch cache queue inside the instruction fetch module has enough instructions in each clock cycle, so that the instructions can be continuously given to the pipeline module for subsequent pipeline processing, ensuring the saturation of pipeline instruction execution and improving the efficiency of the pipeline.

[0119] Specifically, in the actual simulation test of message forwarding processing, it was found that when fetching instructions through only one instruction fetch module in the traditional way, the total time for the CPU pipeline to process all processes was about 2100 clock cycles. When the processor provided by the embodiment of the present application is applied and 4 instruction fetch modules are specifically set, the message processing time is reduced to about 1400 clock cycles, and the pipeline processing efficiency is significantly improved.

[0120] Based on the same inventive concept, an embodiment of the present application further provides a chip, in which the processor provided by any of the foregoing embodiments of the present application is integrated.

[0121] Based on the same inventive concept, an embodiment of the present application further provides a computer device, which includes the chip provided by the aforementioned embodiment of the present application.

[0122] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0123] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0124] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A processor, characterized in that: It includes an arbitration module and a plurality of instruction fetch modules, wherein the plurality of instruction fetch modules respectively have respective instruction pre-fetch cache queues; The arbitration module is used for allocating an instruction fetch module to a process process included in the processing flow of the message to be processed in response to the completion of receiving the message to be processed, and sending an instruction fetch message to the instruction fetch module; the instruction fetch message carries the instruction storage address of the process allocated to the instruction fetch module; Each of the instruction fetch modules fetches corresponding instructions from the memory according to the instruction storage address in the instruction fetch message received by itself, and stores the fetched instructions into its own instruction prefetch cache queue.

2. The processor according to claim 1, characterized in that The instruction fetch module is further configured to, in the process of fetching instructions from the memory, suspend instruction fetching for the current process and set its own working state to idle if a preset wait type instruction is obtained; the execution of the preset wait type instruction depends on the return of the first execution result of other instructions; The arbitration module is specifically used to allocate an idle instruction fetch module to the process in the message to be processed, and send an instruction fetch message to the idle instruction fetch module.

3. The processor according to claim 2, characterized in that The processes respectively correspond to their own first program counters, and the first program counters are used to record the storage addresses of unexecuted instructions in the corresponding processes; The arbitration module is further configured to allocate an instruction fetch module to the suspended process from idle instruction fetch modules in response to the return of a first execution result to which the suspended process depends; The instruction storage address of the unexecuted instruction of the suspended process is obtained from the first program counter, a first instruction fetch message is generated according to the instruction storage address of the unexecuted instruction, and the first instruction fetch message is sent to the instruction fetch module.

4. The processor according to claim 2 or 3, characterized in that: The processor maintains a process queue to be executed, wherein the process queue to be executed caches processes waiting for instruction fetch; wherein the initial state of each process is a ready state; The arbitration module is specifically used to allocate an idle instruction fetch module to a process in a ready state according to the to-be-executed process queue; The instruction fetch module is further used to switch the first process back to the queue of processes to be executed after terminating instruction fetching for the first process; wherein the first process enters a waiting state after being switched back to the queue of processes to be executed by the instruction fetch module, and the first process is updated to a ready state after detecting the return of a first execution result on which it depends.

5. The processor according to claim 2 or 3, characterized in that: The preset wait type instructions include: instructions in a process that depend on the execution results of other processes.

6. The processor according to claim 1, wherein: The instruction fetch module is further used to suspend the instruction fetching process of the current process when a branch instruction is obtained; and continue to execute the instruction fetching process of the current process in response to the second execution result of the branch instruction being returned.

7. The processor according to claim 1, wherein: The multiple instruction fetch modules each have their own second program counter, the count value of the second program counter represents the instruction storage address of the current instruction to be fetched; the instruction fetch message carries the instruction storage address of the first instruction of the process assigned to the instruction fetch module; the instruction fetch module fetches the instruction according to the count value of its own second program counter; The second program counter is used to update its own count value to the instruction storage address carried in the instruction fetch message after receiving the instruction fetch message sent by the arbitration module, and increase the preset value on its own count value after the instruction fetch module completes the extraction of the current instruction.

8. The processor according to claim 1, wherein: The processor also includes a pipeline module; The pipeline module is used to poll and read instructions in the multiple instruction fetch modules, and perform subsequent pipeline processing on the read instructions.

9. A chip, characterized in that: Comprising a processor as claimed in any one of claims 1-8.

10. A computer device, characterized in that: Comprising the chip as claimed in claim 9.

Images