A Phase-Locked Loop with Adaptive Adjustment of Dead Zone of Phase-Frequency Detector

Abstract

The present invention discloses a phase-locked loop (PLL) for adaptively adjusting the dead zone of a phase frequency detector, which relates to an integrated circuit. This solution is proposed to address the problem of difficulty in controlling the dead zone of a phase frequency detector in the prior art. A first capacitor is provided to sample and compare the charging current of the charge pump; a second capacitor is provided to sample and compare the discharge current of the charge pump; a digital algorithm module is provided to adjust the reset pulse width of the phase frequency detector according to the output results of the first comparator and the second comparator; a selection switch is provided to input a reference signal or a feedback signal to the feedback input terminal of the phase frequency detector according to the selection signal of the digital algorithm module. The advantage is that the reset pulse width of the phase frequency detector is controlled according to the results of the two comparators to achieve an optimal value. It can adapt to phase-locked loops under any process node and can ensure that the narrowest available reset pulse width is obtained.

Description

Technical Field

[0001] The present invention relates to an integrated circuit, in particular to a phase-locked loop for adaptively adjusting a dead zone of a frequency and phase detector. Background Art

[0002] Conventional phase-locked loop structure such as Figure 1 As shown, the phase frequency detector (PFD) identifies the phase difference between the input reference signal Fref and the feedback signal Fdiv output by the frequency divider DIV, and converts the phase difference into the control signals UP and DN of the charge pump CP to control the current output of the charge pump CP. The current output of the charge pump CP is converted into the control voltage of the voltage controlled oscillator (VCO) through the low-pass filter (LPF) to control the output oscillation frequency of the voltage controlled oscillator (VCO). The output signal F VCO After passing through the frequency divider DIV, the signal returns to the phase frequency detector PFD.

[0003] As an indispensable component of a phase-locked loop (PLL), the phase frequency detector (PFD) will produce dead zones and blind zones in actual situations. The existence of dead zones will make it impossible for the loop to correct errors when the phase difference between the two input signals is too small. When the phase difference between the two signals is very small, the charging signal UP and the discharging signal DN output by the phase frequency detector (PFD) cannot fully open the switch of the charge pump CP, resulting in no current flowing through the low-pass filter (LPF), which will not affect the output of the voltage-controlled oscillator (VCO). Figure 2 As shown in , the tuning voltage of the voltage-controlled oscillator does not change as required. The most common approach is to compensate by increasing the reset pulse width, but as the reset pulse width increases, the blind area of the phase frequency detector (PFD) becomes larger. The choice of reset pulse width will affect the blind area of the PFD, resulting in a reduction in its phase detection range and possible erroneous output conditions, such as Figure 3 As shown in , a reset pulse that is too wide will increase the current noise contributed by the PFD / CP when the entire phase-locked loop is locked, affecting the performance of the entire phase-locked loop.

[0004] In general, the reset pulse width of the phase frequency detector (PFD) is manually adjusted to find a minimum noise point. However, the dead zone size varies with different processes and temperatures, so it is difficult to obtain an optimal value under different conditions.

[0005] Related Literature

[0006] Li Zhiqun, Wang Zhigong. Radio Frequency Integrated Circuits and Systems[M]. Beijing: Science Press, 2008;

[0007] Lacaita AL, Levantino S, Samori C. Integrated Frequency Synthesizers for Wireless Systems[M].Cambridge University Press, New York, 2007;

[0008] FE Liu,ZG Wang,ZQ Li,Q Li,S Chen.Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop[J].J.Semicond.,2014,35(10):105006.doi:10.1088 / 1674-4926 / 35 / 10 / 105006.

[0009] Nanda,U.,Acharya,DP&Patra,SKDesign of an efficient phasefrequency detector to reduce blind zone in a PLL.Microsyst Technol 23,533–539(2017).

[0010] P.Trivedi and BBTiwari, "High Operating Frequency, Low-Power PFD for PLL Applications," 2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT), Delhi, India, 2023, pp.1-5, doi:10.1109 / ICCCCNT56998.2023.10307191. Summary of the Invention

[0011] The present invention aims to provide a phase-locked loop for adaptively adjusting the dead zone of a phase frequency detector to solve the problems existing in the above-mentioned prior art. It can compensate for the dead zone of the phase frequency detector while minimizing its blind zone as much as possible, thus achieving a better compromise.

[0012] The present invention provides a phase-locked loop for adaptively adjusting the dead zone of a phase frequency detector, comprising a phase frequency detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator, which are sequentially connected in signal connection; a frequency divider is provided between the output side of the voltage-controlled oscillator and the input side of the phase frequency detector to form a feedback loop;

[0013] A first capacitor is set to sample and compare the charging current of the charge pump: the sampling end of the first capacitor is respectively connected to the inverting input end of the first comparator, is grounded through the third switch, and samples the charging current through the first switch; the other end of the first capacitor is grounded;

[0014] A second capacitor is set to sample and compare the discharge current of the charge pump: a sampling end of the second capacitor is respectively connected to the non-inverting input end of the second comparator, connected to VDD through the fourth switch, and samples the discharge current through the second switch; the other end of the second capacitor is grounded;

[0015] A digital algorithm module is set to adjust the reset pulse width of the phase frequency detector according to the output results of the first comparator and the second comparator: the non-inverting input terminal of the first comparator is connected to the first reference voltage, and the output terminal of the first comparator is connected to the first input terminal of the digital algorithm module; the inverting input terminal of the second comparator is connected to the second reference voltage, and the output terminal of the second comparator is connected to the second input terminal of the digital algorithm module; the control output terminal of the digital algorithm module is connected to the reset pulse width control input terminal of the phase frequency detector;

[0016] A gating switch is provided to input a reference signal or a feedback signal into the feedback input terminal of the frequency and phase detector according to a gating signal of the digital algorithm module.

[0017] The phase-locked loop (PLL) with adaptive dead-band adjustment for a phase frequency detector (PFD) described in the present invention has the advantage of controlling the PFD's reset pulse width to an optimal value based on the results of two comparators. This approach is adaptable to PLDs of any process node and consistently ensures the narrowest available reset pulse width. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural diagram of a phase-locked loop in the prior art.

[0019] Figure 2 This is a timing diagram of a dead zone in a phase-locked loop in the prior art.

[0020] Figure 3 This is a timing diagram of a phase-locked loop in the prior art that outputs an erroneous signal due to an excessively large reset pulse width.

[0021] Figure 4 It is a structural diagram of the phase-locked loop described in the present invention.

[0022] Figure 5It is a schematic diagram of the reset pulse width adjustment process of the phase-locked loop described in the present invention.

[0023] Figure 6 It is a schematic diagram of the reset pulse width adjustment timing of the phase-locked loop described in the present invention.

[0024] Reference numerals:

[0025] PFD-phase frequency detector, CP-charge pump, LPF-low-pass filter, VCO-voltage controlled oscillator, DIV-divider, PC-digital algorithm module;

[0026] Fref-reference signal, Fdiv-feedback signal, FVCO-voltage controlled oscillator VCO output signal, UP-charge signal, DN-discharge signal, RST-reset pulse signal, V UP -The output result of the first comparator, V UP - output result of the second comparator, Vref1-first reference voltage, Vref2-second reference voltage;

[0027] I UP -Charge pump charging current, I DN - discharge current of the charge pump;

[0028] S0-selector switch, S1-first switch, S2-second switch, S3-third switch, S4-fourth switch;

[0029] C1-first capacitor, C2-second capacitor;

[0030] U1-first comparator, U2-second comparator. DETAILED DESCRIPTION

[0031] like Figure 4 As shown, the present invention discloses a phase-locked loop (PLL) for adaptively adjusting the dead band of a phase frequency detector (PFD), comprising a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), and a voltage-controlled oscillator (VCO) connected in sequence. A frequency divider is provided between the output of the VCO and the input of the PFD to form a feedback loop.

[0032] A first capacitor C1 is set to sample and compare the charging current of the charge pump CP: the sampling end of the first capacitor C1 is connected to the inverting input end of the first comparator U1, grounded through the third switch S3, and samples the charging current through the first switch S1. The other end of the first capacitor C1 is grounded.

[0033] A second capacitor C2 is provided to sample and compare the discharge current of the charge pump CP: a sampling terminal of the second capacitor C2 is connected to the non-inverting input terminal of the second comparator U2, connected to VDD via the fourth switch S4, and samples the discharge current via the second switch S2. The other terminal of the second capacitor C2 is grounded.

[0034] A digital algorithm module PC is configured to adjust the reset pulse width of the phase frequency detector (PFD) based on the outputs of the first comparator U1 and the second comparator U2: the non-inverting input of the first comparator U1 is connected to a first reference voltage Vref1, and the output of the first comparator U1 is connected to the first input of the digital algorithm module PC. The inverting input of the second comparator U2 is connected to a second reference voltage Vref2, and the output of the second comparator U2 is connected to the second input of the digital algorithm module PC. The control output of the digital algorithm module PC is connected to the reset pulse width control input of the phase frequency detector (PFD).

[0035] The selection switch S0 is set to input the reference signal Fref or the feedback signal Fdiv to the feedback input terminal of the phase frequency detector PFD according to the selection signal of the digital algorithm module PC.

[0036] The digital algorithm module PC uses the 3-bit control bit DELAY<2:0> to step-by-step adjust the reset pulse width of the phase frequency detector (PFD). When the 3-bit control bit DELAY<2:0> is 000, the reset pulse width is minimum. When the 3-bit control bit DELAY<2:0> is 111, the reset pulse width is maximum.

[0037] During initialization, the digital algorithm module PC outputs 000 to the phase frequency detector (PFD). The output results of the first comparator U1 and the second comparator U2 are cyclically detected. When the output of the first comparator U1 or the second comparator U2 is 1, the reset pulse width of the phase frequency detector (PFD) is increased step by step until the outputs of the first comparator U1 and the second comparator U2 are both 0. The result of the 3-bit control bit DELAY<2:0> is locked.

[0038] When the digital algorithm module PC performs reset pulse width adjustment, the control gate switch S0 is controlled to select the reference signal Fref and input it to the feedback input terminal of the phase frequency detector PFD. Otherwise, the control gate switch S0 is controlled to select the feedback signal Fdiv and input it to the feedback input terminal of the phase frequency detector PFD, thereby ensuring that the output of the phase frequency detector PFD only has a reset pulse signal.

[0039] The phase-locked loop of the present invention which adaptively adjusts the dead zone of the phase frequency detector completes the reset pulse width control by the following steps: Figure 5 and Figure 6 As shown:

[0040] Step 0. The digital algorithm module PC outputs the minimum value of the 3-bit control bit DELAY<2:0> to the phase and frequency detector PFD.

[0041] Step 1. Open the first switch S1 and the second switch S2. Close the third switch S3 and the fourth switch S4 to discharge the first capacitor C1 to 0 and charge the second capacitor C2 to VDD.

[0042] Step 2. Open the third switch S3 and the fourth switch S4. Close the first switch S1 and the second switch S2. The first comparator U1 compares the voltage of the first capacitor C1 with the first reference voltage Vref1 and outputs the result to the first input terminal of the digital algorithm module PC. The second comparator U2 compares the voltage of the second capacitor C2 with the second reference voltage Vref2 and outputs the result to the second input terminal of the digital algorithm module PC.

[0043] In this step, the charging current I UP The first capacitor C1 is charged and the discharge current I DN The second capacitor C2 will be discharged. The potential on the two capacitors will change according to the size of the charging and discharging current and time. When the pulse width of the phase frequency detector (PFD) has a certain duration, the first capacitor C1 will be charged, causing its potential to increase. When it is less than the first reference voltage Vref1, the first comparator U1 will continue to output the result as 1 until it increases to exceed the first reference voltage Vref1. At this time, the output result of the first comparator U1 is 0. Similarly, when the discharge pulse width reaches the requirement, the potential on the second capacitor C2 will be less than the second reference voltage Vref2. At this time, the output result of the second comparator U2 will also be 0, otherwise it will continue to output 1.

[0044] Step 3. The digital algorithm module PC determines whether the outputs of the first comparator U1 and the second comparator U2 are both 0. If so, the current value of the 3-bit control bits DELAY<2:0> is fixed as the final result and the process ends. Otherwise, the 3-bit control bits DELAY<2:0> are incremented by 1 and the process returns to Step 1.

[0045] Those skilled in the art can make various other corresponding changes and deformations based on the technical solutions and concepts described above, and all of these changes and deformations should fall within the scope of protection of the claims of the present invention.

Claims

1. A phase-locked loop (PLL) for adaptively adjusting a phase frequency detector (PFD) dead zone, comprising a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), and a voltage-controlled oscillator (VCO) connected in sequence; a frequency divider is provided between the output of the voltage-controlled oscillator (VCO) and the input of the PFD to form a feedback loop; It is characterized in that A first capacitor (C1) is provided to sample and compare the charging current of the charge pump (CP): a sampling end of the first capacitor (C1) is respectively connected to the inverting input end of the first comparator (U1), is grounded via a third switch (S3), and samples the charging current via the first switch (S1); the other end of the first capacitor (C1) is grounded; A second capacitor (C2) is provided to sample and compare the discharge current of the charge pump (CP): a sampling end of the second capacitor (C2) is respectively connected to the non-inverting input end of the second comparator (U2), connected to VDD via a fourth switch (S4), and samples the discharge current via the second switch (S2); The other end of the second capacitor (C2) is grounded; A digital algorithm module (PC) is set to adjust the reset pulse width of the phase frequency detector (PFD) according to the output results of the first comparator (U1) and the second comparator (U2): the first comparator (U1) non-inverting input terminal is connected to the first reference voltage (Vref1), and the first comparator (U1) output terminal is connected to the first input terminal of the digital algorithm module (PC); the second comparator (U2) inverting input terminal is connected to the second reference voltage (Vref2), and the second comparator (U2) output terminal is connected to the second input terminal of the digital algorithm module (PC); the digital algorithm module (PC) control output terminal is connected to the reset pulse width control input terminal of the phase frequency detector (PFD); A strobe switch (S0) is set to input a reference signal (Fref) or a feedback signal (Fdiv) into a feedback input terminal of the phase frequency detector (PFD) according to a strobe signal of a digital algorithm module (PC).

2. A phase-locked loop for adaptively adjusting the dead zone of a phase frequency detector according to claim 1, characterized in that: The digital algorithm module (PC) uses the 3-bit control bit DELAY<2:0> to step-by-step adjust the reset pulse width of the phase frequency detector (PFD); when the 3-bit control bit DELAY<2:0> is 000, the reset pulse width is minimum; When the 3-bit control bit DELAY<2:0> is 111, the reset pulse width is the maximum; During initialization, the digital algorithm module (PC) outputs 000 to the phase frequency detector (PFD); the output results of the first comparator (U1) and the second comparator (U2) are cyclically detected. When the output of the first comparator (U1) or the second comparator (U2) is 1, the reset pulse width of the phase frequency detector (PFD) is increased step by step until the outputs of the first comparator (U1) and the second comparator (U2) are both 0, and the result of the 3-bit control bit DELAY<2:0> is locked.

3. A phase-locked loop for adaptively adjusting the dead zone of a phase frequency detector according to claim 2, characterized in that: When the digital algorithm module (PC) performs reset pulse width adjustment, the gating switch (S0) is controlled to select a reference signal (Fref) to be input to a feedback input end of a phase frequency detector (PFD); otherwise, the gating switch (S0) is controlled to select a feedback signal (Fdiv) to be input to the feedback input end of the phase frequency detector (PFD).

4. A phase-locked loop for adaptively adjusting the dead zone of a phase frequency detector according to claim 3, characterized in that: The reset pulse width control is accomplished by the following steps: Step 0. The digital algorithm module (PC) outputs the minimum value of the 3-bit control bits DELAY<2:0> to the phase frequency detector (PFD); Step 1. Disconnect the first switch (S1) and the second switch (S2); close the third switch (S3) and the fourth switch (S4) to discharge the first capacitor (C1) and charge the second capacitor (C2); Step 2. Open the third switch (S3) and the fourth switch (S4); close the first switch (S1) and the second switch (S2); the first comparator (U1) compares the voltage of the first capacitor (C1) with the first reference voltage (Vref1) and outputs the result to the first input terminal of the digital algorithm module (PC); the second comparator (U2) compares the voltage of the second capacitor (C2) with the second reference voltage (Vref2) and outputs the result to the second input terminal of the digital algorithm module (PC); Step 3. The digital arithmetic module (PC) determines whether the output results of the first comparator (U1) and the second comparator (U2) are both 0. If so, the current value of the 3-bit control bit DELAY<2:0> is fixed as the final result and the process ends. If not, the 3-bit control bit DELAY<2:0> is incremented by 1 and the process returns to Step 1.

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