Asynchronous parallel processing method and system for address correlation in superscalar processor

Abstract

The invention discloses an asynchronous parallel processing method and system for address correlation in a superscalar processor, after an instruction data packet enters a transmitting unit, instructions are sent to a corresponding transmitting queue according to the type of each instruction, the transmitting queue requests to transmit the instructions in a polling mode, and when the selected instruction meets a transmitting condition, the selected instruction is transmitted; in one round of instructions, the Load instructions are grouped by taking the Store instructions as boundaries, and the Load instructions in the groups are executed out of order; after the memory access instruction enters the memory access stage, when the Store instruction is executed, the Store instruction is temporarily stored in the buffer table, when the Load instruction is executed, whether address correlation exists between the current Load instruction and the Store instruction in the buffer table or not is detected, if the address correlation does not exist, the internal access number is accessed, and if the address correlation exists, the number is fetched from the buffer table. On the basis of the design of the asynchronous circuit, a memory access instruction part out-of-order execution and memory access instruction address correlation processing mechanism is introduced, the memory access instruction throughput efficiency of the superscalar processor is improved, and the instruction execution speed and processing efficiency are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of processors, and in particular relates to an asynchronous parallel processing method and system for address correlation in a superscalar processor. Background Art

[0002] As computing tasks become more complex, superscalar processors widely use designs that execute multiple instructions in parallel to improve performance. However, as the complexity of instruction execution increases, address correlation in memory access has become a key bottleneck limiting processor parallelism. Address correlation refers to the data dependency generated when multiple instructions access the same memory address during execution. This dependency imposes restrictions on the execution order of instructions, requiring the processor to judge and coordinate the access order before execution to ensure data consistency. When address correlation occurs in memory access instructions, it is usually accompanied by three types of data hazards: read after write (WAR), write after read (RAW), and write after write (WAW). Each type of dependency requires instructions to be executed in sequence, thereby reducing the efficiency of instruction parallel processing.

[0003] Existing technologies mainly deal with address dependencies through two methods: address prediction and hardware detection, attempting to alleviate the limitation of such dependencies on parallelism. The address prediction method attempts to predict the memory address to be accessed and put the data into the cache in advance so that it can be quickly accessed when the instruction arrives. For example, the step prediction method is applicable to the case where the memory access pattern is fixed, and improves parallelism by predicting the access address of the fixed step length; while the last value prediction method assumes that the next access address is the same as the previous one, and is applicable to access scenarios with less regularity. These methods can effectively reduce access latency in specific applications, but the prediction accuracy is low in dynamically changing or complex memory access patterns, which limits processing efficiency. Hardware detection technology introduces dedicated hardware units in the processor to quickly detect whether there is an address conflict between the instructions to be executed, and usually solves the address dependency problem through dynamic scheduling or out-of-order execution. For example, the scoreboard method maintains a record table inside the processor to track the status of each register or memory address to determine whether there is a conflict. The Tomasulo algorithm tracks the data dependency of each instruction through tags, supports dynamic instruction scheduling, and thus reduces the waiting time caused by dependencies. In addition, the load-store queue is specifically used for dependency detection of load and store instructions, dynamically handling dependencies by detecting whether load and store instructions access the same address. These hardware detection methods have significant effects on performance, but they consume more hardware resources and increase the power consumption of the processor, which is particularly difficult to implement in power-sensitive devices.

[0004] To meet the above challenges, asynchronous architecture has been gradually introduced into the design of superscalar processors, becoming a new option for solving address correlation. The asynchronous architecture manages instruction scheduling in an event-driven manner and does not rely on a unified global clock signal. Unlike the synchronous architecture, the asynchronous processor can flexibly arrange the execution order according to the completion status of the instruction, thereby more efficiently handling the address correlation between instructions. This clock-free design significantly reduces the system's clock jitter and offset problems, can effectively reduce power consumption, and improve system stability. However, when a superscalar processor executes instructions in parallel, there are often multiple Laod instructions or Store instructions in a round of instructions that are processed in parallel, and there are address correlations among them; the existing asynchronous processing technology still lacks precise control means when processing complex address dependencies, and it is difficult to achieve optimal performance in high parallel situations. Multiple Laod instructions and Store instructions are executed in sequence, affecting processor efficiency. Summary of the invention

[0005] In view of the problems existing in the above-mentioned background technology, the purpose of the present invention is to provide an asynchronous parallel processing method and system for address correlation in a superscalar processor, so as to improve the parallel execution efficiency of instructions of the processor under complex address dependencies.

[0006] In order to achieve the above object, the present invention adopts the following technical solution: An asynchronous parallel processing method for address correlation in a superscalar processor comprises the following steps: In the emission phase of the instruction execution cycle, after the instruction data packet enters the emission unit, the emission unit top level parses the type of each instruction, obtains the existence sequence of the Store instruction, and then sends the Store instruction to the Store emission queue, and sends the existence sequence of the Store instruction and the Load instruction to the Load emission queue; the emission queue uses a polling method to request the emission instruction, and emits it when the selected instruction meets the emission conditions; In a round of instructions, when the operands of the Store instruction are ready, it can be sent to the execution stage to execute the instruction. After the Store instruction is executed, the instruction number of the Store instruction is returned to the existing sequence of the Store instruction. For Load instructions, the Store instruction is used as the boundary to group them, and the Load instructions in the group are executed out of order. When the operands of the Load instruction are ready and all the Store instructions before the Load instruction are executed, it can be sent to the execution stage to execute the instruction. In the memory access phase of the instruction execution cycle, the Store Buffer table is set. After the instruction data and event signal enter the memory access phase, the Store Buffer table is used to store the data, address, type, valid bit and instruction number of the Store instruction when the Store instruction is executed. When executing the subsequent Load instruction, it is detected whether there is an address correlation between the Load instruction being executed and the Store instruction in the StoreBuffer table. If there is an address correlation, data is directly taken from the StoreBuffer table. If there is no address correlation, the memory is accessed to retrieve the data.

[0007] Furthermore, in a round of instructions, the Store instructions are executed out of order, and then the data, address, type, valid bit and instruction number of the Store instructions are temporarily stored in the Store Buffer buffer table, and the Store instructions are submitted sequentially in the subsequent exit stage.

[0008] Furthermore, after the instruction data packet enters the memory access stage, the instruction type is first determined. If it is Store instruction data, it is stored. If it is Load instruction data, the address correlation between the Load instruction data and the stored Store instruction data is detected, and then the data is taken out according to the address correlation result and the instruction is submitted.

[0009] Furthermore, the highest bit of the instruction data packet is set to distinguish the type code of the Store instruction and the Load instruction, and the instruction type can be determined by detecting the type code of the highest bit of the data packet.

[0010] The present invention further provides an asynchronous parallel processing system for address correlation in a superscalar processor, including an instruction address correlation processing module in a memory access stage, which is used to process input instruction data and event signals, and the instruction address correlation processing module includes: Data_select module: used to determine whether the input instruction data is Store instruction data or Load instruction data; if it is Store instruction data, the Data_select module directly sends the Store instruction data and event signal to the Store_Buffer module for storage; if it is Load instruction data, the Data_select module sends the Load instruction data and event signal to the Addr_check module; Store_Buffer module: sets the Store Buffer table to store Store instruction data and event signals; Addr_check module: used to detect whether the current Load instruction data has address correlation with the previous Store instruction data; after receiving the Load instruction data and event signal sent by the Data_select module, the Addr_check module sends request data to the Store_Buffer module, and the Store_Buffer module sends the data stored in the current Store Buffer buffer table back to the Addr_check module. After receiving the data stored in the Store Buffer buffer table, the Addr_check module starts to detect whether the instruction has address correlation. If there is address correlation, the data is directly taken from the Buffer row corresponding to the most recent Store instruction with address correlation and sent to the Output To_Rou module. If there is no address correlation, the Load instruction address data and event signal are sent to the Sram module to obtain data; Sram module: used to receive the Load instruction address data and event signal data sent by the Addr_check module and store the Store address data sent by the Store_Buffer module, and submit the data to the Output To_Rou module after taking out the data; Output To_Rou module: used to submit instructions. When the Store instruction is submitted, the Output To_Rou module sends the instruction number and event signal of the store instruction to the Store_Buffer module. After receiving it, the Store_Buffer module sends the Store address data of the corresponding row to the Sram module for storage. The Sram module then submits the data to the Output To_Rou module.

[0011] Furthermore, the Store_Buffer module includes three input interfaces and two output interfaces. The three input interfaces are respectively a Store instruction data input interface, a correlation detection read Buffer request input interface, and an outgoing Store instruction number input interface. The two output interfaces are respectively a correlation detection read Buffer data output interface and an outgoing Store address data output.

[0012] Furthermore, the method for detecting whether the instruction has address correlation is as follows: the valid bit of the Store instruction in the Store_Buffer module is set to 1, and the valid bits of the remaining instructions are set to 0; the number of detection sub-modules Checker equal to the number of Buffer rows in the Store_Buffer module is set in the Addr_check module; Load instruction data is input to each detection sub-module Checker respectively and parallel detection is performed with the corresponding Buffer row data; if the valid bit of the data of the current Buffer row is 1 and the address is the same as the address of the Load instruction, and the instruction number of the Load instruction is greater than the instruction number of the Store instruction, the instruction has address correlation, and the address correlation signal output by the detection sub-module Checker is 1, otherwise it is 0, and then the address correlation signal is sent to the priority selection circuit in sequence.

[0013] Furthermore, multiple Addr_check modules are provided in the instruction address correlation processing module, which can further improve the throughput speed and parallel execution degree of the Load instructions in the instruction queue.

[0014] Compared with the shortcomings and deficiencies of the prior art, the present invention has the following beneficial effects: 1. The present invention adopts a partially out-of-order memory access instruction execution method, which can effectively improve the concurrency of the Load memory access instruction execution and improve the memory access instruction throughput efficiency of the superscalar processor. At the same time, through the asynchronous circuit design, highly parallel processing of instructions can be achieved, which can ensure the improvement of processing efficiency on the basis of low power consumption; 2. The present invention adopts an instruction address correlation processing design to reduce the number of times the Load instruction accesses the memory, effectively improving the execution speed of the superscalar processor; 3. The present invention adopts an asynchronous circuit of a two-phase single-rail self-timing Click controller family based on a bounded data binding handshake protocol to implement the module's detection of instruction address relevance. The clock-free asynchronous architecture uses a "request-response" event-driven mechanism to enable each module to operate independently according to actual needs, reducing the high-frequency switching caused by the synchronous clock, thereby significantly reducing system power consumption; in addition, the BBD handshake protocol can not only ensure precise synchronization between modules, but also maintain stability in a low-power environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of partially out-of-order execution of instructions provided by an embodiment of the present invention; Figure 2 is a structural diagram of an instruction address correlation processing module provided by an embodiment of the present invention; Figure 3It is a schematic diagram of the Addr_check module provided by an embodiment of the present invention performing parallel detection of address correlation. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0017] A method for asynchronous parallel processing of address dependencies in a superscalar processor: According to the principle of locality, the Load instructions and Store instructions with address correlation are usually very close in the instruction sequence. Therefore, when the superscalar processor executes instructions in parallel, there are often multiple Load instructions or Store instructions in one round of instructions that are processed in parallel, and there are address correlations. For a Load instruction and a Store instruction before it, if there is address correlation (that is, the destination addresses of the two instructions are the same), the Load instruction must fetch data after the previous Store instruction is executed; and for a Load instruction and multiple Store instructions before it, if there is address correlation (that is, the destination addresses of these instructions are the same), the Load instruction must fetch data after the Store instruction closest to the Load instruction is executed. Otherwise, the Load instruction will fetch wrong data from the memory. The mechanism of superscalar parallel execution of instructions also puts forward requirements for the execution order of Store instructions, because it must ensure that the processor can write correct data to the memory. Therefore, if there are multiple Store instructions to the same destination address in one round of instructions, the last Store instruction among these Store instructions must be executed last to ensure that the correct data is written to the memory.

[0018] In the emission phase of the instruction execution cycle, after the instruction data packet enters the emission unit, the emission unit top level parses the type of each instruction, obtains the existence sequence of the Store instruction, and then sends the Store instruction to the Store emission queue, and sends the existence sequence of the Store instruction and the Load instruction to the Load emission queue. The existence sequence of the Store instruction can be set in a similar array form. Taking the similar array form as an example, taking 16 instructions as an example, the 16 instructions correspond to positions 0 to 15, the corresponding position of the Store instruction existence sequence is 1, and the corresponding position of the remaining instruction existence sequence is 0. The emission queue uses polling to request the emission of instructions, and emits when the selected instruction meets the emission conditions.

[0019] In order to improve the parallelism of instructions and the speed of instruction execution, the present invention adopts a partially out-of-order instruction execution method. In one round of instructions, when the operands of the Store instruction are ready, it can be sent to the execution stage to execute the instruction. After the Store instruction is executed, the instruction number of the Store instruction is returned to the existing sequence of the Store instruction, and then the corresponding position of the Store instruction existing sequence is set from 1 to 0. For Load instructions, the Store instruction is used as the boundary to group, and the Load instructions in the group are executed out of order. When the operands of the Load instruction are ready and all the Store instructions before the Load instruction are executed, it can be sent to the execution stage to execute the instruction.

[0020] As a further improvement of this embodiment, in a round of instructions, Store instructions can also be executed out of order, and then the data, address, type, valid bit and instruction number of the Store instruction are temporarily stored in the Store Buffer buffer table, waiting for the submission signal of the exit stage and for subsequent Load instruction address correlation detection. The Store instruction only needs to be submitted sequentially in the final exit stage.

[0021] like Figure 1 The diagram of partial out-of-order execution of instructions shown in the figure shows that in the execution stage, all Store instructions can be executed out of order; Load instructions 1 and 2 must be executed after Store instruction 1 is executed, and Load instructions 1 and 2 can be executed out of order; Load instructions 3, 4, and 5 must be executed after Store instructions 1, 2, and 3 are executed, and Load instructions 3, 4, and 5 can be executed out of order.

[0022] In the instruction stream, Store instructions and Load instructions usually appear in pairs and point to the same address. Therefore, when there is a Store instruction before a Load instruction, and the addresses of both instructions point to the same address space, if the data is recorded directly from the execution process of the Store instruction, and then the data is directly used when the Load instruction is executed, the number of times the processor accesses the memory can be reduced, and the instruction processing efficiency of the processor can be improved. In the memory access phase of the instruction execution cycle, the Store Buffer buffer table is set. After the instruction data and event signal enter the memory access phase, when executing the Store instruction, the data, address, type, valid bit and instruction number of the Store instruction are stored in the Store Buffer buffer table. When executing the subsequent Load instruction, it is detected whether there is an address correlation between the Load instruction being executed and the Store instruction in the Store Buffer buffer table. If there is an address correlation, the data is directly fetched from the Store Buffer buffer table. If there is no address correlation, the memory is accessed to fetch the data.

[0023] After the instruction data packet enters the memory access stage, the instruction type is first determined. The type code that distinguishes between Store instructions and Load instructions can be set in the highest bit of the instruction data packet. The instruction type can be determined by detecting the type code in the highest bit of the data packet. If it is Store instruction data, it is stored. If it is Load instruction data, the address correlation between the Load instruction data and the stored Store instruction data is detected, and then the data is retrieved according to the address correlation result and the instruction is submitted.

[0024] In order to implement the asynchronous parallel processing method of address correlation in the above-mentioned superscalar processor, the present invention provides an asynchronous parallel processing system of address correlation in a superscalar processor, which includes an instruction address correlation processing module in the memory access stage for processing input instruction data and event signals.

[0025] Reference Figure 2 , the instruction address correlation processing module includes: Data_select module: used to determine whether the input instruction data is Store instruction data or Load instruction data. Generally, the type code to distinguish between Store instruction and Load instruction is set in the highest bit of the instruction data packet, 1 for Store instruction and 0 for Load instruction. If it is Store instruction data Inst_Store, the Data_select module directly sends the Store instruction data and event signal to the Store_Buffer module for storage; if it is Load instruction data Inst_Load, the Data_select module sends the Load instruction data and event signal to the Addr_check module; Store_Buffer module: Set up the Store Buffer table to store Store instruction data and event signals; because the Store instruction is temporarily stored in the Store Buffer table after execution, waiting for the subsequent OutputTo_Rou module to submit in sequence, it can be executed out of order in the execution phase (assuming that the register data is ready); Addr_check module: used to detect whether the current Load instruction data Inst_Load has address correlation with the previous Store instruction data Inst_Store; after receiving the Load instruction data Inst_Load and event signal sent by the Data_select module, the Addr_check module sends request data Require to the Store_Buffer module, and the Store_Buffer module sends the data Buffer_Data stored in the current Store Buffer buffer table back to the Addr_check module. After receiving the data Buffer_Data, the Addr_check module starts to detect whether the instruction has address correlation. If there is address correlation, the data Load_Data is directly taken out from the Buffer row corresponding to the most recent Store instruction with address correlation and sent to the Output To_Rou module. If there is no address correlation, the Load instruction address data and event signal are sent to the Sram module to obtain the data Load_Req; Sram module: used to receive the Load instruction address data and event signal Load_Req sent by the Addr_check module and store the Store address data Soad_Data sent by the Store_Buffer module, and submit the data L_Data to the Output To_Rou module after taking out the data; Output To_Rou module: used to submit instructions. When the Store instruction is submitted, the Output To_Rou module sends the instruction number and event signal of the Store instruction to the Store_Buffer module. After receiving it, the Store_Buffer module sends the Store address data Soad_Data of the corresponding row to the Sram module for storage. The Sram module then submits the data L_Data to the Output To_Rou module.

[0026] In the instruction address correlation processing module of the present invention, the Store_Buffer module is designed with three input interfaces and two output interfaces. The three input interfaces are respectively the Store instruction data input interface, the correlation detection read buffer request input interface, and the outgoing Store instruction number (Input Rou_index) input interface, and the two output interfaces are respectively the correlation detection read buffer data output interface and the outgoing Store address data output. However, in the specific design, the input and output interfaces can be increased or decreased according to the architecture and module expansion.

[0027] Since the instruction address correlation processing module of the present invention is implemented by an asynchronous circuit of a two-phase single-rail self-timing Click controller family based on the bounded data binding (BBD) handshake protocol, it can effectively realize clock-free control. Its clock-free asynchronous architecture uses a "request-response" event-driven mechanism to enable each module to operate independently according to actual needs, reducing the high-frequency switching caused by the synchronous clock, thereby significantly reducing system power consumption. In the detection of whether the instruction has address correlation, when the Addr_check module receives the top-level Load instruction data, it sends request data Require to the Store_Buffer module to retrieve the data Buffer_Data stored in the Store Buffer buffer table. After receiving the data, the data is split for parallel detection, referring to Figure 3 The specific method is: set the valid bit of the Store instruction in the Store_Buffer module to 1, and the valid bits of the other instructions to 0. Take 16 lines of Buffer data as an example, and instantiate 16 detection submodules Checker inside the Addr_check module, namely Checker_0~ Checker_15. Based on the BBD type asynchronous circuit, setting 16 detection submodules Checker will not increase the occupied space. The BBD handshake protocol can not only ensure the precise synchronization between the modules, but also reduce power consumption and maintain stability in a low-power environment. Load instruction data and 0~15 rows of Buffer data are input to Checker_0~Checker_15 respectively for parallel detection. If the valid bit of the data in the current Buffer row is 1 and the address is the same as the Load instruction address, and the instruction number of the Load instruction is greater than the instruction number of the Store instruction, the instruction has address correlation, and the address correlation signal Sign output by the detection submodule Checker is 1, otherwise it is 0. Checker_0~Checker_15 respectively generate Sign_0~Sign_15, and then send the address correlation signal Sign to the priority selection circuit Priority selector (the priority can be set according to actual needs). If the instruction has address correlation (at least one of the address correlation signals is 1), the instruction number of the relevant Store instruction closest to the Load instruction is output, and the data Load_Data is taken out from the corresponding row and sent directly to the Output To_Rou module; if the instruction does not have address correlation, the Load instruction address data and the event signal Load_Req are sent to the Sram module to fetch the data, and then sent to the OutputTo_Rou module by the Sram module.

[0028] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for asynchronous parallel processing of address dependencies in a superscalar processor, characterized in that: The steps include: In the emission phase of the instruction execution cycle, after the instruction data packet enters the emission unit, the emission unit top level parses the type of each instruction, obtains the existence sequence of the Store instruction, and then sends the Store instruction to the Store emission queue, and sends the existence sequence of the Store instruction and the Load instruction to the Load emission queue; the emission queue uses a polling method to request the emission instruction, and emits it when the selected instruction meets the emission conditions; In a round of instructions, when the operands of the Store instruction are ready, it can be sent to the execution stage to execute the instruction. After the Store instruction is executed, the instruction number of the Store instruction is returned to the existing sequence of the Store instruction. For Load instructions, the Store instruction is used as the boundary to group, and the Load instructions in the group are executed out of order. When the operands of the Load instruction are ready and all the Store instructions before the Load instruction are executed, it is sent to the execution stage to execute the instruction. In the memory access phase of the instruction execution cycle, the Store Buffer table is set. After the instruction data and event signal enter the memory access phase, the Store Buffer table is used to store the data, address, type, valid bit and instruction number of the Store instruction when the Store instruction is executed. When executing the subsequent Load instruction, it is detected whether there is an address correlation between the Load instruction being executed and the Store instruction in the StoreBuffer table. If there is an address correlation, data is directly taken from the StoreBuffer table. If there is no address correlation, the memory is accessed to retrieve the data.

2. The method for asynchronous parallel processing of address dependencies in a superscalar processor according to claim 1, wherein: In a round of instructions, Store instructions are executed out of order, and then the data, address, type, valid bit and instruction number of the Store instruction are temporarily stored in the Store Buffer buffer table. The Store instructions are submitted sequentially in the subsequent exit stage.

3. The method for asynchronous parallel processing of address dependencies in a superscalar processor according to claim 1, wherein: After the instruction data packet enters the memory access stage, the instruction type is first determined. If it is Store instruction data, it is stored. If it is Load instruction data, the address correlation between the Load instruction data and the stored Store instruction data is detected, and then the data is taken out according to the address correlation result and the instruction is submitted.

4. The method for asynchronous parallel processing of address dependencies in a superscalar processor according to claim 3, characterized in that: The highest bit of the instruction data packet is used to set a type code to distinguish between a Store instruction and a Load instruction. The instruction type can be determined by detecting the type code of the highest bit of the data packet.

5. An address-dependent asynchronous parallel processing system in a superscalar processor implementing the asynchronous parallel processing method according to any one of claims 1 to 4, characterized in that: An instruction address correlation processing module is included in the memory access stage, which is used to process input instruction data and event signals. The instruction address correlation processing module includes: Data_select module: used to determine whether the input instruction data is Store instruction data or Load instruction data; if it is Store instruction data, the Data_select module directly sends the Store instruction data and event signal to the Store_Buffer module for storage; if it is Load instruction data, the Data_select module sends the Load instruction data and event signal to the Addr_check module; Store_Buffer module: sets the Store Buffer table to store Store instruction data and event signals; Addr_check module: used to detect whether the current Load instruction data has address correlation with the previous Store instruction data; after receiving the Load instruction data and event signal sent by the Data_select module, the Addr_check module sends request data to the Store_Buffer module, and the Store_Buffer module sends the data stored in the current Store Buffer buffer table back to the Addr_check module. After receiving the data stored in the Store Buffer buffer table, the Addr_check module starts to detect whether the instruction has address correlation. If there is address correlation, the data is directly taken from the Buffer row corresponding to the most recent Store instruction with address correlation and sent to the Output To_Rou module. If there is no address correlation, the Load instruction address data and event signal are sent to the Sram module to obtain data; Sram module: used to receive the Load instruction address data and event signal data sent by the Addr_check module and store the Store address data sent by the Store_Buffer module, and submit the data to the Output To_Rou module after taking out the data; Output To_Rou module: used to submit instructions. When the Store instruction is submitted, the Output To_Rou module sends the instruction number and event signal of the store instruction to the Store_Buffer module. After receiving it, the Store_Buffer module sends the Store address data of the corresponding row to the Sram module for storage. The Sram module then submits the data to the Output To_Rou module.

6. The address-dependent asynchronous parallel processing system in a superscalar processor according to claim 5, characterized in that: The Store_Buffer module includes three input interfaces and two output interfaces. The three input interfaces are respectively a Store instruction data input interface, a correlation detection read Buffer request input interface, and an outgoing Store instruction number input interface. The two output interfaces are respectively a correlation detection read Buffer data output interface and an outgoing Store address data output.

7. The address-dependent asynchronous parallel processing system in a superscalar processor according to claim 5, wherein: The method for detecting whether the instruction has address correlation is as follows: in the Store_Buffer module, the valid bit of the Store instruction is set to 1, and the valid bits of the other instructions are set to 0; in the Addr_check module, a number of detection sub-modules Checker equal to the number of Buffer rows in the Store_Buffer module is set; Load instruction data is input to each detection sub-module Checker respectively and parallel detection is performed with the corresponding Buffer row data; if the valid bit of the data of the current Buffer row is 1 and the address is the same as the address of the Load instruction, and the instruction number of the Load instruction is greater than the instruction number of the Store instruction, it means that the instruction has address correlation, and the address correlation signal output by the detection sub-module Checker is 1, otherwise it is 0, and then the address correlation signal is sent to the priority selection circuit in sequence.

8. The address-dependent asynchronous parallel processing system in a superscalar processor according to claim 5, wherein: A plurality of Addr_check modules are arranged in the instruction address dependency processing module.

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