A monolithic 3D integrated circuit layout method, apparatus, device and medium

Abstract

The application discloses a monolithic 3D integrated circuit layout method, device, equipment and medium, and relates to the technical field of layout and wiring, to solve the problem of excessive total length of the connection line of the existing 3D integrated circuit layout. The method comprises the following steps: obtaining unit information of an integrated circuit to be laid out; determining a first root unit and a unit to be distributed; for any one unit in the unit to be distributed, determining the area of a current first circuit layer and a second circuit layer according to the unit width and the unit height, and determining the circuit layer with smaller area as a target circuit layer of the unit to be distributed; based on the connection information and the port coordinates, determining the position of the unit to be distributed in the target circuit layer as a target position when the total length of the connection line of the 3D integrated circuit is the shortest; and sequentially determining the target circuit layer and the target position of the remaining units, to complete the layout of the 3D integrated circuit. The monolithic 3D integrated circuit layout method provided by the application is used for shortening the total length of the connection line of the 3D integrated circuit, and improving the performance of the 3D integrated circuit.

Description

Technical Field

[0001] The present invention relates to the field of layout and wiring technology, and in particular to a monolithic 3D integrated circuit layout method, device, equipment and medium. Background Art

[0002] 3D integrated circuits, also known as stereoscopic integrated circuits or three-dimensional integrated circuits, are a technology that vertically stacks multiple layers of chips and interconnects them through tiny through-holes.

[0003] Existing 3D integrated circuit layout typically converts a 2D circuit netlist into a hypergraph, then calculates the hypergraph's weight. Each cell and line length is assigned a numerical value, and the line lengths are sorted from longest to shortest. If a line length is greater than the via between the upper and lower layers of the monolithic 3D circuit, the circuit is split, and the split cells are placed in a new circuit layer to create a new hypergraph, which is then converted into a 3D netlist. Because the division between cells is based solely on line length, if a hyperedge connects multiple hyperedges, cutting based on this principle can easily result in a longer total line length.

[0004] Therefore, there is an urgent need for a monolithic 3D integrated circuit layout method, device, equipment and medium. Summary of the Invention

[0005] The present invention aims to provide a monolithic 3D integrated circuit layout method, apparatus, device and medium for reducing the total area of ​​the 3D integrated circuit and the total connection length.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a monolithic 3D integrated circuit layout method, comprising:

[0008] Obtaining cell information of each cell of the integrated circuit to be laid out; the cell information includes cell height, cell width, connection information, and port coordinates;

[0009] Determine a first root unit and units to be allocated according to the connection information; the first root unit is the unit with the largest number of connected units; the units to be allocated are multiple units connected to the first root unit;

[0010] For any one of the units to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with the smaller area as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit;

[0011] Based on the connection information and the port coordinates, determining a position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as a target position;

[0012] The target circuit layers and target positions of the remaining units are determined in sequence to complete the 3D integrated circuit layout.

[0013] Compared with the prior art, the present invention provides a monolithic 3D integrated circuit layout method, which includes obtaining unit information of each unit of the integrated circuit to be laid out; determining a first root unit and a unit to be allocated based on connection information; for any unit in the units to be allocated, determining the areas of the current first circuit layer and the second circuit layer based on the unit width and the unit height, and determining the circuit layer with the smaller area as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in the 3D integrated circuit; based on the connection information and port coordinates, determining the position of the unit to be allocated in the target circuit layer when the total length of the connection line of the 3D integrated circuit is the shortest as the target position; and determining the target circuit layers and target positions of the remaining units in sequence to complete the 3D integrated circuit layout. The present invention effectively reduces the total wiring length of a 3D integrated circuit by first determining a root cell, allocating cells connected to the root cell, and then allocating other cells. Furthermore, the cells are always allocated to the circuit layer with the smallest area. The resulting 3D integrated circuit has two circuit layers with similar areas, meeting preset conditions and effectively reducing the area of ​​the resulting 3D integrated circuit. Furthermore, the location with the smallest total wiring length is always determined as the target location, also shortening the total wiring length of the 3D integrated circuit. The present invention can directly generate a 3D integrated circuit layout based on cell information, without the need for conversion to a 2D circuit, resulting in a simple method.

[0014] Optionally, for any one of the units to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with the smaller area as the target circuit layer for placing the unit to be allocated includes:

[0015] For a first target cell among the cells to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the cell width and cell height, and determining the circuit layer with the smaller area as the target circuit layer for placing the first target cell; the first target cell is the cell with the smallest cell width among the cells to be allocated;

[0016] For the second target unit in the unit to be allocated, the areas of the current first circuit layer and the second circuit layer are determined according to the unit width and the unit height, and the circuit layer with the smaller area is determined as the target circuit layer for placing the second target unit; the second target unit is the unit with the smallest unit width among the units to be allocated except the first target unit; until the target circuit layers of all units in the unit to be allocated are determined.

[0017] Optionally, determining, based on the connection information and the port coordinates, a position of the to-be-allocated unit in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as the target position includes:

[0018] The preset position of the unit to be allocated is determined according to the position of the laid-out unit in the target circuit layer; the laid-out unit is all the units in the target circuit layer whose target positions have been determined; the preset position is arranged along the circumference of the laid-out unit, and the preset position is in contact with one side of the laid-out unit.

[0019] Calculate the total length of the connection corresponding to each preset position according to the port coordinates and connection information;

[0020] The preset position corresponding to the minimum total length of the connection line is determined as the target position.

[0021] Optionally, calculating the total length of the connection corresponding to each preset position according to the port coordinates and the connection information includes:

[0022] determining a first port and a second port connected to each other according to the connection information;

[0023] Based on the first and second ports, the formula is:

[0024] H=|X1-X2|+|Y1-Y2

[0025] Calculating the length of the connection between the first port and the second port;

[0026] Where H is the length of the line between the first port and the second port, X1 is the target horizontal coordinate of the first port, X2 is the target horizontal coordinate of the second port, Y1 is the target vertical coordinate of the first port, and Y2 is the target vertical coordinate of the second port;

[0027] The total length of the wires is determined as the sum of the lengths of all wires.

[0028] Optionally, the first circuit layer is located below the second circuit layer; and before determining, for any one of the units to be allocated, the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with the smaller area as the target circuit layer for placing the unit to be allocated, the method further includes:

[0029] The first root cell is placed in a first circuit layer.

[0030] Optionally, the integrated circuit to be laid out includes a plurality of root cells; and sequentially determining target circuit layers and target positions of remaining cells includes:

[0031] Determine a second root unit; the second root unit is a unit with the largest number of connected units in the integrated circuit to be laid out, excluding the first root unit;

[0032] sequentially determining a target circuit layer and a target position of the second root unit and a unit connected to the second root unit;

[0033] Continue to determine the third root cell in the remaining unassigned cells until the target circuit layers and target positions of all cells in the integrated circuit to be laid out are confirmed.

[0034] Optionally, when the areas of the first circuit layer and the second circuit layer are equal, one of the circuit layers is selected as the target circuit layer of the unit to be allocated.

[0035] In a second aspect, the present invention provides a monolithic 3D integrated circuit layout device, comprising:

[0036] A unit information acquisition module is used to obtain unit information of each unit of the integrated circuit to be laid out; the unit information includes unit height, unit width, connection information and port coordinates;

[0037] a first root unit and to-be-allocated unit determination module, configured to determine a first root unit and to-be-allocated units based on the connection information; the first root unit being the unit with the largest number of connected units; and the to-be-allocated units being the multiple units connected to the first root unit;

[0038] a target circuit layer determination module, configured to determine, for any one of the units to be allocated, the areas of the current first circuit layer and the second circuit layer based on the unit width and the unit height, and determine the circuit layer with the smaller area as the target circuit layer for placement of the unit to be allocated; the first circuit layer and the second circuit layer being two circuit layers vertically stacked in a 3D integrated circuit;

[0039] a target position determining module, configured to determine, based on the connection information and the port coordinates, a position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as a target position;

[0040] The loop module is used to sequentially determine the target circuit layers and target positions of the remaining cells to complete the 3D integrated circuit layout.

[0041] In a third aspect, the present invention provides a monolithic 3D integrated circuit layout device, comprising:

[0042] A communication unit / communication interface, configured to obtain unit information of each unit of the integrated circuit to be laid out; the unit information includes unit height, unit width, connection information, and port coordinates;

[0043] a processing unit / processor, configured to determine a first root unit and units to be allocated according to the connection information; the first root unit is the unit with the largest number of connected units; the units to be allocated are multiple units connected to the first root unit;

[0044] For any one of the units to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with the smaller area as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit;

[0045] Based on the connection information and the port coordinates, determining a position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as a target position;

[0046] The target circuit layers and target positions of the remaining units are determined in sequence to complete the 3D integrated circuit layout.

[0047] In a fourth aspect, the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, and when the instructions are executed, the monolithic 3D integrated circuit layout method is implemented.

[0048] The technical effects achieved by the device-type solution provided in the second aspect, the equipment-type solution provided in the third aspect, and the computer-readable storage medium solution provided in the fourth aspect are the same as those of the method-type solution provided in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0050] Figure 1 This is a schematic diagram of the connection before segmentation in the prior art;

[0051] Figure 2 This is a schematic diagram of the connection after segmentation in the prior art;

[0052] Figure 3 A flow chart of a monolithic 3D integrated circuit layout method provided by the present invention;

[0053] Figure 4 Flowchart of the minimum width arrangement algorithm provided by the present invention;

[0054] Figure 5 A schematic diagram of a 3D integrated circuit structure after placing the inv2 unit and the inv3_1 unit provided by the present invention;

[0055] Figure 6 A schematic diagram of a 3D integrated circuit structure after placement of the inv3_2 unit provided by the present invention;

[0056] Figure 7 A schematic diagram of the 3D integrated circuit structure after placement of the inv8_1 unit provided by the present invention;

[0057] Figure 8 A schematic diagram of a first preset position of the inv8_2 unit provided by the present invention;

[0058] Figure 9 A schematic diagram of the second preset position of the inv8_2 unit provided by the present invention;

[0059] Figure 10 A schematic diagram of a first preset position of the PG unit provided by the present invention;

[0060] Figure 11 A schematic diagram of a second preset position of the PG unit provided by the present invention;

[0061] Figure 12 A schematic diagram of a third preset position of the PG unit provided by the present invention;

[0062] Figure 13 A schematic structural diagram of a monolithic 3D integrated circuit layout device provided by the present invention;

[0063] Figure 14 This is a structural schematic diagram of a monolithic 3D integrated circuit layout device provided by the present invention. DETAILED DESCRIPTION

[0064] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the words "first" and "second" are used in the embodiments of the present invention to distinguish between identical or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are merely used to distinguish between different thresholds and do not limit their order. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean that they are different.

[0065] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0066] In the present invention, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0067] See also Figure 1 and Figure 2 When dividing units, the existing technology only cuts according to the line length of the unit. If a hyperedge connects multiple hyperedges, the following situation is likely to occur: there are four hyperedges A, B, C, and D, and B is connected to A, C, and D. The existing layout method is to cut off the connection between A and B and move B to the top of A. At this time, the length of the connection between B and A is shortened, but the length of the connection between B and C, and B and D will be longer.

[0068] To solve the above problems, the present invention provides a monolithic 3D integrated circuit layout method, device, equipment and medium, such as Figure 3 As shown, the minimum width arrangement algorithm is used. The root cell is first determined, and then the cells connected to the root cell are arranged in ascending order according to the cell width value. The upper and lower layers are compared in area, and the cells are placed in the layer with the smaller area. The cells are placed at the position corresponding to the minimum connection length. Then, it is determined whether the cells connected to the root cell are arranged. If not, the remaining cells connected to the root cell are arranged. If so, it is determined whether all cells are arranged. If so, the arrangement ends. If not, the remaining cells are allocated. The present invention can convert cell information into a 3D integrated circuit layout, shorten the total connection length, and reduce the area. The following is a detailed description.

[0069] Figure 4 A flow chart of a monolithic 3D integrated circuit layout method provided by the present invention, such as Figure 3As shown, a monolithic 3D integrated circuit layout method includes the following steps:

[0070] Step S1: obtaining unit information of each unit of the integrated circuit to be laid out; the unit information includes unit height, unit width, connection information and port coordinates;

[0071] A cell is a component in a 3D integrated circuit. Port coordinates are the coordinates of the port within the cell. The origin of the cell's coordinate system is located at the vertex in the lower right corner of the cell. The cell width is the horizontal axis, and the cell height is the vertical axis. Connection information includes the cells connected to the cell and the corresponding ports connecting two connected cells. All cells have the same cell height. If a circuit layer has multiple rows, the height of each row is the cell height.

[0072] Step S2: determining the first root unit and the unit to be allocated according to the connection information;

[0073] The first root unit is the unit with the largest number of connected units; the units to be allocated are multiple units connected to the first root unit;

[0074] Before step S3, the first root unit is placed in the first circuit layer. At this time, the area of ​​the first circuit layer is the area of ​​the root unit. Since the first circuit layer and the second circuit layer are empty at the beginning, there is no need to determine the target position of the root unit in the first circuit layer.

[0075] Step S3: for any one of the units to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with the smaller area as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit;

[0076] As an optional method, step S3 can be implemented by the following steps:

[0077] Step S31: for a first target cell among the cells to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the cell width and cell height, and determining the circuit layer with the smaller area as the target circuit layer for placing the first target cell; the first target cell is the cell with the smallest cell width among the cells to be allocated;

[0078] As an alternative, use the formula:

[0079] S=max(w1,w2,w3...w i )×(i×h)

[0080] Calculate the area of ​​the first circuit layer or the second circuit layer; where S is the area of ​​the first circuit layer or the area of ​​the second circuit layer, w i is the cell width of the i-th cell, i is the total number of cells in the first circuit layer or the total number of cells in the second circuit layer, h is the cell height, max(w1,w2,w3...w i ) is the cell width with the largest value among all cell widths.

[0081] For example, if the first circuit layer has three rows of cells, the cell height of each cell is 8 mm, the height of each row of cells is the cell height, the cell width of the first row of cells is 11 mm, the width of the second row of cells is 9 mm, and the width of the third row of cells is 13 mm, the total cell height of the first circuit layer is 3×8 mm=24 mm, and the area of ​​the first circuit layer is 13 mm×24 mm=312 mm. 2 .

[0082] Step S32: For the second target unit in the unit to be allocated, determine the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determine the circuit layer with a smaller area as the target circuit layer for placing the second target unit; the second target unit is the unit with the smallest unit width among the units to be allocated except the first target unit; until the target circuit layers of all units in the unit to be allocated are determined.

[0083] It is understandable that the sequence numbers of the above steps are only for explanation of the steps and do not limit the order of the steps, that is, step S32 is not executed immediately after the target circuit layer of the first target unit is determined.

[0084] Step S4: Based on the connection information and the port coordinates, determining the position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as the target position;

[0085] As an optional method, step S4 may include:

[0086] Step S41: determining a preset position of a unit to be allocated according to the position of the laid-out units in the target circuit layer;

[0087] The laid-out cells are all cells in the target circuit layer whose target positions have been determined; the preset positions are arranged along the circumference of the laid-out cells, and the preset positions are in contact with one side of the laid-out cells; or the preset positions partially overlap with the cells in the laid-out cells. It should be noted that "the preset position is in contact with one side of the laid-out cells" means that when the laid-out cells are placed horizontally, the preset position is in contact with any side surface of the laid-out cells, and the side surface is the surface composed of the width side or height side and thickness of the laid-out cells. The preset position is the position where the unit to be allocated can be placed, and "the preset position partially overlaps with the cells in the laid-out cells" means that the unit to be allocated can be placed at the position where the laid-out cells have been laid out. If the position satisfies the shortest total length of the connection, the unit to be allocated is placed at the position, and then the laid-out cells originally located at the position are moved to a position in contact with the side surface of the unit to be allocated.

[0088] Step S42: Calculating the total length of the connection corresponding to each preset position according to the port coordinates and connection information;

[0089] Step S43: determining the preset position corresponding to the minimum total length of the connection line as the target position.

[0090] As an optional method, the above step S42 may include:

[0091] determining a first port and a second port connected to each other according to the connection information;

[0092] According to the first port and the second port, the port coordinates of the first port are converted into the coordinates of the first port in the 3D integrated circuit coordinate system, and the port coordinates of the second port are converted into the coordinates of the second port in the 3D integrated circuit coordinate system. Based on the coordinates of the first port in the 3D integrated circuit coordinate system and the coordinates of the second port in the 3D integrated circuit coordinate system, a semi-perimeter model is used to calculate the length of the connection between the first port and the second port, as shown in formula (1):

[0093] H=|X1-X2|+|Y1-Y2|(1)

[0094] Wherein, H is the length of the connection between the first port and the second port, X1 is the target horizontal coordinate of the first port, X2 is the target horizontal coordinate of the second port, Y1 is the target vertical coordinate of the first port, and Y2 is the target vertical coordinate of the second port; it should be understood that the target horizontal coordinate of the first port is the horizontal coordinate of the first port in the coordinate system of the entire 3D integrated circuit, the target horizontal coordinate of the second port is the horizontal coordinate of the second port in the coordinate system of the entire 3D integrated circuit, the target vertical coordinate of the first port is the vertical coordinate of the first port in the coordinate system of the entire 3D integrated circuit, and the target vertical coordinate of the second port is the vertical coordinate of the second port in the coordinate system of the entire 3D integrated circuit, that is, X1, X2, Y1 and Y2 are all values ​​in the same coordinate system.

[0095] The total length of the wires is determined as the sum of the lengths of all wires.

[0096] Step S5: sequentially determining the target circuit layers and target positions of the remaining cells to complete the 3D integrated circuit layout.

[0097] As an optional manner, the integrated circuit to be laid out includes a plurality of root cells; and sequentially determining target circuit layers and target positions of remaining cells includes:

[0098] Determine a second root unit among the remaining unassigned units; the second root unit is the unit with the largest number of connected units except the first root unit;

[0099] sequentially determining a target circuit layer and a target position of the second root unit and a unit connected to the second root unit;

[0100] Continue to determine the third root cell in the remaining unassigned cells until the target circuit layers and target positions of all cells in the integrated circuit to be laid out are confirmed.

[0101] As an optional manner, when the remaining unallocated units include multiple second root units with the same number of connected units, the unit with the smallest unit width among the multiple second root units is first used as the currently determined root unit for unit allocation.

[0102] As another optional method, the integrated circuit to be laid out includes only one root unit. After the root unit and the units connected to the root unit are allocated, the target circuit layer and target position of the remaining units not connected to the root unit are determined until all units are allocated and the layout of the 3D integrated circuit is output.

[0103] First, determine whether the cells connected to the root are fully arranged: Check whether the cells connected to the root are fully arranged. If any omissions affect the entire circuit. If the cells connected to the root are fully arranged, continue the process to the next step to check whether all cells are fully arranged. If not, jump to step S3.

[0104] Then determine whether all units have been arranged. In a circuit, one root can rarely connect all units. Therefore, after arranging the units connected to the root, it is necessary to check whether there are other unarranged units. If all units have been arranged, the entire process ends. If not, jump to step S2 to continue the process.

[0105] Exemplarily, the integrated circuit to be laid out includes only one root cell: for example, the integrated circuit to be laid out includes only the root cell and cells connected to the root cell; or the number of cells connected to the remaining cells not connected to the root cell is the same.

[0106] As an optional manner, when the areas of the first circuit layer and the second circuit layer are equal, one of the circuit layers is selected as the target circuit layer of the unit to be allocated.

[0107] Through the above steps, it can be seen that the present invention first determines the root unit, and then arranges the units connected to the root in order of unit width from small to large, first allocates the unit with the smallest unit width, and then determines the smallest unit except the unit with the smallest unit width, that is, allocates the unit with the smallest unit width each time, and allocates the root unit and the unit connected to the root unit before allocating other units. This allocation order can effectively reduce the total length of the connection of the 3D integrated circuit, and when allocating, each time it is allocated to the circuit layer with a small area. The area size of the two circuit layers of the 3D integrated circuit finally obtained is similar, which meets the preset conditions and can effectively reduce the area of ​​the formed 3D integrated circuit. In addition, each time the position with the smallest total connection length is determined as the target position, which can also shorten the total length of the connection of the 3D integrated circuit. The present invention can directly generate a 3D integrated circuit layout based on unit information without converting it into a 2D circuit, and the method is simple.

[0108] The technical solution of the present invention is described in detail below by way of examples.

[0109] The integrated circuit to be laid out is an SRAM circuit, including inverters of three sizes: inv2, inv3, and inv8, and a PG transmission gate. The cell information is as follows: the cell height of inv2, inv3, inv8, and PG is the same, 11.88 μm.

[0110] inv2: width 9.755, in(1.06, 5.35), out(8.925, 6.595)

[0111] inv3: width 11.09, in(1.42, 5.375), out(10.18, 5.835)

[0112] inv8: width 25.36, in(1.145, 5.645), out(23.59, 5.555)

[0113] PG: width 41.28, P1 (40.37, 5.89), P2 (1.3, 5.89)

[0114] The integrated circuit to be laid out includes two inv3s: inv3_1 and inv3_2, two inv8s: inv8_1 and inv8_2, and one PG. inv3_1 connects the most units, including inv2, inv3_2, and inv8_1.

[0115] In this example, the number of rows of cells in the circuit layer is limited. Each circuit layer can only arrange components in one row. Therefore, the preset positions are only the left and right sides of any cell in the laid-out cells.

[0116] It should be noted that the coordinates in the above brackets are the coordinates of the port in this unit, the horizontal coordinate is the width value of the port in this unit, the vertical coordinate is the height value of the port in this unit, and the coordinate origin is the vertex in the lower right corner of the unit.

[0117] Step 1: Place inv3_1 in the first circuit layer of the lower layer. The area of ​​the second circuit layer is 0. The area of ​​the first circuit layer is 11.09*11.88. Place inv2 in the second circuit layer. Figure 5 As shown, the layer where inv2 is located is the second circuit layer, and the layer where inv3_1 is located is the first circuit layer. What needs to be understood is Figure 5 This is just a schematic diagram and is arranged in this way to facilitate the display of connection lengths. Since the vertical line connecting two points is the shortest, the length of the connection between inv2 and inv3_1 is: inv2-inv3_1=(6.595-5.375)+1=2.22

[0118] Step 2: Place inv3_2. The area of ​​the second circuit layer is 9.755*11.88, which is less than the area of ​​the first circuit layer 11.09*11.88. Therefore, place inv3_2 on the second circuit layer. Figure 6 As shown, placing inv3_2 on the left side of inv2 can ensure the shortest total length of the connection. The length of the connection between inv3_1 and inv3_2 is: inv3_1-inv3_2=(10.18-1.42)+(9.755-8.925)+1.42+1=7.51.

[0119] Step 3: Place inv8_1. The area of ​​the second circuit layer is (9.755+11.09)*11.88> the area of ​​the first circuit layer is 11.09*11.88. Place inv8_1 on the first circuit layer, as shown in the following example: Figure 7As shown, since the out ports of inv8_1 and inv3_1 are connected, the total length of the connection is the shortest when inv8_1 is placed close to the out port of inv3_1. The length of the connection between inv3_1 and inv8_1 is: inv3_1-inv8_1=(11.09-10.18+1.145)+|5.835-5.645|=2.245.

[0120] Arrangement is completed with inv3_1 as the root, leaving inv8_2 and PG. Since the number of connection units of inv3_2 and inv8_2 is 2, the unit width of inv3_2 is smaller than the unit width of inv8_1, inv8_2 is arranged with inv3_2 as the root.

[0121] Step 4: Place inv8_2. The area of ​​the second circuit layer is (9.755+11.09)*11.88<the area of ​​the first circuit layer is (11.09+25.36)*11.88. Place inv8_2 on the second circuit layer. There are two locations where it can be placed, such as Figure 8 and Figure 9 The dotted line position in Figure 8 The length of the line between the positions in is: inv3_1-inv3_2=7.51

[0122] inv3_2-inv8_2=(11.09-10.18)+(25.36-1.145)+(5.835-5.645)=25.315

[0123] Figure 9 The length of the line connecting the positions in is:

[0124] inv3_1-inv3_2=(1.42+25.36+(9.755-8.925))-(10.18-1.42)+1=19.85

[0125] inv3_2-inv8_2=10.18+1.145+|5.835-5.645|=11.515

[0126] Since: 7.51+25.315>19.85+11.515, Figure 9 The length of the line connecting the positions in is less than Figure 8 The length of the connection position in the Figure 9 At the dotted line position in .

[0127] Step 5: Place PG, second circuit layer area (11.09 + 9.755 + 25.36) * 11.88 > first circuit layer area (25.36 + 11.09) * 11.88, place PG in the first circuit layer. At this time there are three positions that can be placed, as shown by the dashed positions in Figure 10-12 .

[0128] wherein, Figure 10 the length of the connecting line of the position in

[0129] inv8_1-PG = (25.36 - 23.59) + 1.3 + |5.555 - 5.89| = 3.405

[0130] inv8_2-PG = (40.37 + 25.36 + 11.09 - 1.42) - ((9.755 - 8.925) + (25.36 - 23.59)) + |5.555 - 5.89| + 1 = 74.135

[0131] Figure 11 the length of the connecting line of the position in

[0132] inv8_1-PG = (23.59 + 11.09 + 41.28 - 1.3) + |5.555 - 5.89| = 74.995

[0133] inv8_2-PG = (25.36 - 23.59) + (9.755 - 8.925) + 1.42 + (41.28 - 40.37) + |5.555 - 5.89| + 1 = 6.265

[0134] Since: 3.405 + 74.134 < 74.995 + 6.265, Figure 10 the total length of the connecting line corresponding to the position in Figure 11 is less than the total length of the connecting line of the position in

[0135] Figure 12 the length of the connecting line of the position in

[0136] inv8_1-inv3_1 = (1.145 + 41.28 + (11.09 - 10.18)) + |5.645 - 5.835| = 43.67

[0137] inv8_1-PG = (23.59 + (41.28 - 1.3)) + |5.89 - 5.555| = 63.905

[0138] inv8_2-PG = (40.37 + (11.09 - 1.42)) - ((25.36 - 23.59) + (9.755 - 8.925))

[0139] +|5.89-5.555|+1=48.775

[0140] Since: 74.135+3.405+2.245<43.67+63.905+48.775, therefore, Figure 10 The position in is the target placement position of the PG.

[0141] Minimum width arrangement total length = 2.22 + 2.245 + 19.85 + 11.515 + 3.405 + 74.134 = 113.369

[0142] The 3D SRAM circuit created using this method is approximately 45% smaller in area than a 2D SRAM circuit. In terms of performance, both the write-0 and write-1 times are roughly halved compared to a 2D SRAM circuit.

[0143] The embodiments of the present invention can be divided into functional modules according to the above-mentioned method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated into a single processing module. The above-mentioned integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the division of modules in the embodiments of the present invention is illustrative and is only a logical functional division. In actual implementation, other division methods may be used.

[0144] In the case of dividing each functional module into corresponding functional modules, Figure 13 This is a schematic diagram of the structure of a monolithic 3D integrated circuit layout device provided by the present invention. Figure 13 As shown, the device includes:

[0145] The unit information acquisition module 111 is used to obtain unit information of each unit of the integrated circuit to be laid out; the unit information includes unit height, unit width, connection information and port coordinates;

[0146] A first root unit and to-be-allocated unit determination module 112 is configured to determine a first root unit and to-be-allocated units based on the connection information; the first root unit is the unit with the largest number of connected units; the to-be-allocated units are the multiple units connected to the first root unit;

[0147] a target circuit layer determination module 113 configured to determine, for any one of the cells to be allocated, the areas of the current first circuit layer and the second circuit layer based on the cell width and cell height, and determine the circuit layer with the smaller area as the target circuit layer for placement of the cell to be allocated; the first circuit layer and the second circuit layer being two circuit layers vertically stacked in a 3D integrated circuit;

[0148] a target position determining module 114 for determining, based on the connection information and the port coordinates, a position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as a target position;

[0149] The loop module 115 is used to sequentially determine the target circuit layers and target positions of the remaining cells to complete the 3D integrated circuit layout.

[0150] Optionally, the target circuit layer determination module 113 may include:

[0151] a target circuit layer determining unit for a first target unit, configured to determine, for a first target unit among the units to be allocated, the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determine the circuit layer with the smaller area as the target circuit layer for placement of the first target unit; the first target unit being the unit with the smallest unit width among the units to be allocated;

[0152] The target circuit layer determination unit of the next target unit is used to determine the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height for the second target unit in the unit to be allocated, and determine the circuit layer with a smaller area as the target circuit layer for placing the second target unit; the second target unit is the unit with the smallest unit width among the units to be allocated except the first target unit; until the target circuit layers of all units in the units to be allocated are determined.

[0153] Optionally, the target location determination module 114 may include:

[0154] A preset position determination unit is used to determine the preset position of the unit to be allocated based on the position of the already laid out unit in the target circuit layer; the already laid out unit is all the units in the target circuit layer whose target positions have been determined; the preset position is arranged along the circumference of the already laid out unit, and the preset position is in contact with one side of the already laid out unit; or the preset position partially overlaps with a unit in the already laid out unit.

[0155] A total line length calculation unit, configured to calculate the total line length corresponding to each preset position according to the port coordinates and connection information;

[0156] The target position determining unit is configured to determine a preset position corresponding to the minimum total length of the connection line as a target position.

[0157] Optionally, the total line length calculation unit may be specifically used to:

[0158] determining a first port and a second port connected to each other according to the connection information;

[0159] Based on the first and second ports, the formula is:

[0160] H=|X1-X2|+|Y1-Y2

[0161] Calculating the length of the connection between the first port and the second port;

[0162] Where H is the length of the line between the first port and the second port, X1 is the target horizontal coordinate of the first port, X2 is the target horizontal coordinate of the second port, Y1 is the target vertical coordinate of the first port, and Y2 is the target vertical coordinate of the second port;

[0163] The total length of the wires is determined as the sum of the lengths of all wires.

[0164] Optionally, the first circuit layer is located below the second circuit layer; the device further includes a first root unit placement unit, configured to place the first root unit in the first circuit layer.

[0165] Optionally, the integrated circuit to be laid out includes multiple root units; the loop module 115 may be configured to:

[0166] Determine a second root unit; the second root unit is a unit with the largest number of connected units in the integrated circuit to be laid out, excluding the first root unit;

[0167] sequentially determining a target circuit layer and a target position of the second root unit and a unit connected to the second root unit;

[0168] Continue to determine the third root cell in the remaining unassigned cells until the target circuit layers and target positions of all cells in the integrated circuit to be laid out are confirmed.

[0169] Optionally, when the areas of the first circuit layer and the second circuit layer are equal, one of the circuit layers is selected as the target circuit layer of the unit to be allocated.

[0170] The above mainly introduces the solution provided by the embodiment of the present invention from the perspective of the interaction between the various modules. It can be understood that in order to realize the above functions, it includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present invention can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0171] In the case of using the corresponding integrated unit, Figure 14 This is a schematic diagram of the structure of a monolithic 3D integrated circuit layout device provided by the present invention. Figure 14 As shown, the device includes:

[0172] A communication unit / communication interface, configured to obtain unit information of each unit of the integrated circuit to be laid out; the unit information includes unit height, unit width, connection information, and port coordinates;

[0173] a processing unit / processor, configured to determine a first root unit and units to be allocated according to the connection information; the first root unit is the unit with the largest number of connected units; the units to be allocated are multiple units connected to the first root unit;

[0174] For any one of the units to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with the smaller area as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit;

[0175] Based on the connection information and the port coordinates, determining a position of the to-be-allocated unit in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as a target position;

[0176] The target circuit layers and target positions of the remaining units are determined in sequence to complete the 3D integrated circuit layout.

[0177] like Figure 14 As shown, the processor can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. The communication interface can be one or more. The communication interface can use any device such as a transceiver for communicating with other devices or a communication network.

[0178] like Figure 14 As shown, the terminal device may further include a communication line. The communication line may include a path for transmitting information between the components.

[0179] Optional, such as Figure 14 As shown, the terminal device may further include a memory. The memory is used to store computer-executable instructions for executing the solution of the present invention, and the execution is controlled by the processor. The processor is used to execute the computer-executable instructions stored in the memory, thereby implementing the method provided by the embodiment of the present invention.

[0180] like Figure 14 As shown, the memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to this. The memory can exist independently and be connected to the processor through a communication line. The memory can also be integrated with the processor.

[0181] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in the embodiment of the present invention.

[0182] In a specific implementation, as an embodiment, Figure 14 As shown, the processor may include one or more CPUs, such as Figure 14 CPU0 and CPU1 in.

[0183] In a specific implementation, as an embodiment, Figure 14 As shown, the terminal device may include multiple processors, such as Figure 14 Each of these processors can be a single-core processor or a multi-core processor.

[0184] In one aspect, a computer-readable storage medium is provided, wherein instructions are stored in the computer-readable storage medium. When the instructions are executed, the above-mentioned monolithic 3D integrated circuit layout method is implemented.

[0185] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer programs or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user device, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disc (DVD); or a semiconductor medium, such as a solid-state drive (SSD).

[0186] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0187] Although the present invention has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. It will be apparent that various modifications and variations may be made to the present invention by those skilled in the art without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such modifications and variations as fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A monolithic 3D integrated circuit layout method, characterized in that: include: Obtaining unit information of each unit of the integrated circuit to be laid out; The unit information includes unit height, unit width, connection information and port coordinates; Determine a first root unit and units to be allocated according to the connection information; the first root unit is the unit with the largest number of connected units; the units to be allocated are multiple units connected to the first root unit; For any one of the units to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with the smaller area as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit; Based on the connection information and the port coordinates, determining a position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as a target position; The target circuit layers and target positions of the remaining units are determined in sequence to complete the 3D integrated circuit layout.

2. The monolithic 3D integrated circuit layout method according to claim 1, wherein: The method of determining, for any one of the units to be allocated, the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with the smaller area as the target circuit layer for placing the unit to be allocated includes: For a first target cell among the cells to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the cell width and cell height, and determining the circuit layer with the smaller area as the target circuit layer for placing the first target cell; the first target cell is the cell with the smallest cell width among the cells to be allocated; For the second target unit in the unit to be allocated, the areas of the current first circuit layer and the second circuit layer are determined according to the unit width and the unit height, and the circuit layer with the smaller area is determined as the target circuit layer for placing the second target unit; the second target unit is the unit with the smallest unit width among the units to be allocated except the first target unit; until the target circuit layers of all units in the unit to be allocated are determined.

3. The monolithic 3D integrated circuit layout method according to claim 1, wherein: The determining, based on the connection information and the port coordinates, the position of the to-be-allocated unit in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as the target position includes: Determining a preset position of the unit to be allocated according to the position of the already laid out units in the target circuit layer; the already laid out units are all units in the target circuit layer whose target positions have been determined; the preset position is arranged along the circumference of the already laid out units, and the preset position contacts one side of the already laid out units; Calculate the total length of the connection corresponding to each preset position according to the port coordinates and connection information; The preset position corresponding to the minimum total length of the connection line is determined as the target position.

4. The monolithic 3D integrated circuit layout method according to claim 3, wherein: Calculating the total length of the connection corresponding to each preset position according to the port coordinates and the connection information includes: determining a first port and a second port connected to each other according to the connection information; Based on the first and second ports, the formula is: ； Calculating the length of the connection between the first port and the second port; in, is the length of the line between the first port and the second port, is the target horizontal coordinate of the first port, is the target abscissa of the second port, is the target ordinate of the first port, is the target ordinate of the second port; The total length of the wires is determined as the sum of the lengths of all wires.

5. The monolithic 3D integrated circuit layout method according to claim 4, wherein: The first circuit layer is located below the second circuit layer; and before the determining, for any one of the to-be-allocated units, the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with the smaller area as the target circuit layer for placing the to-be-allocated unit, the method further comprises: The first root cell is placed in a first circuit layer.

6. The monolithic 3D integrated circuit layout method according to claim 3, wherein: The integrated circuit to be laid out includes a plurality of root cells; and sequentially determining target circuit layers and target positions of the remaining cells includes: Determine a second root unit; the second root unit is a unit with the largest number of connected units in the integrated circuit to be laid out, excluding the first root unit; sequentially determining a target circuit layer and a target position of the second root unit and a unit connected to the second root unit; Continue to determine the third root cell in the remaining unassigned cells until the target circuit layers and target positions of all cells in the integrated circuit to be laid out are confirmed.

7. The monolithic 3D integrated circuit layout method according to claim 1, wherein: When the areas of the first circuit layer and the second circuit layer are equal, one of the circuit layers is selected as the target circuit layer of the unit to be allocated.

8. A monolithic 3D integrated circuit layout device, characterized in that: include: A unit information acquisition module is used to obtain unit information of each unit of the integrated circuit to be laid out; The unit information includes unit height, unit width, connection information and port coordinates; a first root unit and to-be-allocated unit determination module, configured to determine a first root unit and to-be-allocated units based on the connection information; the first root unit being the unit with the largest number of connected units; and the to-be-allocated units being the multiple units connected to the first root unit; a target circuit layer determination module, configured to determine, for any one of the units to be allocated, the areas of the current first circuit layer and the second circuit layer based on the unit width and the unit height, and determine the circuit layer with the smaller area as the target circuit layer for placement of the unit to be allocated; the first circuit layer and the second circuit layer being two circuit layers vertically stacked in a 3D integrated circuit; a target position determining module, configured to determine, based on the connection information and the port coordinates, a position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as a target position; The loop module is used to sequentially determine the target circuit layers and target positions of the remaining cells to complete the 3D integrated circuit layout.

9. A monolithic 3D integrated circuit layout device, characterized in that: include: A communication unit / communication interface, used to obtain unit information of each unit of the integrated circuit to be laid out; The unit information includes unit height, unit width, connection information and port coordinates; a processing unit / processor, configured to determine a first root unit and units to be allocated according to the connection information; the first root unit is the unit with the largest number of connected units; the units to be allocated are multiple units connected to the first root unit; For any one of the units to be allocated, determining the areas of the current first circuit layer and the second circuit layer according to the unit width and the unit height, and determining the circuit layer with the smaller area as the target circuit layer for placing the unit to be allocated; the first circuit layer and the second circuit layer are two circuit layers vertically stacked in a 3D integrated circuit; Based on the connection information and the port coordinates, determining a position of the unit to be allocated in the target circuit layer when the total length of the connection lines of the 3D integrated circuit is the shortest as a target position; The target circuit layers and target positions of the remaining units are determined in sequence to complete the 3D integrated circuit layout.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores instructions, and when the instructions are executed, the monolithic 3D integrated circuit layout method according to any one of claims 1 to 7 is implemented.

Images