F2F three-dimensional integrated circuit layout optimization method based on improved simulated annealing

Abstract

The invention provides an F2F three-dimensional integrated circuit layout optimization method based on improved simulated annealing. The F2F three-dimensional integrated circuit layout optimization method comprises the following steps: constructing an initial three-dimensional layout; configuring simulated annealing algorithm parameters, and initializing a multi-target layout cost evaluation model containing cross-layer network interconnection cost; circularly executing the following operations until a termination condition is met: applying controllable random disturbance to the current layout to generate a new layout candidate scheme, wherein the disturbance at least comprises module cross-layer migration meeting F2F bonding interlayer spacing constraint; identifying a network and a layout area affected by disturbance, only calculating representative network cost change of an affected network group through network topology feature grouping, and deducing overall cost variation; according to the current temperature and the overall cost variation, whether a new layout is accepted or not is determined according to the Metropolis criterion; if accepting, updating the current layout and the cost value, and if rejecting, discarding the new layout and not executing state rollback; and adjusting the current temperature through a self-adaptive temperature scheduling strategy, and outputting an optimal layout scheme after iteration is ended.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit design automation, and particularly relates to a three-dimensional chip layout optimization method for a face-to-face bonding (F2F) scenario. BACKGROUND

[0002] In recent years, with the advent of the three-dimensional integrated circuit era, face-to-face bonding technology has become a key solution for three-dimensional integrated circuit design due to its excellent interconnection performance. In the field of high-performance electrical equipment such as high-end computing chips and artificial intelligence accelerators, three-dimensional stacking architecture has achieved unprecedented integration density and performance improvement through vertical interconnection. According to industry technical reports, the vertical interconnection density of three-dimensional integrated circuits using face-to-face bonding technology can be more than 7 times that of traditional TSV technology, which provides a new technical path to break through the limitations of Moore's Law.

[0003] However, the rapid development of three-dimensional integrated circuits also brings new technical challenges. In the face-to-face bonding architecture, the direct interconnection of upper and lower chips makes the layout optimization problem present new characteristics: first, the distribution of bonding points directly affects signal transmission performance and heat conduction efficiency; second, high-density interconnection leads to increased electromagnetic coupling effects; third, the difference in thermal expansion coefficients of different functional layers causes new reliability problems. These characteristics make it difficult for traditional two-dimensional layout optimization methods to be directly applicable, and it is urgent to develop three-dimensional layout optimization technology specifically for face-to-face bonding scenarios.

[0004] As a solution to this problem, the Simulated Annealing Method [2] has received widespread attention. As is known, compared to other combinatorial problem optimization algorithms, the Simulated Annealing Method can obtain better quality solutions. The Simulated Annealing Method simulates the crystallization process of a substance, starting with a random state at a high temperature, simulating the thermal equilibrium state at each temperature during the cooling process, and obtaining an approximate optimal solution at a low temperature close to 0 degrees. This simulation process requires a long time to execute.

[0005] The current chip layout simulation annealing optimization technology mainly faces the following key technical bottlenecks: First, in terms of computational efficiency, the traditional simulated annealing algorithm has serious performance limitations. This algorithm needs a large number of iterations to reach thermal equilibrium, resulting in long computation time. Although there have been attempts to improve the state selection strategy to improve algorithm stability [3], but the effect is very small in terms of computation time optimization. Although the fast simulated annealing algorithm (Fast SA) based on B*Tree proposed by Chen et al. [4] has improved the calculation speed, its solution space exploration ability is obviously insufficient, and it is difficult to meet the optimization needs of modern three-dimensional integrated circuits. Secondly, in terms of technical adaptability, the research on the simulated annealing cost function under the face-to-face bonding characteristics is almost in a blank state. Although the multi-layer SA optimization framework developed by Ren et al. [5] represents the current technical level, its design is originally intended for traditional through-silicon vias (TSV) structures, and when applied to face-to-face bonding scenarios, its temperature scheduling strategy will significantly reduce the solution space exploration efficiency, and the optimization effect will be greatly discounted. In addition, the traditional method needs to save the complete state to support the rollback operation after rejecting the disturbance, which has high memory occupation.

[0006] More specifically, these technical limitations mainly manifest in: (1) the computational complexity grows nonlinearly with the layout size, making it difficult to cope with modern ultra-large-scale integrated circuit design; (2) existing improved algorithms perform poorly in solution space exploration ability, easily falling into local optimum; (3) lack of specialized optimization strategies for face-to-face bonding characteristics; (4) rollback operation leads to high memory overhead.

[0007] References:

[0008] [1] https: / / www.broadcom.cn / company / news / product-releases / 62691

[0009] [2] S. Kirkpatrik, C.D. Gelatt, Jr., M.P.Vecchi, “Optimization by using simulated annealing,” Science, 220, pp.671-680,1983.

[0010] [3] A faster SA method TOSA for Global Placement.2015

[0011] [4] T. C. Chen and Y. W. Chang, "Modern floorplanning based on B*Tree and Fast simulated annealing", IEEE Trans. CAD, vol. 25, no. 4, pp. 510-522, 2006.

[0012] [5] Z. Ren, A. Alqahtani, N. Bagherzadeh and J. Lee, "Thermal TSV Optimization and Hierarchical Floorplanning for 3-D Integrated Circuits," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 4, pp. 599-610, April 2020.

[0013] [6] D. -q. Wang, M. Toyonaga, H. Hu, J. -w. Ma and X. -l. Fu, "A Faster SA Method TOSA for Global Placement," 2010 International Conference on Electrical and Control Engineering, Wuhan, China, 2010.

[0014] [7] B. Fu, L. Liu, Y. Sun, W. -H. Lau, M. D. F. Wong and E. F. Y. Young, "CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs," 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), Incheon, Korea, Republic of, 2024. SUMMARY

[0015] In view of the low calculation efficiency, insufficient solution space exploration ability and large memory overhead of the prior art, the application provides a face-to-face bonding (F2F) three-dimensional integrated circuit layout optimization method and system based on an improved simulated annealing algorithm.

[0016] The core of the application is to construct an efficient incremental calculation architecture. In particular, a wire net topology feature hashing grouping mechanism is innovatively introduced, which groups wire nets with the same connection mode into a group, and only the cost change of the representative wire net is calculated to derive the overall impact, thereby significantly reducing the calculation redundancy. In addition to module displacement, exchange and soft block shape adjustment, a module cross-layer migration operation that meets the F2F bonding interlayer spacing constraint is specially designed to adapt to the three-dimensional integration characteristics.

[0017] The method guides optimization through a multi-objective cost model (including wire length, layout density, interlayer area balance and cross-layer interconnection cost) and uses an adaptive temperature scheduling strategy to control convergence.

[0018] The technical scheme adopted by the application to solve the technical problem is:

[0019] A F2F three-dimensional integrated circuit layout optimization method based on an improved simulated annealing algorithm, comprising the following steps:

[0020] Read the circuit netlist and chip parameters of the three-dimensional integrated circuit to construct an initial three-dimensional layout; configure the simulated annealing algorithm parameters and initialize the multi-objective layout cost evaluation model including the cross-layer network interconnection cost;

[0021] Loop the following operations until the termination condition is met:

[0022] Apply controllable random disturbance to the current layout to generate a new layout candidate, and the disturbance at least includes module cross-layer migration that meets the F2F bonding interlayer spacing constraint;

[0023] Identify the wire net and layout area affected by the disturbance, and only calculate the representative wire net cost change of the affected wire net group through wire net topology feature grouping to derive the overall cost change;

[0024] According to the current temperature and the overall cost change, decide whether to accept the new layout according to the Metropolis criterion; if accepted, update the current layout and cost value, and if rejected, discard the new layout and do not perform state rollback;

[0025] The current temperature is adjusted by an adaptive temperature scheduling strategy, and an optimal layout scheme is output after iteration termination.

[0026] Further, the constructing initial three-dimensional layout adopts a hierarchical structure-based module clustering and window partitioning method; the configuring simulated annealing algorithm parameters comprises setting an initial temperature, a termination temperature threshold and an internal loop iteration coefficient, and the internal loop iteration coefficient is used to control the number of disturbance iterations at each temperature.

[0027] Further, the total cost of the multi-objective layout cost evaluation model is calculated by weighting the line length cost, area overflow rate, cross-layer area balance cost and cross-layer network interconnection cost according to preset weights.

[0028] Further, the preset weights are dynamically adjusted according to the performance requirements of the three-dimensional integrated circuit; wherein the line length cost is calculated based on a half-perimeter line length model, specifically, the sum of the maximum horizontal difference and the maximum vertical difference of all soft block coordinates connected by each line network is calculated, multiplied by the line network weight, summed, and then normalized by the ratio of the preset initial half-perimeter line length.

[0029] Further, the cross-layer area balance cost is calculated by the absolute value of the difference between the ratio of the total area of soft blocks contained in the lower chip and the total area of soft blocks contained in the upper chip and 1; the cross-layer network interconnection cost is calculated by calculating the ratio of the number of cross-layer line networks in each soft block associated line network to the total number of soft block associated line networks, and then taking the average value of the ratio of all soft blocks; the cross-layer line network is a line network connecting soft blocks in different chip layers.

[0030] Further, the line network topology feature grouping is realized by establishing a hash coding system of line network topology features, performing hash operation on the soft block set connected by each line network, and grouping the line networks with the same hash result into the same group, and the representative line network is a randomly selected or preset line network in each group; after identifying the line networks and layout areas affected by disturbance, only the line length cost of the related line networks and the density cost of the related grids in the affected areas are updated, and the update is only performed when the disturbance is accepted, without the need to save the historical layout state to support the rollback operation after disturbance rejection.

[0031] Further, the controllable random disturbance further comprises adjusting the geometry of the soft block within a preset aspect ratio range, and the preset aspect ratio range and the adjustment step are set according to the soft block size accuracy requirements of the three-dimensional integrated circuit; the soft block of the three-dimensional integrated circuit comprises macro modules and standard cells (a soft block may contain several macro modules and standard cells), and the chip parameters include chip size, soft block shape variation range and F2F bonding layer spacing threshold.

[0032] Furthermore, the termination conditions include at least one of the following: reaching a preset termination temperature threshold, the total cost change of a preset number of consecutive iterations being less than a stability threshold, and the cumulative number of iterations reaching the maximum number of iterations limit; the adaptive temperature scheduling strategy is a multi-stage adaptive cooling strategy, which divides the temperature range of the simulated annealing process into multiple stages, each stage adopting a different cooling rate. The relatively high temperature stage uses a slower cooling rate to ensure the solution space exploration capability, while the relatively low temperature stage uses a faster cooling rate to promote layout convergence.

[0033] And, an F2F three-dimensional integrated circuit layout optimization system based on improved simulated annealing, comprising:

[0034] The layout initialization module is used to read the circuit netlist and chip parameters of the 3D integrated circuit, construct the initial 3D layout, configure the simulated annealing algorithm parameters, and initialize the multi-objective layout cost evaluation model containing cross-layer network interconnection costs.

[0035] The iterative optimization module includes a perturbation unit, an incremental evaluation unit, and a decision update unit: the perturbation unit is used to apply a controllable random perturbation to the current layout to generate new layout candidate schemes, the perturbation at least includes module cross-layer migration that satisfies the F2F bond layer spacing constraint; the incremental evaluation unit is used to identify the nets and layout regions affected by the perturbation, and calculates only the cost change of representative nets in the affected net groups by grouping them by net topology features, and derives the overall cost change; the decision update unit is used to decide whether to accept the new layout according to the current temperature and the overall cost change, based on the Metropolis criterion, if accepted, the current layout and cost value are updated, if rejected, the new layout is discarded and no state rollback is performed.

[0036] The temperature scheduling and output module is used to adjust the current temperature through an adaptive temperature scheduling strategy, and outputs the optimal layout scheme after the iteration meets the termination condition.

[0037] Furthermore, the total cost of the multi-objective layout cost evaluation model is calculated by weighting the line length cost, area overflow rate, cross-layer area balance cost, and cross-layer network interconnection cost according to preset weights; the network topology feature grouping is achieved by establishing a hash coding system for network topology features, performing hash operations on the soft block set connected by each network, and grouping networks with the same hash result into the same group.

[0038] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method described above.

[0039] A non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0040] Compared with the prior art, the present invention and its preferred embodiments have at least the following beneficial effects:

[0041] In terms of computational efficiency, the incremental cost calculation and zero-rollback architecture only update the cost of the nets and layout areas in the affected region, without saving historical states to support rollback operations, significantly reducing memory usage. Combined with the net grouping optimization mechanism based on topology hashing, nets with the same connection characteristics are hash-encoded into groups, and only the cost change of the representative nets in the affected net groups is calculated. The overall cost change is derived through the multiple relationship of the number of nets in the group, which greatly reduces the overhead of repeated calculations and improves the efficiency of the algorithm.

[0042] In terms of technical adaptability, a dedicated optimization strategy is designed for face-to-face bonding (F2F) scenarios. By satisfying the interlayer spacing constraint through cross-layer migration mechanism and dynamic adjustment of soft block aspect ratio, the adaptability of layout and high-density bonding structure is improved. A multi-objective cost evaluation model is constructed to integrate line length cost, area overflow rate, cross-layer area balance cost and cross-layer network interconnection cost. By dynamically adjusting the preset weights, it can adapt to different performance requirements and enhance the support capability for the diversified design goals of 3D integrated circuits.

[0043] In terms of quality optimization, the synergy of controllable random perturbation and adaptive temperature scheduling strategy balances solution space exploration and convergence efficiency, reducing the risk of getting trapped in local optima; the dynamic adjustment mechanism of soft block shape further improves the layout area utilization rate, and cross-layer area balancing and interconnection cost optimization help improve signal transmission performance and heat conduction efficiency, thereby improving the overall performance of 3D chip layout. Attached Figure Description

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0045] Figure 1 This is a flowchart illustrating the implementation of the method in an embodiment of the present invention.

[0046] Figure 2 The actual test results are from the embodiments of the present invention. Figure 1 ;

[0047] Figure 3 The actual test results are from the embodiments of the present invention. Figure 2 . Detailed Implementation

[0048] To make the features and advantages of the present invention more apparent and understandable, specific embodiments are described below in detail:

[0049] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0050] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0051] To provide a better solution for high-density interconnected integrated circuit design, this invention proposes a three-dimensional chip layout optimization method based on an improved simulated annealing algorithm, which is particularly suitable for high-density face-to-face bonding three-dimensional integrated circuit design. The core design of this invention includes: incremental cost calculation architecture, net grouping optimization based on topology hashing, perturbation strategy oriented towards face-to-face bonding constraints, and dynamic optimization of soft block (Partition Module) aspect ratio. Specifically: (1) Incremental cost calculation and zero rollback architecture design: by identifying the local area affected by perturbation, only the cost values ​​of related nets and densities are updated, avoiding global recalculation. Updates are only made when the perturbation is accepted, achieving zero rollback. (2) Net grouping optimization based on topology hashing: nets with the same connection characteristics are grouped to reduce redundant calculation overhead. (3) Perturbation strategy: considering face-to-face bonding constraints, a cross-layer migration mechanism that conforms to the inter-layer interconnection rules is added on the basis of soft block displacement and exchange operations. (4) Dynamic optimization of soft block aspect ratio: a soft block shape adjustment mechanism is introduced during the perturbation process to further improve the layout area utilization.

[0052] The specific technical solution includes layout model initialization, cost function evaluation, layout perturbation generation, topology-aware cost update, annealing decision mechanism, and optimization process control. The specific implementation process is as follows: (1) Initialize the layout model by reading information such as circuit netlist, chip size parameters, and standard cell specifications, and construct the initial three-dimensional layout solution using the module clustering and window partitioning method based on hierarchical structure. (2) Evaluate the layout cost using incremental calculation, including line length cost based on the half-perimeter line length (HPWL) model, density cost based on mesh partitioning, area balance cost, and cross-layer network (Cut Net) interconnection cost index. Changes in the line net connection relationship trigger the local update mechanism, and only the cost components of the affected area are recalculated. (3) Generate new layout candidate schemes through controllable random perturbation operations, including adjusting the coordinate position of the selected module within the allowable displacement range; exchanging the spatial positions of two selected modules (including planar coordinates and the chip layer to which they belong); migrating the selected module to the adjacent chip layer under the condition of considering the face-to-face bonding spacing constraint; and adjusting the shape of the soft block by selecting a reasonable aspect ratio based on the pre-calculated aspect ratio of the soft block. (4) Establish a hash coding system for the topology characteristics of the network and group and mark the networks with the same connection pattern. When the layout disturbance affects a specific topology group, only the cost change of the network representing the group needs to be calculated, and the overall impact value is derived through the multiple relationship within the group, which greatly reduces the computational redundancy. (5) The annealing decision mechanism decides whether to accept the new layout scheme according to the Metropolis criterion based on the current temperature parameters and cost change. Disturbances that reduce the total cost are accepted unconditionally, while disturbances that increase the cost are selectively accepted with a certain probability. (6) The system temperature is gradually reduced through an adaptive temperature scheduling strategy, which promotes the convergence of the layout scheme while maintaining sufficient search capability. The optimization process continues to iterate until the preset termination conditions are met, including temperature threshold, cost stability threshold or maximum iteration limit.

[0053] The 3D chip soft block layout optimization method based on the improved simulated annealing algorithm provided by this invention demonstrates significant technical advancements in computational efficiency, system architecture, and optimization effectiveness. Compared with existing technologies, the advantages of this invention are specifically reflected in the following aspects:

[0054] In terms of computational efficiency, this invention achieves a significant reduction in computational complexity through innovative hierarchical clustering technology and network topology grouping modeling based on module set hashing. Traditional line length cost calculation methods (such as the scheme proposed by Wang et al. [6]) have a time complexity of O(N·P), while this invention optimizes it to O(G·P) through an incremental calculation strategy, where N represents the total number of networks, G represents the number of network structures affected by disturbances, and G≪N. Experimental data show that in test cases with a scale of 1 million units, the density calculation method of this invention is 20.5 times more efficient than traditional global calculation methods (such as the scheme proposed by Fu et al. at DAC 2024 [7]), and is particularly suitable for the rapid identification of high-density interconnection regions in face-to-face bonding scenarios.

[0055] The innovative design of this invention in terms of system architecture is mainly reflected in its efficient disturbance evaluation mechanism. Compared with the traditional technical solution that uses a state rollback mechanism, this invention proposes a more optimized processing method. Its core lies in the fact that when a new disturbance occurs, the system first calculates the incremental cost corresponding to the disturbance, and then makes a decision based on the Metropolis criterion. If the disturbance is accepted, the disturbance state is applied to the current layout; otherwise, the disturbance is discarded and the original state remains unchanged. This innovative mechanism eliminates the need for explicit state rollback operations throughout the optimization process.

[0056] Regarding optimization performance, the parameterized cost combination of this invention supports weighted calculation of four cost factors: line length, density, area, and interconnection. In particular, the collaborative optimization system developed for face-to-face bonding scenarios, compared to existing methods (such as patent document CN113688593A), significantly reduces the bond violation rate by considering both the number of bonds and the uniformity of bond distribution. Furthermore, an innovative aspect ratio perturbation mechanism significantly improves area utilization.

[0057] The above technical effects are all based on measured data under standard test benchmarks. Those skilled in the art can adjust the relevant parameters according to specific application requirements, and these adjustments should be included within the protection scope of this invention.

[0058] The implementation of the present invention will be further illustrated below with reference to the accompanying drawings through a more specific embodiment:

[0059] This invention provides a method for optimizing the layout of a three-dimensional chip. The method uses soft blocks clustered in a hierarchical structure as the optimization object, and the technical scenario is a three-dimensional chip with face-to-face bonding. An example of the specific implementation process includes:

[0060] System Architecture and Initialization

[0061] Given a set of soft blocks clustered using hierarchical results, along with the soft block nets containing weight information and pins for connection, we also need to provide the range of soft block shape variations. Each soft block contains macro modules and standard cells. The 3D layout optimization problem is modeled as a hypergraph G(M,E), where the vertex set M represents the set of soft blocks, and the edge set E represents the connections between soft blocks.

[0062] The system initialization phase involves the following steps: First, input data is loaded, including soft block geometry information, net connections and their weights, pin location data, and soft block shape variation range parameters. Then, an initial layout scheme is established, determining the spatial location, geometry, and chip layer of each soft block. Simultaneously, simulated annealing algorithm parameters are configured, including initial temperature, termination temperature threshold, adaptive cooling rate strategy, and internal loop iteration control parameters. Based on this, four key cost evaluation models are initialized: a routing cost model based on half-perimeter line length, a mesh density distribution model, a cross-chip layer area balancing model, and a cross-layer interconnect cost model. Finally, the initial layout state and its total cost are recorded as an optimization baseline.

[0063] Optimize algorithm process

[0064] The core optimization algorithm in this embodiment adopts an improved simulated annealing framework, implemented through a double-loop structure. The pseudocode of the process is shown below:

[0065] Input: initial_placement, temperature T0, cooling schedule, max_iter

[0066] Output: optimized_placement

[0067] / * Initialize the state and compute initial cost * /

[0068] 1: current ← initial_placement

[0069] 2: best ← current

[0070] 3: current_cost ← EvaluateCost(current)

[0071] 4: best_cost ← current_cost

[0072] / * Outer temperature loop * /

[0073] 5: while T > Tmin and iter < max_iter do

[0074] 6: for i ← 1 to module_count × inner_loop_coef do

[0075] 7: perturb ← GenerateRandomPerturbation(current)

[0076] 8: if not IsLegal(perturb) then

[0077] 9: continue

[0078] 10: end

[0079] / * Evaluate perturbation incrementally * /

[0080] 11: delta_cost ← EvaluateCost(perturb) - current_cost

[0081] / * Metropolis acceptance criterion * /

[0082] 12: if delta_cost ≤ 0 or Random(0, 1) < exp(-delta_cost / T)then

[0083] 13: ApplyPerturbation(current, perturb)

[0084] 14: current_cost ← current_cost + delta_cost

[0085] / * Update best state if improved * /

[0086] 15: if current_cost < best_cost then

[0087] 16: best ← current

[0088] 17: best_cost ← current_cost

[0089] 18: end

[0090] 19: end

[0091] 20: end

[0092] / * Update temperature according to cooling schedule * /

[0093] 21: T ← UpdateTemperature(T)

[0094] 22: end

[0095] / * Output the best layout found * /

[0096] 23: Output(best)

[0097] The implementation process is as follows Figure 1 As shown:

[0098] The external circulation control module runs continuously until the temperature convergence condition is met or the maximum number of iterations is reached. After each external circulation iteration, the cooling rate is dynamically adjusted based on the current temperature state, and finally, the historical optimal layout scheme is output.

[0099] The number of iterations of the inner loop execution module is determined by the number of soft blocks and the inner loop coefficient. Each inner loop randomly selects and executes one of four perturbation strategies: (1) Position movement: Adjust the module coordinates within the temperature-adaptive movement window; (2) Shape transformation: Change the module geometry within the preset aspect ratio range; (3) Position exchange: Swap the spatial positions of two modules; (4) Interlayer migration: Transfer the module to other chip layers.

[0100] Each perturbation operation must undergo legality verification, including boundary constraint checks and overlap assessment. The Metropolis criterion is used for perturbation acceptance decisions: when the cost change Δcost ≤ 0, the new state is automatically accepted; when Δcost > 0, it is selectively accepted with probability exp(-Δcost / T). Accepted perturbations trigger layout state updates; if the current cost is better than historical records, the optimal state is updated synchronously.

[0101] The disturbance cost is calculated, and the disturbance cost is given by the multi-objective combination function:

[0102]

[0103] Among them, CHPWL It's the cost of line length, Overflow is the area overflow rate, C Area It is the cost of area equilibrium, C Cut This represents the cost of cross-layer network interconnection. α, β, γ, and δ are weighting coefficients for each cost, which can be adjusted according to design requirements. All costs are obtained through perturbation increment calculation, avoiding a full scan after each perturbation and greatly improving efficiency.

[0104] Key technology innovation

[0105] (1) Incremental calculation mechanism of line length cost

[0106] The formula for calculating line length cost is:

[0107]

[0108] Where E is the set of wire meshes, w e Let x be the weight of the wire mesh e. i ,y i The coordinates of soft block i connected to net e; HPWL init The HPWL, or initial half-circumference line length of the normalized baseline, is calculated during the initialization of the simulated annealing algorithm. The goal of this module is to calculate the impact of disturbances on the bus length. However, due to the large number of nets, recalculating the full line length for each disturbance would significantly impact speed. Therefore, this invention introduces a network topology hash signature mechanism. For each network connection's soft block set {m1, m2, ..., m...}, ... k The algorithm performs hashing; networks with the same set of soft blocks are grouped; for each perturbation, it only needs to identify the affected networks, determine their respective network groups, calculate the line length of each affected network group once, and multiply the result by the number of networks within the network group. In terms of time complexity, if the network topology is not used, it is O(N); this method is only O(G′), where G′ is the number of affected network groups, and G′ is much smaller than N.

[0109] (2) Incremental calculation mechanism of density cost

[0110] The goal of this module is to control the congestion level of the layout region, avoiding excessive soft block density or idle areas. First, the layout region is divided into two-dimensional grid bins (each bin records the soft block area density). When incremental calculations are needed to evaluate density costs for perturbation actions, the bin regions covered by the perturbed soft block before and after the perturbation must be determined. Only the density values ​​of the affected bins are updated. The density cost change is calculated based on the density difference. For the rollback mechanism, if the perturbation is not accepted, the saved bin state does not need to be rolled back; the bin state is only updated when the perturbation is accepted. This module design avoids recalculating the density of all soft blocks, significantly reducing memory and computational overhead.

[0111] (3) Incremental calculation mechanism of area balance cost

[0112]

[0113] Where A0 represents the area of ​​the soft block contained in the lower-layer chip, and A1 represents the area of ​​the soft block contained in the upper-layer chip. The goal of this module design is to maintain a balanced area distribution of soft blocks among different chips in a 3D chip. Each perturbation only affects the position or layer change of one or two soft blocks, and only requires addition or subtraction of the area data of the chip containing the perturbed soft block. The time complexity of calculating the area balance index is O(1).

[0114] (4) Incremental calculation mechanism of cross-layer network interconnection cost

[0115]

[0116] Where m is a soft block, M is the set of all soft blocks, |M| is the total number of soft blocks, and E m Let |E be the set of networks e contained in the current soft block. m |: The number of networks contained in the current soft block. When 'e' is a cross-layer network, 1[e is cut] is 1; otherwise, it is 0. The goal of this module design is to minimize cross-layer network connections, reducing wiring complexity and manufacturing costs. Traditional solutions iterate through all networks to determine if they are cross-layer networks, but this results in high time complexity and excessively long runtime. This invention establishes an "affected module set" and an "associated network set" for each module during initialization; each disturbance only updates the cross-layer network state related to the affected module. Therefore, the time complexity of interconnect cost updates is reduced from O(N) to O(K), where K is the number of networks related to the disturbed module, and K is much smaller than N.

[0117] like Figure 2 , Figure 3 As shown, a specific application example (ct_topscan) demonstrates the application effect in a standard F2F bonding structure. The test uses a lower layer of 1.05 mm × 1.05 mm (corresponding to...) Figure 2 The upper layer has a chip size configuration of 1.05 mm × 1.05 mm (corresponding to...). Figure 3 The aspect ratio of the soft block varies from 0.5 to 2.0 (step size 0.05). The algorithm parameters are set to an initial temperature of T=40000 and a ten-stage adaptive cooling strategy is adopted. Experimental data show that this method reduces the optimization convergence time to 6 minutes and the overlap rate to below 0.1%.

[0118] The above embodiments demonstrate the significant advantages of this invention in terms of computational efficiency and optimization quality. Those skilled in the art can adjust the relevant parameters according to specific application scenarios, and all such adjustments should be included within the scope of protection of this invention.

[0119] Based on the same inventive concept, this invention also provides a computer device, comprising: one or more processors, and a memory for storing one or more computer programs; the programs include program instructions, and the processor executes the program instructions stored in the memory. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, used to implement one or more instructions, specifically for loading and executing one or more instructions stored in a computer storage medium to implement the above-described method.

[0120] It should be further explained that, based on the same inventive concept, the present invention also provides a computer storage medium storing a computer program, which, when executed by a processor, performs the above-described method. This storage medium can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0121] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0122] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

[0123] This invention is not limited to the above-described preferred embodiments. Anyone inspired by this invention can derive other forms of F2F three-dimensional integrated circuit layout optimization methods based on improved simulated annealing. All equivalent variations and modifications made within the scope of the claims of this invention shall fall within the scope of this invention.

Claims

1. A method for F2F three-dimensional integrated circuit layout optimization based on improved simulated annealing, characterized in that, The method comprises the following steps: reading a circuit netlist and chip parameters of a three-dimensional integrated circuit to construct an initial three-dimensional layout; configuring parameters of a simulated annealing algorithm and initializing a multi-objective layout cost evaluation model containing a cross-layer network interconnection cost; performing the following operations in a loop until a termination condition is met: applying a controllable random disturbance to the current layout to generate a new layout candidate, the disturbance at least including module cross-layer migration satisfying F2F bonding interlayer spacing constraints; identifying line nets and layout regions affected by the disturbance, calculating only representative line net cost changes of affected line net groups through line net topology feature grouping, and deriving an overall cost change amount; determining whether to accept the new layout according to the Metropolis criterion based on the current temperature and the overall cost change amount; if accepted, updating the current layout and the cost value, and if rejected, discarding the new layout and not performing state rollback; adjusting the current temperature through an adaptive temperature scheduling strategy, and outputting an optimal layout scheme after iteration termination.

2. The F2F three-dimensional integrated circuit layout optimization method based on improved simulated annealing according to claim 1, characterized in that: The initial three-dimensional layout is constructed using a hierarchical structure-based module clustering and window partitioning method; the simulated annealing algorithm parameters are configured to include setting an initial temperature, a termination temperature threshold, and an internal loop iteration coefficient, which is used to control the number of disturbance iterations at each temperature.

3. The F2F three-dimensional integrated circuit layout optimization method based on improved simulated annealing of claim 1, wherein: The total cost of the multi-objective layout cost evaluation model is calculated by weighting the line length cost, area overflow rate, cross-layer area balance cost, and cross-layer network interconnection cost according to preset weights.

4. The F2F three-dimensional integrated circuit layout optimization method based on improved simulated annealing of claim 1, wherein: The preset weights are dynamically adjusted according to the performance requirements of the three-dimensional integrated circuit; the line length cost is calculated based on a half-perimeter line length model, specifically by calculating the sum of the maximum horizontal difference and the maximum vertical difference of all soft block coordinates connected by each line net, multiplying the sum by the line net weight, and then normalizing it by the ratio of the initial half-perimeter line length.

5. The F2F three-dimensional integrated circuit layout optimization method based on improved simulated annealing of claim 1, wherein: The cross-layer area balance cost is calculated by the absolute value of the difference between the ratio of the total area of soft blocks contained in the lower chip and the total area of soft blocks contained in the upper chip and 1; the cross-layer network interconnection cost is calculated by taking the average of the ratio of the number of cross-layer line nets in each soft block associated line net to the total number of soft block associated line nets for all soft blocks, the cross-layer line net being a line net connecting soft blocks of different chip layers.

6. The F2F three-dimensional integrated circuit layout optimization method based on improved simulated annealing of claim 1, wherein: The line net topology feature grouping is achieved by establishing a hash coding system of line net topology features, performing hash operations on the soft block set connected by each line net, and grouping line nets with the same hash result into the same group, the representative line net being a randomly selected or preset line net in each group; after identifying the line nets and layout regions affected by the disturbance, only the line length cost of the relevant line nets and the density cost of the relevant grids in the affected regions are updated, and the update is only performed when the disturbance is accepted, without the need to save historical layout states to support rollback operations after disturbance rejection.

7. The F2F three-dimensional integrated circuit layout optimization method based on improved simulated annealing of claim 1, wherein: The controllable random disturbance further comprises adjusting the geometry of the soft block within a preset aspect ratio range, and the preset aspect ratio range and the adjustment step are set according to the soft block size accuracy requirement of the three-dimensional integrated circuit; the soft block of the three-dimensional integrated circuit comprises a macro module and a standard cell, and the chip parameters comprise a chip size, a soft block shape variation range and an F2F bonding layer spacing threshold.

8. The F2F three-dimensional integrated circuit layout optimization method based on improved simulated annealing of claim 1, wherein: The termination condition comprises at least one of the following: reaching a preset termination temperature threshold, the total cost change amount of continuous preset number of iterations being less than a stability threshold, and the cumulative iteration number reaching a maximum iteration number limit; and the adaptive temperature scheduling strategy is a multi-stage adaptive cooling strategy, which divides the temperature range of the simulated annealing process into multiple stages, each stage adopts a different cooling rate, a relatively high temperature stage uses a slower cooling rate to ensure the solution space exploration ability, and a relatively low temperature stage uses a faster cooling rate to promote the layout convergence.

9. A system for F2F three-dimensional integrated circuit layout optimization based on improved simulated annealing, characterized by, Comprise: A layout initialization module for reading a circuit netlist and chip parameters of a three-dimensional integrated circuit, constructing an initial three-dimensional layout, configuring simulated annealing algorithm parameters, and initializing a multi-objective layout cost evaluation model containing a cross-layer network interconnection cost; An iterative optimization module comprising a disturbance unit, an incremental evaluation unit and a decision update unit: the disturbance unit is used to apply controllable random disturbance to the current layout to generate a new layout candidate scheme, and the disturbance at least comprises module cross-layer migration meeting the F2F bonding layer spacing constraint; the incremental evaluation unit is used to identify the line net and the layout area affected by the disturbance, calculate the representative line net cost change of only the affected line net group through line net topology feature grouping, and derive the overall cost change amount; the decision update unit is used to determine whether to accept the new layout according to the Metropolis criterion according to the current temperature and the overall cost change amount, update the current layout and the cost value if accepted, and discard the new layout and do not perform state rollback if rejected; A temperature scheduling and output module for adjusting the current temperature through an adaptive temperature scheduling strategy, and outputting an optimal layout scheme after the iteration meets the termination condition.

10. The F2F three-dimensional integrated circuit layout optimization system based on improved simulated annealing of claim 9, wherein: The total cost of the multi-objective layout cost evaluation model is calculated by weighting the line length cost, the area overflow rate, the cross-layer area balance cost and the cross-layer network interconnection cost according to a preset weight; and the line net topology feature grouping is realized by establishing a hash coding system of the line net topology feature, and the soft block set connected by each line net is subjected to hash operation, and the line nets with the same hash result are grouped into the same group.

Images