Adaptive synchronous rectification control method for CLLLC resonant converter

Abstract

An adaptive synchronous rectification control method for a CLLLC resonant converter solves the problem of the relatively complex theoretical calculation process for synchronous rectification of a CLLLC resonant converter, and belongs to the field of CLLLC resonant converter control. Based on the circuit characteristics and operating process of the CLLLC converter, the present invention analyzes the influence of the converter's synchronous rectification drive signal on the output frequency of the converter when the converter outputs a stable output signal, derives an equation for the relationship between the change in the synchronous rectification signal and the change in the operating frequency near the ideal synchronous rectification signal, and utilizes the law of this equation to implement the synchronous rectification function of the CLLLC converter. In the rectification control, a certain disturbance signal is given to the synchronous rectification signal, and then the synchronous rectification signal of the converter is gradually brought closer to the ideal synchronous rectification state based on the change in the operating frequency before and after the converter reaches a stable output signal. The present invention does not require additional sensors and avoids complex theoretical calculations.

Description

Technical Field

[0001] The invention relates to an adaptive synchronous rectification control method suitable for a CLLLC resonant converter, and belongs to the field of CLLLC resonant converter control. Background Art

[0002] By adding LLC resonant cavity structures to the primary and secondary sides of the transformer, the CLLLC resonant converter boasts a wide input voltage range and excellent soft-switching characteristics. This allows for natural soft switching without the need for additional auxiliary circuitry, and has been widely used in aerospace energy, electric vehicles, distributed energy storage, and other fields. However, both the input and output sides of the converter are full-bridge structures. Compared to utilizing the reverse conduction characteristics of the switching transistor, synchronous rectification can further improve the converter's efficiency.

[0003] Existing synchronous rectification methods mainly include voltage detection, current detection, and theoretical calculation. The voltage detection method typically measures the voltage between the source and drain of the device. When the device is reverse conducting, the voltage between the drain and drain becomes positive, enabling synchronous rectification. The current detection method uses a current sensor to detect the current flowing through the diode on the rectifier side, and determines the synchronous rectification signal based on its polarity. The theoretical calculation method establishes a mathematical model of the CLLLC resonant converter and uses mathematical calculations to determine the phase and duty cycle of the rectifier-side current under different operating conditions, which serves as the basis for synchronous rectification. Currently, the most commonly used CLLLC resonant converter modeling method is the fundamental wave analysis method, which approximates the phase difference between the rectifier-side current and the driver-side voltage, thereby deriving the synchronous rectification signal on the rectifier side. However, this method suffers from significant deviations in sub-resonant operation, making it difficult to obtain a relatively accurate synchronous rectification signal. Although the extended harmonic analysis method is more accurate than the fundamental wave analysis method, it still cannot solve the problem of discontinuous resonant current in sub-resonant operation. Compared with the frequency domain model, the time domain model can solve this problem well, but the CLLLC resonant converter has 5 resonant elements, and its solution process is more complicated.

[0004] Comparing the above three methods, it can be seen that the theoretical calculation method does not require the addition of any additional sensors. It can determine the synchronous rectification signal based on state information such as switching frequency, output voltage and current. It can effectively improve the working efficiency and power density of the converter, but its calculation process is relatively complicated. Summary of the Invention

[0005] In view of the problem that the theoretical calculation process of the synchronous rectification of the CLLLC resonant converter is relatively complicated, the present invention provides an adaptive synchronous rectification control method applicable to the CLLLC resonant converter without changing the circuit structure.

[0006] An adaptive synchronous rectification control method applicable to a CLLLC resonant converter of the present invention comprises:

[0007] The output voltage V of the CLLLC resonant converter o Perform real-time acquisition and output the real-time acquired output voltage as a signal V o With a given voltage V ref Comparison is performed and the compared error signal is sent to the loop controller to stabilize the output voltage of the CLLLC resonant converter;

[0008] When the output voltage of the CLLLC resonant converter is stable and the CLLLC resonant converter operates in sub-resonant mode, synchronous rectification optimization is performed:

[0009] S1, giving the converter the initial synchronous rectification signal conduction time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k-1 ;The initial value of k is 1;

[0010] S2, giving the converter a fixed disturbance ΔT on the synchronous rectification signal SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , get a reference value of frequency change Δf ref =|f s,k -f s,k-1 |; The time interval between two disturbances satisfies the time required for the output voltage to adjust to the reference value;

[0011] S3, giving the converter a fixed disturbance ΔT on the synchronous rectification signal SR , let the on-time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |;

[0012] S4. If Δf≥AΔf ref , let T SR,k+1 =T SR,k -ΔT SR , the on-time of the ideal synchronous rectification in sub-resonant mode is determined to be T SR,k+1 , end, if Δf<AΔf ref, then update Δf ref The value is Δf, k=k+1, go to S3, A is 1.5.

[0013] When the output voltage of the CLLLC resonant converter is stable and the CLLLC resonant converter operates in over-resonance mode, synchronous rectification optimization is performed:

[0014] S1, synchronous rectification signal lag time of converter After that, the initial synchronous rectification signal conduction time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k-1 ;The initial value of k is 1; Meet the maximum lag time of the converter under all working conditions;

[0015] S2, synchronous rectification signal lag time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , get a reference value of frequency change Δf ref =|f s,k -f s,k-1 |;

[0016] S3, synchronous rectification signal lag time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the on-time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |; The time interval between two disturbances satisfies the time required for the output voltage to adjust to the reference value;

[0017] S4. If Δf≥AΔf ref , let T SR,k+1 =T SR,k -ΔT SR , Determine the ideal synchronous rectification signal hysteresis time in over-resonance state And the conduction time is T SR,k+1 , end, if Δf<AΔf ref , then update Δf refThe value is Δf, k=k+1, go to S3, A is 1.5.

[0018] The present invention provides a beneficial effect. By applying a certain disturbance signal to the synchronous rectification signal, and then according to the change in the operating frequency before and after the converter reaches a stable output signal, the synchronous rectification signal of the converter gradually approaches the ideal synchronous rectification state. The advantages of the present invention are mainly manifested in that, because the CLLLC resonant converter already has an output voltage detection unit to detect the output voltage, the switching frequency under variable frequency control can be directly obtained by the microcontroller. Therefore, this method can achieve ideal synchronous rectification without the need for additional sensors, while avoiding complex theoretical calculations. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the control method of the present invention;

[0020] Figure 2 Flowchart for optimizing the present invention;

[0021] Figure 3 For the definition of different rectification states;

[0022] Figure 4 Different operating modes of the CLLLC resonant converter under the time domain model;

[0023] Figure 5 is the working waveform of the converter when it is in the synchronous rectification distortion state in the sub-resonant working mode;

[0024] Figure 6 T is the sub-resonant working mode SR With load R o and operating frequency f s The relationship curve diagram;

[0025] Figure 7 When the input voltage is 400V and the output voltage is 1000W, the stable output voltage is 54V. SR With the operating frequency f s The relationship curve of

[0026] Figure 8 When the input voltage is 400V and the output voltage is 1000W, the stable output voltage is 54V. SR With f s Dynamic adjustment process;

[0027] Figure 9 This is the working waveform when the input is 400V and the output is stable at 54V under 1000W working conditions;

[0028] Figure 10 is the working waveform of the converter in the over-resonance working mode;

[0029] Figure 11 is the phase angle of lag in over-resonance mode With load R o and operating frequency f s The relationship curve diagram;

[0030] Figure 12 When the input voltage is 420V and the output voltage is 1000W, the stable output voltage is 48V. SR With the operating frequency f s The relationship curve of

[0031] Figure 13 When the input voltage is 420V and the output voltage is 1000W, the stable output voltage is 48V. SR With f s Dynamic adjustment process;

[0032] Figure 14 This is the working waveform when the input is 420V and the output is stable at 48V under 1000W working conditions. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0034] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0035] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0036] The adaptive synchronous rectification control method for a CLLLC resonant converter according to this embodiment is based on the circuit characteristics and operating process of the CLLLC converter. It analyzes the influence of the converter's synchronous rectification drive signal on the output frequency of the converter when the converter stabilizes the output signal, derives an equation for the relationship between the change in the synchronous rectification signal and the change in the operating frequency near the ideal synchronous rectification signal, and uses the law of this equation to realize the synchronous rectification function of the CLLLC converter.

[0037] The CLLLC converter can operate bidirectionally and in different modes depending on the operating frequency. The following describes the CLLLC converter operating in the under-resonant and over-resonant modes during forward operation.

[0038] Example 1: Taking the converter working in sub-resonant mode as an example, when the converter works in sub-resonant mode, it is considered to be in an ideal synchronous rectification state. According to the time domain analysis method, it works in P mode and O mode, such as Figure 4 shown.

[0039] According to Kirchhoff's voltage law and current law, the expressions of the resonant current, resonant capacitor voltage and excitation current of mode P and mode O can be obtained.

[0040]

[0041] in

[0042]

[0043] In order to obtain the unknowns in the above formula, certain constraints need to be considered:

[0044] ① The inductor current and capacitor voltage will not change suddenly. Therefore, when switching between two adjacent modes, the values ​​of the inductor current and capacitor voltage should be equal.

[0045]

[0046] ② Because the converter adopts a variable frequency modulation strategy, the waveform satisfies half-cycle symmetry during steady-state operation, that is, the value of the state variable at the starting moment of a cycle and the value at the half-cycle moment are opposite to each other;

[0047]

[0048] ③Since the analysis is based on an ideal model, the influence of loss is not considered, that is, the input and output power of the converter are equal.

[0049]

[0050] After iterative calculation by Matlab, the relationship curve between the driving time of the synchronous rectification signal, the operating frequency and the output power of the converter in the under-resonance working mode is obtained as follows: Figure 6 As shown in the figure, in the under-resonance working mode, the minimum time of the synchronous rectification drive signal is about T r =π / ω a1 .

[0051] Based on the above calculation, taking the design parameters of this embodiment as an example, L r =57.068μH,C r =44.386nF, L m= 285.341 μH, n = 8. Assuming the converter input voltage is 400 V, the output voltage is 54 V, and the full load is 1 kW, the time domain model calculation shows that the converter operating frequency is 87 kHz when losses are ignored.

[0052] At this time, the voltage and current coefficients of the converter in P mode and O mode are P a1 =-155.4738, P a2 =-72.1478, P a3 =-422.5267, P a4 =-239.2876, t1 = 5.088e-6, O1 = -278.3431, O2 = 311.0252. Considering the rectifier diode directional conduction voltage drop V f =The loss caused by 0.3V.

[0053]

[0054] The change in output voltage can be expressed as

[0055]

[0056] If the converter output is still maintained at 54V, the coefficient of the converter operating in the 87kHz time domain model is used as a reference, and the time relationship diagram of the converter operating frequency and the synchronous rectification drive signal can be obtained as follows: Figure 7 If the on-time of the synchronous rectifier is further increased, the converter will have two additional operating modes, and the operating waveforms are as follows: Figure 5 As shown. In [t1,t 1_mi ] period, the inductor L r1 With capacitor C r1 Resonance still occurs and the circuit continues to operate in P mode. At this time, the current reverses, so the secondary side transfers energy to the primary side.

[0057] In [t 1_mi During the time period t2], due to the existence of the inductor, the current cannot change suddenly. Since the switch tube is turned off, the current will be conducted by the parasitic diode of the other switch tube in the bridge arm. At this time, the converter works in N mode.

[0058] The time domain expression in N mode is similar to that in P mode. It only needs to change V'2 to -V'2, that is,

[0059]

[0060] The final value of the P mode is the initial value of the N mode. Substituting the final value of the P mode into the initial value of the N mode, we can obtain the energy transferred from the secondary side to the primary side of the converter.

[0061]

[0062] The change in output voltage can be expressed as

[0063]

[0064] Since the synchronous rectification driving time is performed with a small disturbance, the time domain parameters at 87kHz are still used, and |Δf s |With T SR The relationship curve is as follows Figure 7 As shown in (b). Figure 7 From (b), we can see that when T SR If you still want to maintain a certain input voltage after exceeding the ideal synchronous rectification signal, the operating frequency of the converter will change significantly. Therefore, you can gradually increase T SR By judging the relative change of the operating frequency, it can be determined whether the converter is in the ideal synchronous rectification state.

[0065] Based on the above analysis, an adaptive synchronous rectification control method suitable for CLLLC resonant converter is obtained, as shown in Figure 2 As shown in (a) and (b). First, according to the collected voltage and current, it is determined that the working state of the converter will not change. At the same time, the output signal V o Perform real-time sampling and compare it with the given value V ref The error signal is sent to the loop controller. When the output is stable, the working state of the converter is obtained. The CLLLC resonant converter operates in sub-resonant mode and performs synchronous rectification optimization:

[0066] Step 1: Give the converter an initial synchronous rectification signal on-time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k-1 ; The initial value of k is 1; In this embodiment, T SR,0 =0.48T r1 , T r1 is the resonant period;

[0067] Step 2: As the loss of the converter synchronous rectifier tube decreases, the converter operating frequency needs to be further adjusted to stabilize the output voltage. After the converter output is stable, a fixed disturbance ΔT is given to the converter synchronous rectifier signal. SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , get a reference value of frequency change Δfref =|f s,k -f s,k-1 |.

[0068] Step 3: Give the converter synchronous rectification signal a fixed disturbance ΔT SR , let the on-time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |; In this embodiment, T SR,0 =0.48T r1 , T r1 is the resonant period;

[0069] Step 4: If Δf < AΔf ref , then let Δf ref =Δf, go to step 3; if Δf≥AΔf ref , the converter is considered to be in a synchronous rectification error state. At this time, the synchronous rectification drive signal needs to fall back to the previous state. The ideal synchronous rectification on-time in the sub-resonant mode is determined to be T SR,k+1 In this example, A = 1.5, ΔT SR The change in value is changed in 1% steps; at the same time, the time interval between two disturbances satisfies the time required for the output voltage to adjust to the reference value. In order to ensure that the output has enough time to stabilize after the disturbance is added, the time of each superimposed disturbance is set to 1ms.

[0070] According to the established model, the optimization process of the synchronous rectification drive signal is as follows: Figure 8 The adjusted experimental results are shown in Figure 9 shown.

[0071] Example 2: Take the converter working in over-resonance mode as an example. When the converter works in over-resonance mode, it is considered to be in ideal synchronous rectification state. According to the time domain analysis method, it works in N mode and P mode. The working waveform is as follows: Figure 10 shown.

[0072] According to Kirchhoff's voltage law and current law, the expressions of the resonant current, resonant capacitor voltage and excitation current of mode N and mode P can be obtained.

[0073]

[0074] In the case of over-resonance, the circuit is inductive and the load current will lag behind the primary drive for a certain period of time. Using the boundary conditions, we can get that in the over-resonance mode, with the secondary side current zero crossing point t0 as the reference, T SR With the operating frequency f s and load R o The relationship curve is as follows Figure 11 shown. It is used to set the initial turn-on time of the secondary-side rectifier tube. When the synchronous rectification method proposed in this embodiment is subsequently used, no calculation is required. A larger time can be set. The subsequent turn-on time can be corrected by the optimization algorithm.

[0075] Based on the above calculation, the converter input voltage is 420V, the output voltage is 48V, and the full load is 1kW. The time domain model is used to calculate that the operating frequency of the converter is 115kHz when the loss is ignored.

[0076] At this time, the voltage and current coefficients of the converter in N mode and P mode are N b1 =-521.7242, N b2 =-120.017, N b3 =-14.8509, N b4 =-167.1706, P b1 =-149.0349, P b2 =-50.4038, P b3 =-405.4478, P b4 =-167.1706. Considering the conduction voltage drop V of the rectifier diode f =The loss caused by 0.3V.

[0077]

[0078] The change in output voltage can be expressed as

[0079]

[0080] If the converter output is still maintained at 48V, the coefficient of the converter operating in the 115kHz time domain model can be used as a reference to obtain the time relationship between the converter operating frequency and the synchronous rectification drive signal with the secondary side current zero crossing point as the reference. Figure 12 As shown in (a).

[0081] Under the above working conditions, it is known through iterative calculation that the lag time of the synchronous rectification signal is 0.21μs. Under the over-resonant operating state, the initial lag value of the synchronous rectification signal needs to meet the maximum lag time under all working conditions, so as to meet the lag time of the driving signal. As an example, we analyze the converter. When the converter is in over-resonance, the current flowing through the secondary side is continuous. If the on-time T of the synchronous rectifier is further increased, SR Since the converter has a large margin at the initial moment of synchronous rectification, the converter will reach a new equilibrium state. At this time, time t1 can be calculated as a known quantity. At this time, the converter is also in the combination of N mode and P mode.

[0082] After iterative calculation, in this working mode, if the output voltage is to be maintained at 48V, the operating frequency needs to be adjusted to 122.8kHz. Then, the waveform of the transition from the incomplete synchronous rectification state to the ideal synchronous rectification state can be obtained as follows: Figure 12 As shown in (b).

[0083] Therefore, in over-resonance mode, the initial value can lag behind the primary drive signal by a significant amount, which can be measured in practice with a certain margin. After finding the ideal turn-off time of the synchronous rectifier using the same optimization algorithm as for under-resonance, its turn-on time can be found by assuming a normal switching frequency for the on-time. When the CLLLC resonant converter operates in over-resonance mode, the process of optimizing synchronous rectification includes:

[0084] Step 1: Synchronous rectification signal lag time of the converter After that, the initial synchronous rectification signal conduction time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k-1 ; To meet the maximum hysteresis time of the converter under all working conditions, this embodiment T S Represents the switching cycle; the initial value of k is 1,

[0085] Step 2: Synchronous rectification signal lag time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , get a reference value of frequency change Δf ref =|f s,k -f s,k-1 |; In this embodiment, ΔT SR =0.01T S , T S represents the switching cycle;

[0086] Step 3: Synchronous rectification signal lag time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the on-time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |;

[0087] Step 4: If Δf ≥ AΔf ref , let T SR,k+1 =T SR,k -ΔT SR , Determine the ideal synchronous rectification signal hysteresis time in over-resonance state And the conduction time is T SR,k+1 , end, if Δf<AΔf ref , then update Δf ref The value of is Δf, k=k+1, go to step 3, in this example A=1.5, ΔT SR The change in value is changed in 1% steps; at the same time, the time interval between two disturbances satisfies the time required for the output voltage to adjust to the reference value. In order to ensure that the output has enough time to stabilize after the disturbance is added, the time of each superimposed disturbance is set to 1ms.

[0088] According to the established model, the optimization process of the synchronous rectification drive signal is as follows: Figure 13 The adjusted experimental results are shown in Figure 14 shown.

[0089] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the invention. It should be understood that many modifications may be made to the illustrative embodiments, and that other arrangements may be devised, without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in ways other than those described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be employed in conjunction with other described embodiments.

Claims

1. An adaptive synchronous rectification control method for a CLLLC resonant converter, characterized in that: include: The output voltage V of the CLLLC resonant converter o Perform real-time acquisition and output the real-time acquired output voltage as a signal V o With a given voltage V ref Comparison is performed and the compared error signal is sent to the loop controller to stabilize the output voltage of the CLLLC resonant converter; When the output voltage of the CLLLC resonant converter is stable and the CLLLC resonant converter operates in sub-resonant mode, synchronous rectification optimization is performed: S1, giving the converter the initial synchronous rectification signal conduction time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k-1 ;The initial value of k is 1; S2, giving the converter a fixed disturbance ΔT on the synchronous rectification signal SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , get a reference value of frequency change Δf ref =|f s,k -f s,k-1 |; The time interval between two disturbances satisfies the time required for the output voltage to adjust to the reference value; S3, giving the converter a fixed disturbance ΔT on the synchronous rectification signal SR , let the on-time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |; S4. If Δf≥AΔf ref , let T SR,k+1 =T SR,k -ΔT SR , the on-time of the ideal synchronous rectification in sub-resonant mode is determined to be T SR,k+1 , end, if Δf<AΔf ref , then update Δf ref The value is Δf, k=k+1, go to S3, A is 1.

5.

2. The adaptive synchronous rectification control method for a CLLLC resonant converter according to claim 1, wherein: T SR,0 =0.48T r1 , T r1 is the resonant period.

3. The adaptive synchronous rectification control method for a CLLLC resonant converter according to claim 1, wherein: ΔT SR =0.01T r1 , T r1 is the resonant period.

4. The adaptive synchronous rectification control method for a CLLLC resonant converter according to claim 1, wherein: The time interval between two disturbances is 1ms.

5. An adaptive synchronous rectification control method for a CLLLC resonant converter, characterized in that: include: The output voltage V of the CLLLC resonant converter o Perform real-time acquisition and output the real-time acquired output voltage as a signal V o With a given voltage V ref Comparison is performed and the compared error signal is sent to the loop controller to stabilize the output voltage of the CLLLC resonant converter; When the output voltage of the CLLLC resonant converter is stable and the CLLLC resonant converter operates in over-resonance mode, synchronous rectification optimization is performed: S1, synchronous rectification signal lag time of converter After that, the initial synchronous rectification signal conduction time T SR,k-1 After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k-1 ;The initial value of k is 1; Meet the maximum lag time of the converter under all working conditions; S2, synchronous rectification signal lag time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the synchronous rectification signal conduction time T SR,k =T SR,k-1 +ΔT SR After the output voltage of the CLLLC resonant converter is stable, the operating frequency at this time is recorded as f s,k , get a reference value of frequency change Δf ref =|f s,k -f s,k-1 |; S3, synchronous rectification signal lag time After that, a fixed disturbance ΔT is given to the synchronous rectification signal of the converter. SR , let the on-time of the synchronous rectification signal be T SR,k+1 =T SR,k +ΔT SR After the output voltage of the CLLLC resonant converter is stable, record the operating frequency f at this time. s,k+1 , we get a frequency change Δf=|f s,k+1 -f s,k |; The time interval between two disturbances satisfies the time required for the output voltage to adjust to the reference value; S4. If Δf≥AΔf ref , let T SR,k+1 =T SR,k -ΔT SR , determine the ideal synchronous rectification signal lag time in the over-resonance state And the conduction time is T SR,k+1 , end, if Δf<AΔf ref , then update Δf ref The value is Δf, k=k+1, go to S3, A is 1.

5.

6. The adaptive synchronous rectification control method for a CLLLC resonant converter according to claim 5, wherein: T S Indicates the switching cycle.

7. The adaptive synchronous rectification control method for a CLLLC resonant converter according to claim 5, wherein: T S Indicates the switching cycle.

8. The adaptive synchronous rectification control method for a CLLLC resonant converter according to claim 5, wherein: ΔT SR =0.01T S , T S Indicates the switching cycle.

Images